TWI689198B - Method and apparatus for encoding processing blocks of a frame of a sequence of video frames using skip scheme - Google Patents

Abstract

A video encoding apparatus is disclosed. The apparatus is used to process a sequence of frames of video data and each frame comprises a plurality of processing blocks. The apparatus comprises a skip decision circuit and an encoder. The skip decision circuit generates a control signal according to a similarity checking result and a comparison result between a first quantization parameter for a first processing block from a current frame and a second quantization parameter for a second processing block from a previous frame. The encoder encodes the first processing block to generate an encoded bit stream and the first quantization parameter. The second processing block resides at the same location in the previous frame as the first processing block in the current frame.

Description

Use the skip mechanism to encode the processing block of one of a series of video frames Method and device

The present invention relates to video compression technology, and more particularly to a method and device for processing block encoding of a frame in a series of video frames using a skip mechanism.

The moving picture experts group (MPEG) standard strictly defines a skip macroblock (16x16 pixels) as a forward predictive-coded image (P image) For the giant block, when the giant block is compared with its reference giant block, the forward prediction encoded image has zero prediction error value and zero motion vector. In a bidirectional predictive coded picture (B picture), a skipped giant block has zero prediction error value and a motion vector, which is the same as the motion vector of a previous giant block, and the previous giant block It is not an intracoded giant block. Once distinguished, there is no need to encode the skipped giant block in any bits, and no information (ie, no encoding coefficients, no headers, and no prediction information) is sent to the decoder .

In H.264, an encoder can select the skip mode for a skipped giant block in a P/B slice; a decoder estimates from a coded giant block adjacent to the skipped giant block The motion vector of the skipped giant block, and the motion vector is used to calculate the motion compensation prediction of the skipped giant block. Because there is no residual, the motion compensation prediction is directly embedded in the decoded frame or field. The encoder decides whether to encode or skip a huge block. Generally speaking, when the rate-distortion cost of the bypass mode is lower than any encoding mode, that is, the weighted combination of bit rate and distortion (quality loss of decoding huge blocks) is low, the The encoder may choose to skip. To omit calculations, the encoder may "guess" the skip mode suitable for using other criteria, such as local scene statistics.

However, with regard to extended video applications, low latency and limited transmission bandwidth limit the video coding architecture. The video coding architecture cannot afford several frame delays adopted by the MPEG-like standard. Moreover, due to the limited bandwidth, in the case where consecutive frames have the same image content and the perceived quality of the encoded frame does not deteriorate, the video coding architecture must try to save bits.

In view of the above problems, one object of the present invention is to provide a video encoding device that can reduce the total number of bits required to encode a frame and still maintain video details and quality.

According to an embodiment of the invention, a video encoding device is provided for processing video data of a series of frames, each frame including a plurality of For processing blocks, the device includes a skip decision circuit and an encoder. The skip determination circuit generates a comparison result of a similarity check result and a first quantization parameter of a first processing block in a current frame and a second quantization parameter of a second processing block in a previous frame One control signal. The encoder encodes the first processing block to generate an encoded bit stream and the first quantization parameter. Wherein, the position of the second processing block in the previous frame is the same as the position of the first processing block in the current frame.

Another embodiment of the present invention provides a video encoding method for processing video data of a series of frames. Each frame includes a plurality of processing blocks. The method includes: according to a similarity check result and a current frame The comparison result of the first quantization parameter of the first processing block and the second quantization parameter of a second processing block of a previous frame generates a control signal; and, encodes the first processing block to generate an encoded bit Meta stream and the first quantization parameter; wherein the position of the second processing block in the previous frame is the same as the position of the first processing block in the current frame.

According to another embodiment of the present invention, a video encoding device is provided for processing video data of a series of frames. Each frame includes a plurality of processing blocks. The device includes a skip decision circuit and an encoder. The skip decision circuit is based on a block type, a similarity check result, and a first quantization parameter of a first processing block of a current frame and a second quantization of a second processing block of a previous frame The comparison result of the parameters generates a control signal. The encoder encodes a third processing block to generate a Encode the bit stream and the first quantization parameter. Wherein, the third processing block is one of the first processing block and a residual; and wherein the position of the second processing block in the previous frame is the same as that of the first processing block The position of the current frame.

Another embodiment of the present invention provides a video encoding method for processing video data of a series of frames. Each frame includes a plurality of processing blocks. The method includes: according to a block type, a similarity check result, and a The comparison result of the first quantization parameter of a first processing block in the current frame and the second quantization parameter of a second processing block in a previous frame generates a control signal; and, encoding a third processing area Block to generate a coded bit stream and the first quantization parameter. Wherein, the third processing block is one of the first processing block and a residual; and, wherein the position of the second processing block in the previous frame is the same as the position of the first processing block At the current frame position.

According to another embodiment of the present invention, a video transmission system is provided for transmitting video data of a series of frames, each frame includes a plurality of processing blocks, the device includes: a communication channel, a video encoding device, a transmission Receiver, a receiver and a video decoding device. The video encoding device includes a skip determination circuit and an encoder. The skip determination circuit generates a comparison result of a similarity check result and a first quantization parameter of a first processing block in a current frame and a second quantization parameter of a second processing block in a previous frame One control signal. The encoder, the The first processing block is coded to generate a coded bit stream and the first quantization parameter. The transmitter converts a first formatted bit stream into multiple data packets, and transmits the data packets to the communication channel. The receiver receives the data packets and converts the data packets into a second formatted bit stream. The video decoding device includes a reference buffer for dividing the second formatted bit stream into a second encoded bit stream and a second skip flag, and according to the second skip flag One of the second coded bit stream and the reference buffer reconstructs a third processing block. Wherein, the position of the second processing block in the previous frame is the same as the position of the first processing block in the current frame.

According to another embodiment of the present invention, a video transmission system is provided for transmitting video data of a series of frames, each frame includes a plurality of processing blocks, the device includes: a communication channel, a video encoding device, a transmission Receiver, a receiver and a video decoding device. The video encoding device includes a skip determination circuit and an encoder. The skip decision circuit is based on a block type, a similarity check result, and a first quantization parameter of a first processing block of a current frame and a second quantization of a second processing block of a previous frame The comparison result of the parameters generates a control signal. The encoder encodes a third processing block to generate an encoded bit stream and the first quantization parameter, where the third processing block is one of the first processing block and a residual. The transmitter converts a first formatted bit stream into multiple data packets, and transmits the data packets to the communication channel. The receiver receives the data packets and converts the data packets into a second formatted bit stream. The video decoding device includes a reference buffer and a difference buffer for dividing the second formatted bit stream into a second encoded bit stream, a second type flag, and a second skip A flag, and a fifth processing area is reconstructed from at least one of the second coded bit stream, the difference buffer and the reference buffer according to the second type flag and the second skip flag Piece. Wherein, the position of the second processing block in the previous frame is the same as the position of the first processing block in the current frame.

In conjunction with the following figures, detailed description of the embodiments and the scope of patent application, the above and other objects and advantages of the present invention will be described in detail later. .

100A, 100B, 100C, 200, 300, 400, 500A, 500B

110‧‧‧Current frame

120‧‧‧Encoder

121‧‧‧ Conversion unit

122‧‧‧Quantizer

123‧‧‧Entropy encoder

124‧‧‧ Bit rate control unit

130a, 130b, 130c ‧‧‧ bit stream formatting unit

140‧‧‧symptom storage device

150a, 150b ‧‧‧ similarity check circuit

160a, 160b ‧‧‧ skip the decision unit

170‧‧‧QP storage device

180‧‧‧symptom generator

210‧‧‧Previous frame

221‧‧‧SAD calculation unit

222, 324, 350 ‧‧‧ comparator

310‧‧‧Reference buffer

320, 320’‧‧‧ type selector

321‧‧‧Total unit

322‧‧‧ Absolute Total Unit

323‧‧‧Subtractor

325, 613‧‧‧Multiplexer

330‧‧‧Update controller

340, 813‧‧‧ output controller

510‧‧‧Mobile estimation unit

600, 700, 800, 900 ‧‧‧ video decoding device

610, 810, 910‧‧‧ storage and select output circuit

611‧‧‧ Output controller

612‧‧‧DRAM

620a, 620b ‧‧‧ parser

630, 630a‧‧‧ decoder

631‧‧‧Entropy decoder

632‧‧‧Inverse quantizer

633‧‧‧Inverse conversion unit

811‧‧‧ Difference buffer

812‧‧‧ Reference buffer

814‧‧‧Source selector

830‧‧‧Adder

911‧‧‧Data extraction unit

1000‧‧‧Video transmission system

1010‧‧‧Image source

1020‧‧‧Video encoding device

1030‧‧‧Transmitter

1040‧‧‧Communication channel

1050‧‧‧Receiver

1060‧‧‧Video decoding device

1070‧‧‧Monitor

FIG. 1A is a block diagram showing a video encoding device according to an embodiment of the present invention.

FIG. 1B is a block diagram showing a video encoding device according to another embodiment of the present invention.

FIG. 1C is a block diagram showing a video encoding device according to another embodiment of the present invention.

FIG. 2 is a block diagram showing a video encoding device according to another embodiment of the present invention.

FIG. 3A is a block diagram showing a video encoding device according to another embodiment of the present invention.

FIG. 3B is a block diagram showing a type selector according to an embodiment of the invention.

FIG. 3C is a block diagram showing a type selector according to another embodiment of the present invention.

FIG. 4 is a block diagram showing a video encoding device according to another embodiment of the present invention.

FIG. 5A is a block diagram showing a video encoding device according to another embodiment of the present invention.

FIG. 5B is a block diagram showing a video encoding device according to another embodiment of the present invention.

FIG. 6 is a block diagram showing a video decoding device according to an embodiment of the present invention.

FIG. 7 is a block diagram showing a video decoding device according to another embodiment of the present invention.

FIG. 8 is a block diagram showing a video decoding device according to another embodiment of the present invention.

FIG. 9 is a block diagram showing a video decoding device according to another embodiment of the present invention.

FIG. 10 is a block diagram showing a video transmission system according to an embodiment of the present invention.

Mentioned throughout the specification and subsequent requests The terms "a" and "the" in singular form include both singular and plural meanings unless otherwise specified in this specification.

Before feeding a series of video frames into the video encoding system of the present invention, each frame is divided into a plurality of processing blocks, and each processing block includes a plurality of pixels. For example, a processing block may include 16x16 pixels, so the industry is also called a macroblock (MB). For ease of description, giant blocks are used for description in the following examples and embodiments. However, it should be noted that the processing block is not limited to the giant block, but can be any size other than 16x16. For example, the processing block may be 8x8 pixels, suitable for still image compression standard (JPEG) encoding, or one pixel line or two pixel lines, suitable for line-based encoding.

The present invention uses a similarity (similarity) check mechanism and a skip giant block mechanism to encode a plurality of giant blocks in one frame of a series of video frames. One of the features of the present invention is to decide whether to skip encoding a giant block based on the image similarity and quantization value of two corresponding giant blocks at the same position in two adjacent frames, so as to reduce the encoding of one frame to facilitate transmission The total number of bits required while still maintaining video detail and quality. Another feature of the present invention is: if the current giant block of a current frame and the corresponding block of a previous frame (located in the previous frame are at the same position as the current giant block in the current frame Location) with similar video content and the quantization parameter (QP1) of the current giant block is greater than or equal to the quantization parameter (QP2) of the corresponding block, then skip it Encode the current giant block, otherwise, encode the current giant block. As is well known in the industry, “QP1>=QP2” indicates that the image quality of the current giant block is not as good as or equal to the corresponding block of the previous frame. Therefore, there is no need to encode huge blocks with poor image quality for transmission, so transmission bandwidth can be saved and image quality can be maintained.

In the entire specification and subsequent requests, the term "similarity check mechanism" refers to the calculation of a sum of absolute differences for two corresponding giant blocks located at the same position in two adjacent frames. , SAD) value or compare the image features of the two corresponding giant blocks to determine the image similarity, where the image features are cyclic redundancy check (CRC), hash and checksum One or a combination thereof. For example, if the SAD value of two corresponding giant blocks of two adjacent frames is less than a critical value, it is determined that the two corresponding giant blocks are similar. The term "I giant block" refers to an intra-coded giant block, and the term "P giant block" refers to a forward prediction encoded giant block. Another feature of the present invention is that each frame is a combination of multiple I giant blocks or/and P giant blocks. In one embodiment, the block type of each giant block in a frame (i.e., I giant block or P giant block) is determined by a type selector 320/320' (to be discussed later). The term "IPP mode" refers to a sequence of giant blocks located at the same position in adjacent frames, where the sequence begins with an I giant block, followed by a plurality of P giant blocks, and The encoding of each P giant block uses the I giant block as a reference block. In contrast, the term "I-I-I mode" refers to a sequence of I giant blocks at the same position in a plurality of adjacent frames, where each I giant block uses only the Encode the video information of the body frame.

FIG. 1A is a block diagram showing a video encoding device according to an embodiment of the present invention. Referring to FIG. 1A, the video encoding device 100A of the present invention operates in the III mode and includes an encoder 120, a bitstream formatting unit 130a, a syndrome storage device 140, and a similarity check The circuit 150a, a skip decision unit 160a, a QP storage device 170 and a symptom generator 180. The video encoding device (100A/B/C, 200, 300, 400, 500A/B) of the present invention processes a series of frames of video data, and each frame includes a plurality of giant blocks. Specifically, the video encoding device 100A is used to receive a previous giant block MB1 of a current frame, determine whether to encode the current giant block MB1, and generate a formatted bit stream. The formatted bit stream is fed into a transmitter 1030 for transmission through a communication channel 1040 (please refer to FIG. 10). Generally speaking, the pixel value of the giant block MB1 can be R, G, B signal or Y, Cb, Cr signal, which is output from a video camera as an 8-bit digital signal, but these pixel values are not Limited to the above example.

According to the control signal C1 from the skip decision unit 160a, the encoder 120 receives the current macroblock MB1 with 16x16 pixels of the current frame 110 and encodes the current macroblock MB1 to generate an encoded bit stream And a quantization parameter QP _C. The quantization parameter includes, but is not limited to, the quantization step in JPEG/MPEG and the quantization level in H.264. The symptom generator 180 receives the current giant block MB1, calculates a current symptom S _C , and stores the current symptom S _C to the symptom storage device 140. The symptom S _C /S _P includes, but is not limited to, CRC, hash and checksum. The similarity check circuit 150a compares the current macroblock MB1 current symptoms S _C and a previous frame to a corresponding macroblock in FIG. (A position at which the previous frame is the same as the current in the current macroblock MB1 FIG. The position of the box) the previous symptom S _P to produce a check result Sim. In one embodiment, the similarity check circuit 150a is implemented by a comparator (not shown); the logical value of the check result Sim is equal to 1, indicating that the current symptom S _C is equal to the previous symptom S _P (indicating The current giant block MB1 and the corresponding giant block have similar image contents), and the logical value of the check result Sim is equal to 0, indicating that the current symptom S _{C is} different from the previous symptom S _P (indicating that the current giant area Block MB1 and the corresponding giant block have completely different image contents). In one embodiment, the skip decision unit 160a is implemented by a comparator (not shown), the comparator is controlled by the check result Sim; if the check result Sim has a logic value of 0, the skip decision The unit 160a is disabled and generates a control signal C1 with a logic value 0; if the check result Sim has a logic value 1, the skip determination unit 160a is enabled and compares the current quantization parameter QP _{C of} the current giant block MB1 And the previous quantization parameter QP _{P of} the corresponding giant block generates the control signal C1. If the check result Sim has a logic value of 1 and the current quantization parameter QP _{C of} the current giant block MB1 is greater than or equal to the previous quantization parameter QP _{P of} the corresponding giant block, it means that the image quality of the current giant block MB1 is not as good as or Is equal to the corresponding giant block, so there is no need to encode the current giant block MB1 for transmission, therefore, the current giant block MB1 is skipped (ie, the current giant block MB1 is not encoded), and the skip decision unit 160a is Generate a control signal C1 with a logic value of 1. If the check result Sim has a logical value of 1 and the current quantization parameter QP _{C of} the current giant block MB1 is less than the previous quantization parameter QP _{P of} the corresponding giant block, it means that the image quality of the current giant block MB1 is better than the corresponding For the giant block, it is necessary to encode the current giant block MB1 for transmission. Therefore, the skip determination unit 160a generates a control signal C1 with a logic value of 0 (indicating that the current giant block MB1 is not skipped). In another embodiment, the skip determination unit 160a may be implemented by software, or a combination of hardware and software.

According to the present invention, the wiring of the control signal C1, the encoder 120, and the bit stream formatting unit 130a is configured into one of three configurations (ie, single-wire configuration, two-wire configuration, and bypass configuration) (1) to output a corresponding formatted bit stream. When the wiring of the control signal C1, the encoder 120 and the bit stream formatting unit 130a is configured in a two-wire configuration, the control signal C1 is provided to the encoder 120 and the bit stream formatting unit 130a, As shown in Figure 1A. If the control signal C1 has a logic value of 1, the encoder 120 is disabled and does not generate any output, and the bit stream formatting unit 130a sets a skip flag to 1 (indicating that skipping does not encode the current The giant block MB1) incorporates the skip flag into the formatted bit stream. If the control signal C1 has a logic value of 0, the encoder 120 is enabled and generates an encoded bit stream, and the bit stream formatting unit 130a sets a skip flag to 0 (indicating that it has not been skipped (i.e. Coded) the current giant block MB1) and merge the skip flag and the coded bitstream into the formatted bitstream.

When the control signal C1, the encoder 120 and the bit stream format When the wiring of the conversion unit 130a is configured in a single-wire configuration, only the control signal C1 is provided to the bit stream formatting unit 130a, and the encoder 120 is always in the enabled state to generate the coded bit stream, as shown in the first As shown in Figure 1B. If the control signal C1 has a logic value of 1, the bit stream formatting unit 130a sets a skip flag to 1 and incorporates the skip flag into the formatted bit stream (excluding the encoded bit stream) Otherwise, the bit stream formatting unit 130a sets the skip flag to 0 (indicating that the current giant block MB1 is not skipped) and incorporates the skip flag and the encoded bit stream into the format Bit stream. When the wiring of the control signal C1, the encoder 120, and the bit stream formatting unit 130a is configured in a shunt configuration, only the control signal C1 is provided to the encoder 120, and the encoder 120 is separately transmitted The bit stream formatting unit 130a is shown in FIG. 1C. If the control signal C1 has a logic value of 1, the encoder 120 is disabled, and only the control signal C1 is sent to the bit stream formatting unit 130a without generating any encoded bit stream, and the bit The stream formatting unit 130a sets a skip flag to 1 and incorporates the skip flag into the formatted bit stream. If the control signal C1 has a logic value of 0, the encoder 120 is enabled and generates the encoded bit stream, and transmits the encoded bit stream and the control signal C1 to the bit stream formatting unit 130a, and the bit The element stream formatting unit 130a sets a skip flag to 0 and merges the skip flag and the encoded bit stream into the formatted bit stream. Please note that although Figures 2, 3A, 4, and 5A/B only show the wiring of the control signal C1, the encoder 120, and the bitstream formatting unit 130a/b/c are configured in a two-wire configuration, the The single-line configuration and the shunt configuration are also applicable to video encoding devices 200, 300, 400 and 500A/B.

Referring to FIG. 1A, the encoder 120 includes a conversion unit 121, a quantizer 122, an entropy encoder 123, and a bit rate control unit 124. Depending on the size of the processing blocks, the conversion unit 121 may be a discrete cosine transform (discrete cosine transform) unit, a tile wavelet (tile wavelet) transform unit, or a line-based wavelet ( wavelet) conversion unit. The conversion unit 121 converts the current giant block MB1 to generate 256 conversion coefficients. After that, the quantizer 122 quantizes the conversion coefficients in a block-by-block manner according to the current quantization parameter (QP _C ) to generate multiple Quantization parameters. Then, after the entropy encoder 123 encodes the quantization parameter into the encoded bit stream, the bit rate control unit 124 dynamically adjusts the current quantization parameter according to the bit rate output from the entropy encoder 123 (QP _C ) To achieve a target bit rate. The bit rate control unit 124 allocates some bits to each giant block. The current quantization parameter (QP _C ) is provided to the quantizer 122, the skip decision unit 160a, and the QP storage device 170. The symptom storage device 140 and the QP storage device 170 can be implemented with SRAM buffers or DRAM buffers. In this specification, circuit elements with the same function use the same reference symbols.

FIG. 2 is a block diagram showing a video encoding device according to another embodiment of the present invention. Referring to FIG. 2, the video encoding device 200 of the present invention operates in the I-I-I mode and includes an encoder 120, a bit stream formatting unit 130a, a similarity check circuit 150b, and a skip decision unit 160a. And a QP storage device 170. The video encoding device 200 of the present invention is used to receive a current giant block MB1 of a current frame 110 and a previous giant block MB2 of a previous frame 210, determine whether to encode the current giant block MB1 and generate a formatted bit stream . Compared to the video encoding device 100A, the video encoding device 200 adds the similarity checking circuit 150b, and deletes the symptom storage device 140, the similarity checking circuit 150a, and the symptom generator 180.

The similarity check circuit 150b includes a SAD calculation unit 221 and a comparator 222. The SAD calculation unit 221 receives a current giant block MB1 of the current frame 110 and a previous giant block MB2 of the previous frame 120 (the position in the previous frame 210 is the same as the current giant block MB1 in the current frame (The position of block 110), calculate the sum of the absolute errors of the pixel values in the current giant block MB1 relative to the previous giant block MB2, and generate a SAD value. The comparator 222 compares the SAD value with a threshold value th1 to generate a check result Sim. In one embodiment, the output Sim of the similarity checking circuit 150b has a logical value of 1 representing two giant blocks MB1, MB2 having similar image content, and the output Sim of the similarity checking circuit 150b has a logical value of 0 representing two The huge blocks MB1 and MB2 have completely different image contents. The same elements in FIGS. 1A and 2 will not be repeated here. The difference between Figure 1A and Figure 2 is that Figure 1A uses the symptom (CRC/hash/checksum) between the corresponding giant blocks of adjacent frames to perform similarity check, while Figure 2 uses the adjacent frame The similarity check is performed corresponding to the SAD value between giant blocks.

FIG. 3A is a block diagram showing a video encoding device according to another embodiment of the present invention. Referring to FIG. 3A, the video encoding device 300 of the present invention operates in the IPP mode and includes an encoder 120, a bit stream formatting unit 130b, a similarity check circuit 150b, a skip determination unit 160b, and a QP storage device 170. A type selector 320, an update controller 330, a reference buffer 310, and a decoder 630. The video encoding device 300 of the present invention is used to receive a current giant block MB1 of a current frame, a corresponding giant block MB2 of a previous frame 210, and a corresponding giant block of a reference frame stored in the reference buffer 310 Block MB3 determines whether to encode the current giant block MB1 or a difference giant block (MB1-MB3) to generate a formatted bit stream. Wherein, the positions of the two corresponding giant blocks MB2 and MB3 in the previous frame 210 and the reference frame are the same as the position of the current giant block MB1 in the current frame 110.

FIG. 3B is a schematic diagram showing the structure of a type selector according to an embodiment of the invention. Referring to FIG. 3B, the type selector 320 includes a subtractor 323, a summing unit 321, an absolute summing unit 322, a comparator 324, and a multiplexer 325. The summation unit 321 calculates the sum of the pixel values of the current giant block MB1 to generate a summation value s1. The subtractor 323 subtracts the corresponding giant block MB3 from the current giant block MB1 in a pixel-by-pixel manner to generate a difference giant block (MB1-MB3) with 256 differences ). The absolute summation unit 322 calculates the sum of the absolute values of the 256 difference values in the difference giant blocks (MB1-MB3) to generate a summation value s2. The comparator 324 After comparing the two summed values s1 and s2 to generate a block type signal Md, the block type signal Md is sent to the bit stream formatting unit 130b, the skip decision unit 160b, and the update controller 330 . In one embodiment, the block type signal Md has a logic value 1 indicating that the current giant block MB1 is an I giant block, that is, s1<s2; and the signal Md has a logic value 0 representing the current giant block MB1 It is a P giant block, that is, s1>s2. The multiplexer 325 outputs one of the current giant block MB1 and the difference giant block (MB1-MB3) according to the signal Md. If the signal Md has a logic value of 1 (representing that the current giant block MB1 is an I giant block), the multiplexer 325 outputs the current giant block MB1 to the encoder 120, otherwise the multiplexer 325 outputs the Difference block (MB1-MB3) to the encoder 120.

Returning to FIG. 3A, please note that in addition to setting the skip flag (please refer to the related description in FIG. 1A), the bit stream formatting unit 130b also sets a type flag according to the signal Md, and then The type flag, the skip flag, and the encoded bit stream are merged into the formatted bit stream. In one embodiment, if the signal Md has a logical value of 1, the bit stream formatting unit 130b sets the type flag to 1 (representing that the current giant block MB1 is an I giant block), otherwise the bit The stream formatting unit 130b sets the type flag to 0 (representing that the current giant block MB1 is a P giant block); finally, the type flag and the skip flag, together with or excluding the encoding bit The stream (depending on the value of the skipped flag) is incorporated into the formatted bit stream. If the signal Md has a logic value of 1, the update controller 330 is enabled to transmit the encoded bit stream to the decoder 630, which then decodes the encoded bit stream as decoded data and updates the reference The decoded data at the corresponding position in the reference frame of the buffer; if the signal Md has a logic value of 0, the update controller 330 is disabled. The skip decision unit 160b includes an output controller 340 and a comparator 350. The comparator 350 compares the quantization parameter QP _{C of} the current giant block MB1 with a corresponding quantization parameter QP _P from the QP storage device 170 to generate an output signal Cm. If the signal Md has a logic value of 1 (representing that the current giant block MB1 is an I giant block), the output controller 340 directly generates a control signal C1 having a logic value of 0; if the signal Md has a logic value of 0 (representing The current giant block MB1 is a P giant block), and the output controller 340 generates a control signal C1 having a logic value of 0 or 1 according to the output signal Cm. For example, if the signal Md has a logic value of 0 and QP _C >= QP _P (indicating that the image quality of the current giant block MB1 is inferior or equal to the corresponding giant block MB2), the output controller 340 generates a signal with a logic value of 1. Control signal C1 to skip without encoding the current giant block MB1; if the signal Md has a logic value of 0 and QP _C <QP _P (indicating that the current giant block MB1 has better image quality than the corresponding giant block MB2 ), the output controller 340 generates a control signal C1 having a logic value of 0 to encode the current giant block MB1. The block diagram and functions of the decoder 630 will be introduced in Figure 6. In another embodiment, the positions of the reference buffer 310 and the decoder 630 are interchangeable, as shown in FIG. 4. The same elements in FIGS. 1A, 2, and 3A will not be repeated here.

FIG. 4 is a block diagram showing a video encoding device according to another embodiment of the present invention. Referring to FIG. 4, the video encoding device 400 of the present invention It operates in IPP mode and includes an encoder 120, a bit stream formatting unit 130b, a symptom storage device 140, a similarity check circuit 150a, a skip decision unit 160b, a QP storage device 170, an The shape generator 180, a type selector 320, an update controller 330, a reference buffer 310, and a decoder 630. The video encoding device 400 of the present invention is used to receive a current giant block MB1 of a current frame and a corresponding giant block MB3 of a reference frame to determine whether to encode the current giant block MB1 or the difference giant block (MB1) -MB3) to generate a formatted bit stream. The reference buffer 310 stores the reference frame in a bit stream format, and the position of the corresponding giant block MB3 in the reference frame is the same as the position of the current giant block MB1 in the current frame 110. In another embodiment, the positions of the reference buffer 310 and the decoder 630 are interchangeable, as shown in FIG. 3A. All the components in Figure 4 have been introduced in the relevant descriptions in Figures 1A, 2, and 3A-3B, so they will not be repeated here. However, the circuit architecture of Figure 4 is different from Figures 1A, 2, and 3A.

FIG. 5A is a block diagram showing a video encoding device according to another embodiment of the present invention. Referring to FIG. 5A, the video encoding device 500A of the present invention operates in the IPP mode and includes an encoder 120, a bit stream formatting unit 130c, a similarity check circuit 150b, a skip decision unit 160b, and a QP storage device 170. A reference buffer 310, a type selector 320', an update controller 330, a motion estimation unit 510, and a decoder 630. The video encoding device 500A of the present invention is used to receive a current macroblock MB1 of a current frame 110, a reference frame and a previous frame 210 For a corresponding macroblock MB2, it is determined whether to encode the current macroblock MB1 or a current residual RSc to generate a formatted bit stream. Wherein, the position of the corresponding giant block MB2 in the previous frame 210 is the same as the position of the current giant block MB1 in the current frame 110. The same elements in Figures 1A, 2, 3A, and 4 are not described here.

The motion estimation unit 510 compares the current giant block MB1 with a preset search range stored in the reference frame of the reference buffer 310 to generate a current motion vector that best matches the giant block in the reference frame MVc, and subtract the best matching giant block from the current giant block MB1 to generate a current residual RSc. The motion estimation unit 510 transmits the current motion vector MVc of the current giant block MB1 to the bit stream formatting unit 130c, and transmits the current residual RSc of the current giant block MB1 to the type selector 320 '. The function of the type selector 320' is similar to that of the type selector 320. Referring to FIG. 3C, the type selector 320' includes a summing unit 321, an absolute summing unit 322, a comparator 324, and a multiplexer 325. In one embodiment, the signal Md has a logic value 1 indicating that the current giant block MB1 is an I giant block, that is, s1<s2; and the signal Md has a logic value 0 indicating that the current giant block MB1 is a P The giant block, that is, s1>s2. The multiplexer 325 outputs one of the current giant block MB1 and the current residual RSc according to the signal Md. If the signal Md has a logic value of 1 (representing that the current giant block MB1 is an I giant block), the multiplexer 325 outputs the current giant block MB1 to the encoder 120, otherwise the multiplexer 325 outputs the The current residual RSc is sent to the encoder 120.

Returning to FIG. 5A, please note that in addition to setting the skip flag and the type flag, the bit stream formatting unit 130c adds the type flag and the skip flag together with or excludes the current movement The vector MVc and the encoded bit stream are merged into the formatted bit stream. In one embodiment, if the signal Md has a logic value of 1 (representing that the current giant block MB1 is an I giant block), the bit stream formatting unit 130c combines the type flag and the skip flag together with Or exclude the encoded bit stream (excluding the current motion vector MVc) into the formatted bit stream; otherwise, if the signal Md has a logical value of 0 (representing that the current giant block MB1 is a P giant block), The bit stream formatting unit 130c incorporates the type flag, the skip flag, and the current motion vector MVc together with or excludes the coded bit stream into the formatted bit stream.

FIG. 5B is a block diagram showing a video encoding device according to another embodiment of the present invention. Referring to FIG. 5B, the video encoding device 500A of the present invention operates in the IPP mode and includes an encoder 120, a bit stream formatting unit 130c, a symptom storage device 140, a similarity check circuit 150a, and a skip decision Unit 160b, a QP storage device 170, a symptom generator 180, a reference buffer 310, a type selector 320', an update controller 330, a motion estimation unit 510 and a decoder 630. The video encoding device 500B of the present invention is used to receive a current macroblock MB1 of a current frame 110 and a reference frame to determine whether to encode the current macroblock MB1 or a current residual RSc to generate a formatted bit stream. The same elements in FIGS. 1A, 2, 3A, 4, and 5A will not be repeated here. Please note that the reference buffer 310 and the The position of the decoder 630 can be exchanged, as shown in FIG. 4.

Please note that although the motion estimation unit 510 is not shown in FIGS. 3A and 4, the video encoding device in FIGS. 3A and 4 can be regarded as the current motion vector MVc in FIGS. 5A-5B equal to 0 and the motion estimation unit Two special examples of 510 working together. Accordingly, the huge difference blocks (MB1-MB3) output from the type selector 320 are also a special example of outputting the current residual RSc from the type selector 320'. This is because when the current motion vector MVc in FIGS. 5A-5B is equal to 0, the current giant block MB1 and the corresponding giant block MB3 must be located at the same position of the current frame 110 and the reference frame, respectively.

FIG. 6 is a block diagram showing a video decoding device according to an embodiment of the present invention. The video decoding device (600, 700, 800, 900) of the present invention is used to receive a formatted bit stream from a receiver 1050 and generate video reconstruction data for use in a display 1070 (please refer to FIG. 10). Specifically, the video decoding device 600/700 divides the formatted bit stream into an encoded bit stream and a skip flag, and buffers the encoded bit stream and a DRAM according to the skip flag The device 612 (stores a reference frame in the format of a bit stream or reconstruction data) reconstructs a current giant block. Referring to FIG. 6, the video decoding device 600 of the present invention operates in the I-I-I mode and includes a storage and selection output circuit 610, a syntax analyzer 620a, and a decoder 630. The parser 620a parses a formatted bit stream from a receiver 1050, and divides the formatted bit stream into a coded bit stream and a Skip the flag. The decoder 630 includes an entropy decoder 631, an inverse quantizer 632, and an inverse conversion unit 633. The entropy decoder 631 receives the encoded bit stream and decodes the encoded bit stream into quantized conversion data, and the inverse quantizer 632 performs inverse quantization on the quantized conversion data to generate inverse quantized conversion data. The inverse conversion unit 633 inversely converts the inverse quantized conversion data to generate the current reconstruction data.

The storage and selection output circuit 610 includes an output controller 611, a DRAM 612, and a multiplexer 613. The DRAM 612 stores a reconstruction data of a reference frame. The skip flag is used as the control signal of the output controller 611 and the multiplexer 613. In an embodiment, if the skip flag has a logic value of 1 (representing that the current giant block MB1 is skipped), the output controller 611 is disabled without outputting any data, and the multiplexer 613 is based on the At present, the macroblock MB1 is at the position of the current frame 110 and outputs the previously reconstructed data of the reference frame stored in the DRAM 612 as video data; otherwise, if the skip flag has a logical value of 0 (representing the current The giant block MB1 is not skipped), the output controller 611 stores the current reconstruction data from the decoder 630 in the DRAM 612 according to the position of the current giant block MB1 in the current frame 110, and the multiple The tool 613 outputs the current reconstruction data as video data.

FIG. 7 is a block diagram showing a video decoding device according to another embodiment of the present invention. Comparing Figures 6-7, although the video decoding devices 600 and 700 have the same components, the circuit connections are completely different. Specifically, Figure 6 The DRAM 612 of FIG. 7 stores a reconstruction data of a reference frame, and the DRAM 612 of FIG. 7 stores the reference frame in the form of a bit stream. Therefore, compared with the video decoding device 600, the video decoding device 700 saves the bandwidth of the DRAM. The video decoding device 700 operates in I-I-I mode.

FIG. 8 is a block diagram showing a video decoding device according to another embodiment of the present invention. The video decoding device 800/900 of the present invention divides the formatted bit stream into a coded bit stream, a type flag, and a skip flag, and according to the type flag and the skip flag, from the code Bit stream, a reference buffer 812 (storage I block of each frame in bit stream or reconstruction data format) and a difference buffer 811 (storage frame in bit stream or reconstruction data format) At least one of the P giant blocks), rebuild a current giant block. Referring to FIG. 8, the video decoding device 800 of the present invention operates in the I-P-P mode and includes two decoders 630 and 630a, a storage and selection output circuit 810, an adder 830, and a syntax analyzer 620b. The parser 620b parses a formatted bit stream from a receiver 1050, and divides the formatted bit stream into a coded bit stream, a type flag, and a skip flag. The decoder 630a includes all functions of the decoder 630, and the activation of the decoder 630a is controlled by the type flag and the skip flag.

The storage and selection output circuit 810 includes an output controller 813, a source selector 814, a difference buffer 811, and a reference buffer 812. The skip flag and the type flag are regarded as the output controller 813, The source selector 814 and the control signal of the decoder 630a. In response to skipping the flag and the type flag, the output controller 813 determines whether to transmit the encoded bit stream to one of the difference buffer 811 and the reference buffer 812, and the source selector 814 determines whether to transmit One of the encoded bit stream and the previous difference bit stream reaches the decoder 630, and the decoder 630a determines whether to decode the reference bit stream as reference reconstruction data. In one embodiment, if the skip flag has a logical value of 1 (representing that the current giant block MB1 is skipped) and the type flag has a logical value of 1 (representing that the current giant block MB1 is an I giant block) , The output controller 813 and the source selector 814 are disabled without outputting any data, and the decoder 630a is enabled to obtain the reference from the reference according to the position of the current giant block MB1 in the current frame 110 The reference bit stream of the buffer 812 is decoded into reference reconstruction data; finally, the adder 830 outputs the reference reconstruction data as video data. If the skip flag has a logic value of 0 (indicating that the current giant block MB1 has not been skipped) and the type flag has a logic value of 1 (indicating that the current giant block MB1 is an I giant block), the output control The transmitter 813 transmits the coded bit stream to the reference buffer 812 and stores the coded bit stream to the reference buffer 812 according to the position of the current macroblock MB1 in the current frame 110; the decoder 630a is Disabled, and the source selector 814 transmits the encoded bit stream to the decoder 630; the decoder 630 decodes the encoded bit stream into reference reconstruction data; finally, the adder 830 outputs the reference reconstruction data as Video data. If the skip flag has a logic value of 1 and the type flag has a logic value of 0 (representing that the current giant block MB1 is P giant block), the output controller 813 is disabled without outputting any data; the decoder 630a is enabled to come from the reference buffer according to the position of the current giant block MB1 in the current frame 110 The reference bit stream of 812 is decoded as reference reconstruction data; the source selector 814 (based on the position of the current macroblock MB1 in the current frame 110) transmits the previous difference bit stream from the difference buffer 811 To the decoder 630; the decoder 630 decodes the previous difference bit stream into the previous difference difference data; finally, the adder 830 adds the previous difference data and the reference reconstruction data as video data . If the skip flag has a logic value of 0 and the type flag has a logic value of 0, the output controller 813 transmits the encoded bit stream to the difference buffer 811 and based on the current giant block MB1 in the current map The position of block 110 stores the encoding bit device into the difference buffer 811; the decoder 630a is enabled to come from the reference buffer according to the position of the current macroblock MB1 in the current frame 110 The reference bit stream of 812 is decoded into reference reconstruction data; the source selector 814 transmits the encoded bit stream to the decoder 630; the decoder 630 decodes the encoded bit stream into the current difference data; finally, the The adder 830 adds the current difference data and the reference reconstruction data as video data.

FIG. 9 is a block diagram showing a video decoding device according to another embodiment of the present invention. Referring to FIG. 9, the video decoding device 900 of the present invention operates in the I-P-P mode and includes a decoder 630, a storage and selection output circuit 910, an adder 830, and a syntax analyzer 620b. Comparing Figures 8-9, the video decoding devices 800, 900 have similar components, but the circuit connection is complete It's different. Specifically, the difference buffer 811 and the reference buffer 812 of FIG. 8 store encoded bit streams, and the difference buffer 811 and the reference buffer 812 of FIG. 9 store reconstruction data. Therefore, compared to the video decoding device 900, the video decoding device 800 saves memory bandwidth.

The decoder 630 decodes the encoded bit stream from the parser 620b into decoded data. The storage and selection output circuit 910 includes an output controller 813, a source selector 814, a difference buffer 811, a data extraction unit 911, and a reference buffer 812. The skip flag and the type flag are used as control signals of the output controller 813, the source selector 814, and the data extraction unit 911.

In response to skipping the flag and the type flag, the output controller 813 determines whether to transmit the decoded data to one of the difference buffer 811 and the reference buffer 812, and the source selector 814 determines whether to transmit the decode One of the data and the previous difference data is sent to the adder 830, and the data extraction unit 911 determines whether to send the reference data to the adder 830. In one embodiment, if the skip flag has a logical value of 1 (representing that the current giant block MB1 is skipped) and the type flag has a logical value of 1 (representing that the current giant block MB1 is an I giant block) , The output controller 813 and the source selector 814 are disabled without outputting any data, and the data extraction unit 911 transmits the reference data from the reference buffer 812 (according to the current giant block MB1 in the current The position of the frame 110) is given to the adder 830; finally, the adder 830 outputs the reference data as video data. If you should skip the flag There is a logical value of 0 (indicating that the current macroblock MB1 has not been skipped) and the type flag has a logical value of 1, the output controller 813 sends the decoded data to the reference buffer 812 and according to the current macroblock MB1 At the position of the current frame 110, the decoded data is stored in the reference buffer 812; the source selector 814 sends the decoded data to the adder 830; finally, the adder 830 outputs the decoded data as video data . If the skip flag has a logic value of 1 and the type flag has a logic value of 0 (representing that the current giant block MB1 is a P giant block), the output controller 813 is disabled without outputting any data; the data The extraction unit 911 is enabled to transmit the reference data from the reference buffer 812 to the adder 830 according to the position of the current macroblock MB1 in the current frame 110; the source selector 814 (based on the At present, the macroblock MB1 is at the position of the current frame 110) to send the previous difference data from the difference buffer 811 to the adder 830; finally, the adder 830 adds the previous difference data and the reference data Treat as video data. If the skip flag has a logic value of 0 and the type flag has a logic value of 0, the output controller 813 sends the decoded data to the difference buffer 811 and based on the current giant block MB1 in the current frame 110 The decoded data is stored in the difference buffer 811; the source selector 814 sends the decoded data to the adder 830; the data extraction unit 911 is enabled based on the current giant block MB1 in the At the current position of the frame 110, the reference data from the reference buffer 812 is sent to the adder 830; finally, the adder 830 adds the decoded data and the reference data as video data.

FIG. 10 is a block diagram showing a video transmission system with a skip mechanism according to an embodiment of the present invention. Referring to FIG. 10, the video transmission system 1000 of the present invention with a skip mechanism includes a video encoding device 1020, a transmitter 1030, a communication channel 1040, a receiver 1050, and a video decoding device 1060. An image source 1010 provides a series of video frames to the video encoding device 1020, and each video frame includes a plurality of processing blocks. The video encoding device 1020 encodes each processing block into a formatted bit stream, and then sends the formatted bit stream to the transmitter 1030. The transmitter 1030 converts the formatted bit stream into a plurality of data packets, and then transmits the data packets to the receiver 1050 through the communication channel 1040. The communication channel 1040 is a network channel, which communicates the transmitter 1030 and the receiver 1050 by exchanging packets. The receiver 1050 receives data packets from the communication channel 1040, converts the data packets into a formatted bit stream, and then transmits the formatted bit stream to the video decoding device 1060. Next, the video decoding device 1060 decodes the formatted bit stream into video data (reconstructed data), and then displays the video data on the display 1070. Please note that in FIG. 10, although the video encoding device 1020 and the transmitter 1030 are shown separately, they can also be integrated together and operate as a single component. Similarly, the receiver 1050 and the video decoding device 1060 can also be integrated together and operate as a single component.

The video encoding devices 100A/B/C and 200 in Figures 1A~1C and 2 operate in the III mode, while the video encoding devices 300, 400 and 500A/B in Figures 3A, 4 and 5A~5B operate in IPP mode. In Figures 6 to 7 The video decoding devices 600 and 700 operate in the I-I-I mode, and the video decoding devices 800 and 900 in FIGS. 8 and 9 operate in the I-P-P mode. Therefore, when the video transmission system 1000 operates in the III mode, the video encoding device 1020 can be implemented using one of the video encoding devices 100A/B/C and 200, and the video decoding device 1050 can utilize the video decoding devices One of 600 and 700 to implement. When the video transmission system 1000 operates in the IPP mode, the video encoding device 1020 can be implemented using one of the video encoding devices 300, 400, and 500A/B, and the video decoding device 1050 can utilize the video decoding devices 800 and One of 900 to implement.

The above are only preferred embodiments of the present invention, and are not intended to limit the scope of the patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the following application Within the scope of the patent.

100A‧‧‧Video encoding device

110‧‧‧Current frame

120‧‧‧Encoder

121‧‧‧ Conversion unit

122‧‧‧Quantizer

123‧‧‧Entropy encoder

124‧‧‧ Bit rate control unit

130a‧‧‧bit stream formatting unit

140‧‧‧symptom storage device

150a‧‧‧similarity check circuit

160a‧‧‧ skipped the decision unit

170‧‧‧QP storage device

180‧‧‧symptom generator

Claims (14)

A video transmission system is used to transmit a series of frames of video data, each frame includes a plurality of processing blocks, including: a communication channel; a video encoding device, including: a skip decision circuit, according to a block type, A similarity check result and a comparison result of a first quantization parameter of a first processing block in a current frame and a second quantization parameter of a second processing block in a previous frame, generating a control signal; and a The encoder encodes a third processing block to generate a first encoded bit stream and the first quantization parameter, wherein the third processing block is one of the first processing block and a residual; one The transmitter converts a first formatted bit stream into a plurality of data packets and transmits the data packets to the communication channel; a receiver receives the data packets and converts the data packets into a second format Bit stream; a video decoding device including a reference buffer and a difference buffer for dividing the second formatted bit stream into a second encoded bit stream, a second type flag, and a A second skip flag, and according to the second type flag and the second skip flag, from the at least one of the second coded bit stream, the difference buffer and the reference buffer, a reconstruction Fifth processing block: Wherein, the position of the second processing block in the previous frame is the same as the position of the first processing block in the current frame; wherein the video decoding device includes: a parser for The two formatted bit stream is divided into the second encoded bit stream, the second type flag and the second skip flag; a storage and selection output circuit has an input terminal, a first output terminal and a The second output terminal includes: the difference buffer; the reference buffer; and a selective output circuit connected to the reference buffer and the difference buffer, based on the second type flag and the second skip Flag, decide whether to send input data from the input to the reference buffer or one of the difference buffers, decide whether to send part of the difference buffer and one of the input data to the first An output terminal, and determining whether to transfer a part of the content of the reference buffer to the second output terminal; a decoding device, connected to the input terminal or the two output terminals of the storage and selection output circuit; and an adder , Whose first and second input terminals are connected to the first and second output terminals of the storage and selection output circuit or an output terminal of the decoding device; wherein the decoding device is connected to the parser and the storage and selection Between the input terminals of the output circuit, and the first and second input terminals of the adder are connected to the first and second of the storage and selection output circuit, respectively Output; wherein if the second skip flag indicates that the fifth processing block is skipped and the second type flag indicates forward predictive coding, the selection output circuit transmits the portion of the difference buffer to the The first input of the adder and the second input of the reference buffer are transferred to the second input of the adder, wherein if the second skip flag indicates that the fifth processing block is skipped and the The second type flag indicates in-frame coding, and the selection output circuit transmits the part of the reference buffer to the second input terminal of the adder, wherein if the second skip flag indicates that the fifth is not skipped Processing block and the second type flag indicates in-frame coding, the selection output circuit transmits the input data to the first input of the adder and the reference buffer, and wherein if the second skip flag indicates Without omitting the fifth processing block and the second type flag indicating forward predictive coding, the selective output circuit transmits the input data to the first input terminal of the adder and the difference buffer, and the The part of the reference buffer is transferred to the second input of the adder. The system as described in item 1 of the patent application scope, wherein the video encoding device further includes: a bit stream formatting circuit, coupled to the encoder, according to the control signal and the block type, set a first strategy Passing a flag and a first type flag, and determining whether to combine the first encoded bit stream, the first skip flag, and the first type flag as the first formatted bit stream. The system as described in item 2 of the patent application scope, wherein the residual is a difference block between the first processing block and a fourth processing block of a reference frame, and further includes: a type selection circuit, Evaluate the first processing block and the fourth processing block to determine the block type and output the third processing block; and a similarity check circuit, coupled to the skip determination circuit, to calculate the first processing The sum of absolute errors between the block and the second processing block to generate the similarity check result; wherein, the position of the fourth processing block in the reference frame is the same as that of the first processing block The position of the current frame. The system as described in item 2 of the patent application scope, wherein the residual is a difference block between the first processing block and a fourth processing block of a reference frame, and further includes: a type selection circuit, Evaluate the first processing block and the fourth processing block to determine the block type and output the third processing block; a first storage device to store the symptoms of each processing block of each frame; A symptom generator, receiving the first processing block, calculating a current symptom of the first processing block and storing the current symptom in the first storage device; a similarity check circuit, coupled to the strategy Through the decision circuit, the symptom generator and the first storage device, the current symptom of the first processing block is compared with a previous symptom from the second processing block in the first storage device To generate the similarity check result; wherein, the current symptom and the previous symptom are one or a combination of cyclic redundancy check, hash, and check; and wherein the fourth processing block is at the reference The position of the frame is the same as the position of the first processing block in the current frame. According to the system described in item 2 of the patent application scope, the bit stream formatting circuit further decides whether to combine the coded bit stream, a motion vector, the skip flag and the combination of the coded bit stream according to the control signal and the block type The type flag is the formatted bit stream. The system as described in item 5 of the patent application scope, wherein the video encoding device further includes: a motion estimation circuit that estimates the vector of the first processing block relative to a reference frame to generate the motion vector and the residual A type selection circuit that evaluates the first processing block and the residual to determine the block type and outputs the third processing block; and a similarity check circuit, coupled to the skip determination circuit, calculates the The sum of absolute errors between the first processing block and the second processing block to generate the similarity check result. . The system as described in item 5 of the patent application scope, wherein the video encoding device further includes: a motion estimation circuit that estimates the vector of the first processing block relative to a reference frame to generate a motion vector and the residual ; A type selection circuit, evaluating the first processing block and the residual to determine the block type and outputting the third processing block; a first storage device for storing the characteristics of each processing block of each frame A symptom generator, receiving the first processing block, calculating a current symptom of the first processing block and storing the current symptom in the first storage device; a similarity check circuit, coupled to The skip determination circuit, the symptom generator and the first storage device compare the current symptom of the first processing block with a previous symptom from the second processing block in the first storage device, To generate the similarity check result; wherein, the current symptom and the previous symptom are one or a combination of cyclic redundancy check, hash, and checksum. The system as described in item 1 of the patent application scope, wherein if the type flag is forward predictive coding, the similarity check result indicates that the first and second processing blocks are similar and the first quantization parameter is greater than or equal to For the second quantization parameter, the control signal indicates that the third processing block is skipped, otherwise, the control signal indicates that the third processing block is not skipped. The system as described in item 2 of the patent application scope, in which the encoder is controlled by the control signal. The system as described in item 9 of the patent application scope, wherein the skip determination circuit only sends the control signal to the encoder, and the encoder then sends the control signal to the bit stream formatting circuit. The system as described in item 9 of the patent application scope, wherein the skip determination circuit only transmits the control signal to the bit stream formatting circuit and the encoder. The system as described in item 2 of the patent application scope, wherein the skip determination circuit only transmits the control signal to the bit stream formatting circuit. The system as described in item 1 of the patent application scope, wherein the video encoding device further includes: a second storage device, coupled to the encoder and the skip decision circuit, for storing each processing block of each frame Quantization parameters. A video transmission system is used to transmit a series of frames of video data. Each frame includes a plurality of processing blocks, including: a communication channel; a video encoding device, including; a skip decision circuit, according to a block type, A similarity check result and a comparison result of a first quantization parameter of a first processing block in a current frame and a second quantization parameter of a second processing block in a previous frame, generating a control signal; and a The encoder encodes a third processing block to generate a first encoded bit stream and the first quantization parameter, wherein the third processing block is one of the first processing block and a residual; one The transmitter converts a first formatted bit stream into a plurality of data packets and transmits the data packets to the communication channel; a receiver receives the data packets and converts the data packets into a Second formatted bit stream; a video decoding device, including a reference buffer and a difference buffer, for dividing the second formatted bit stream into a second encoded bit stream and a type flag And a skip flag, and according to the type flag and the skip flag, a fifth is reconstructed from at least one of the second coded bit stream, the difference buffer and the reference buffer: where , The position of the second processing block in the previous frame is the same as the position of the first processing block in the current frame; wherein the video decoding device includes: a parser for the second The formatted bit stream is divided into the second encoded bit stream, the type flag, and the skip flag; a storage and selection output circuit having an input terminal, a first output terminal, and a second output terminal, Including: the difference buffer; the reference buffer; and a selection output circuit, connected to the reference buffer and the difference buffer, according to the type flag and the skip flag, decide whether to input data from The input is sent to one of the reference buffer and the difference buffer, to decide whether to transfer part of the difference buffer and one of the input data to the first output, and to decide whether to A part of the content of the reference buffer is transmitted to the second output terminal; a decoding device is connected to the input terminal of the storage and selection output circuit or The two output terminals; and an adder whose first and second input terminals are connected to the first and second output terminals of the storage and selection output circuit or an output terminal of the decoding device; wherein the video decoding device It includes a first decoder and a second decoder, wherein the first decoder is connected between the first output terminal of the storage and selection output circuit and the first input terminal of the adder, and wherein the second The decoder is connected between the second output terminal of the storage and selection output circuit and the second input terminal of the adder; wherein if the skip flag indicates that the fifth processing block is skipped and the type flag indicates Forward predictive coding, the selection output circuit transfers the part of the difference buffer to the first decoder, and the part of the reference buffer to the second decoder, where if it is skipped The flag indicates that the fifth processing block is skipped and the type flag indicates in-frame encoding, the selection output circuit transmits the part of the content of the reference buffer to the second decoder, wherein if the skip flag indicates The fifth processing block is not skipped and the type flag indicates in-frame coding, the selection output circuit transmits the input data to the first decoder and the reference buffer, and if the skip flag indicates not The fifth processing block is skipped and the type flag indicates forward predictive coding, the selection output circuit transmits the input data to the first decoder and the difference buffer, and the part of the reference buffer The content is transferred to the second decoder.

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