CN110430431B - Video decoding method, chip, device, computer equipment and storage medium - Google Patents
Video decoding method, chip, device, computer equipment and storage medium Download PDFInfo
- Publication number
- CN110430431B CN110430431B CN201910555314.0A CN201910555314A CN110430431B CN 110430431 B CN110430431 B CN 110430431B CN 201910555314 A CN201910555314 A CN 201910555314A CN 110430431 B CN110430431 B CN 110430431B
- Authority
- CN
- China
- Prior art keywords
- input channel
- video
- detection result
- target
- output mode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
- H04N19/157—Assigned coding mode, i.e. the coding mode being predefined or preselected to be further used for selection of another element or parameter
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G5/005—Adapting incoming signals to the display format of the display terminal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
- H04N19/136—Incoming video signal characteristics or properties
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
- H04N19/146—Data rate or code amount at the encoder output
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
- H04N19/156—Availability of hardware or computational resources, e.g. encoding based on power-saving criteria
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
- H04N19/184—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being bits, e.g. of the compressed video stream
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/44—Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2370/00—Aspects of data communication
- G09G2370/20—Details of the management of multiple sources of image data
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/436—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
- H04N5/77—Interface circuits between an apparatus for recording and another apparatus between a recording apparatus and a television camera
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Computing Systems (AREA)
- Compression Or Coding Systems Of Tv Signals (AREA)
- Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
Abstract
According to the video decoding method, the chip, the device, the computer equipment and the storage medium, a first detection result is obtained by detecting whether flag bits on a plurality of input channels change or not; and controlling the running state of the functional module of each input channel according to the first detection result, configuring an output mode corresponding to the input channel in the starting state, and starting a target output interface according to the output mode. In the process of video decoding, the operation state of the functional modules of each input channel is controlled according to the first detection result, so that the functional modules of the input channels accessed with the video are in an open state, the functional modules of the input channels not accessed with the video are in a closed state, and the target output interface is selected according to the output mode to output signals.
Description
Technical Field
The present application relates to the field of video processing technologies, and in particular, to a video decoding method, a video decoding chip, a video decoding apparatus, a computer device, and a storage medium.
Background
With the development of video decoding technology, video decoding chips are widely used, and video access to any video system, decoding and outputting to a Central Processing Unit (CPU) for Processing and storage can be realized by using the video decoding chips.
Currently, a video decoding chip includes an equalization module (EQ), a rectification/feedback module (AFE), a backup restoration decoding module (VDP), and a VO module. When the video decoding chip is used for processing the accessed video, the EQ equalization module, the AFE module, the VDP decoding module and the VO module corresponding to each channel are all opened, so that the video decoding chip can decode the accessed analog video signal to output a digital signal, and send the output digital signal to the CPU for processing and storing the video signal.
However, the above video decoding method has a problem of high power consumption.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a video decoding method, apparatus, computer device and storage medium capable of effectively reducing power consumption.
In a first aspect, a method of video decoding, the method comprising:
detecting whether flag bits on a plurality of input channels change or not to obtain a first detection result;
controlling the running state of the functional module of each input channel according to the first detection result, configuring an output mode corresponding to the input channel in the starting state, and starting a target output interface according to the output mode; the operation state comprises an opening state and a closing state; the functional module is used for decoding the accessed video on the input channel.
In one embodiment, controlling the operating state of the functional module of each input channel according to the first detection result, configuring an output mode corresponding to the input channel in the enabled state, and enabling the target output interface according to the output mode includes:
if the first detection result is that the input channel with the changed zone bit exists, determining the input channel corresponding to the changed zone bit as a target input channel;
and controlling the running state of a functional module on the target input channel to be changed into an open state, configuring an output mode corresponding to the target input channel according to the video format of the access video on the target channel, and opening a target output interface corresponding to the output mode.
In one embodiment, the method further comprises:
detecting whether a video system of an access video on a target input channel changes to obtain a second detection result, and detecting whether a zone bit of the target input channel changes to obtain a third detection result;
and controlling the running state of the functional module of the target input channel and the output mode corresponding to the target input channel according to the second detection result and the third detection result.
In one embodiment, controlling the operating state of the functional module of the target input channel and the output mode corresponding to the target input channel according to the second detection result and the third detection result includes:
and if the second detection result is that the video system of the accessed video on the target channel is changed and the third detection result is that the zone bit on the target input channel is changed, controlling the running state of the functional module on the target input channel to be kept in an open state, configuring a new output mode corresponding to the target input channel according to the new video system, and opening a target output interface corresponding to the new output mode.
In one embodiment, the controlling the operating state of the functional module of the target input channel and the output mode corresponding to the target input channel according to the second detection result and the third detection result includes:
and if the second detection result is that the video system of the video accessed on the target channel is changed and the third detection result is that the zone bit on the target input channel is not changed, configuring a new output mode corresponding to the target input channel according to the new video system, and starting a target output interface corresponding to the new output mode.
In one embodiment, controlling the operating state of the functional module of the target input channel and the output mode corresponding to the target input channel according to the second detection result and the third detection result includes:
and if the second detection result is that the video system of the video accessed on the target channel is not changed and the third detection result is that the flag bit on the target input channel is changed, controlling the running state of the functional module on the target input channel to be kept in an open state, configuring a new output mode corresponding to the target input channel according to the new video system, and opening a target output interface corresponding to the new output mode.
In one embodiment, controlling the operating state of the functional module of the target input channel and the output mode corresponding to the target input channel according to the second detection result and the third detection result includes:
and if the second detection result is that the video system of the accessed video on the target channel is not changed and the third detection result is that the zone bit on the target input channel is not changed, returning to execute the steps of detecting whether the video system of the accessed video on the target input channel is changed or not to obtain the second detection result and detecting whether the zone bit of the target input channel is changed or not to obtain the third detection result.
In one embodiment, the video format includes a data amount of the video and a resolution of the video.
In a second aspect, a video decoding chip is configured to perform the video decoding method of any embodiment of the first aspect.
In a third aspect, a video decoding apparatus, the apparatus comprising:
the first detection module is used for detecting whether flag bits on the plurality of input channels change or not to obtain a first detection result;
the configuration module is used for controlling the running state of the functional module of each input channel according to the first detection result, configuring an output mode corresponding to the input channel in an open state, and opening a target output interface according to the output mode; the operation state comprises an opening state and a closing state; the functional module is used for decoding the access video on the input channel.
In one embodiment, the configuration module includes:
the determining unit is used for determining the input channel corresponding to the changed zone bit as a target input channel when the first detection result indicates that the input channel with the changed zone bit exists;
and the control unit is used for controlling the running state of the functional module on the target input channel to be changed into an opening state, configuring an output mode corresponding to the target input channel according to the video format of the access video on the target channel, and opening a target output interface corresponding to the output mode.
In one embodiment, the video decoding apparatus further includes:
the second detection module is used for detecting whether a video system of an access video on the target input channel changes to obtain a second detection result, and detecting whether a zone bit of the target input channel changes to obtain a third detection result;
and the control module is used for controlling the running state of the functional module of the target input channel and the output mode corresponding to the target input channel according to the second detection result and the third detection result.
In an embodiment, the control module is specifically configured to, when the second detection result is that a video format of an access video on the target channel changes, and the third detection result is that a flag bit on the target input channel changes, control an operating state of a functional module on the target input channel to be kept in an on state, configure a new output mode corresponding to the target input channel according to the new video format, and open a target output interface corresponding to the new output mode.
In an embodiment, the control module is further specifically configured to configure a new output mode corresponding to the target input channel according to a new video format when the second detection result indicates that a video format of the video accessed to the target channel changes, and the third detection result indicates that a flag bit on the target input channel does not change, and start a target output interface corresponding to the new output mode.
In an embodiment, the control module is further specifically configured to, when the second detection result indicates that a video format of a video accessed to the target channel has not changed and the third detection result indicates that a flag bit on the target input channel has changed, control an operating state of a function module on the target input channel to be kept in an on state, configure a new output mode corresponding to the target input channel according to the new video format, and open a target output interface corresponding to the new output mode.
In an embodiment, the control module is further specifically configured to, when the second detection result indicates that the video format of the video accessed to the target channel has not changed and the third detection result indicates that the flag bit on the target input channel has not changed, return to the step of detecting whether the video format of the video accessed to the target input channel has changed to obtain the second detection result and detecting whether the flag bit of the target input channel has changed to obtain the third detection result.
In one embodiment, the video format includes a data size of the video and a resolution of the video.
In a fourth aspect, a computer device comprises a memory and a processor, the memory stores a computer program, and the processor implements the video decoding method according to any of the embodiments of the first aspect when executing the computer program.
In a fifth aspect, a computer-readable storage medium has stored thereon a computer program which, when executed by a processor, implements the video decoding method of any of the embodiments of the first aspect.
According to the video decoding method, the chip, the device, the computer equipment and the storage medium, a first detection result is obtained by detecting whether flag bits on a plurality of input channels change or not; and controlling the running state of the functional module of each input channel according to the first detection result, configuring an output mode corresponding to the input channel in the starting state, and starting a target output interface according to the output mode. In the process of video decoding, the running state of the functional modules of each input channel is controlled according to the first detection result, so that the functional modules of the input channels accessed to the video are in the open state, and the functional modules of the input channels not accessed to the video are in the closed state. In addition, in the video decoding process of the scheme, the output mode is configured according to the video system of the accessed video, so that the target output interface is selected to output signals according to the output mode.
Drawings
FIG. 1 is a diagram illustrating an application scenario provided by an embodiment;
fig. 2 is a flowchart of a video decoding method according to an embodiment;
FIG. 3 is a flow chart of another implementation of S102 in the embodiment of FIG. 2;
fig. 4 is a flowchart of a video decoding method according to an embodiment;
FIG. 5 is a block diagram illustrating an exemplary configuration mode;
FIG. 6 is a block diagram illustrating an exemplary configuration mode;
fig. 7 is a flowchart of a video decoding method according to an embodiment;
fig. 8 is a schematic structural diagram of a video decoding apparatus according to an embodiment;
fig. 9 is a schematic structural diagram of a video decoding apparatus according to an embodiment;
fig. 10 is a schematic structural diagram of a video decoding apparatus according to an embodiment;
fig. 11 is a schematic internal structural diagram of a computer device according to an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The video decoding method provided by the application can be applied to the application environment shown in fig. 1. The video decoding chip is connected with the terminal through a bus, and is used for receiving an external analog video source signal, decoding the analog video source signal to obtain a decoded digital video signal, and transmitting the digital video signal to the terminal through the bus for storage or processing. The Video decoding chip can be disposed in, but not limited to, a Digital Video Recorder (DVR), a Network Video Recorder (DVD), and other devices. The terminal may be, but is not limited to, various personal computers, notebook computers, smart phones, tablet computers, and portable wearable devices.
The following describes in detail the technical solutions of the present application and how the technical solutions of the present application solve the above technical problems by embodiments and with reference to the drawings. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Fig. 2 is a flowchart of a video decoding method according to an embodiment, where the main execution body of the method is the video decoding chip in fig. 1, and the method relates to a process in which the video decoding chip decodes an accessed analog video signal and outputs a digital video signal. As shown in fig. 2, the method includes:
s101, detecting whether flag bits on a plurality of input channels change or not to obtain a first detection result.
The input channel is used for accessing an external analog video signal to the video decoding chip and decoding the accessed analog video signal. A video decoding chip may contain multiple input channels. The input channel may include an input interface for accessing a video signal, and various functional devices for decoding, such as an equalization module (EQ), a rectification/feedback module (AFE), a backup restoration decoding module (VDP), and so on. The flag is used to indicate whether the video decoding chip accesses an external analog video signal, and may be represented by letters, numbers, symbols, serial numbers, and the like, which is not limited in this embodiment. For example, the flag bit of the input channel may be set to 0 at the time of initialization of the video decoding chip. The first detection result represents the change condition of the zone bit on each input channel on the video decoding chip, and can represent that the input channel with the changed zone bit exists on the video decoding chip, which is equivalent to that the video decoding chip has video access; it can also indicate that there is no input channel with changed flag bit on the video decoding chip, which is equivalent to no video access on the video decoding chip.
In practical application, after a video decoding chip is powered on, whether flag bits on input channels on the video decoding chip are changed or not is immediately detected, whether video access exists or not is checked, a first detection result is obtained, and then the next working flow is started according to the first detection result.
S102, controlling the running state of the functional module of each input channel according to the first detection result, configuring an output mode corresponding to the input channel in the starting state, and starting a target output interface according to the output mode; the operation state comprises an opening state and a closing state; the functional module is used for decoding the accessed video on the input channel.
The functional modules in this embodiment specifically include, but are not limited to, an EQ equalization module, an AFE module, and a VDP decoding module. Each input channel corresponds to a respective EQ equalization module, AFE module and VDP decoding module, and is used for decoding the respective accessed analog video signal. The target output interface represents an output interface which needs to output a digital video signal, the number of the target output interfaces can be determined according to the output mode, one target output interface needs to be configured in some output modes, and a plurality of target output interfaces need to be configured in some output modes.
After the video decoding chip obtains the first detection result, the operation state of the functional module of each input channel on the video decoding chip can be further controlled according to the indication of the first detection result, so that the functional module which needs to execute the function is opened, and the functional module which does not need to execute the function is closed. In addition, the video decoding chip can further configure a corresponding output mode for the input channel in the on state, so that a signal output by the input channel in the on state after decoding the access video signal can be output to the outside of the video coding chip through a corresponding output interface. Therefore, after the video decoding chip configures the output mode of the input channel, the target output interface which needs to output signals can be started according to the output mode.
It should be noted that, in practical application, there are multiple application scenarios, one of which is: in this case, after the video decoding chip obtains the first detection result, the functional module of the input channel required to be used is controlled to be in an open state, and correspondingly, the output interface required to be used is controlled to be in an open state according to the output mode corresponding to the input channel.
The other is as follows: after the video decoding chip is powered on, the functional modules and the output interfaces of the input channels on the video decoding chip are both in an open state, or some functional modules of the input channels are in an open state, some functional modules of the input channels are in a closed state, or some output interfaces are in an open state, and some output interfaces are in a closed state. In this case, after the video decoding chip obtains the first detection result, the functional module of the input channel that needs to be used is controlled to be in an open state, the functional module of the input channel that does not need to be used is controlled to be in a closed state, and correspondingly, the output interface that needs to be used is controlled to be in an open state according to the output mode corresponding to the open input channel, and the output interface that does not need to be used is controlled to be in a closed state. For the description of the two cases, the initial settings of the video decoding chips are different, the initial operating states of the functional modules and the output interfaces on the corresponding video decoding chips are different, and no matter which setting does not affect the implementation of the scheme, the setting is within the protection range of the scheme, and the embodiment is not limited.
In the above embodiment, a first detection result is obtained by detecting whether flag bits on a plurality of input channels change; and controlling the running state of the functional module of each input channel according to the first detection result, configuring an output mode corresponding to the input channel in the starting state, and starting a target output interface according to the output mode. In the process of video decoding, the running state of the functional modules of each input channel is controlled according to the first detection result, so that the functional modules of the input channels accessed to the video are in the open state, and the functional modules of the input channels not accessed to the video are in the closed state. In addition, in the video decoding process of the scheme, the output mode is configured according to the video system of the accessed video, so that the target output interface is selected according to the output mode.
Fig. 3 is a flowchart of another implementation manner of S102 in the embodiment of fig. 2, where as shown in fig. 3, the step S102 "controls an operation state of a functional module of each input channel according to a first detection result, configures an output mode corresponding to an input channel in an on state, and turns on a target output interface according to the output mode" includes:
s301, if the first detection result is that the input channel with the changed zone bit exists, determining the input channel corresponding to the changed zone bit as a target input channel.
The present embodiment relates to a case where the first detection result is that there is an input channel with a changed flag bit, which indicates that there is video signal access on one or more input channels on the video decoding chip, and at this time, the video decoding chip is required to receive the video signal access on the input channel, so as to perform decoding operation on the accessed video signal later. In this embodiment, when the video decoding chip detects an input channel with a changed flag bit, the input channel is determined as a target input channel, so that the video decoding chip processes a video signal on the target input channel.
S302, controlling the operation state of the functional module on the target input channel to be changed into an open state, configuring an output mode corresponding to the target input channel according to the video system of the access video on the target channel, and opening a target output interface corresponding to the output mode.
The video format is used to represent performance parameters of a video signal accessed by the video decoding chip, and for example, the video format may include parameters such as a data amount of the video signal, a resolution of the video signal, and a frequency of the video signal. The target output interface is used for representing an output interface used by the video decoding chip.
When the video decoding chip determines that the video signal is accessed to the target input channel, all the functional modules on the target input channel can be simultaneously started, so that all the functional modules on the target input channel can work normally, the decoding operation of the video signal accessed to the target input channel is executed, and when the video decoding chip needs to output the decoded digital video signal after decoding, the output mode corresponding to the target input channel can be further configured according to the video format of the accessed video, and the corresponding output interface is started according to the output mode, so that the digital video signal output by the target input channel can be output to the outside of the video decoding chip through the corresponding output interface.
In an application scenario, when the video decoding chip controls the functional modules of the input channels to operate normally, the plugging and unplugging condition of the video decoding chip and the input cable and the change condition of the video decoding chip to the video system of the access video are often required to be detected at any time. Therefore, the present application further provides a video decoding method to adapt to the application environment, as shown in fig. 4, the method includes:
s401, detecting whether a video system of an access video on a target input channel changes to obtain a second detection result, and detecting whether a zone bit of the target input channel changes to obtain a third detection result.
The second detection result represents a change situation of a video format of the access video on the target input channel, which may represent that the video format is changed or that the video format is not changed. The third detection result indicates a change of the flag bit of the target input channel, which may indicate that the flag bit of the target input channel changes or that the flag bit of the target input channel does not change.
S402, controlling the running state of the functional module of the target input channel and the output mode corresponding to the target input channel according to the second detection result and the third detection result.
When the video decoding chip executes step S401 to obtain the second detection result and the third detection result, the functional module of the target input channel may be controlled to be in an on state or an off state according to the indication of the second detection result and the third detection result, and an output mode corresponding to the target input channel may be configured, so as to control the target output interface selected according to the output mode to be in the on state, or control the output interface not selected according to the output mode to be in the off state.
In the above embodiment, the video decoding chip controls the running state of the functional module of the target input channel and the output mode corresponding to the target input channel through the cooperation of the second detection result and the third detection result, so that the flexible configuration process is realized, the used functional module and the output interface are in the on state, and the unused functional module and the output interface are in the off state, so that the power consumption of the video decoding chip is greatly reduced, and the service life of the video decoding chip is prolonged.
Based on the above embodiment, in the above S402, "controlling the operation state of the functional module of the target input channel and the output mode corresponding to the target input channel according to the second detection result and the third detection result" may have the following four implementation manners:
a first implementation, comprising:
and if the second detection result is that the video system of the accessed video on the target channel is changed and the third detection result is that the zone bit on the target input channel is changed, controlling the running state of the functional module on the target input channel to be kept in an open state, configuring a new output mode corresponding to the target input channel according to the new video system, and opening a target output interface corresponding to the new output mode.
The first implementation manner relates to a situation that a video format of an access video on a target channel changes and a flag bit on a target input channel changes, which indicates that an input cable connected to the target input channel is plugged again in and unplugged from the target input channel, a new video signal is accessed to the target input channel, and after the input cable is plugged again, the input channel corresponding to the input cable is automatically powered off. Therefore, in the face of the above situation, the video decoding chip may correspondingly control the running state of the functional module on the target input channel to be re-started, so that each functional module is in a started state, and after the video format of the newly-accessed video is determined, a new output mode corresponding to the target input channel is configured according to the new video format, and then a corresponding target output interface is determined to be started according to the new output mode, so as to output the encoded digital video signal through the target output interface.
A second implementation, comprising:
and if the second detection result is that the video system of the video accessed on the target channel is changed and the third detection result is that the zone bit on the target input channel is not changed, configuring a new output mode corresponding to the target input channel according to the new video system, and starting a target output interface corresponding to the new output mode.
The second implementation manner relates to a situation that a video format of an accessed video on a target channel changes and a flag bit on a target input channel does not change, which means that in practical application, when a functional module of the target input channel decodes a video accessed on the input channel, the video format of the accessed video is changed according to application requirements, for example, the input channel compresses a data amount of the accessed video to obtain a video signal with the changed data amount. Therefore, in the above situation, the video decoding chip configures a new output mode corresponding to the target input channel according to the changed video format, i.e., the new video format, and then determines to open the corresponding target output interface according to the new output mode, so as to output the encoded digital video signal through the target output interface.
A third implementation, comprising:
and if the second detection result is that the video system of the video accessed on the target channel is not changed and the third detection result is that the flag bit on the target input channel is changed, controlling the running state of the functional module on the target input channel to be kept in an open state, configuring a new output mode corresponding to the target input channel according to the new video system, and opening a target output interface corresponding to the new output mode.
The third implementation manner relates to a situation that a video format of an access video on a target channel is not changed and a flag bit on a target input channel is changed, which indicates that an input cable connected with the target input channel is not plugged again in and out in practical application and works normally, but a video source is changed, so that the input channel is accessed with a new video signal again. Therefore, in the face of the above situation, the video decoding chip correspondingly controls the operating state of the functional module on the target input channel to be kept in the on state, so that each functional module works normally, a new output mode corresponding to the target input channel is configured according to a new video format, and then a corresponding target output interface is determined to be turned on according to the new output mode, so as to output the encoded digital video signal through the target output interface.
A fourth implementation, comprising:
and if the second detection result is that the video system of the accessed video on the target channel is not changed and the third detection result is that the zone bit on the target input channel is not changed, returning to execute the steps of detecting whether the video system of the accessed video on the target input channel is changed or not to obtain the second detection result and detecting whether the zone bit of the target input channel is changed or not to obtain the third detection result.
The fourth implementation manner relates to a case that a video format of an access video on a target channel is not changed and a flag bit on a target input channel is not changed, which indicates that an input cable connected with the target input channel is not plugged again in practical application, and the target input channel is normally operated and does not access a new video signal. Therefore, in the above situation, the video decoding chip will return to the step of S401 to continue to control the operation state of the functional module of the target input channel and the output mode corresponding to the target input channel according to the second detection result and the third detection result.
In one embodiment, the video format of the access video referred to in any of the above embodiments includes the data volume of the video and the resolution of the video. As is apparent from the foregoing description, different output modes are configured according to different video formats, and the configuration method described above is exemplified below.
Example 1: assuming that there is an accessed video on channel 1 of the video decoding chip, the data size of the video included in the video format of the video is 4M or 4K, and the resolution of the video is less than or equal to 720p, the corresponding output interface can be selectively turned on according to the mode shown in fig. 5. In this example, the input channel 1 of the video decoding chip is in an on state, the output interface VO1 corresponding to the input channel 1 is in an on state, and the V02-V04 output interfaces are in an off state.
Example 2: assuming that there is an accessed video on the channel 1 of the video decoding chip, the data volume of the video included in the video format of the video is 4M or 4K, and the resolution of the video is less than or equal to 1080p, the corresponding output interface can be selectively turned on according to the mode shown in fig. 6. In this example, input channel 1 of the video decoding chip is in an on state, VO1-V02 output interfaces corresponding to the input channel 1 are in an on state, and V03-V04 output interfaces are in an off state.
Example 3: assuming that there is an accessed video on the channel 1 of the video decoding chip, the data amount of the video included in the video format of the video is less than or equal to 4K, and the resolution of the video is any resolution, the corresponding output interface can be selectively turned on according to the mode shown in fig. 5. In this example, input channel 1 of the video decoding chip is in an on state, the VO1 output interface corresponding to the input channel 1 is in an on state, and the V02-V04 output interface is in an off state.
The above is merely an example, and many configuration modes may exist, and this embodiment is not limited as long as the output mode can be configured according to the video system.
In summary of all the above embodiments, the present application further provides a video decoding method, as shown in fig. 7, the method including:
s501, detecting whether flag bits on a plurality of input channels change or not, if so, executing step S502, and if not, executing step S503.
S502, determining the changed input channel as a target input channel, controlling the running state of a functional module on the target input channel to be changed into an open state, configuring a corresponding output mode according to a video mode of an access video on the target input channel, and opening an output interface corresponding to the output mode.
S503, return to execute S501.
S504, detecting whether the video system of the access video on the target input channel changes, if so, executing step S505, and if not, executing step S506.
And S505, detecting whether the flag bit on the target input channel changes, if so, executing S507, and if not, executing S508.
S506, detecting whether the flag bit on the target input channel changes, if so, executing S507, and if not, executing S509.
And S507, controlling the running state of the functional module on the target input channel to be kept in an opening state, configuring a new output mode corresponding to the target input channel according to the new video system, and opening a target output interface corresponding to the new output mode.
And S508, configuring a new output mode corresponding to the target input channel according to the new video system, and starting a target output interface corresponding to the new output mode.
S509, the process returns to the step of executing S504.
The video decoding method provided in the foregoing embodiment controls the operating state of the functional module of each input channel according to the flag bit of the input channel and the video format of the access video, and configures a corresponding output mode, thereby controlling the operating state of the output interface. The method realizes the flexible configuration of each functional module and the output interface on the video decoding chip, enables the functional module and the output interface to be used to be in an open state, and enables the functional module and the output interface not to be used to be in a closed state, thereby greatly reducing the power consumption required during video coding and further prolonging the service life of the video decoding chip and surrounding devices.
It should be understood that although the various steps in the flow charts of fig. 2-7 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 2-7 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential.
In an embodiment, the present application further provides a video decoding chip, where the video decoding chip is configured to perform the video decoding method described in any of the above embodiments. For a method for decoding an access video by using the video decoding chip, please refer to the contents of the foregoing embodiments, and the description will not be repeated here.
In one embodiment, as shown in fig. 8, there is provided a video decoding apparatus including: a first detection module 11 and a configuration module 12, wherein:
the first detection module 11 is configured to detect whether flag bits on the multiple input channels change, so as to obtain a first detection result;
the configuration module 12 is configured to control an operating state of a functional module of each input channel according to the first detection result, configure an output mode corresponding to an input channel in an open state, and open a target output interface according to the output mode; the operation state comprises an opening state and a closing state; the functional module is used for decoding the access video on the input channel.
In one embodiment, as shown in fig. 9, the configuration module 12 includes:
a determining unit 121, configured to determine, when the first detection result is that there is an input channel with a changed flag bit, the input channel corresponding to the changed flag bit as a target input channel;
a control unit 122, configured to control an operating state of a function module on the target input channel to change to an open state, configure an output mode corresponding to the target input channel according to a video format of an access video on the target channel, and open a target output interface corresponding to the output mode.
In one embodiment, as shown in fig. 10, the video decoding apparatus further includes:
the second detection module 13 is configured to detect whether a video format of an access video on the target input channel changes, to obtain a second detection result, and detect whether a flag bit of the target input channel changes, to obtain a third detection result;
and a control module 14, configured to control an operating state of a functional module of the target input channel and an output mode corresponding to the target input channel according to the second detection result and the third detection result.
In an embodiment, the control module is specifically configured to, when the second detection result is that a video format of an access video on the target channel changes, and the third detection result is that a flag bit on the target input channel changes, control an operating state of a functional module on the target input channel to be kept in an on state, configure a new output mode corresponding to the target input channel according to the new video format, and open a target output interface corresponding to the new output mode.
In an embodiment, the control module is further specifically configured to configure a new output mode corresponding to the target input channel according to a new video format when the second detection result indicates that a video format of the video accessed to the target channel changes, and the third detection result indicates that a flag bit on the target input channel does not change, and start a target output interface corresponding to the new output mode.
In an embodiment, the control module is further specifically configured to, when the second detection result indicates that a video format of a video accessed to the target channel has not changed and the third detection result indicates that a flag bit on the target input channel has changed, control an operating state of a function module on the target input channel to be kept in an on state, configure a new output mode corresponding to the target input channel according to the new video format, and open a target output interface corresponding to the new output mode.
In an embodiment, the control module is further specifically configured to, when the second detection result indicates that the video format of the video accessed to the target channel has not changed and the third detection result indicates that the flag bit on the target input channel has not changed, return to the step of detecting whether the video format of the video accessed to the target input channel has changed to obtain the second detection result and detecting whether the flag bit of the target input channel has changed to obtain the third detection result.
In one embodiment, the video format includes a data size of the video and a resolution of the video.
For specific limitations of the video decoding apparatus, reference may be made to the above limitations of a video decoding method, which are not described herein again. The respective modules in the above video decoding apparatus may be wholly or partially implemented by software, hardware, and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
The video decoding method provided by the application can be applied to the computer equipment shown in FIG. 11. The computer device may be a server, and its internal structure diagram may be as shown in fig. 11. The computer device includes a processor, a memory, a network interface, and a database connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The database of the computer device is used for storing video data. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a video decoding method.
Those skilled in the art will appreciate that the architecture shown in fig. 11 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, a computer device is provided, comprising a memory and a processor, the memory having a computer program stored therein, the processor implementing the following steps when executing the computer program:
detecting whether flag bits on a plurality of input channels change or not to obtain a first detection result;
controlling the running state of the functional module of each input channel according to the first detection result, configuring an output mode corresponding to the input channel in an open state, and opening a target output interface according to the output mode; the operation state comprises an opening state and a closing state; the functional module is used for decoding the access video on the input channel.
The implementation principle and technical effect of the computer device provided by the above embodiment are similar to those of the above method embodiment, and are not described herein again.
In one embodiment, a computer-readable storage medium is provided, having a computer program stored thereon, the computer program, when executed by a processor, further implementing the steps of:
detecting whether flag bits on a plurality of input channels change or not to obtain a first detection result;
controlling the running state of the functional module of each input channel according to the first detection result, configuring an output mode corresponding to the input channel in an open state, and opening a target output interface according to the output mode; the operation state comprises an opening state and a closing state; the functional module is used for decoding the access video on the input channel.
The implementation principle and technical effect of the computer-readable storage medium provided by the above embodiments are similar to those of the above method embodiments, and are not described herein again.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), synchronous Link (Synchlink) DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and bus dynamic RAM (RDRAM).
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (11)
1. A method of video decoding, the method comprising:
detecting whether flag bits on a plurality of input channels change or not to obtain a first detection result;
controlling the running state of the functional module of each input channel according to the first detection result, configuring an output mode corresponding to the input channel in an open state, and opening a target output interface according to the output mode;
the controlling the operating state of the functional module of each input channel according to the first detection result, and configuring an output mode corresponding to the input channel in an open state, wherein opening a target output interface according to the output mode includes:
if the first detection result is that the input channel with the changed zone bit exists, determining the input channel corresponding to the changed zone bit as a target input channel;
controlling the running state of a functional module on the target input channel to be changed into an open state, configuring an output mode corresponding to the target input channel according to a video format of an access video on the target channel, and opening a target output interface corresponding to the output mode;
the operation state comprises an opening state and a closing state; the functional module is used for decoding the access video on the input channel.
2. The method of claim 1, further comprising:
detecting whether a video system of an access video on the target input channel changes to obtain a second detection result, and detecting whether a zone bit of the target input channel changes to obtain a third detection result;
and controlling the running state of the functional module of the target input channel and the output mode corresponding to the target input channel according to the second detection result and the third detection result.
3. The method according to claim 2, wherein controlling the operation state of the functional module of the target input channel and the output mode corresponding to the target input channel according to the second detection result and the third detection result comprises:
if the second detection result is that the video format of the accessed video on the target channel is changed, and the third detection result is that the flag bit on the target input channel is changed, controlling the running state of the functional module on the target input channel to be kept in an open state, configuring a new output mode corresponding to the target input channel according to the new video format, and opening a target output interface corresponding to the new output mode.
4. The method according to claim 2, wherein the controlling the operation state of the functional module of the target input channel and the output mode corresponding to the target input channel according to the second detection result and the third detection result comprises:
and if the second detection result indicates that the video format of the video accessed to the target channel is changed and the third detection result indicates that the flag bit on the target input channel is not changed, configuring a new output mode corresponding to the target input channel according to the new video format, and starting a target output interface corresponding to the new output mode.
5. The method according to claim 2, wherein the controlling the operation state of the functional module of the target input channel and the output mode corresponding to the target input channel according to the second detection result and the third detection result comprises:
if the second detection result indicates that the video format of the video accessed to the target channel is not changed and the third detection result indicates that the flag bit on the target input channel is changed, controlling the running state of the functional module on the target input channel to be kept in an open state, configuring a new output mode corresponding to the target input channel according to the new video format, and opening a target output interface corresponding to the new output mode.
6. The method according to claim 2, wherein the controlling the operation state of the functional module of the target input channel and the output mode corresponding to the target input channel according to the second detection result and the third detection result comprises:
and if the second detection result is that the video system of the accessed video on the target channel is not changed and the third detection result is that the zone bit on the target input channel is not changed, returning to execute the steps of detecting whether the video system of the accessed video on the target input channel is changed or not to obtain a second detection result and detecting whether the zone bit of the target input channel is changed or not to obtain a third detection result.
7. The method according to any one of claims 1 to 6, wherein the video format includes a data amount of the video and a resolution of the video.
8. A video decoding chip, wherein the video decoding chip is configured to perform the video decoding method of claim 7.
9. A video decoding apparatus, characterized in that the apparatus comprises:
the first detection module is used for detecting whether flag bits on the plurality of input channels change or not to obtain a first detection result;
the configuration module is used for controlling the running state of the functional module of each input channel according to the first detection result, configuring an output mode corresponding to the input channel in an open state, and opening a target output interface according to the output mode;
the controlling the operating state of the functional module of each input channel according to the first detection result, and configuring an output mode corresponding to the input channel in an open state, wherein opening a target output interface according to the output mode includes: if the first detection result is that the input channel with the changed zone bit exists, determining the input channel corresponding to the changed zone bit as a target input channel;
controlling the running state of a functional module on the target input channel to be changed into an open state, configuring an output mode corresponding to the target input channel according to a video format of an access video on the target channel, and opening a target output interface corresponding to the output mode;
the operation state comprises an opening state and a closing state; the functional module is used for decoding the access video on the input channel.
10. A computer device comprising a memory and a processor, the memory storing a computer program, wherein the processor implements the steps of the method of any one of claims 1 to 7 when executing the computer program.
11. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 7.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910555314.0A CN110430431B (en) | 2019-06-25 | 2019-06-25 | Video decoding method, chip, device, computer equipment and storage medium |
| EP19934684.2A EP3949408A4 (en) | 2019-06-25 | 2019-12-27 | Systems and methods for video decoding |
| PCT/CN2019/129304 WO2020258805A1 (en) | 2019-06-25 | 2019-12-27 | Systems and methods for video decoding |
| US17/457,921 US20220094944A1 (en) | 2019-06-25 | 2021-12-07 | Systems and methods for video decoding |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910555314.0A CN110430431B (en) | 2019-06-25 | 2019-06-25 | Video decoding method, chip, device, computer equipment and storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110430431A CN110430431A (en) | 2019-11-08 |
| CN110430431B true CN110430431B (en) | 2021-10-22 |
Family
ID=68408637
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910555314.0A Active CN110430431B (en) | 2019-06-25 | 2019-06-25 | Video decoding method, chip, device, computer equipment and storage medium |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US20220094944A1 (en) |
| EP (1) | EP3949408A4 (en) |
| CN (1) | CN110430431B (en) |
| WO (1) | WO2020258805A1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110430431B (en) * | 2019-06-25 | 2021-10-22 | 浙江大华技术股份有限公司 | Video decoding method, chip, device, computer equipment and storage medium |
| CN112860426B (en) * | 2019-11-28 | 2024-03-01 | 杭州海康消防科技有限公司 | Intelligent analysis method, intelligent analysis device, electronic equipment and readable storage medium |
| CN113890771B (en) * | 2021-11-30 | 2022-03-18 | 长芯盛（武汉）科技有限公司 | Device and method for reducing power consumption of active cable |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102075745A (en) * | 2010-12-02 | 2011-05-25 | 北京世纪鼎点软件有限公司 | Device and method for dynamically configuring input and output of video coder-transcoder |
| CN104185027A (en) * | 2014-09-10 | 2014-12-03 | 中航华东光电有限公司 | FPGA-based method for controlling enabling end of coding and decoding chip |
| CN205265822U (en) * | 2016-01-04 | 2016-05-25 | 京东方科技集团股份有限公司 | Image processing system |
| CN105761681A (en) * | 2014-12-18 | 2016-07-13 | 深圳Tcl数字技术有限公司 | Window display method and device of screen |
| CN106534852A (en) * | 2016-11-22 | 2017-03-22 | 浙江大华技术股份有限公司 | Decoding method and apparatus of decoding card |
| CN106657815A (en) * | 2016-09-30 | 2017-05-10 | 南京巨鲨医疗科技有限公司 | Video splicing treatment system and method |
| CN106791551A (en) * | 2016-12-12 | 2017-05-31 | 广东威创视讯科技股份有限公司 | A kind of method of automatic regulating signal source resolution ratio, mosaic screen and system |
| CN108400977A (en) * | 2018-02-07 | 2018-08-14 | 苏州科达科技股份有限公司 | Video data transfers method and device |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4863438B2 (en) * | 2004-09-10 | 2012-01-25 | キヤノン株式会社 | Data processing apparatus and processing method |
| US8270920B2 (en) * | 2008-06-05 | 2012-09-18 | Broadcom Corporation | Systems and methods for receiving and transferring video information |
| JP2013026859A (en) * | 2011-07-21 | 2013-02-04 | Toshiba Corp | Video display device, information reproduction method and information reproduction device |
| CN103096163B (en) * | 2011-11-01 | 2015-12-09 | 中国移动通信集团公司 | The player method of media player and media file |
| JP6031750B2 (en) * | 2011-11-25 | 2016-11-24 | 株式会社リコー | Display control apparatus, image display system, display control method, and program |
| US9565404B2 (en) * | 2012-07-30 | 2017-02-07 | Apple Inc. | Encoding techniques for banding reduction |
| US10368089B2 (en) * | 2013-01-23 | 2019-07-30 | Samsung Electronics Co., Ltd. | Video encoding method and apparatus, and video decoding method and apparatus |
| JP6202330B2 (en) * | 2013-10-15 | 2017-09-27 | ソニー株式会社 | Decoding device and decoding method, and encoding device and encoding method |
| CN104683860B (en) * | 2015-02-02 | 2018-11-30 | 北京神州天脉网络计算机有限公司 | A kind of acoustic-video multi-way concurrently decodes accelerator card and its decoding accelerated method |
| KR102385365B1 (en) * | 2017-07-21 | 2022-04-12 | 삼성전자주식회사 | Electronic device and method for encoding image data in the electronic device |
| CN107948198B (en) * | 2017-12-26 | 2020-11-13 | 北京东土科技股份有限公司 | Stream media safety isolation network gate |
| US10484688B2 (en) * | 2018-01-23 | 2019-11-19 | Aspeed Technology Inc. | Method and apparatus for encoding processing blocks of a frame of a sequence of video frames using skip scheme |
| BR112020025569A2 (en) * | 2018-09-18 | 2021-03-23 | Huawei Technologies Co., Ltd. | video encoder, video decoder and corresponding methods |
| SG11202103023TA (en) * | 2018-11-02 | 2021-04-29 | Sony Corp | Image processing device and image processing method |
| KR20200084516A (en) * | 2019-01-03 | 2020-07-13 | 삼성전자주식회사 | Display apparatus, apparatus for providing image and method of controlling the same |
| CN110430431B (en) * | 2019-06-25 | 2021-10-22 | 浙江大华技术股份有限公司 | Video decoding method, chip, device, computer equipment and storage medium |
-
2019
- 2019-06-25 CN CN201910555314.0A patent/CN110430431B/en active Active
- 2019-12-27 WO PCT/CN2019/129304 patent/WO2020258805A1/en unknown
- 2019-12-27 EP EP19934684.2A patent/EP3949408A4/en active Pending
-
2021
- 2021-12-07 US US17/457,921 patent/US20220094944A1/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102075745A (en) * | 2010-12-02 | 2011-05-25 | 北京世纪鼎点软件有限公司 | Device and method for dynamically configuring input and output of video coder-transcoder |
| CN104185027A (en) * | 2014-09-10 | 2014-12-03 | 中航华东光电有限公司 | FPGA-based method for controlling enabling end of coding and decoding chip |
| CN105761681A (en) * | 2014-12-18 | 2016-07-13 | 深圳Tcl数字技术有限公司 | Window display method and device of screen |
| CN205265822U (en) * | 2016-01-04 | 2016-05-25 | 京东方科技集团股份有限公司 | Image processing system |
| CN106657815A (en) * | 2016-09-30 | 2017-05-10 | 南京巨鲨医疗科技有限公司 | Video splicing treatment system and method |
| CN106534852A (en) * | 2016-11-22 | 2017-03-22 | 浙江大华技术股份有限公司 | Decoding method and apparatus of decoding card |
| CN106791551A (en) * | 2016-12-12 | 2017-05-31 | 广东威创视讯科技股份有限公司 | A kind of method of automatic regulating signal source resolution ratio, mosaic screen and system |
| CN108400977A (en) * | 2018-02-07 | 2018-08-14 | 苏州科达科技股份有限公司 | Video data transfers method and device |
Also Published As
| Publication number | Publication date |
|---|---|
| EP3949408A1 (en) | 2022-02-09 |
| CN110430431A (en) | 2019-11-08 |
| WO2020258805A1 (en) | 2020-12-30 |
| EP3949408A4 (en) | 2022-05-25 |
| US20220094944A1 (en) | 2022-03-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110430431B (en) | Video decoding method, chip, device, computer equipment and storage medium | |
| US10438004B2 (en) | Dual-system electronic apparatus and terminal | |
| US8082374B2 (en) | Information processing apparatus, information processing system, method of processing information, and computer program | |
| US20150065035A1 (en) | Method and apparatus for providing user with information received by electronic device | |
| US20150113355A1 (en) | Data storage device | |
| US20060041611A1 (en) | Data transfer control system, electronic apparatus, and program | |
| US8433886B2 (en) | Nonvolatile memory device including a buffer RAM and boot code management method thereof | |
| CN106372527A (en) | Data processing method and terminal | |
| KR102137686B1 (en) | Method for controlling an content integrity and an electronic device | |
| KR100625811B1 (en) | Method and apparatus for correcting code data error | |
| CN103425539B (en) | Information processing method and device | |
| EP2618259B1 (en) | Data erasable method of memory in smart card and smart card thereof | |
| US11645220B2 (en) | Method and apparatus for multi-bus device fused access | |
| CN110704288B (en) | Information processing method and electronic equipment | |
| CN111475435A (en) | Storage medium sharing method and device, electronic equipment and storage medium | |
| CN107749949B (en) | Camera self-adaption method, camera self-adaption device and electronic equipment | |
| US8341334B2 (en) | Flash memory apparatus and method for operating the same and data storage system | |
| KR102063566B1 (en) | Operating Method For Text Message and Electronic Device supporting the same | |
| KR100743253B1 (en) | Method and apparatus for correcting code data error | |
| CN105404467A (en) | Portable electronic device and user data access method therefor | |
| CN110493185A (en) | Channel stops method, apparatus, computer equipment and storage medium | |
| KR102143521B1 (en) | Non-volatile Memory System, Memory Card Having The Same and Operating Method of Non-volatile Memory System | |
| CN111949103B (en) | Integrated electronic device with data access, transmission and power management and method thereof | |
| CN116340208A (en) | Flash access method and application based on QSPI | |
| KR102165150B1 (en) | Operating Method For Text Message and Electronic Device supporting the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |