TWI686806B - Memory device - Google Patents
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- TWI686806B TWI686806B TW108104790A TW108104790A TWI686806B TW I686806 B TWI686806 B TW I686806B TW 108104790 A TW108104790 A TW 108104790A TW 108104790 A TW108104790 A TW 108104790A TW I686806 B TWI686806 B TW I686806B
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本發明是有關於一種記憶體裝置,且特別是有關於一種利用全域電源線提供高電壓至記憶體區塊之記憶體裝置。 The present invention relates to a memory device, and in particular to a memory device that uses a global power line to provide a high voltage to a memory block.
請參見第1圖,其係三維記憶體結構之示意圖。三維記憶體具有多層的字元墊WLPad,於垂直方向(z方向)上堆疊。字元墊WLPad[k-1]、WLPak[k]與接地選擇層GSL的兩側具有多個指狀結構。此外,平行條狀的串列選擇線SSL[j-1]、SSL[j]、SSL[j+1]則設置在字元線WL對應位置的上方。位元線BL[n]、BL[n+1]除了跨接在串列選擇線SSL[j-1]、SSL[j]、SSL[j+1]的上方外,還會下方以平行z方向延伸。各條位元線BL[n]、BL[n+1]和串列選擇線SSL[j-1]、SSL[j]、SSL[j+1]的交會處為串列選擇電晶體(serial selection transistor,簡稱為SSM),位元線BL[n]、BL[n+1]和字元線WL的交會處為記憶胞電晶體(memory cell,簡稱為MC);位元線BL[n]、BL[n+1]與接地選擇層GSL的交會處為接地選擇電晶體(Ground selection transistor,簡稱為GSM)。在本文中,將平行於串列選擇線SSL的方向定義為x方向;以及,將平行於位元線BL的方向定義為y方向。 Please refer to Figure 1, which is a schematic diagram of a three-dimensional memory structure. The three-dimensional memory has multiple layers of character pads WLPad, which are stacked in the vertical direction (z direction). The character pads WLPad[k-1], WLPak[k] and the ground selection layer GSL have multiple finger structures on both sides. In addition, the parallel strip-shaped tandem selection lines SSL[j-1], SSL[j], and SSL[j+1] are provided above the corresponding positions of the character line WL. The bit lines BL[n], BL[n+1] are not only connected above the serial selection lines SSL[j-1], SSL[j], SSL[j+1], but also parallel to the bottom. Direction extends. The intersection of each bit line BL[n], BL[n+1] and the serial selection line SSL[j-1], SSL[j], SSL[j+1] is a serial selection transistor (serial selection transistor (SSM), the intersection of the bit lines BL[n], BL[n+1] and the word line WL is a memory cell (MC); the bit line BL[n ] The intersection of BL[n+1] and the ground selection layer GSL is a ground selection transistor (Ground selection transistor, GSM for short). Herein, the direction parallel to the serial selection line SSL is defined as the x direction; and the direction parallel to the bit line BL is defined as the y direction.
請參見第2圖,其係三維記憶體結構中的全域字元線GWL與字元墊WLPad之示意圖。在三維記憶體結構中,字元線WL可包含全域字元 線(global word line,簡稱為GWL)GWL[k-1]、GWL[k]、GWL[k+1],以及與記憶體區塊(Block,簡稱為Blk)對應設置的字元墊WLPad[k-1]、WLPad[k]、WLPad[k+1]。其中,字元墊WLPad[k-1]、WLPad[k]、WLPad[k+1]以階梯結構(stair structure)彼此重疊設置,且全域字元線GWL[k-1]、GWL[k]、GWL[k+1]分別電連接至多層字元墊WLPad[k-1]、WLPad[k]、WLPad[k+1]。 Please refer to FIG. 2, which is a schematic diagram of the global character line GWL and the character pad WLPad in the three-dimensional memory structure. In a three-dimensional memory structure, the character line WL may contain global characters Line (global word line, GWL for short) GWL[k-1], GWL[k], GWL[k+1], and the character pad WLPad set corresponding to the memory block (Block, for short Blk) k-1], WLPad[k], WLPad[k+1]. Among them, the character pads WLPad[k-1], WLPad[k], WLPad[k+1] are overlapped with each other in a stair structure, and the global character lines GWL[k-1], GWL[k] , GWL[k+1] are electrically connected to the multi-layer character pads WLPad[k-1], WLPad[k], WLPad[k+1], respectively.
在這些字元線WL中,使用金屬線材的全域字元線GWL[k-1]、GWL[k]、GWL[k+1]的電阻R和電容C甚小,使用多晶矽(poly-silicon)的字元墊WLPad[k-1]、WLPad[k]、WLPad[k+1]的電阻R和電容C較大。因此,對字元線WL而言,其電阻電容延遲(RC delay)主要取決於字元墊WLPad[k-1]、WLPad[k]、WLPad[k+1]的面積。 In these character lines WL, the global character lines GWL[k-1], GWL[k], and GWL[k+1] using metal wires have very small resistance R and capacitance C, and use poly-silicon (poly-silicon) The character pads WLPad[k-1], WLPad[k], WLPad[k+1] have larger resistance R and capacitance C. Therefore, for the word line WL, the resistance capacitance delay (RC delay) mainly depends on the areas of the word pads WLPad[k-1], WLPad[k], and WLPad[k+1].
基於提升記憶體裝置容量的考量,經常需要增加字元墊WLPad[k-1]、WLPad[k]、WLPad[k+1]的層數。基於製程的限制,用於將字元墊WLPad[k-1]、WLPad[k]、WLPad[k+1]連接至字元線WL的階梯結構的尺寸無法隨著字元墊WLPad[k-1]、WLPad[k]、WLPad[k+1]的層數增加而縮小。換言之,隨著字元墊WLPad[k-1]、WLPad[k]、WLPad[k+1]層數的增加,階梯結構所需的面積增加,且字元墊WLPad[k-1]、WLPad[k]、WLPad[k+1]的面積也隨著增加。然而,字元墊WLPad[k-1]、WLPad[k]、WLPad[k+1]的面積越大,字元線WL的電阻電容延遲也越久。在第2圖中,將字元墊的指狀交叉部分定義為區段(segment)10。對字元線WL進行充電時,產生電阻電容延遲的主要來源為兩兩字元墊WLPad[k-1]、WLPad[k]、WLPad[k+1]之間的區段10。換言之,區段10的大小左右字元線WL的電阻電容延遲。 Based on the consideration of increasing the capacity of the memory device, it is often necessary to increase the number of character pads WLPad[k-1], WLPad[k], WLPad[k+1]. Due to process limitations, the size of the ladder structure used to connect the character pads WLPad[k-1], WLPad[k], WLPad[k+1] to the character line WL cannot follow the character pad WLPad[k- 1], WLPad[k], WLPad[k+1] layers increase and shrink. In other words, as the number of layers of character pads WLPad[k-1], WLPad[k], WLPad[k+1] increases, the area required for the ladder structure increases, and the character pads WLPad[k-1], WLPad The area of [k] and WLPad[k+1] also increases. However, the larger the area of the character pads WLPad[k-1], WLPad[k], and WLPad[k+1], the longer the resistance capacitance delay of the word line WL. In FIG. 2, the finger intersecting portion of the character pad is defined as a segment 10. When charging the word line WL, the main source of resistance capacitance delay is the section 10 between the two character pads WLPad[k-1], WLPad[k], WLPad[k+1]. In other words, the resistance of the word line WL is delayed by the size of the segment 10.
請參見第3A、3B圖,其係隨著記憶體容量增加,使字元墊WLPad面積增加,進而使字元墊的電容C與電阻R增加之示意圖。請同時參看第3A、3B圖,第3A圖所示為字元墊層數WLPad較少時,字元墊WLPad的面積與其階梯結構STR1所需佔用的面積都較小;第3B圖所示為字元墊層數WLPad較多時,字元墊WLPad的面積與其階梯結構STR2所需佔用的面積都較大。據此可以得知,字元墊WLPad[k-1]、WLPad[k]、WLPad[k+1]的面積增加相當於,使跨字元墊WLPad[k-1]、WLPad[k]、WLPad[k+1]間的電容C增加,且各個字元墊WLPad[k-1]、WLPad[k]、WLPad[k+1]本身的電阻R也隨著增加。 Please refer to Figures 3A and 3B, which are schematic diagrams of increasing the area of the character pad WLPad as the memory capacity increases, thereby increasing the capacitance C and resistance R of the character pad. Please also refer to Figures 3A and 3B. Figure 3A shows that when the number of character pad layers WLPad is less, the area of the character pad WLPad and the area occupied by the ladder structure STR1 are smaller; Figure 3B shows When the number of character pad layers WLPad is large, the area of the character pad WLPad and the area occupied by the step structure STR2 are both large. It can be seen from this that the increase in the area of the character pads WLPad[k-1], WLPad[k], WLPad[k+1] is equivalent to making the cross-character pads WLPad[k-1], WLPad[k], The capacitance C between WLPad[k+1] increases, and the resistance R of each character pad WLPad[k-1], WLPad[k], WLPad[k+1] itself also increases.
對NAND快閃記憶體而言,對記憶體區塊Blk進行程式化(抹除操作或寫入操作)時,都需要透過字元線WL提供高電壓(例如:20V~25V)。但是,當字元墊WLPad的電阻R與電容C增加時,電阻電容延遲效應將越趨明顯。換言之,記憶體控制器較不容易快速地將字元線WL拉高至所需的電壓。 For NAND flash memory, when programming the memory block Blk (erase operation or write operation), it is necessary to provide a high voltage (for example, 20V~25V) through the word line WL. However, as the resistance R and capacitance C of the character pad WLPad increase, the resistance-capacitance delay effect will become more obvious. In other words, it is less easy for the memory controller to quickly pull up the word line WL to the required voltage.
本發明係有關於一種記憶體裝置,藉由在記憶體區塊對應設置全域電源線的方式,針對被選取之記憶體區塊提供一個高電壓,故能快速拉高字元線WL的電壓。 The invention relates to a memory device, which provides a high voltage for the selected memory block by correspondingly setting a global power line in the memory block, so that the voltage of the word line WL can be quickly raised.
根據本發明之一方面,提出一種記憶體裝置。記憶體裝置包含:I個記憶體區塊、I條全域電源線,以及I個第一區域驅動模組。I個記憶體區塊中的第i個記憶體區塊包含:M條閘極控制線,以及複數個電晶體單元。在記憶體區塊內的電晶體單元排列為M列,其中位 於第m列的該等電晶體單元的閘極電連接於該等閘極控制線中的第m條閘極控制線。I條全域電源線分別電連接於I個預驅動電路與I個記憶體區塊。I個第一區域驅動模組分別電連接於I條全域電源線與I個記憶體區塊。其中,I個第一區域驅動模組中的第i個第一區域驅動模組電連接於I條全域電源線中的第i條全域電源線與第i個記憶體區塊。第i個第一區域驅動模組包含:M個第一區域驅動電路。M個第一區域驅動電路共同電連接於第i條全域電源線,且M個第一區域驅動電路中的第m個第一區域驅動電路電連接於第m條閘極控制線。其中,m、M、i與I均為正整數、m小於或等於M,且i小於或等於I。 According to one aspect of the present invention, a memory device is proposed. The memory device includes: 1 memory block, 1 global power cord, and 1 first area driving module. The ith memory block of the I memory blocks includes: M gate control lines, and a plurality of transistor units. The transistor cells in the memory block are arranged in M rows, with the median The gates of the transistor cells in the mth column are electrically connected to the mth gate control line among the gate control lines. I global power lines are electrically connected to one pre-driving circuit and one memory block, respectively. One first area driving module is electrically connected to one global power line and one memory block, respectively. Wherein, the ith first area driving module in the I first area driving modules is electrically connected to the ith global power line and the ith memory block in the I global power lines. The i-th first-region driving module includes: M first-region driving circuits. The M first region driving circuits are electrically connected to the ith global power line, and the mth first region driving circuit among the M first region driving circuits is electrically connected to the mth gate control line. Among them, m, M, i and I are all positive integers, m is less than or equal to M, and i is less than or equal to I.
為了對本發明之上述及其他方面有更佳的瞭解,下文特舉實施例,並配合所附圖式詳細說明如下: In order to have a better understanding of the above and other aspects of the present invention, the following examples are specifically described in conjunction with the accompanying drawings as follows:
MC:記憶胞電晶體 MC: memory cell transistor
GSL:接地選擇層 GSL: ground selection layer
GSM、GSM[i][j]、GSM[i][j-1]、GSM[i][1]~GSM[i][J/2]、GSM[i][J/2+1]~GSM[i][J]、GSM[j]、GSM[j+1]:接地選擇電晶體 GSM, GSM[i][j], GSM[i][j-1], GSM[i][1]~GSM[i][J/2], GSM[i][J/2+1]~ GSM[i][J], GSM[j], GSM[j+1]: ground select transistor
SSL[j-1]、SSL[j]、SSL[j+1]、SSL[i][j]:串列選擇線 SSL[j-1], SSL[j], SSL[j+1], SSL[i][j]: serial selection line
SSM:串列選擇電晶體 SSM: tandem selection transistor
BL[n]、BL[n+1]:位元線 BL[n], BL[n+1]: bit line
C、C1、C2:電容 C, C1, C2: capacitance
WLPad[k-1]、WLPad[k]、WLPad[k+1]:字元墊 WLPad[k-1], WLPad[k], WLPad[k+1]: character pad
WL[k]、WL[1]、WL[K]、WL[2]、WL[3]、WL[4]、WL[5]、WL[j,1]、WL[j,K]、WL[j+1,1]、WL[j+1,K]、WL[K/2]、WL[K/2+1]、WL[K-1]:字元線 WL[k], WL[1], WL[K], WL[2], WL[3], WL[4], WL[5], WL[j,1], WL[j,K], WL [j+1,1], WL[j+1,K], WL[K/2], WL[K/2+1], WL[K-1]: character line
GWL[k-1]、GWL[k]、GWL[k+1]:全域字元線 GWL[k-1], GWL[k], GWL[k+1]: global character line
10、seg[i][1]、seg[i][2]、seg[1][1]、seg[i][2]、seg[i][3]、seg[i][4]:區段 10. seg[i][1], seg[i][2], seg[1][1], seg[i][2], seg[i][3], seg[i][4]: Section
STR1、STR2:階梯結構 STR1, STR2: ladder structure
20:記憶體裝置 20: Memory device
21:解多工電路 21: Demultiplexing circuit
23:預驅動模組 23: Pre-drive module
25a:區域驅動組A 25a: Regional drive group A
25b:區域驅動組B 25b: Regional drive group B
27:記憶體陣列 27: memory array
29:頁緩衝電路 29: Page buffer circuit
GPL[1]~GPL[I]、GPL[i]:全域電源線 GPL[1]~GPL[I], GPL[i]: global power cord
LMa[1]、LMa[I]、LMa[i]、LMa[i-1]:區域驅動模組 LMa[1], LMa[I], LMa[i], LMa[i-1]: regional drive module
LMb[1]、LMb[I]、LMa[i]、LMb[i-1]:區域驅動模組 LMb[1], LMb[I], LMa[i], LMb[i-1]: regional drive module
Sin:輸入線(信號) Sin: input line (signal)
BLK[1]、BLK[I]、BLK[i]、BLK[2]:記憶體區塊 BLK[1], BLK[I], BLK[i], BLK[2]: memory blocks
Ssel[1]、Ssel[2]、Ssel[I]、Ssel[i]:區塊選擇線(信號) Ssel[1], Ssel[2], Ssel[I], Ssel[i]: block selection line (signal)
Sfla[1]、Sflb[1]、Sfla[I]、Sflb[I]、Sfla[i]、Sflb[i]:浮接線 Sfla[1], Sflb[1], Sfla[I], Sflb[I], Sfla[i], Sflb[i]: floating wire
GCL[1][1]~GCL[1][M]、GCL[I][1]~GCL[I][M]、GCL[i][1]~GCL[i][M]、GCL[i-1][1]、GCL[i-1][M]:閘極控制線 GCL[1][1]~GCL[1][M], GCL[I][1]~GCL[I][M], GCL[i][1]~GCL[i][M], GCL[ i-1][1], GCL[i-1][M]: gate control line
PC[i]、PC[i-1]:預驅動電路 PC[i], PC[i-1]: pre-driving circuit
Spre[1]~Spre[I]、Spre[i]:預驅動電壓 Spre[1]~Spre[I], Spre[i]: pre-drive voltage
LCa[i][1]、LCa[i][2]、LCa[i][3]、LCa[i][M-1]、LCa[i][M]、LCb[i][1]、LCb[i][2]、LCb[i][3]、LCb[i][M-1]、LCb[i][M]、LCa[i][4]、LCa[i][5]、LCb[i][4]、LCb[i][5]:區域驅動電路 LCa[i][1], LCa[i][2], LCa[i][3], LCa[i][M-1], LCa[i][M], LCb[i][1], LCb[i][2], LCb[i][3], LCb[i][M-1], LCb[i][M], LCa[i][4], LCa[i][5], LCb[i][4], LCb[i][5]: regional driving circuit
ST[i][j-1]、ST[i][j]、ST[j]、ST[j+1]:記憶體串列 ST[i][j-1], ST[i][j], ST[j], ST[j+1]: memory sequence
GSL[i][p]、GSL[j,p]、GSL[j+1,p]、GSL:接地選擇線 GSL[i][p], GSL[j,p], GSL[j+1,p], GSL: ground selection line
M1、M2、M3:預驅動電晶體 M1, M2, M3: pre-drive transistor
Vpp:第一電源電壓 Vpp: the first power supply voltage
Vss:第二電源電壓 Vss: second power supply voltage
i1、i2:位移電流 i1, i2: displacement current
Npre:預充電節點 Npre: pre-charge node
GSL_WLPad[i][1]、GSL_WLPad[i][2]、GSL_WLPad[1][1]、GSL_WLPad[1][2]、GSL_WLPad[1][3]:接地-字元墊 GSL_WLPad[i][1], GSL_WLPad[i][2], GSL_WLPad[1][1], GSL_WLPad[1][2], GSL_WLPad[1][3]: ground-character pad
SSL_WLPad[i][1]、SSL_WLPad[1][1]、SSL_WLPad[1][2]、SSL_WLPad[1][3]:串列-字元墊 SSL_WLPad[i][1], SSL_WLPad[1][1], SSL_WLPad[1][2], SSL_WLPad[1][3]: serial-character pad
第1圖,其係三維記憶體結構之示意圖。 Figure 1 is a schematic diagram of a three-dimensional memory structure.
第2圖,其係三維記憶體結構中的全域字元線GWL與字元墊WLPad之示意圖。 Figure 2 is a schematic diagram of the global character line GWL and the character pad WLPad in the three-dimensional memory structure.
第3A、3B圖,其係隨著記憶體容量增加,使字元墊WLPad面積增加,進而使字元墊的電容C與電阻R增加之示意圖。 Figures 3A and 3B are schematic diagrams of increasing the area of the character pad WLPad as the memory capacity increases, thereby increasing the capacitance C and resistance R of the character pad.
第4圖,其係根據本發明實施例的記憶體裝置之示意圖。 FIG. 4 is a schematic diagram of a memory device according to an embodiment of the invention.
第5圖,其係根據本發明實施例的記憶體裝置,於多個記憶體區塊設置全域電源線GPL的連接關係之示意圖。 FIG. 5 is a schematic diagram of a memory device according to an embodiment of the present invention, in which a global power line GPL connection relationship is provided in a plurality of memory blocks.
第6圖,其係以記憶體區塊Blk[i]為例,說明與其對應之預驅動電路PC[i]、區域驅動模組LMa[i]、區域驅動模組LMb[i]之間的連接關係之示意圖。 Figure 6, which uses the memory block Blk[i] as an example to illustrate the corresponding between the pre-driving circuit PC[i], the area driving module LMa[i], and the area driving module LMb[i] Schematic diagram of the connection relationship.
第7A、7B圖,其係預驅動電路的操作模式之示意圖。 7A and 7B are schematic diagrams of the operation modes of the pre-driving circuit.
第8圖,其係以字元線作為閘極控制線GCL的舉例,說明在三維記憶體結構中設置全域電源線GPL之示意圖。 FIG. 8 is an example of using the word line as the gate control line GCL, and illustrates a schematic diagram of setting the global power line GPL in the three-dimensional memory structure.
第9圖,其係進一步繪式全域電源線GPL如何透過閘極控制線GCL,與串列選擇電晶體SSM與記憶胞電晶體MC相連之示意圖。 FIG. 9 is a schematic diagram illustrating how the global power line GPL is connected to the serial selection transistor SSM and the memory cell transistor MC through the gate control line GCL.
第10A圖,其係記憶體串列採用底部源極串列連接方式之示意圖。 FIG. 10A is a schematic diagram of the bottom source tandem connection method of the memory string.
第10B圖,其係記憶體串列採用底部源極串列連接方式時的記憶體結構之示意圖。 FIG. 10B is a schematic diagram of the memory structure when the memory series adopts the bottom source series connection method.
第11圖,其係記憶體串列採用底部源極串列連接方式時的一個記憶體區塊之俯視圖。 Fig. 11 is a top view of a memory block when the memory string is connected with the bottom source string.
第12A圖,其係設置在一個記憶體區塊之多條閘極控制線GCL的示意圖。 FIG. 12A is a schematic diagram of a plurality of gate control lines GCL provided in a memory block.
第12B圖,其係設置在一個記憶體區塊之全域電源線GPL與浮接線的示意圖。 FIG. 12B is a schematic diagram of the global power line GPL and floating wiring provided in a memory block.
第13圖,其係將第11圖所示之記憶體區塊,搭配第12A圖的閘極控制線GCL,以及第12B圖的全域電源線GPL與浮接線之示意圖。 Figure 13 is a schematic diagram of the memory block shown in Figure 11 with the gate control line GCL in Figure 12A, and the global power line GPL and floating wiring in Figure 12B.
第14A圖,其係記憶體串列採用U型串列連接方式之示意圖。 Fig. 14A is a schematic diagram of the U-shaped serial connection method of the memory serial.
第14B圖,其係記憶體串列採用U型串列連接方式時的記憶體結構之示意圖。 FIG. 14B is a schematic diagram of the memory structure when the memory string adopts the U-shaped serial connection method.
第15圖,其係記憶體串列採用U型串列連接方式時的一個記憶體區塊之俯視圖。 Figure 15 is a top view of a memory block when the memory string is connected in a U-shaped string.
第16圖,其係將第15圖所示之記憶體區塊,搭配第12A圖的閘極控制線GCL,以及第12B圖的全域電源線GPL與浮接線之示意圖。 FIG. 16 is a schematic diagram of the memory block shown in FIG. 15 in combination with the gate control line GCL in FIG. 12A, and the global power line GPL and floating wiring in FIG. 12B.
第17圖,其係根據本發明實施例的記憶體裝置,搭配複數個記憶體區塊之示意圖。 FIG. 17 is a schematic diagram of a memory device according to an embodiment of the present invention, with a plurality of memory blocks.
第18A圖,其係多個記憶體區塊之俯視圖。 Figure 18A is a top view of multiple memory blocks.
第18B圖,將第18A圖的記憶體區塊,搭配閘極控制線GCL、全域電源線GPL與浮接線之示意圖。 Figure 18B is a schematic diagram of the memory block of Figure 18A, with the gate control line GCL, the global power line GPL and the floating wiring.
請參見第4圖,其係根據本發明實施例的記憶體裝置之示意圖。記憶體裝置20包含:解多工電路21、預驅動模組23、區域驅動組A 25a、區域驅動組B 25b、頁緩衝電路29,I條全域電源線GPL[1]~GPL[I],以及記憶體陣列27。為便於說明,此處假設記憶體陣列27包含記憶體區塊Blk[1]~Blk[I],且每個記憶體區塊Blk包含一個或多個記憶體分頁(page)。其中,各個記憶體區塊Blk[1]~Blk[I]分別對應於全域電源線GPL[1]~GPL[I]。例如,記憶體區塊Blk[i]對應於全域電源線GPL[i]。
Please refer to FIG. 4, which is a schematic diagram of a memory device according to an embodiment of the present invention. The
解多工電路21電連接於預驅動模組23,且預驅動模組23透過I條全域電源線GPL而電連接於區域驅動組A 25a與區域驅動組B 25b。頁緩衝電路29電連接於記憶體陣列27。為便於說明,以下將
各個接線及在接線上的信號,以相同的符號表示。例如,以Ssel表示區塊選擇線與區塊選擇信號,其餘信號與接線的標示方式亦同。
The
參見第5圖,其係本發明實施例的記憶體裝置,於區域驅動模組與記憶體區塊間設置全域電源線GPL之示意圖。解多工電路21具有一條輸入線Sin與I條區塊選擇線Ssel[1]~Ssel[I]。解多工電路21從記憶體控制器接收輸入信號Sin,用於決定記憶體區塊Blk[1]~Blk[I]中的何者被用於存取。因此,解多工電路21產生的區塊選擇信號Ssel[1]~Ssel[I]分別對應於記憶體區塊Blk[1]~Blk[I]。
Referring to FIG. 5, which is a schematic diagram of a memory device according to an embodiment of the present invention, a global power line GPL is provided between a regional driving module and a memory block. The
當區塊選擇信號Ssel[i]代表記憶體區塊Blk[i]被選取時,第i條區塊選擇線Ssel[i]具有第一邏輯位準(例如,邏輯低位準L)。當區塊選擇信號Ssel[i]代表記憶體區塊Blk[i]未被選取時,區塊選擇線Ssel[i]具有第二邏輯位準(例如,邏輯高位準H)。 When the block selection signal Ssel[i] represents that the memory block Blk[i] is selected, the i-th block selection line Ssel[i] has a first logic level (for example, a logic low level L). When the block selection signal Ssel[i] represents that the memory block Blk[i] is not selected, the block selection line Ssel[i] has a second logic level (for example, a logic high level H).
預驅動模組23包含預驅動電路PC[1]~PC[I],分別用於接收與記憶體區塊Blk[1]~Blk[I]相對應的區塊選擇信號Ssel[1]~Ssel[I]。預驅動電路PC[1]~PC[I]接收區塊選擇信號Ssel[1]~Ssel[I],分別對應輸出預驅動電壓Spre[1]~Spre[I]。
The
根據本發明的構想,針對每一個記憶體區塊Blk[1]~Blk[J],分別提供一條全域電源線GPL[1]~GPL[I]。這些全域電源線GPL[1]~GPL[I]用於傳送預驅動電壓Spre[1]~Spre[I]。此外,在每一條全域電源線GPL[1]~GPL[I]的兩側,還分別設置浮接線Sfla、Sflb。例如,在全域電源線GPL[1]的兩側設置浮接線Sfla[1]、Sflb[1];以及,在全域電源線GPL[I]的兩側設置浮接線Sfla[I]、Sflb[I]。此外,每個記憶體區塊Blk[1]~Blk[J]各自包含M條閘極控制 線GCL。例如,記憶體區塊Blk[1]包含閘極控制線GCL[1][1]~GCL[1][M];記憶體區塊Blk[I]包含閘極控制線GCL[I][1]~GCL[I][M]。 According to the concept of the present invention, for each memory block Blk[1]~Blk[J], a global power line GPL[1]~GPL[I] is provided respectively. These global power lines GPL[1]~GPL[I] are used to transmit the pre-drive voltages Spre[1]~Spre[I]. In addition, on both sides of each global power line GPL[1]~GPL[I], floating wires Sfla and Sflb are respectively provided. For example, floating wires Sfla[1] and Sflb[1] are provided on both sides of the global power line GPL[1]; and floating wires Sfla[I] and Sflb[I are provided on both sides of the global power line GPL[I] ]. In addition, each memory block Blk[1]~Blk[J] contains M gate controls Line GCL. For example, the memory block Blk[1] contains the gate control line GCL[1][1]~GCL[1][M]; the memory block Blk[I] contains the gate control line GCL[I][1 ]~GCL[I][M].
區域驅動組A 25a包含與記憶體區塊Blk[1]~Blk[I]相對應的區域驅動模組LMa[1]~LMa[I];區域驅動組B 25b包含與記憶體區塊Blk[1]~Blk[I]相對應的區域驅動模組LMb[1]~LMb[I]。區域驅動模組LMa[1]~LMa[I]分別經由全域電源線GPL[1]~GPL[I]接收預驅動電路PC[1]~PC[I]產生的預驅動電壓Spre[1]~Spre[I],且區域驅動模組LMb[1]~LMb[I]分別經由全域電源線GPL[1]~GPL[I]接收預驅動電路PC[1]~PC[I]產生的預驅動電壓Spre[1]~Spre[I]。
The regional
請參見第6圖,其係以記憶體區塊Blk[i]為例,說明與其對應之預驅動電路PC[i]、區域驅動模組LMa[i]、區域驅動模組LMb[i]之間的連接關係之示意圖。記憶體區塊Blk[i]經由全域電源線GPL[i]而電連接至預驅動電路PC[i]。此外,全域電源線GPL[i]的兩側還設有浮接線Sfla[i]、Sflb[i]。 Please refer to FIG. 6, which takes the memory block Blk[i] as an example to illustrate the corresponding pre-driving circuit PC[i], area driving module LMa[i], area driving module LMb[i] Schematic diagram of the connection relationship between. The memory block Blk[i] is electrically connected to the pre-driving circuit PC[i] via the global power line GPL[i]. In addition, floating wires Sfla[i] and Sflb[i] are also provided on both sides of the global power line GPL[i].
區域驅動模組LMa[i]包含M個區域驅動電路LCa[i][1]~LCa[i][M];區域驅動模組LMb[i]包含M個區域驅動電路LCb[i][1]~LCb[i][M]。區域驅動電路LCa[i][1]~LCa[i][M]透過一共同接線連接至全域電源線GPL[i];以及,區域驅動電路LCb[i][1]~LCb[i][M]透過另一共同接線連接至全域電源線GPL[i]。 The regional driving module LMa[i] contains M regional driving circuits LCa[i][1]~LCa[i][M]; the regional driving module LMB[i] contains M regional driving circuits LCb[i][1 ]~LCb[i][M]. The regional driving circuits LCa[i][1]~LCa[i][M] are connected to the global power line GPL[i] through a common wiring; and, the regional driving circuits LCb[i][1]~LCb[i][ M] is connected to the global power line GPL[i] through another common wiring.
記憶體區塊Blk[i]包含:閘極控制線GCL[i][1]~GCL[i][M]。其中,閘極控制線GCL[i][1]~GCL[i][M]的一部分為串列選擇線SSL[i][1]~SSL[i][J]、一部分為字元線WL[1]~WL[K],以及一部分為接地選擇線GSL[i][1]~GSL[i][P](第6 圖僅繪式GSL[i][p])。區域驅動電路LCa[i][1]~LCa[i][M]分別電連接至閘極控制線GCL[i][1]~GCL[i][M];區域驅動電路LCb[i][1]~LCb[i][M]亦分別電連接至閘極控制線GCL[i][1]~GCL[i][M]。 The memory block Blk[i] includes: gate control lines GCL[i][1]~GCL[i][M]. Among them, part of the gate control lines GCL[i][1]~GCL[i][M] is the serial selection line SSL[i][1]~SSL[i][J], and part is the character line WL [1]~WL[K], and a part of the ground selection line GSL[i][1]~GSL[i][P] (Section 6 The figure only draws the formula GSL[i][p]). The regional driving circuits LCa[i][1]~LCa[i][M] are electrically connected to the gate control lines GCL[i][1]~GCL[i][M]; the regional driving circuit LCb[i][ 1]~LCb[i][M] are also electrically connected to the gate control lines GCL[i][1]~GCL[i][M], respectively.
預驅動電路PC[1]~PC[I]彼此具有類似的結構,此處僅以預驅動電路PC[i]為例。預驅動電路PC[i]包含:預驅動電晶體M1、M2、M3。其中,預驅動電晶體M1、M2、M3均為耐高壓型電晶體。預驅動電晶體M1為PMOS電晶體、預驅動電晶體M2、M3為NMOS電晶體,且預驅動電晶體M2為空乏型(depletion mode)電晶體。預驅動電晶體M3可為一般NMOS電晶體或三阱NMOS電晶體。 The pre-drive circuits PC[1]~PC[I] have similar structures to each other, and here only the pre-drive circuit PC[i] is taken as an example. The pre-drive circuit PC[i] includes: pre-drive transistors M1, M2, M3. Among them, the pre-driving transistors M1, M2, M3 are high-voltage-resistant transistors. The pre-driving transistor M1 is a PMOS transistor, the pre-driving transistors M2 and M3 are NMOS transistors, and the pre-driving transistor M2 is a depletion mode transistor. The pre-driving transistor M3 may be a general NMOS transistor or a triple well NMOS transistor.
預驅動電晶體M1電連接於區塊選擇線Ssel[i];預驅動電晶體M2電連接於預驅動電晶體M1以及全域電源線GPL[i]。預驅動電晶體M2自第一電壓源Vpp接收第一電源電壓Vpp。預驅動電晶體M3電連接於預驅動電晶體M1以及全域電源線GPL[i]。預驅動電晶體M3自第二電壓源Vss接收第二電源電壓Vss。預驅動電晶體M1的源極端與基極端(body)彼此電連接,且預驅動電晶體M1的汲極端與預驅動電晶體M2的閘極端共同電連接於全域電源線GPL[i]。 The pre-driving transistor M1 is electrically connected to the block selection line Ssel[i]; the pre-driving transistor M2 is electrically connected to the pre-driving transistor M1 and the global power line GPL[i]. The pre-driving transistor M2 receives the first power supply voltage Vpp from the first voltage source Vpp. The pre-drive transistor M3 is electrically connected to the pre-drive transistor M1 and the global power line GPL[i]. The pre-drive transistor M3 receives the second power supply voltage Vss from the second voltage source Vss. The source terminal and the base terminal of the pre-driving transistor M1 are electrically connected to each other, and the drain terminal of the pre-driving transistor M1 and the gate terminal of the pre-driving transistor M2 are electrically connected to the global power line GPL[i].
在本發明的實施例中,第一電源電壓Vpp高於記憶體的讀取電壓Vrd、記憶體的寫入電壓Vwr與記憶體的抹除電壓Vers。第二電源電壓Vss低於記憶體的讀取電壓Vrd、記憶體的寫入電壓Vwr與記憶體的抹除電壓Vers。在某些應用中,讀取電壓Vrd和抹除電壓Vers可能低於接地電壓(0V)。在此同時,第二電源電壓Vss為一負電壓。由於第二電源電壓Vss仍維持在最低電位的緣故,可避免電晶體產生異常的順向導通(forward turn-on)。此外,所有基極接到負電壓Vss 的NMOS電晶體都需採用三阱NMOS電晶體,例如區域驅動電路LCa、LCb與預驅動電晶體M3等。據此,可以避免影響到同一記憶體裝置的其他NMOS電晶體。 In the embodiment of the present invention, the first power voltage Vpp is higher than the read voltage Vrd of the memory, the write voltage Vwr of the memory, and the erase voltage Vers of the memory. The second power supply voltage Vss is lower than the memory read voltage Vrd, the memory write voltage Vwr, and the memory erase voltage Vers. In some applications, the read voltage Vrd and the erase voltage Vers may be lower than the ground voltage (0V). At the same time, the second power supply voltage Vss is a negative voltage. Since the second power supply voltage Vss is still maintained at the lowest potential, abnormal forward turn-on of the transistor can be avoided. In addition, all bases are connected to a negative voltage Vss All NMOS transistors need to use triple-well NMOS transistors, such as regional drive circuits LCa, LCb and pre-drive transistor M3. Accordingly, it is possible to avoid affecting other NMOS transistors of the same memory device.
當記憶體控制器選取任何一個記憶體區塊Blk[1]~Blk[I]前,解多工電路21輸出的區塊選擇線Ssel[1]~Ssel[I]均具有邏輯高位準H。假設記憶體控制器所產之輸入信號Sin代表選取記憶體區塊Blk[i]的情況,則解多工電路21輸出的區塊選擇線Ssel[i]為邏輯低位準L,區塊選擇線Ssel[1]~Ssel[i-1]、Ssel[i+1]~Ssel[I]為邏輯高位準H。邏輯高位準H可為4V、邏輯低位準L可為0V。
Before any one of the memory blocks Blk[1]~Blk[I] is selected by the memory controller, the block selection lines Ssel[1]~Ssel[I] output by the
請參見第7A、7B圖,其係與記憶體區塊Blk[i]對應的預驅動電路PC[i]的操作模式之示意圖。其中,第7A圖為記憶體區塊Blk[i]未被選取的情形;第7B圖為記憶體區塊Blk[i]被選取的情形。由第7A、7B圖可以看出,無論記憶體區塊Blk[i]是否被選取,預驅動電晶體M1維持接收第一電源電壓Vpp(例如,30V),且預驅動電晶體M3維持接收第二電源電壓Vss。 Please refer to FIGS. 7A and 7B, which are schematic diagrams of operation modes of the pre-driving circuit PC[i] corresponding to the memory block Blk[i]. Among them, FIG. 7A is a case where the memory block Blk[i] is not selected; FIG. 7B is a case where the memory block Blk[i] is selected. As can be seen from FIGS. 7A and 7B, regardless of whether the memory block Blk[i] is selected, the pre-drive transistor M1 maintains receiving the first power supply voltage Vpp (for example, 30V), and the pre-drive transistor M3 maintains receiving the first Two power supply voltage Vss.
在第7A圖中,預驅動電晶體M3接收預充電用的第二電源電壓Vss;預驅動電晶體M1接收第一電源電壓Vpp,且預充電節點Npre的電壓為第二電源電壓Vss。因為區塊選擇線Ssel[i]具有邏輯高位準H時,預驅動電晶體M1維持為斷開,且預驅動電晶體M2也保持斷開。此時,僅有預驅動電晶體M3導通。 In FIG. 7A, the pre-drive transistor M3 receives the second power supply voltage Vss for pre-charging; the pre-drive transistor M1 receives the first power supply voltage Vpp, and the voltage of the pre-charge node Npre is the second power supply voltage Vss. Because the block selection line Ssel[i] has a logic high level H, the pre-driving transistor M1 remains off, and the pre-driving transistor M2 also remains off. At this time, only the pre-drive transistor M3 is turned on.
因此,當記憶體區塊Blk[i]未被選取時,預驅動電路PC[i]因為內部電荷不平衡而產生位移電流(displacement current)i1。因此,與預充電節點Npre相連接的預驅動信號線上的電壓(預驅動電壓)Spre[i]為,經由預驅動電晶體M3而傳送至全域電源線 GPL[i]的第二電源電壓Vss。連帶的,與記憶體區塊Blk[i]相對應的兩個區域驅動模組LMa[i]、LMb[i],均從全域電源線GPL[i]接收到第二電源電壓Vss。是故,記憶體區塊Blk[i]並不會進行各種記憶體操作。附帶一提的是,位移電流i1並不會持續產生。一旦電位達到平衡(Spre=Vss)之後,位移電流i1將消失。 Therefore, when the memory block Blk[i] is not selected, the pre-drive circuit PC[i] generates a displacement current i1 due to the imbalance of internal charges. Therefore, the voltage (pre-driving voltage) Spre[i] on the pre-driving signal line connected to the pre-charging node Npre is transmitted to the global power line through the pre-driving transistor M3 The second power supply voltage Vss of GPL[i]. In conjunction, the two regional drive modules LMa[i] and LMb[i] corresponding to the memory block Blk[i] receive the second power supply voltage Vss from the global power supply line GPL[i]. Therefore, the memory block Blk[i] does not perform various memory operations. Incidentally, the displacement current i1 will not continue to be generated. Once the potential reaches equilibrium (Spre=Vss), the displacement current i1 will disappear.
在第7B圖中,預驅動電晶體M3接收預充電用的第二電源電壓Vss;預驅動電晶體M1接收第一電源電壓Vpp,且預充電節點Npre的電壓在剛開始為第二電源電壓Vss。當區塊選擇線Ssel[i]具有邏輯低位準L時,因為預驅動電晶體M2為空乏型電晶體的緣故,其臨界電壓Vth小於0V,因而使預驅動電晶體M2呈現部分導通的情形。 In FIG. 7B, the pre-drive transistor M3 receives the second power supply voltage Vss for pre-charging; the pre-drive transistor M1 receives the first power supply voltage Vpp, and the voltage of the pre-charge node Npre is the second power supply voltage Vss at the beginning . When the block selection line Ssel[i] has a logic low level L, because the pre-driving transistor M2 is a depleted transistor, the threshold voltage Vth is less than 0V, so that the pre-driving transistor M2 is partially turned on.
對預驅動電晶體M1而言,因為閘極接收低邏輯位準L的電壓,而源極透過預驅動電晶體M2逐漸接收第一電源電壓Vpp的緣故,預驅動電晶體M1將開始形成弱導通(weak turn-on)。當預驅動電晶體M1導通時,預驅動電晶體M1的源極電壓將傳送至預驅動電晶體M1的汲極,也就是預充電節點Npre。而預充電節點Npre的電壓又將牽動預驅動電晶體M2的閘極電壓,使預驅動電晶體M2的開啟狀態更加完全,如此形成在預驅動電晶體M1、M2之間導通電流的正回授(positive feedback)效果。 For the pre-drive transistor M1, because the gate receives the voltage of the low logic level L, and the source gradually receives the first power supply voltage Vpp through the pre-drive transistor M2, the pre-drive transistor M1 will start to form a weak conduction (weak turn-on). When the pre-driving transistor M1 is turned on, the source voltage of the pre-driving transistor M1 will be transmitted to the drain of the pre-driving transistor M1, that is, the pre-charge node Npre. The voltage of the pre-charge node Npre will affect the gate voltage of the pre-drive transistor M2, making the pre-drive transistor M2 more fully on, thus forming a positive feedback of the on-current between the pre-drive transistors M1, M2 (positive feedback) effect.
此時,預驅動電晶體M1、M2導通,並使預充電節點Npre的電壓上升至第一電源電壓Vpp。在此同時,預驅動電晶體M3為斷開。在此種狀況下,預驅動電晶體M1的閘極連接至0V,而預驅動電晶體M1的源極與N-阱(well)連接到第一電源電壓Vpp。因此,預驅動電晶體M1需使用具有較高崩潰電壓(breakdown voltage)的電晶 體。例如,預驅動電晶體M1的閘極氧化層(oxide)的厚度需較一般的PMOS電晶體更厚。 At this time, the pre-drive transistors M1 and M2 are turned on, and the voltage of the pre-charge node Npre is raised to the first power supply voltage Vpp. At the same time, the pre-drive transistor M3 is turned off. In this case, the gate of the pre-driving transistor M1 is connected to 0V, and the source and the N-well of the pre-driving transistor M1 are connected to the first power supply voltage Vpp. Therefore, the pre-driving transistor M1 needs to use a transistor with a higher breakdown voltage body. For example, the thickness of the gate oxide layer of the pre-drive transistor M1 needs to be thicker than that of a general PMOS transistor.
當記憶體區塊Blk[i]被選取時,預驅動電路PC[i]產生位移電流i2。因此,與預充電節點Npre相連接的預驅動信號線上的電壓(預驅動電壓)Spre[i]為第一電源電壓Vpp。由於預驅動信號線Spre[i]連接至全域電源線GPL[i],與記憶體區塊Blk[i]相對應的兩個區域驅動模組LMa[i]、LMb[i],都將從全域電源線GPL[i]接收到第一電源電壓Vpp。是故,記憶體控制器可控制被選取的記憶體區塊Blk[i]進行各種記憶體操作。 When the memory block Blk[i] is selected, the pre-drive circuit PC[i] generates a displacement current i2. Therefore, the voltage (pre-driving voltage) Spre[i] on the pre-driving signal line connected to the pre-charging node Npre is the first power supply voltage Vpp. Since the pre-drive signal line Spre[i] is connected to the global power line GPL[i], the two regional drive modules LMa[i] and LMb[i] corresponding to the memory block Blk[i] will be switched from The global power line GPL[i] receives the first power voltage Vpp. Therefore, the memory controller can control the selected memory block Blk[i] to perform various memory operations.
承上所述,當解多工電路21輸出的區塊選擇線Ssel[i]具有邏輯低位準L時,代表記憶體區塊Blk[i]被選取。此時,預驅動電路PC[i]會輸出第一電源電壓Vpp至與記憶體區塊Blk[i]對應的全域電源線GPL[i]。當解多工電路21輸出的區塊選擇線Ssel[i]具有邏輯高位準H時,代表記憶體區塊Blk[i]未被選取。此時,預驅動電路PC[i]輸出第二電源電壓Vss至與記憶體區塊Blk[i]對應的全域電源線GPL[i]。
As described above, when the block selection line Ssel[i] output from the
由於第一電源電壓Vpp為記憶體裝置所提供的最高電壓,為避免與被選取之記憶體區塊Blk[i]相對應的全域電源線GPL[i]的高電壓與周邊的信號線形成過大的壓差,進而破壞記憶體的結構,本發明的實施例還在全域電源線GPL[i]的兩側設置浮接線Sfla[i]、Sflb[i]。浮接線Sfla[i]、Sflb[i]的設置,可以稍微減緩具有高電壓之全域電源線GPL[i]對周邊其他信號線可能產生的影響。 Since the first power supply voltage Vpp is the highest voltage provided by the memory device, in order to avoid the high voltage of the global power supply line GPL[i] corresponding to the selected memory block Blk[i] and the surrounding signal line from being too large The pressure difference of the device will further destroy the structure of the memory. In the embodiment of the present invention, floating wires Sfla[i] and Sflb[i] are also provided on both sides of the global power line GPL[i]. The setting of the floating wires Sfla[i] and Sflb[i] can slightly alleviate the possible impact of the global power line GPL[i] with high voltage on other signal lines around it.
請參見第8圖,其係繪式字元墊WLPad的階梯結構,說明在三維記憶體中設置全域電源線GPL之示意圖。解多工電路21藉由區塊選擇線Ssel[i]而電連接於預驅動電路PC[i],且預驅動電路PC[i]
透過全域電源線GPL[i]而電連接於區域驅動模組LMa[i]與區域驅動模組LMb[i]。預驅動電路PC[i]輸出位準為第一電源電壓Vpp或第二電源電壓Vss的預驅動電壓Spre[i]至全域電源線GPL[i]。此處假設區域驅動模組LMa[i]包含區域驅動電路LCa[i][1]~LCa[i][5],且區域驅動模組LMb[i]包含區域驅動電路LCb[i][1]~LCb[i][5]。其中,區域驅動電路LCa[i][1]與區域驅動電路LCb[i][1]共同電連接於階梯結構中的字元墊WLPad[i][1];區域驅動電路LCa[i][2]與區域驅動電路LCb[i][2]共同電連接於階梯結構中的字元墊WLPad[i][2];其餘類推。
Please refer to FIG. 8, which is a ladder structure of a character pad WLPad, illustrating a schematic diagram of setting a global power line GPL in a three-dimensional memory. The
如前所述,除了字元線WL[1]~WL[K]外,閘極控制線GCL[1]~GCL[M]中的一部分可為串列選擇線SSL[1]~SSL[J]與接地選擇線GSL[i][1]~GSL[i][P]。在記憶體區塊Blk[i]的第j個記憶體串列ST[i][j]中,包含串列選擇電晶體SSM[i][j]、K個記憶胞電晶體MC[i][j][1]~MC[i][j][K],以及一個接地選擇電晶體GSM[i][j]。記憶胞電晶體MC[i][j][1]~MC[i][j][K]可為浮動閘極電晶體或電荷捕捉元件(charge trapping device)等非揮發性記憶體。實際應用時,並不需要限定記憶胞電晶體MC[i][j][1]~MC[i][j][K]的類型。 As mentioned above, in addition to the word lines WL[1]~WL[K], part of the gate control lines GCL[1]~GCL[M] can select the serial selection lines SSL[1]~SSL[J ] And the ground selection line GSL[i][1]~GSL[i][P]. The jth memory string ST[i][j] of the memory block Blk[i] contains the string selection transistor SSM[i][j] and K memory cell transistors MC[i] [j][1]~MC[i][j][K], and a ground selection transistor GSM[i][j]. Memory cell transistors MC[i][j][1]~MC[i][j][K] can be non-volatile memories such as floating gate transistors or charge trapping devices. In practical application, there is no need to limit the types of memory cell transistors MC[i][j][1]~MC[i][j][K].
請參見第9圖,其係進一步繪式全域電源線GPL[i]如何透過閘極控制線GCL,與串列選擇電晶體SSM與記憶胞電晶體MC相連之示意圖。此圖式簡要繪式記憶體區塊Blk[i]中的電晶體單元與各類接線的關係。 Please refer to FIG. 9, which is a schematic diagram of how the global power line GPL[i] is connected to the serial selection transistor SSM and the memory cell transistor MC through the gate control line GCL. This diagram briefly illustrates the relationship between the transistor unit in the memory block Blk[i] and various wiring.
記憶體區塊Blk[i]包含記憶體串列ST[i][1]~ST[i][J],此處僅以記憶體區塊Blk[i]中的記憶體串列ST[i][j-1]和記憶體串列ST[i][j]為例。記憶體串列ST[i][j-1]包含:串列選擇電晶體SSM[i][j-1]、與字元線WL[1]~WL[K]相連的K個記憶胞電晶體 MC[i][j-1][1]~MC[i][j-1][K],一個接地選擇電晶體GSM[i][j-1]。記憶體串列ST[i][j]包含:串列選擇電晶體SSM[i][j]、與字元線WL[1]~WL[K]相連的K個記憶胞電晶體MC[i][j][1]~MC[i][j][K],接地選擇電晶體GSM[i][j]。 The memory block Blk[i] contains the memory string ST[i][1]~ST[i][J], here only the memory string ST[i in the memory block Blk[i] ][j-1] and memory string ST[i][j] as an example. The memory string ST[i][j-1] includes: the string selection transistor SSM[i][j-1], and K memory cells connected to the word line WL[1]~WL[K] Crystal MC[i][j-1][1]~MC[i][j-1][K], a ground selection transistor GSM[i][j-1]. The memory string ST[i][j] includes: a string selection transistor SSM[i][j], and K memory cell transistors MC[i connected to the word line WL[1]~WL[K] ][j][1]~MC[i][j][K], ground select transistor GSM[i][j].
據此,記憶體區塊Blk[i]中的記憶體串列ST[i][j](其中,j=1~J)對應於一個串列選擇電晶體SSM[i][j]、K個記憶胞電晶體MC[i][j][1]~MC[i][j][K]、以及一個接地選擇電晶體GSM[i][j]。記憶體區塊Blk[i]的不同串列中的接地選擇電晶體GSM[i][j-1]、GSM[i][j]的閘極共同連接至P條接地選擇線GSL[i][1]~GSL[i][P]。為便於說明,此處假設P=1。此外,記憶體區塊Blk[i]的不同串列中的接地選擇電晶體GSM[i][j-1]、GSM[i][j]均電連接至同一條共用源極線(common source line)CSL[i]。 Accordingly, the memory string ST[i][j] (where j=1~J) in the memory block Blk[i] corresponds to a string selection transistor SSM[i][j], K One memory cell transistor MC[i][j][1]~MC[i][j][K], and one ground selection transistor GSM[i][j]. The gates of the ground selection transistors GSM[i][j-1] and GSM[i][j] in different series of the memory block Blk[i] are connected to P ground selection lines GSL[i] [1]~GSL[i][P]. For ease of explanation, it is assumed here that P=1. In addition, the ground selection transistors GSM[i][j-1] and GSM[i][j] in different series of the memory block Blk[i] are electrically connected to the same common source line (common source) line)CSL[i].
另一方面,若P≠1時,則可將J個記憶體串列分為P個串列組,其中,J可能大於或等於P。屬於同一個串列組之記憶體串列中的接地選擇電晶體GSM[i][j]的閘極共同連接至同一條接地選擇線GSL[i][p]。例如,假設J為偶數且P=2時,可將J個記憶體串列分為2個串列組。其中,第一個串列組包含記憶體串列ST[i][1]~ST[i][J/2];第二個串列組包含記憶體串列ST[i][J/2+1]~ST[i][J]。據此,屬於記憶體串列ST[i][1]~ST[i][J/2]的接地選擇電晶體GSM[i][1]~GSM[i][J/2]的閘極共同連接至接地選擇線GSL[i][1];屬於記憶體串列ST[i][J/2+1]~ST[i][J]的接地選擇電晶體GSM[i][J/2+1]~GSM[i][J]的閘極共同連接至接地選擇線GSL[i][2]。 On the other hand, if P≠1, then J memory strings may be divided into P string groups, where J may be greater than or equal to P. The gates of the ground selection transistors GSM[i][j] in the memory series belonging to the same series group are connected to the same ground selection line GSL[i][p]. For example, assuming that J is even and P=2, J memory strings can be divided into 2 string groups. Among them, the first serial group contains memory series ST[i][1]~ST[i][J/2]; the second serial group contains memory series ST[i][J/2 +1]~ST[i][J]. Accordingly, the ground selection transistors belonging to the memory series ST[i][1]~ST[i][J/2] select the gate of the transistor GSM[i][1]~GSM[i][J/2] Commonly connected to the ground selection line GSL[i][1]; the ground selection transistor GSM[i][J/ belonging to the memory string ST[i][J/2+1]~ST[i][J] The gates of 2+1]~GSM[i][J] are connected to the ground selection line GSL[i][2].
另須留意的是,為便於說明電晶體單元與區域驅動電路LCa、LCb之間的連線關係,此處所繪出之記憶體串列ST[j-1]、ST[j] 的串列選擇電晶體SSM的高度並不相同。然而,在記憶體的製程中,記憶體串列ST[j-1]、ST[j]的串列選擇電晶體SSM的實際高度為等高。 It should also be noted that, in order to facilitate the description of the connection relationship between the transistor unit and the regional driving circuits LCa, LCb, the memory strings ST[j-1], ST[j] drawn here The height of the tandem selection transistor SSM is not the same. However, in the manufacturing process of the memory, the actual height of the memory string ST[j-1] and the string selection transistor STSM of the ST[j] is equal height.
依據記憶體串列ST的連接方式不同,快閃記憶體可分為兩種連接方式:底部源極(bottom source)串列連接方式與U型(U-turn)串列連接方式。本發明的實施例可任意與採用這兩種串列連接方式的快閃記憶體搭配使用。如前所述,記憶體區塊Blk[i]可能包含J個被區分為P組的記憶體串列。對底部源極串列連接方式之而言,因為接地選擇線GSL位於記憶體結構的底層的緣故,在記憶體製程中通常會將記憶體串列區分為兩組,即,P=2。另一方面,對U型串列連接而言,可以利用淺蝕刻的方式將接地選擇線GSL切成任意不同等分(P可為任意正整數),可以在製程中自由地對U型串列連接的記憶體串列加以分組。 According to different connection methods of the memory string ST, the flash memory can be divided into two connection methods: a bottom source serial connection method and a U-turn serial connection method. The embodiments of the present invention can be used arbitrarily with flash memory using these two serial connection methods. As mentioned above, the memory block Blk[i] may contain J memory strings classified into P groups. For the bottom source tandem connection, because the ground selection line GSL is located at the bottom of the memory structure, the memory string is usually divided into two groups during the memory system process, that is, P=2. On the other hand, for U-type tandem connection, the ground selection line GSL can be cut into any different aliquots by shallow etching (P can be any positive integer), and the U-type tandem can be freely used in the manufacturing process The connected memory strings are grouped.
請參見第10A圖,其係電晶體採用底部源極串列連接方式之示意圖。當記憶體串列ST採用底部源極串列連接方式時,每一行電晶體組成一個記憶體串列ST。此圖式包含兩個記憶體串列ST[j]、ST[j+1]。其中,記憶體串列ST[j]包含一個與串列選擇線SSL[j]電連接的串列選擇電晶體SSM、K個分別與字元線WL[j,1]~WL[j,K]電連接的記憶胞電晶體MC,以及一個與接地選擇線GSL[j,p]電連接的接地選擇電晶體GSM[j];記憶體串列ST[j+1]包含一個與串列選擇線SSL[j+1]電連接的串列選擇電晶體SSM、K個分別與字元線WL[j+1,1]~WL[j+1,K]電連接的記憶胞電晶體MC,以及一個與接地選擇線GSL[j+1,p]電連接的接地選擇電晶體GSM[j+1]。在此圖式中,與記憶體串列ST[j]對應的字元線WL[j,1]~WL[j,K]以及與記憶體串列ST[j+1]對應的字元線WL[j+1,1]~WL[j+1,K]分屬於兩組不同的字元 墊WLpad。同樣的,與記憶體串列ST[j]對應的接地選擇線GSL[j,p],以及與記憶體串列ST[j+1]對應的接地選擇線GSL[j+1,p]分屬於兩個獨立的接地選擇層GSL。 Please refer to FIG. 10A, which is a schematic diagram of a transistor using a bottom source tandem connection. When the memory string ST uses the bottom source tandem connection, each row of transistors constitutes a memory string ST. This scheme includes two memory strings ST[j] and ST[j+1]. Among them, the memory string ST[j] includes a string selection transistor SSM electrically connected to the string selection line SSL[j], and K character transistors WL[j,1]~WL[j,K ]Electrically connected memory cell transistor MC, and a ground selection transistor GSM[j] electrically connected to the ground selection line GSL[j,p]; the memory string ST[j+1] includes a serial selection The serial selection transistor SSM electrically connected by the line SSL[j+1] and K memory cell transistors MC electrically connected to the word lines WL[j+1,1]~WL[j+1,K], And a ground selection transistor GSM[j+1] electrically connected to the ground selection line GSL[j+1,p]. In this diagram, the character lines WL[j,1]~WL[j,K] corresponding to the memory string ST[j] and the character lines corresponding to the memory string ST[j+1] WL[j+1,1]~WL[j+1,K] belong to two groups of different characters Pad WLpad. Similarly, the ground selection line GSL[j,p] corresponding to the memory string ST[j] and the ground selection line GSL[j+1,p] corresponding to the memory string ST[j+1] are divided into It belongs to two independent ground selection layers GSL.
請參見第10B圖,其係記憶體串列採用底部源極串列連接方式時的記憶體結構之示意圖。字元墊WLPad與接地選擇層GSL平行設置,且串列選擇線SSL[j]、SSL[j+1]、SSL[j+2]、SSL[j+3]呈現條狀交錯設置在字元墊WLPad與接地選擇層GSL的上方。 Please refer to FIG. 10B, which is a schematic diagram of the memory structure when the memory string is connected with the bottom source string. The character pad WLPad is set in parallel with the ground selection layer GSL, and the tandem selection lines SSL[j], SSL[j+1], SSL[j+2], SSL[j+3] are displayed in stripe interleaved arrangement in the character The pad WLPad is above the ground selection layer GSL.
請參見第11圖,其係記憶體串列採用底部源極串列連接方式時的一個記憶體區塊之俯視圖。記憶體區塊Blk[i]可包含多個串列選擇-字元墊eSSL_WLPad、oSSL_WLPad。其中,串列選擇-字元墊eSSL_WLPad用於形成位於偶數行的串列;串列選擇-字元墊oSSL_WLPad用於形成位於奇數行的串列。串列選擇-字元墊eSSL_WLPad與串列選擇-字元墊oSSL_WLPad彼此間以指狀結構彼此交錯排列。串列選擇-字元墊eSSL_WLPad與串列選擇-字元墊oSSL_WLPad的交錯排列處即為採用底部源極串列連接方式下的區段seg[1]、seg[2]。此外,在記憶體區塊Blk[i]的上方與下方,分別為共用源極板(CSL plate),用於連接接地選擇電晶體GSM的源極。 Please refer to FIG. 11, which is a top view of a memory block when the memory string is connected with the bottom source string. The memory block Blk[i] may contain multiple serial selection-character pads eSSL_WLPad, oSSL_WLPad. Among them, the string selection-character pad eSSL_WLPad is used to form a string in even rows; the string selection-character pad oSSL_WLPad is used to form a string in odd rows. The serial selection-character pad eSSL_WLPad and the serial selection-character pad oSSL_WLPad are staggered with each other in a finger structure. The interleaved arrangement of the serial selection-character pad eSSL_WLPad and the serial selection-character pad oSSL_WLPad is the segment seg[1] and seg[2] in the bottom source serial connection mode. In addition, above and below the memory block Blk[i] are respectively a common source plate (CSL plate) for connecting the source of the ground selection transistor GSM.
請參見第12A圖,其係設置在記憶體區塊Blk[i]之多條閘極控制線GCL的示意圖。如前所述,閘極控制線GCL[i][1]~GCL[i][M]可為串列選擇線SSL、字元線WL或接地選擇線GSL。 Please refer to FIG. 12A, which is a schematic diagram of a plurality of gate control lines GCL provided in the memory block Blk[i]. As described above, the gate control lines GCL[i][1]~GCL[i][M] can be the serial selection line SSL, the word line WL, or the ground selection line GSL.
請參見第12B圖,其係設置在記憶體區塊Blk[i]之全域電源線GPL與浮接線的示意圖。全域電源線GPL[i]以及浮接線 Sfla[i]、Sflb[i]彼此平行設置,且浮接線Sfla[i]、Sflb[i]分別位於全域電源線GPL[i]的兩側。 Please refer to FIG. 12B, which is a schematic diagram of the global power line GPL and the floating wiring provided in the memory block Blk[i]. Global power line GPL[i] and floating wire Sfla[i] and Sflb[i] are arranged parallel to each other, and the floating wires Sfla[i] and Sflb[i] are located on both sides of the global power line GPL[i], respectively.
將第11圖的記憶體區塊Blk[i]、第12A圖的閘極控制線GCL[i][1]~GCL[i][M],以及第12B圖的全域電源線GPL[i]與浮接線Sfla[i]、Sflb[i]組合後,即可得到第13圖所示之與記憶體區塊Blk[i]對應的俯視圖。 Combine the memory block Blk[i] in Figure 11, the gate control lines GCL[i][1] to GCL[i][M] in Figure 12A, and the global power line GPL[i] in Figure 12B When combined with the floating wires Sfla[i] and Sflb[i], the top view corresponding to the memory block Blk[i] shown in FIG. 13 can be obtained.
請參見第14A圖,其係記憶體串列採用U型串列連接方式之示意圖。當記憶體串列採用U型串列連接方式時,每兩行的電晶體共同組成一個記憶體串列。此圖式包含一個記憶體串列ST。其中包含一個與串列選擇線SSL電連接的串列選擇電晶體SSM、K個分別與字元線WL[1]~WL[K]電連接的記憶胞電晶體MC,一個與接地選擇線GSL電連接的接地選擇電晶體GSM;以及兩個傳遞電晶體(pass transistor)IWLS、IWLG。傳遞電晶體IWLS、IWLG並不會用於儲存資料,僅用於在記憶胞電晶體MC之間傳送電位。傳遞電晶體IWLS、IWLG另可稱為反向閘極(inversion gate,簡稱為IG)或反向字元線(inversion word line,簡稱為IWL)。 Please refer to FIG. 14A, which is a schematic diagram of the U-shaped serial connection method of the memory serial. When the memory strings are connected in a U-shaped string, every two rows of transistors together form a memory string. This pattern contains a memory string ST. It includes a serial selection transistor SSM electrically connected to the serial selection line SSL, K memory cell transistors MC electrically connected to the word lines WL[1]~WL[K], and a ground selection line GSL The ground of the electrical connection selects the transistor GSM; and the two pass transistors (IWLS, IWLG). Transmitting transistors IWLS and IWLG are not used to store data, only to transfer potential between memory cell transistors MC. The transfer transistors IWLS and IWLG may also be called an inversion gate (inversion gate, IG for short) or an inversion word line (inversion word line, IWL for short).
串列選擇電晶體SSM的控制端電連接於串列選擇線SSL、一端電連接於由字元線WL[1]控制的記憶胞電晶體MC,另一端電連接於位元線BL。接地選擇電晶體GSM的控制端電連接於接地選擇線GSL、一端電連接由字元線WL[K]控制的記憶胞電晶體MC,另一端電連接於共用源極線CSL。 The control terminal of the serial selection transistor SSM is electrically connected to the serial selection line SSL, one end is electrically connected to the memory cell transistor MC controlled by the word line WL[1], and the other end is electrically connected to the bit line BL. The control terminal of the ground selection transistor GSM is electrically connected to the ground selection line GSL, one end is electrically connected to the memory cell transistor MC controlled by the word line WL[K], and the other end is electrically connected to the common source line CSL.
請參見第14B圖,其係記憶體串列採用U型串列連接方式時的記憶體結構之示意圖。字元墊WLPad與反向閘極層IG平行設置,且串列選擇線SSL[j]、SSL[j+1]、SSL[j+2]、SSL[j+3]、接地選擇線GSL 呈現條狀交錯設置在字元墊WLPad的上方。此處,接地選擇線GSL除了平行於x方向設置外,在其中一側的y方向也彼此相連。 Please refer to FIG. 14B, which is a schematic diagram of the memory structure when the memory string adopts the U-shaped serial connection method. The character pad WLPad is set in parallel with the reverse gate layer IG, and the serial selection lines SSL[j], SSL[j+1], SSL[j+2], SSL[j+3], and the ground selection line GSL Strips are arranged staggered above the character pad WLPad. Here, in addition to the ground selection lines GSL being provided parallel to the x direction, the y direction on one side is also connected to each other.
請參見第15圖,其係記憶體串列採用U型串列連接方式時的一個記憶體區塊之俯視圖。記憶體區塊Blk[i]可包含多個接地-字元墊GSL_WLPad[i][1]、GSL_WLPad[i][2]以及串列-字元墊SSL_WLPad[i][1]。在接地-字元墊GSL_WLPad[i][1]、GSL_WLPad[i][2]、串列-字元墊SSL_WLPad[i][1]之間以指狀結構彼此交錯排列處即為採用U型串列連接方式下的區段seg[i][1]、seg[i][2]。 Please refer to FIG. 15, which is a top view of a memory block when the memory string adopts a U-shaped serial connection method. The memory block Blk[i] may include multiple ground-character pads GSL_WLPad[i][1], GSL_WLPad[i][2], and serial-character pad SSL_WLPad[i][1]. The U-shape is used where the finger structure is interlaced between the ground-character pads GSL_WLPad[i][1], GSL_WLPad[i][2], and the serial-character pad SSL_WLPad[i][1]. Sections seg[i][1] and seg[i][2] in tandem connection.
將第15圖所示之記憶體區塊Blk[i],搭配第12A圖的閘極控制線GCL[i][1]~GCL[i][M],以及第12B圖的全域電源線GPL[i]與浮接線Sfla[i]、Sflb[i]組合後,即可得到第16圖所示之記憶體區塊Blk[i]相對應的俯視圖。 Combine the memory block Blk[i] shown in Figure 15 with the gate control lines GCL[i][1]~GCL[i][M] in Figure 12A, and the global power line GPL in Figure 12B [i] When combined with the floating wires Sfla[i] and Sflb[i], a top view corresponding to the memory block Blk[i] shown in FIG. 16 can be obtained.
接著,進一步說明將本發明的構想應用於多個記憶體區塊的情形。根據本發明的實施例,可將多組全域電源線GPL[i]與浮接線Sfla[i]、Sflb[i]相對應地設置在記憶體裝置的多個記憶體區塊Blk[1]~Blk[I]。 Next, the case where the concept of the present invention is applied to a plurality of memory blocks will be further explained. According to the embodiments of the present invention, multiple sets of global power lines GPL[i] and floating wires Sfla[i] and Sflb[i] can be provided in the plurality of memory blocks Blk[1] of the memory device. Blk[I].
請參見第17圖,其係根據本發明實施例的記憶體裝置,搭配複數個記憶體區塊之示意圖。此圖式可以看出,全域電源線GPL以及浮接線Sfla、Sflb的設置與記憶體區塊Blk之間的關係。 Please refer to FIG. 17, which is a schematic diagram of a memory device according to an embodiment of the present invention, with a plurality of memory blocks. As can be seen from this diagram, the relationship between the setting of the global power line GPL and the floating wires Sfla, Sflb and the memory block Blk.
對記憶體區塊Blk[i-1]而言,解多工電路21輸出區塊選擇信號Ssel[i-1]至預驅動電路PC[i-1],而預驅動電路PC[i-1]電連接於全域電源線GPL[i-1]。全域電源線GPL[i-1]進一步連接至區域驅動模組A LMa[i-1]與區域驅動模組B LMb[i-1]。區域驅動模組A LMa[i]所
包含的區域驅動電路LCa[i-1][1]~LCa[i-1][M],以及區域驅動模組B LMb[i-1]所包含的區域驅動電路LCb[i-1][1]~LCb[i-1][M]分別透過閘極控制線GCL[i-1][1]~GCL[i-1][M]提供電壓至電晶體單元的閘極。
For the memory block Blk[i-1], the
對記憶體區塊Blk[i]而言,解多工電路21輸出區塊選擇信號Ssel[i]至預驅動電路PC[i],而預驅動電路PC[i]電連接於全域電源線GPL[i]。全域電源線GPL[i]進一步連接至區域驅動模組A LMa[i]與區域驅動模組B LMb[i]。區域驅動模組A LMa[i]所包含的區域驅動電路LCa[i][1]~LCa[i][M],以及區域驅動模組B LMb[i]所包含的區域驅動電路LCb[i][1]~LCb[i][M]分別透過閘極控制線GCL[i][1]~GCL[i][M]提供電壓至電晶體單元的閘極。
For the memory block Blk[i], the
此外,區域驅動模組A LMa[i-1]中的區域驅動電路LCa[i-1][1]~LCa[i-1][M]的源極,分別電連接於全域源極線Sgps[1]~Sgps[M];區域驅動模組A LMa[i]中的區域驅動電路LCa[i][1]~LCa[i][M]的源極,分別電連接於全域源極線Sgps[1]~Sgps[M]。另一方面,區域驅動模組B LMb[i-1]中的區域驅動電路LCb[i-1][1]~LCb[i-1][M]的源極,分別電連接於全域源極線Sgps[1]~Sgps[M];區域驅動模組B LMb[i]中的區域驅動電路LCb[i][1]~LCb[i][M]的源極,分別電連接於全域源極線Sgps[1]~Sgps[M]。根據本發明的實施例,區域驅動模組A、B內的區域驅動電路LCa、LCb的汲極均為浮接,且其電位最終將與源極相等。 In addition, the sources of the area driving circuits LCa[i-1][1]~LCa[i-1][M] in the area driving module A LMa[i-1] are electrically connected to the global source lines Sgps [1]~Sgps[M]; the source of the area driving circuit LCa[i][1]~LCa[i][M] in the area driving module A LMa[i] is electrically connected to the global source line Sgps[1]~Sgps[M]. On the other hand, the sources of the area driving circuits LCb[i-1][1]~LCb[i-1][M] in the area driving module B LMb[i-1] are respectively electrically connected to the global sources Line Sgps[1]~Sgps[M]; the source of the regional drive circuit LCb[i][1]~LCb[i][M] in the regional drive module B LMb[i], which are electrically connected to the global source Polar line Sgps[1]~Sgps[M]. According to the embodiment of the present invention, the drains of the regional driving circuits LCa and LCb in the regional driving modules A and B are all floating, and the potentials thereof will eventually be equal to the source.
接著,以第18A、18B圖繪式將本發明的實施例應用於多個記憶體區塊時的俯視圖。由第12~13、15~16圖可以看出,記憶體區塊採用底部源極串列連接方式,或是採用U型串列連接方式時,雖 然就串列選擇線SSL、共用源極線CSL、接地選擇線GSL的位置與連接關係稍有差異,但就字元墊與串列選擇線SSL的位置與相對關係而言均類似。故此處僅以採用U型串列連接方式的多個記憶體區塊Blk為例。 Next, a top view when the embodiment of the present invention is applied to a plurality of memory blocks in drawing Nos. 18A and 18B. As can be seen from Figures 12~13, 15~16, when the memory block adopts the bottom source tandem connection or the U-type tandem connection, although However, the position and connection relationship of the serial selection line SSL, the common source line CSL, and the ground selection line GSL are slightly different, but the position and relative relationship of the character pad and the serial selection line SSL are similar. Therefore, here only a plurality of memory blocks Blk adopting the U-shaped serial connection method are taken as an example.
請參見第18A圖,其係多個採用U型串列連接方式的記憶體區塊之俯視圖。此圖式的記憶體區塊Blk[1]~Blk[I]各自具有多個區段與字元墊。例如,記憶體區塊Blk[1]包含接地-字元墊GSL_WLPad[1][1]、GSL_WLPad[1][2]、GSL_WLPad[1][3]以及串列-字元墊SSL_WLPad[1][1]、SSL_WLPad[1][2]。若屬於同一個記憶體串列的電晶體單元排列為U型串列連接方式時,這些接地-字元墊GSL-WLPad與串列-字元墊SSL_WLPad彼此交錯設置。在這些接地-字元墊GSL_WLPad[i][1]、GSL_WLPad[i][2]與串列-字元墊SSL_WLPad[i][1]之間形成區段seg。例如,記憶體區塊Blk[1]中包含區段seg[1][1]、seg[1][2]、seg[1][3]、seg[1][4]。 Please refer to FIG. 18A, which is a top view of a plurality of memory blocks using a U-shaped serial connection. The memory blocks Blk[1] to Blk[I] of this pattern each have multiple sections and character pads. For example, the memory block Blk[1] includes ground-character pads GSL_WLPad[1][1], GSL_WLPad[1][2], GSL_WLPad[1][3], and serial-character pad SSL_WLPad[1] [1], SSL_WLPad[1][2]. If the transistor units belonging to the same memory string are arranged in a U-shaped serial connection mode, the ground-character pad GSL-WLPad and the serial-character pad SSL_WLPad are interleaved with each other. A segment seg is formed between these ground-character pads GSL_WLPad[i][1], GSL_WLPad[i][2] and the serial-character pad SSL_WLPad[i][1]. For example, the memory block Blk[1] contains the segments seg[1][1], seg[1][2], seg[1][3], seg[1][4].
請參見第18B圖,將第18A圖的記憶體區塊,搭配控制線GCL、全域電源線GPL與浮接線Sfla、Sflb之示意圖。此圖式說明全域電源線GPL[i]與浮接線Sfla[i]、Sflb[i]與記憶體區塊Blk[i],i=1~I之間的對應關係。例如,針對記憶體區塊BLK[1]設置全域電源線GPL[1]與浮接線Sfla[1]、Sflb[1];針對記憶體區塊BLK[2]設置全域電源線GPL[2]與浮接線Sfla[2]、Sflb[2];針對記憶體區塊BLK[I]設置全域電源線GPL[I]與浮接線Sfla[I]、Sflb[I]。 Please refer to FIG. 18B, which is a schematic diagram of the memory block in FIG. 18A, with the control line GCL, the global power line GPL and the floating wires Sfla, Sflb. This diagram illustrates the correspondence between the global power line GPL[i] and the floating wires Sfla[i], Sflb[i] and the memory block Blk[i], i=1~I. For example, for the memory block BLK[1], set the global power line GPL[1] and the floating wires Sfla[1], Sflb[1]; for the memory block BLK[2], set the global power line GPL[2] and Floating wires Sfla[2], Sflb[2]; set global power lines GPL[I] and floating wires Sfla[I], Sflb[I] for the memory block BLK[I].
根據本發明的構想,針對同一個記憶體區塊BLK[i]中的閘極控制線GCL[i][1]~GCL[i][M],設置一條全域電源線GPL[i]以及兩條浮接線Sfla[i]、Sflb[i]。其中,閘極控制線GCL[i][1]~GCL[i][M]可 能是串列選擇線SSL[i][1]~SSL[i][J]、字元線WL[i][1]~WL[i][K]或接地選擇線GSL[i][1]~GSL[i][P]。與閘極控制線GCL[i][1]~GCL[i][M]相連的電晶體單元在各列的數量,會依據閘極控制線GCL[i][1]~GCL[i][M]的不同而異。閘極控制線GCL[i][m]為串列選擇線SSL時,與其相連的串列選擇電晶體SSM的數量為”1”;閘極控制線GCL[i][m]為接地選擇線GSL[i][1]~GSL[i][P]時,與P條接地選擇線分別相連的接地選擇電晶體GSM的數量為”J/P”個。若以N代表記憶體區塊Blk[i]中的位元線BL的數量,則閘極控制線GCL[i][m]為字元線WL[i][k]時,與其相連的記憶胞電晶體MC的數量為”N”。 According to the idea of the present invention, for the gate control lines GCL[i][1]~GCL[i][M] in the same memory block BLK[i], a global power line GPL[i] and two Strip floating wires Sfla[i], Sflb[i]. Among them, the gate control line GCL[i][1]~GCL[i][M] can Can be serial selection line SSL[i][1]~SSL[i][J], character line WL[i][1]~WL[i][K] or ground selection line GSL[i][1 ]~GSL[i][P]. The number of transistor cells connected to the gate control line GCL[i][1]~GCL[i][M] in each column will depend on the gate control line GCL[i][1]~GCL[i][ M] varies. When the gate control line GCL[i][m] is the serial selection line SSL, the number of the serial selection transistor SSM connected to it is "1"; the gate control line GCL[i][m] is the ground selection line When GSL[i][1]~GSL[i][P], the number of ground selection transistors GSM respectively connected to P ground selection lines is "J/P". If N represents the number of bit lines BL in the memory block Blk[i], then the gate control line GCL[i][m] is the word line WL[i][k], the memory connected to it The number of cell transistors MC is "N".
綜上所述,本發明可透過設置全域電源線GPL[1]、GPL[2]...GPL[I]的方式,達到快速提升被選取之記憶體區塊的閘極控制線GCL的電壓的效果。換言之,原本因為字元墊面積增加所引發之電阻電容延遲的現象,可藉由此種補償方式而降低其影響。 In summary, the present invention can quickly increase the voltage of the gate control line GCL of the selected memory block by setting the global power lines GPL[1], GPL[2]...GPL[I] Effect. In other words, the phenomenon of resistance and capacitance delay caused by the increase of the character pad area can be reduced by this compensation method.
綜上所述,雖然本發明已以實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。 In summary, although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be deemed as defined by the scope of the attached patent application.
20:記憶體裝置 20: Memory device
21:解多工電路 21: Demultiplexing circuit
23:預驅動模組 23: Pre-drive module
25a:區域驅動組A 25a: Regional drive group A
25b:區域驅動組B 25b: Regional drive group B
29:頁緩衝電路 29: Page buffer circuit
27:記憶體陣列 27: memory array
GPL[1]~GPL[I]:全域電源線 GPL[1]~GPL[I]: Global power cord
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5619162A (en) * | 1990-09-12 | 1997-04-08 | Kabushiki Kaisha Toshiba | Dram using word line potential circuit control |
US20010014042A1 (en) * | 1998-05-26 | 2001-08-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device, semiconductor memory device and semiconductor integrated circuit device |
US20020018386A1 (en) * | 1995-08-18 | 2002-02-14 | Tsukasa Ooishi | Semiconductor circuit device with reduced power consumption in slow operation mode |
TW512352B (en) * | 2000-06-13 | 2002-12-01 | Advanced Micro Devices Inc | Method to reduce capacitive loading in flash memory x-decoder for accurate voltage control at wordlines and select lines |
US20060098523A1 (en) * | 1998-06-29 | 2006-05-11 | Fujitsu Limited | Semiconductor memory device capable of driving non-selected word lines to first and second potentials |
US20150179271A1 (en) * | 2013-12-19 | 2015-06-25 | Sang-Wan Nam | Nonvolatile memory device and method of erasing nonvolatile memory device |
-
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- 2019-02-13 TW TW108104790A patent/TWI686806B/en active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5619162A (en) * | 1990-09-12 | 1997-04-08 | Kabushiki Kaisha Toshiba | Dram using word line potential circuit control |
US20020018386A1 (en) * | 1995-08-18 | 2002-02-14 | Tsukasa Ooishi | Semiconductor circuit device with reduced power consumption in slow operation mode |
US20010014042A1 (en) * | 1998-05-26 | 2001-08-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device, semiconductor memory device and semiconductor integrated circuit device |
US20060098523A1 (en) * | 1998-06-29 | 2006-05-11 | Fujitsu Limited | Semiconductor memory device capable of driving non-selected word lines to first and second potentials |
TW512352B (en) * | 2000-06-13 | 2002-12-01 | Advanced Micro Devices Inc | Method to reduce capacitive loading in flash memory x-decoder for accurate voltage control at wordlines and select lines |
US20150179271A1 (en) * | 2013-12-19 | 2015-06-25 | Sang-Wan Nam | Nonvolatile memory device and method of erasing nonvolatile memory device |
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