TWI686806B - Memory device - Google Patents

Memory device Download PDF

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TWI686806B
TWI686806B TW108104790A TW108104790A TWI686806B TW I686806 B TWI686806 B TW I686806B TW 108104790 A TW108104790 A TW 108104790A TW 108104790 A TW108104790 A TW 108104790A TW I686806 B TWI686806 B TW I686806B
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memory
electrically
line
driving
transistor
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TW108104790A
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Chinese (zh)
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TW202030734A (en
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葉騰豪
劉逸青
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旺宏電子股份有限公司
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Abstract

A memory device is provided. The memory device includes I memory blocks, a plurality of transistor units, I global power lines and I first local driving modules. Each of the memory blocks includes M gate control lines and the transistor units being arranged in M rows. The I global power lines are respectively electrically connected to I pre-driving circuits and I memory blocks. Each of the first local driving modules is electrically connected to each of the global power lines and each of the memory blocks. A first local driving module includes M first local drivers. The m-th first local driver is electrically connected to the m-th gate control line.

Description

Memory device

The present invention relates to a memory device, and in particular to a memory device that uses a global power line to provide a high voltage to a memory block.

Please refer to Figure 1, which is a schematic diagram of a three-dimensional memory structure. The three-dimensional memory has multiple layers of character pads WLPad, which are stacked in the vertical direction (z direction). The character pads WLPad[k-1], WLPak[k] and the ground selection layer GSL have multiple finger structures on both sides. In addition, the parallel strip-shaped tandem selection lines SSL[j-1], SSL[j], and SSL[j+1] are provided above the corresponding positions of the character line WL. The bit lines BL[n], BL[n+1] are not only connected above the serial selection lines SSL[j-1], SSL[j], SSL[j+1], but also parallel to the bottom. Direction extends. The intersection of each bit line BL[n], BL[n+1] and the serial selection line SSL[j-1], SSL[j], SSL[j+1] is a serial selection transistor (serial selection transistor (SSM), the intersection of the bit lines BL[n], BL[n+1] and the word line WL is a memory cell (MC); the bit line BL[n ] The intersection of BL[n+1] and the ground selection layer GSL is a ground selection transistor (Ground selection transistor, GSM for short). Herein, the direction parallel to the serial selection line SSL is defined as the x direction; and the direction parallel to the bit line BL is defined as the y direction.

Please refer to FIG. 2, which is a schematic diagram of the global character line GWL and the character pad WLPad in the three-dimensional memory structure. In a three-dimensional memory structure, the character line WL may contain global characters Line (global word line, GWL for short) GWL[k-1], GWL[k], GWL[k+1], and the character pad WLPad set corresponding to the memory block (Block, for short Blk) k-1], WLPad[k], WLPad[k+1]. Among them, the character pads WLPad[k-1], WLPad[k], WLPad[k+1] are overlapped with each other in a stair structure, and the global character lines GWL[k-1], GWL[k] , GWL[k+1] are electrically connected to the multi-layer character pads WLPad[k-1], WLPad[k], WLPad[k+1], respectively.

In these character lines WL, the global character lines GWL[k-1], GWL[k], and GWL[k+1] using metal wires have very small resistance R and capacitance C, and use poly-silicon (poly-silicon) The character pads WLPad[k-1], WLPad[k], WLPad[k+1] have larger resistance R and capacitance C. Therefore, for the word line WL, the resistance capacitance delay (RC delay) mainly depends on the areas of the word pads WLPad[k-1], WLPad[k], and WLPad[k+1].

Based on the consideration of increasing the capacity of the memory device, it is often necessary to increase the number of character pads WLPad[k-1], WLPad[k], WLPad[k+1]. Due to process limitations, the size of the ladder structure used to connect the character pads WLPad[k-1], WLPad[k], WLPad[k+1] to the character line WL cannot follow the character pad WLPad[k- 1], WLPad[k], WLPad[k+1] layers increase and shrink. In other words, as the number of layers of character pads WLPad[k-1], WLPad[k], WLPad[k+1] increases, the area required for the ladder structure increases, and the character pads WLPad[k-1], WLPad The area of [k] and WLPad[k+1] also increases. However, the larger the area of the character pads WLPad[k-1], WLPad[k], and WLPad[k+1], the longer the resistance capacitance delay of the word line WL. In FIG. 2, the finger intersecting portion of the character pad is defined as a segment 10. When charging the word line WL, the main source of resistance capacitance delay is the section 10 between the two character pads WLPad[k-1], WLPad[k], WLPad[k+1]. In other words, the resistance of the word line WL is delayed by the size of the segment 10.

Please refer to Figures 3A and 3B, which are schematic diagrams of increasing the area of the character pad WLPad as the memory capacity increases, thereby increasing the capacitance C and resistance R of the character pad. Please also refer to Figures 3A and 3B. Figure 3A shows that when the number of character pad layers WLPad is less, the area of the character pad WLPad and the area occupied by the ladder structure STR1 are smaller; Figure 3B shows When the number of character pad layers WLPad is large, the area of the character pad WLPad and the area occupied by the step structure STR2 are both large. It can be seen from this that the increase in the area of the character pads WLPad[k-1], WLPad[k], WLPad[k+1] is equivalent to making the cross-character pads WLPad[k-1], WLPad[k], The capacitance C between WLPad[k+1] increases, and the resistance R of each character pad WLPad[k-1], WLPad[k], WLPad[k+1] itself also increases.

For NAND flash memory, when programming the memory block Blk (erase operation or write operation), it is necessary to provide a high voltage (for example, 20V~25V) through the word line WL. However, as the resistance R and capacitance C of the character pad WLPad increase, the resistance-capacitance delay effect will become more obvious. In other words, it is less easy for the memory controller to quickly pull up the word line WL to the required voltage.

The invention relates to a memory device, which provides a high voltage for the selected memory block by correspondingly setting a global power line in the memory block, so that the voltage of the word line WL can be quickly raised.

According to one aspect of the present invention, a memory device is proposed. The memory device includes: 1 memory block, 1 global power cord, and 1 first area driving module. The ith memory block of the I memory blocks includes: M gate control lines, and a plurality of transistor units. The transistor cells in the memory block are arranged in M rows, with the median The gates of the transistor cells in the mth column are electrically connected to the mth gate control line among the gate control lines. I global power lines are electrically connected to one pre-driving circuit and one memory block, respectively. One first area driving module is electrically connected to one global power line and one memory block, respectively. Wherein, the ith first area driving module in the I first area driving modules is electrically connected to the ith global power line and the ith memory block in the I global power lines. The i-th first-region driving module includes: M first-region driving circuits. The M first region driving circuits are electrically connected to the ith global power line, and the mth first region driving circuit among the M first region driving circuits is electrically connected to the mth gate control line. Among them, m, M, i and I are all positive integers, m is less than or equal to M, and i is less than or equal to I.

In order to have a better understanding of the above and other aspects of the present invention, the following examples are specifically described in conjunction with the accompanying drawings as follows:

MC: memory cell transistor

GSL: ground selection layer

GSM, GSM[i][j], GSM[i][j-1], GSM[i][1]~GSM[i][J/2], GSM[i][J/2+1]~ GSM[i][J], GSM[j], GSM[j+1]: ground select transistor

SSL[j-1], SSL[j], SSL[j+1], SSL[i][j]: serial selection line

SSM: tandem selection transistor

BL[n], BL[n+1]: bit line

C, C1, C2: capacitance

WLPad[k-1], WLPad[k], WLPad[k+1]: character pad

WL[k], WL[1], WL[K], WL[2], WL[3], WL[4], WL[5], WL[j,1], WL[j,K], WL [j+1,1], WL[j+1,K], WL[K/2], WL[K/2+1], WL[K-1]: character line

GWL[k-1], GWL[k], GWL[k+1]: global character line

10. seg[i][1], seg[i][2], seg[1][1], seg[i][2], seg[i][3], seg[i][4]: Section

STR1, STR2: ladder structure

20: Memory device

21: Demultiplexing circuit

23: Pre-drive module

25a: Regional drive group A

25b: Regional drive group B

27: memory array

29: Page buffer circuit

GPL[1]~GPL[I], GPL[i]: global power cord

LMa[1], LMa[I], LMa[i], LMa[i-1]: regional drive module

LMb[1], LMb[I], LMa[i], LMb[i-1]: regional drive module

Sin: input line (signal)

BLK[1], BLK[I], BLK[i], BLK[2]: memory blocks

Ssel[1], Ssel[2], Ssel[I], Ssel[i]: block selection line (signal)

Sfla[1], Sflb[1], Sfla[I], Sflb[I], Sfla[i], Sflb[i]: floating wire

GCL[1][1]~GCL[1][M], GCL[I][1]~GCL[I][M], GCL[i][1]~GCL[i][M], GCL[ i-1][1], GCL[i-1][M]: gate control line

PC[i], PC[i-1]: pre-driving circuit

Spre[1]~Spre[I], Spre[i]: pre-drive voltage

LCa[i][1], LCa[i][2], LCa[i][3], LCa[i][M-1], LCa[i][M], LCb[i][1], LCb[i][2], LCb[i][3], LCb[i][M-1], LCb[i][M], LCa[i][4], LCa[i][5], LCb[i][4], LCb[i][5]: regional driving circuit

ST[i][j-1], ST[i][j], ST[j], ST[j+1]: memory sequence

GSL[i][p], GSL[j,p], GSL[j+1,p], GSL: ground selection line

M1, M2, M3: pre-drive transistor

Vpp: the first power supply voltage

Vss: second power supply voltage

i1, i2: displacement current

Npre: pre-charge node

GSL_WLPad[i][1], GSL_WLPad[i][2], GSL_WLPad[1][1], GSL_WLPad[1][2], GSL_WLPad[1][3]: ground-character pad

SSL_WLPad[i][1], SSL_WLPad[1][1], SSL_WLPad[1][2], SSL_WLPad[1][3]: serial-character pad

Figure 1 is a schematic diagram of a three-dimensional memory structure.

Figure 2 is a schematic diagram of the global character line GWL and the character pad WLPad in the three-dimensional memory structure.

Figures 3A and 3B are schematic diagrams of increasing the area of the character pad WLPad as the memory capacity increases, thereby increasing the capacitance C and resistance R of the character pad.

FIG. 4 is a schematic diagram of a memory device according to an embodiment of the invention.

FIG. 5 is a schematic diagram of a memory device according to an embodiment of the present invention, in which a global power line GPL connection relationship is provided in a plurality of memory blocks.

Figure 6, which uses the memory block Blk[i] as an example to illustrate the corresponding between the pre-driving circuit PC[i], the area driving module LMa[i], and the area driving module LMb[i] Schematic diagram of the connection relationship.

7A and 7B are schematic diagrams of the operation modes of the pre-driving circuit.

FIG. 8 is an example of using the word line as the gate control line GCL, and illustrates a schematic diagram of setting the global power line GPL in the three-dimensional memory structure.

FIG. 9 is a schematic diagram illustrating how the global power line GPL is connected to the serial selection transistor SSM and the memory cell transistor MC through the gate control line GCL.

FIG. 10A is a schematic diagram of the bottom source tandem connection method of the memory string.

FIG. 10B is a schematic diagram of the memory structure when the memory series adopts the bottom source series connection method.

Fig. 11 is a top view of a memory block when the memory string is connected with the bottom source string.

FIG. 12A is a schematic diagram of a plurality of gate control lines GCL provided in a memory block.

FIG. 12B is a schematic diagram of the global power line GPL and floating wiring provided in a memory block.

Figure 13 is a schematic diagram of the memory block shown in Figure 11 with the gate control line GCL in Figure 12A, and the global power line GPL and floating wiring in Figure 12B.

Fig. 14A is a schematic diagram of the U-shaped serial connection method of the memory serial.

FIG. 14B is a schematic diagram of the memory structure when the memory string adopts the U-shaped serial connection method.

Figure 15 is a top view of a memory block when the memory string is connected in a U-shaped string.

FIG. 16 is a schematic diagram of the memory block shown in FIG. 15 in combination with the gate control line GCL in FIG. 12A, and the global power line GPL and floating wiring in FIG. 12B.

FIG. 17 is a schematic diagram of a memory device according to an embodiment of the present invention, with a plurality of memory blocks.

Figure 18A is a top view of multiple memory blocks.

Figure 18B is a schematic diagram of the memory block of Figure 18A, with the gate control line GCL, the global power line GPL and the floating wiring.

Please refer to FIG. 4, which is a schematic diagram of a memory device according to an embodiment of the present invention. The memory device 20 includes: a demultiplexing circuit 21, a pre-driving module 23, a regional driving group A 25a, a regional driving group B 25b, a page buffer circuit 29, one global power line GPL[1]~GPL[I],与记忆Memory27。 For ease of description, it is assumed here that the memory array 27 includes memory blocks Blk[1] to Blk[I], and each memory block Blk includes one or more memory pages. Wherein, each memory block Blk[1]~Blk[I] corresponds to the global power line GPL[1]~GPL[I], respectively. For example, the memory block Blk[i] corresponds to the global power line GPL[i].

The demultiplexing circuit 21 is electrically connected to the pre-driving module 23, and the pre-driving module 23 is electrically connected to the regional driving group A 25a and the regional driving group B 25b through one global power line GPL. The page buffer circuit 29 is electrically connected to the memory array 27. For ease of explanation, the following will Each wiring and the signal on the wiring are represented by the same symbol. For example, Ssel is used to indicate the block selection line and block selection signal, and the other signals and wiring are also marked in the same way.

Referring to FIG. 5, which is a schematic diagram of a memory device according to an embodiment of the present invention, a global power line GPL is provided between a regional driving module and a memory block. The demultiplexing circuit 21 has one input line Sin and one block selection line Ssel[1]~Ssel[I]. The demultiplexing circuit 21 receives the input signal Sin from the memory controller and determines which of the memory blocks Blk[1] to Blk[I] is used for access. Therefore, the block selection signals Ssel[1]~Ssel[I] generated by the demultiplexing circuit 21 respectively correspond to the memory blocks Blk[1]~Blk[I].

When the block selection signal Ssel[i] represents that the memory block Blk[i] is selected, the i-th block selection line Ssel[i] has a first logic level (for example, a logic low level L). When the block selection signal Ssel[i] represents that the memory block Blk[i] is not selected, the block selection line Ssel[i] has a second logic level (for example, a logic high level H).

The pre-drive module 23 includes pre-drive circuits PC[1]~PC[I], which are used to receive block selection signals Ssel[1]~Ssel corresponding to the memory blocks Blk[1]~Blk[I], respectively. [I]. The pre-drive circuits PC[1]~PC[I] receive the block selection signals Ssel[1]~Ssel[I], respectively corresponding to the output pre-drive voltages Spre[1]~Spre[I].

According to the concept of the present invention, for each memory block Blk[1]~Blk[J], a global power line GPL[1]~GPL[I] is provided respectively. These global power lines GPL[1]~GPL[I] are used to transmit the pre-drive voltages Spre[1]~Spre[I]. In addition, on both sides of each global power line GPL[1]~GPL[I], floating wires Sfla and Sflb are respectively provided. For example, floating wires Sfla[1] and Sflb[1] are provided on both sides of the global power line GPL[1]; and floating wires Sfla[I] and Sflb[I are provided on both sides of the global power line GPL[I] ]. In addition, each memory block Blk[1]~Blk[J] contains M gate controls Line GCL. For example, the memory block Blk[1] contains the gate control line GCL[1][1]~GCL[1][M]; the memory block Blk[I] contains the gate control line GCL[I][1 ]~GCL[I][M].

The regional driving group A 25a includes the regional driving modules LMa[1]~LMa[I] corresponding to the memory blocks Blk[1]~Blk[I]; the regional driving group B 25b includes the memory block Blk[ 1]~Blk[I] corresponds to the regional drive module LMb[1]~LMb[I]. The regional driving modules LMa[1]~LMa[I] receive the pre-driving voltage Spre[1] generated by the pre-driving circuits PC[1]~PC[I] via the global power lines GPL[1]~GPL[I], respectively. Spre[I], and the regional drive modules LMb[1]~LMb[I] receive the pre-drivers generated by the pre-drive circuits PC[1]~PC[I] via the global power lines GPL[1]~GPL[I] Voltage Spre[1]~Spre[I].

Please refer to FIG. 6, which takes the memory block Blk[i] as an example to illustrate the corresponding pre-driving circuit PC[i], area driving module LMa[i], area driving module LMb[i] Schematic diagram of the connection relationship between. The memory block Blk[i] is electrically connected to the pre-driving circuit PC[i] via the global power line GPL[i]. In addition, floating wires Sfla[i] and Sflb[i] are also provided on both sides of the global power line GPL[i].

The regional driving module LMa[i] contains M regional driving circuits LCa[i][1]~LCa[i][M]; the regional driving module LMB[i] contains M regional driving circuits LCb[i][1 ]~LCb[i][M]. The regional driving circuits LCa[i][1]~LCa[i][M] are connected to the global power line GPL[i] through a common wiring; and, the regional driving circuits LCb[i][1]~LCb[i][ M] is connected to the global power line GPL[i] through another common wiring.

The memory block Blk[i] includes: gate control lines GCL[i][1]~GCL[i][M]. Among them, part of the gate control lines GCL[i][1]~GCL[i][M] is the serial selection line SSL[i][1]~SSL[i][J], and part is the character line WL [1]~WL[K], and a part of the ground selection line GSL[i][1]~GSL[i][P] (Section 6 The figure only draws the formula GSL[i][p]). The regional driving circuits LCa[i][1]~LCa[i][M] are electrically connected to the gate control lines GCL[i][1]~GCL[i][M]; the regional driving circuit LCb[i][ 1]~LCb[i][M] are also electrically connected to the gate control lines GCL[i][1]~GCL[i][M], respectively.

The pre-drive circuits PC[1]~PC[I] have similar structures to each other, and here only the pre-drive circuit PC[i] is taken as an example. The pre-drive circuit PC[i] includes: pre-drive transistors M1, M2, M3. Among them, the pre-driving transistors M1, M2, M3 are high-voltage-resistant transistors. The pre-driving transistor M1 is a PMOS transistor, the pre-driving transistors M2 and M3 are NMOS transistors, and the pre-driving transistor M2 is a depletion mode transistor. The pre-driving transistor M3 may be a general NMOS transistor or a triple well NMOS transistor.

The pre-driving transistor M1 is electrically connected to the block selection line Ssel[i]; the pre-driving transistor M2 is electrically connected to the pre-driving transistor M1 and the global power line GPL[i]. The pre-driving transistor M2 receives the first power supply voltage Vpp from the first voltage source Vpp. The pre-drive transistor M3 is electrically connected to the pre-drive transistor M1 and the global power line GPL[i]. The pre-drive transistor M3 receives the second power supply voltage Vss from the second voltage source Vss. The source terminal and the base terminal of the pre-driving transistor M1 are electrically connected to each other, and the drain terminal of the pre-driving transistor M1 and the gate terminal of the pre-driving transistor M2 are electrically connected to the global power line GPL[i].

In the embodiment of the present invention, the first power voltage Vpp is higher than the read voltage Vrd of the memory, the write voltage Vwr of the memory, and the erase voltage Vers of the memory. The second power supply voltage Vss is lower than the memory read voltage Vrd, the memory write voltage Vwr, and the memory erase voltage Vers. In some applications, the read voltage Vrd and the erase voltage Vers may be lower than the ground voltage (0V). At the same time, the second power supply voltage Vss is a negative voltage. Since the second power supply voltage Vss is still maintained at the lowest potential, abnormal forward turn-on of the transistor can be avoided. In addition, all bases are connected to a negative voltage Vss All NMOS transistors need to use triple-well NMOS transistors, such as regional drive circuits LCa, LCb and pre-drive transistor M3. Accordingly, it is possible to avoid affecting other NMOS transistors of the same memory device.

Before any one of the memory blocks Blk[1]~Blk[I] is selected by the memory controller, the block selection lines Ssel[1]~Ssel[I] output by the demultiplexing circuit 21 have a logic high level H. Assuming that the input signal Sin produced by the memory controller represents the case of selecting the memory block Blk[i], the block selection line Ssel[i] output by the demultiplexing circuit 21 is a logic low level L, and the block selection line Ssel[1]~Ssel[i-1], Ssel[i+1]~Ssel[I] are logic high level H. The logic high level H may be 4V, and the logic low level L may be 0V.

Please refer to FIGS. 7A and 7B, which are schematic diagrams of operation modes of the pre-driving circuit PC[i] corresponding to the memory block Blk[i]. Among them, FIG. 7A is a case where the memory block Blk[i] is not selected; FIG. 7B is a case where the memory block Blk[i] is selected. As can be seen from FIGS. 7A and 7B, regardless of whether the memory block Blk[i] is selected, the pre-drive transistor M1 maintains receiving the first power supply voltage Vpp (for example, 30V), and the pre-drive transistor M3 maintains receiving the first Two power supply voltage Vss.

In FIG. 7A, the pre-drive transistor M3 receives the second power supply voltage Vss for pre-charging; the pre-drive transistor M1 receives the first power supply voltage Vpp, and the voltage of the pre-charge node Npre is the second power supply voltage Vss. Because the block selection line Ssel[i] has a logic high level H, the pre-driving transistor M1 remains off, and the pre-driving transistor M2 also remains off. At this time, only the pre-drive transistor M3 is turned on.

Therefore, when the memory block Blk[i] is not selected, the pre-drive circuit PC[i] generates a displacement current i1 due to the imbalance of internal charges. Therefore, the voltage (pre-driving voltage) Spre[i] on the pre-driving signal line connected to the pre-charging node Npre is transmitted to the global power line through the pre-driving transistor M3 The second power supply voltage Vss of GPL[i]. In conjunction, the two regional drive modules LMa[i] and LMb[i] corresponding to the memory block Blk[i] receive the second power supply voltage Vss from the global power supply line GPL[i]. Therefore, the memory block Blk[i] does not perform various memory operations. Incidentally, the displacement current i1 will not continue to be generated. Once the potential reaches equilibrium (Spre=Vss), the displacement current i1 will disappear.

In FIG. 7B, the pre-drive transistor M3 receives the second power supply voltage Vss for pre-charging; the pre-drive transistor M1 receives the first power supply voltage Vpp, and the voltage of the pre-charge node Npre is the second power supply voltage Vss at the beginning . When the block selection line Ssel[i] has a logic low level L, because the pre-driving transistor M2 is a depleted transistor, the threshold voltage Vth is less than 0V, so that the pre-driving transistor M2 is partially turned on.

For the pre-drive transistor M1, because the gate receives the voltage of the low logic level L, and the source gradually receives the first power supply voltage Vpp through the pre-drive transistor M2, the pre-drive transistor M1 will start to form a weak conduction (weak turn-on). When the pre-driving transistor M1 is turned on, the source voltage of the pre-driving transistor M1 will be transmitted to the drain of the pre-driving transistor M1, that is, the pre-charge node Npre. The voltage of the pre-charge node Npre will affect the gate voltage of the pre-drive transistor M2, making the pre-drive transistor M2 more fully on, thus forming a positive feedback of the on-current between the pre-drive transistors M1, M2 (positive feedback) effect.

At this time, the pre-drive transistors M1 and M2 are turned on, and the voltage of the pre-charge node Npre is raised to the first power supply voltage Vpp. At the same time, the pre-drive transistor M3 is turned off. In this case, the gate of the pre-driving transistor M1 is connected to 0V, and the source and the N-well of the pre-driving transistor M1 are connected to the first power supply voltage Vpp. Therefore, the pre-driving transistor M1 needs to use a transistor with a higher breakdown voltage body. For example, the thickness of the gate oxide layer of the pre-drive transistor M1 needs to be thicker than that of a general PMOS transistor.

When the memory block Blk[i] is selected, the pre-drive circuit PC[i] generates a displacement current i2. Therefore, the voltage (pre-driving voltage) Spre[i] on the pre-driving signal line connected to the pre-charging node Npre is the first power supply voltage Vpp. Since the pre-drive signal line Spre[i] is connected to the global power line GPL[i], the two regional drive modules LMa[i] and LMb[i] corresponding to the memory block Blk[i] will be switched from The global power line GPL[i] receives the first power voltage Vpp. Therefore, the memory controller can control the selected memory block Blk[i] to perform various memory operations.

As described above, when the block selection line Ssel[i] output from the demultiplexing circuit 21 has a logic low level L, it means that the memory block Blk[i] is selected. At this time, the pre-drive circuit PC[i] outputs the first power voltage Vpp to the global power line GPL[i] corresponding to the memory block Blk[i]. When the block selection line Ssel[i] output from the demultiplexing circuit 21 has a logic high level H, it means that the memory block Blk[i] is not selected. At this time, the pre-drive circuit PC[i] outputs the second power voltage Vss to the global power line GPL[i] corresponding to the memory block Blk[i].

Since the first power supply voltage Vpp is the highest voltage provided by the memory device, in order to avoid the high voltage of the global power supply line GPL[i] corresponding to the selected memory block Blk[i] and the surrounding signal line from being too large The pressure difference of the device will further destroy the structure of the memory. In the embodiment of the present invention, floating wires Sfla[i] and Sflb[i] are also provided on both sides of the global power line GPL[i]. The setting of the floating wires Sfla[i] and Sflb[i] can slightly alleviate the possible impact of the global power line GPL[i] with high voltage on other signal lines around it.

Please refer to FIG. 8, which is a ladder structure of a character pad WLPad, illustrating a schematic diagram of setting a global power line GPL in a three-dimensional memory. The demultiplexing circuit 21 is electrically connected to the pre-driving circuit PC[i] through the block selection line Ssel[i], and the pre-driving circuit PC[i] It is electrically connected to the regional driving module LMa[i] and the regional driving module LMb[i] through the global power line GPL[i]. The output level of the pre-drive circuit PC[i] is the pre-drive voltage Spre[i] of the first power supply voltage Vpp or the second power supply voltage Vss to the global power supply line GPL[i]. It is assumed here that the regional driving module LMa[i] includes the regional driving circuit LCa[i][1]~LCa[i][5], and the regional driving module LMb[i] includes the regional driving circuit LCb[i][1 ]~LCb[i][5]. Among them, the regional driving circuit LCa[i][1] and the regional driving circuit LCb[i][1] are electrically connected to the character pad WLPad[i][1] in the ladder structure; the regional driving circuit LCa[i][ 2] It is electrically connected to the character pad WLPad[i][2] in the ladder structure together with the regional driving circuit LCb[i][2]; the rest can be deduced by analogy.

As mentioned above, in addition to the word lines WL[1]~WL[K], part of the gate control lines GCL[1]~GCL[M] can select the serial selection lines SSL[1]~SSL[J ] And the ground selection line GSL[i][1]~GSL[i][P]. The jth memory string ST[i][j] of the memory block Blk[i] contains the string selection transistor SSM[i][j] and K memory cell transistors MC[i] [j][1]~MC[i][j][K], and a ground selection transistor GSM[i][j]. Memory cell transistors MC[i][j][1]~MC[i][j][K] can be non-volatile memories such as floating gate transistors or charge trapping devices. In practical application, there is no need to limit the types of memory cell transistors MC[i][j][1]~MC[i][j][K].

Please refer to FIG. 9, which is a schematic diagram of how the global power line GPL[i] is connected to the serial selection transistor SSM and the memory cell transistor MC through the gate control line GCL. This diagram briefly illustrates the relationship between the transistor unit in the memory block Blk[i] and various wiring.

The memory block Blk[i] contains the memory string ST[i][1]~ST[i][J], here only the memory string ST[i in the memory block Blk[i] ][j-1] and memory string ST[i][j] as an example. The memory string ST[i][j-1] includes: the string selection transistor SSM[i][j-1], and K memory cells connected to the word line WL[1]~WL[K] Crystal MC[i][j-1][1]~MC[i][j-1][K], a ground selection transistor GSM[i][j-1]. The memory string ST[i][j] includes: a string selection transistor SSM[i][j], and K memory cell transistors MC[i connected to the word line WL[1]~WL[K] ][j][1]~MC[i][j][K], ground select transistor GSM[i][j].

Accordingly, the memory string ST[i][j] (where j=1~J) in the memory block Blk[i] corresponds to a string selection transistor SSM[i][j], K One memory cell transistor MC[i][j][1]~MC[i][j][K], and one ground selection transistor GSM[i][j]. The gates of the ground selection transistors GSM[i][j-1] and GSM[i][j] in different series of the memory block Blk[i] are connected to P ground selection lines GSL[i] [1]~GSL[i][P]. For ease of explanation, it is assumed here that P=1. In addition, the ground selection transistors GSM[i][j-1] and GSM[i][j] in different series of the memory block Blk[i] are electrically connected to the same common source line (common source) line)CSL[i].

On the other hand, if P≠1, then J memory strings may be divided into P string groups, where J may be greater than or equal to P. The gates of the ground selection transistors GSM[i][j] in the memory series belonging to the same series group are connected to the same ground selection line GSL[i][p]. For example, assuming that J is even and P=2, J memory strings can be divided into 2 string groups. Among them, the first serial group contains memory series ST[i][1]~ST[i][J/2]; the second serial group contains memory series ST[i][J/2 +1]~ST[i][J]. Accordingly, the ground selection transistors belonging to the memory series ST[i][1]~ST[i][J/2] select the gate of the transistor GSM[i][1]~GSM[i][J/2] Commonly connected to the ground selection line GSL[i][1]; the ground selection transistor GSM[i][J/ belonging to the memory string ST[i][J/2+1]~ST[i][J] The gates of 2+1]~GSM[i][J] are connected to the ground selection line GSL[i][2].

It should also be noted that, in order to facilitate the description of the connection relationship between the transistor unit and the regional driving circuits LCa, LCb, the memory strings ST[j-1], ST[j] drawn here The height of the tandem selection transistor SSM is not the same. However, in the manufacturing process of the memory, the actual height of the memory string ST[j-1] and the string selection transistor STSM of the ST[j] is equal height.

According to different connection methods of the memory string ST, the flash memory can be divided into two connection methods: a bottom source serial connection method and a U-turn serial connection method. The embodiments of the present invention can be used arbitrarily with flash memory using these two serial connection methods. As mentioned above, the memory block Blk[i] may contain J memory strings classified into P groups. For the bottom source tandem connection, because the ground selection line GSL is located at the bottom of the memory structure, the memory string is usually divided into two groups during the memory system process, that is, P=2. On the other hand, for U-type tandem connection, the ground selection line GSL can be cut into any different aliquots by shallow etching (P can be any positive integer), and the U-type tandem can be freely used in the manufacturing process The connected memory strings are grouped.

Please refer to FIG. 10A, which is a schematic diagram of a transistor using a bottom source tandem connection. When the memory string ST uses the bottom source tandem connection, each row of transistors constitutes a memory string ST. This scheme includes two memory strings ST[j] and ST[j+1]. Among them, the memory string ST[j] includes a string selection transistor SSM electrically connected to the string selection line SSL[j], and K character transistors WL[j,1]~WL[j,K ]Electrically connected memory cell transistor MC, and a ground selection transistor GSM[j] electrically connected to the ground selection line GSL[j,p]; the memory string ST[j+1] includes a serial selection The serial selection transistor SSM electrically connected by the line SSL[j+1] and K memory cell transistors MC electrically connected to the word lines WL[j+1,1]~WL[j+1,K], And a ground selection transistor GSM[j+1] electrically connected to the ground selection line GSL[j+1,p]. In this diagram, the character lines WL[j,1]~WL[j,K] corresponding to the memory string ST[j] and the character lines corresponding to the memory string ST[j+1] WL[j+1,1]~WL[j+1,K] belong to two groups of different characters Pad WLpad. Similarly, the ground selection line GSL[j,p] corresponding to the memory string ST[j] and the ground selection line GSL[j+1,p] corresponding to the memory string ST[j+1] are divided into It belongs to two independent ground selection layers GSL.

Please refer to FIG. 10B, which is a schematic diagram of the memory structure when the memory string is connected with the bottom source string. The character pad WLPad is set in parallel with the ground selection layer GSL, and the tandem selection lines SSL[j], SSL[j+1], SSL[j+2], SSL[j+3] are displayed in stripe interleaved arrangement in the character The pad WLPad is above the ground selection layer GSL.

Please refer to FIG. 11, which is a top view of a memory block when the memory string is connected with the bottom source string. The memory block Blk[i] may contain multiple serial selection-character pads eSSL_WLPad, oSSL_WLPad. Among them, the string selection-character pad eSSL_WLPad is used to form a string in even rows; the string selection-character pad oSSL_WLPad is used to form a string in odd rows. The serial selection-character pad eSSL_WLPad and the serial selection-character pad oSSL_WLPad are staggered with each other in a finger structure. The interleaved arrangement of the serial selection-character pad eSSL_WLPad and the serial selection-character pad oSSL_WLPad is the segment seg[1] and seg[2] in the bottom source serial connection mode. In addition, above and below the memory block Blk[i] are respectively a common source plate (CSL plate) for connecting the source of the ground selection transistor GSM.

Please refer to FIG. 12A, which is a schematic diagram of a plurality of gate control lines GCL provided in the memory block Blk[i]. As described above, the gate control lines GCL[i][1]~GCL[i][M] can be the serial selection line SSL, the word line WL, or the ground selection line GSL.

Please refer to FIG. 12B, which is a schematic diagram of the global power line GPL and the floating wiring provided in the memory block Blk[i]. Global power line GPL[i] and floating wire Sfla[i] and Sflb[i] are arranged parallel to each other, and the floating wires Sfla[i] and Sflb[i] are located on both sides of the global power line GPL[i], respectively.

Combine the memory block Blk[i] in Figure 11, the gate control lines GCL[i][1] to GCL[i][M] in Figure 12A, and the global power line GPL[i] in Figure 12B When combined with the floating wires Sfla[i] and Sflb[i], the top view corresponding to the memory block Blk[i] shown in FIG. 13 can be obtained.

Please refer to FIG. 14A, which is a schematic diagram of the U-shaped serial connection method of the memory serial. When the memory strings are connected in a U-shaped string, every two rows of transistors together form a memory string. This pattern contains a memory string ST. It includes a serial selection transistor SSM electrically connected to the serial selection line SSL, K memory cell transistors MC electrically connected to the word lines WL[1]~WL[K], and a ground selection line GSL The ground of the electrical connection selects the transistor GSM; and the two pass transistors (IWLS, IWLG). Transmitting transistors IWLS and IWLG are not used to store data, only to transfer potential between memory cell transistors MC. The transfer transistors IWLS and IWLG may also be called an inversion gate (inversion gate, IG for short) or an inversion word line (inversion word line, IWL for short).

The control terminal of the serial selection transistor SSM is electrically connected to the serial selection line SSL, one end is electrically connected to the memory cell transistor MC controlled by the word line WL[1], and the other end is electrically connected to the bit line BL. The control terminal of the ground selection transistor GSM is electrically connected to the ground selection line GSL, one end is electrically connected to the memory cell transistor MC controlled by the word line WL[K], and the other end is electrically connected to the common source line CSL.

Please refer to FIG. 14B, which is a schematic diagram of the memory structure when the memory string adopts the U-shaped serial connection method. The character pad WLPad is set in parallel with the reverse gate layer IG, and the serial selection lines SSL[j], SSL[j+1], SSL[j+2], SSL[j+3], and the ground selection line GSL Strips are arranged staggered above the character pad WLPad. Here, in addition to the ground selection lines GSL being provided parallel to the x direction, the y direction on one side is also connected to each other.

Please refer to FIG. 15, which is a top view of a memory block when the memory string adopts a U-shaped serial connection method. The memory block Blk[i] may include multiple ground-character pads GSL_WLPad[i][1], GSL_WLPad[i][2], and serial-character pad SSL_WLPad[i][1]. The U-shape is used where the finger structure is interlaced between the ground-character pads GSL_WLPad[i][1], GSL_WLPad[i][2], and the serial-character pad SSL_WLPad[i][1]. Sections seg[i][1] and seg[i][2] in tandem connection.

Combine the memory block Blk[i] shown in Figure 15 with the gate control lines GCL[i][1]~GCL[i][M] in Figure 12A, and the global power line GPL in Figure 12B [i] When combined with the floating wires Sfla[i] and Sflb[i], a top view corresponding to the memory block Blk[i] shown in FIG. 16 can be obtained.

Next, the case where the concept of the present invention is applied to a plurality of memory blocks will be further explained. According to the embodiments of the present invention, multiple sets of global power lines GPL[i] and floating wires Sfla[i] and Sflb[i] can be provided in the plurality of memory blocks Blk[1] of the memory device. Blk[I].

Please refer to FIG. 17, which is a schematic diagram of a memory device according to an embodiment of the present invention, with a plurality of memory blocks. As can be seen from this diagram, the relationship between the setting of the global power line GPL and the floating wires Sfla, Sflb and the memory block Blk.

For the memory block Blk[i-1], the demultiplexing circuit 21 outputs the block selection signal Ssel[i-1] to the pre-drive circuit PC[i-1], and the pre-drive circuit PC[i-1 ]Electrically connected to the global power line GPL[i-1]. The global power line GPL[i-1] is further connected to the regional driving module A LMa[i-1] and the regional driving module B LMb[i-1]. Regional drive module A LMa[i] The included regional driving circuits LCa[i-1][1]~LCa[i-1][M], and the regional driving circuit LCb[i-1][ included in the regional driving module B LMb[i-1] 1]~LCb[i-1][M] provides voltage to the gate of the transistor unit through the gate control lines GCL[i-1][1]~GCL[i-1][M].

For the memory block Blk[i], the demultiplexing circuit 21 outputs the block selection signal Ssel[i] to the pre-drive circuit PC[i], and the pre-drive circuit PC[i] is electrically connected to the global power line GPL [i]. The global power line GPL[i] is further connected to the regional driving module A LMa[i] and the regional driving module B LMb[i]. The area driving circuit LCa[i][1]~LCa[i][M] included in the area driving module A LMa[i], and the area driving circuit LCb[i] included in the area driving module B LMb[i] ][1]~LCb[i][M] provides voltage to the gate of the transistor unit through the gate control lines GCL[i][1]~GCL[i][M].

In addition, the sources of the area driving circuits LCa[i-1][1]~LCa[i-1][M] in the area driving module A LMa[i-1] are electrically connected to the global source lines Sgps [1]~Sgps[M]; the source of the area driving circuit LCa[i][1]~LCa[i][M] in the area driving module A LMa[i] is electrically connected to the global source line Sgps[1]~Sgps[M]. On the other hand, the sources of the area driving circuits LCb[i-1][1]~LCb[i-1][M] in the area driving module B LMb[i-1] are respectively electrically connected to the global sources Line Sgps[1]~Sgps[M]; the source of the regional drive circuit LCb[i][1]~LCb[i][M] in the regional drive module B LMb[i], which are electrically connected to the global source Polar line Sgps[1]~Sgps[M]. According to the embodiment of the present invention, the drains of the regional driving circuits LCa and LCb in the regional driving modules A and B are all floating, and the potentials thereof will eventually be equal to the source.

Next, a top view when the embodiment of the present invention is applied to a plurality of memory blocks in drawing Nos. 18A and 18B. As can be seen from Figures 12~13, 15~16, when the memory block adopts the bottom source tandem connection or the U-type tandem connection, although However, the position and connection relationship of the serial selection line SSL, the common source line CSL, and the ground selection line GSL are slightly different, but the position and relative relationship of the character pad and the serial selection line SSL are similar. Therefore, here only a plurality of memory blocks Blk adopting the U-shaped serial connection method are taken as an example.

Please refer to FIG. 18A, which is a top view of a plurality of memory blocks using a U-shaped serial connection. The memory blocks Blk[1] to Blk[I] of this pattern each have multiple sections and character pads. For example, the memory block Blk[1] includes ground-character pads GSL_WLPad[1][1], GSL_WLPad[1][2], GSL_WLPad[1][3], and serial-character pad SSL_WLPad[1] [1], SSL_WLPad[1][2]. If the transistor units belonging to the same memory string are arranged in a U-shaped serial connection mode, the ground-character pad GSL-WLPad and the serial-character pad SSL_WLPad are interleaved with each other. A segment seg is formed between these ground-character pads GSL_WLPad[i][1], GSL_WLPad[i][2] and the serial-character pad SSL_WLPad[i][1]. For example, the memory block Blk[1] contains the segments seg[1][1], seg[1][2], seg[1][3], seg[1][4].

Please refer to FIG. 18B, which is a schematic diagram of the memory block in FIG. 18A, with the control line GCL, the global power line GPL and the floating wires Sfla, Sflb. This diagram illustrates the correspondence between the global power line GPL[i] and the floating wires Sfla[i], Sflb[i] and the memory block Blk[i], i=1~I. For example, for the memory block BLK[1], set the global power line GPL[1] and the floating wires Sfla[1], Sflb[1]; for the memory block BLK[2], set the global power line GPL[2] and Floating wires Sfla[2], Sflb[2]; set global power lines GPL[I] and floating wires Sfla[I], Sflb[I] for the memory block BLK[I].

According to the idea of the present invention, for the gate control lines GCL[i][1]~GCL[i][M] in the same memory block BLK[i], a global power line GPL[i] and two Strip floating wires Sfla[i], Sflb[i]. Among them, the gate control line GCL[i][1]~GCL[i][M] can Can be serial selection line SSL[i][1]~SSL[i][J], character line WL[i][1]~WL[i][K] or ground selection line GSL[i][1 ]~GSL[i][P]. The number of transistor cells connected to the gate control line GCL[i][1]~GCL[i][M] in each column will depend on the gate control line GCL[i][1]~GCL[i][ M] varies. When the gate control line GCL[i][m] is the serial selection line SSL, the number of the serial selection transistor SSM connected to it is "1"; the gate control line GCL[i][m] is the ground selection line When GSL[i][1]~GSL[i][P], the number of ground selection transistors GSM respectively connected to P ground selection lines is "J/P". If N represents the number of bit lines BL in the memory block Blk[i], then the gate control line GCL[i][m] is the word line WL[i][k], the memory connected to it The number of cell transistors MC is "N".

In summary, the present invention can quickly increase the voltage of the gate control line GCL of the selected memory block by setting the global power lines GPL[1], GPL[2]...GPL[I] Effect. In other words, the phenomenon of resistance and capacitance delay caused by the increase of the character pad area can be reduced by this compensation method.

In summary, although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be deemed as defined by the scope of the attached patent application.

20: Memory device

21: Demultiplexing circuit

23: Pre-drive module

25a: Regional drive group A

25b: Regional drive group B

29: Page buffer circuit

27: memory array

GPL[1]~GPL[I]: Global power cord

Claims (9)

  1. A memory device includes: 1 memory block, wherein an i-th memory block of the 1 memory block includes: M gate control lines; and a plurality of transistor units, arranged It is column M, in which the gates of the transistor units located in column m are electrically connected to an mth gate control line among the gate control lines; I global power lines are respectively electrically connected to Each of the I memory blocks; an I first area drive module, which are electrically connected to each of the I global power lines and each of the I memory blocks, wherein the I first area drive module An i-th first area driving module is electrically connected to an i-th global power line in the I global power line and the i-th memory block, and the i-th first area driving module The system includes: M first-region driving circuits, which are electrically connected to the i-th global power line, and an m-th first-region driving circuit among the M first-region driving circuits is electrically connected to the first m gate control lines, where m, M, i, and I are positive integers, m is less than or equal to M, and i is less than or equal to I; and a demultiplexing circuit with an input line and I block selection Line, wherein each of the I block selection lines corresponds to each of the I memory blocks, and the demultiplexing circuit determines the I block selection lines based on an input signal received from the input line Logic level, wherein one of the I block selection lines has a first logic level, and (I-1) of the I block selection lines has a second logic level; and, A pre-drive module, electrically connected to the demultiplexing circuit, includes: I pre-driving circuits are electrically connected to each of the I block selection lines and each of the I first area driving modules, wherein each of the I pre-driving circuits is based on the logic of the I block selection lines The level generates 1 pre-driving voltage, and each of the 1 pre-driving voltage is transmitted to each of the 1 first area driving modules.
  2. The memory device as described in item 1 of the patent application scope, wherein, when the input signal represents that the i-th memory block is selected, one of the i-block selection lines is the i-th block selection line Having the first logic level, and the ith global power line has a first power voltage; and when the input signal represents that the ith memory block is not selected, the ith block is selected The line has the second logic level, and the i-th global power line has a second power voltage, wherein the first power voltage is higher than a read voltage, a write voltage, and an erase voltage, and the The second power supply voltage is lower than the read voltage, the write voltage and the erase voltage.
  3. The memory device as described in item 2 of the patent application range, wherein an i-th pre-driving circuit of the I pre-driving circuits includes: a first pre-driving transistor electrically connected to the i-th block A selection line; a second pre-driving transistor electrically connected to the first pre-driving transistor and the ith global power line, wherein the second pre-driving transistor system receives the first power supply from a first voltage source Voltage; and A third pre-driving transistor is electrically connected to the first pre-driving transistor and the ith global power line, wherein the third pre-driving transistor system receives the second power voltage from a second voltage source.
  4. The memory device of claim 3, wherein when the i-th block selection line has the first logic level, the first pre-driving transistor and the second pre-driving transistor are conductive , And the third pre-driving transistor is off, wherein the first power supply voltage is transmitted to the i-th global power line through the second pre-driving transistor and the first pre-driving transistor; and when the When the i-th block selection line has the second logic level, the first pre-driving transistor and the second pre-driving transistor are off, and the third pre-driving transistor is on, wherein the second power supply The voltage is transmitted to the ith global power line through the third pre-driving transistor.
  5. The memory device as described in item 1 of the patent application scope, wherein the transistor units include J*K memory cell transistors, J tandem transistors, and J ground selection transistors, wherein the memories The cell transistor system is arranged in J rows and K columns, and the gate control lines include: J tandem selection lines, which are electrically connected to the gates of each of the J tandem transistors; K word lines , Where a k-th word line of the K word lines is electrically connected to the gates of J memory cell transistors located on a k-th line of the K column; and P ground selection lines, The gates electrically connected to each of the J ground selection transistors, where M=(J+K+P), K is greater than J, and J is greater than or equal to P, where J, K, and P are positive integers.
  6. The memory device as described in item 1 of the patent application range, wherein the i-th first region driving module is a region transistor, and the gate of the region transistor is electrically connected to the i-th global power line And the source of the transistor in this area is electrically connected to the m-th gate control line.
  7. The memory device as described in item 1 of the patent application scope, wherein the memory device further includes 2*I floating wires, wherein each of the I memory blocks corresponds to two of the floating wires.
  8. The memory device as described in item 7 of the patent application scope, wherein the two floating wires corresponding to the i-th memory block are provided on both sides of the i-th global power line.
  9. The memory device as described in item 1 of the patent application scope, further comprising: one second area driving module electrically connected to each of the I global power lines and each of the I memory blocks, wherein the An ith second area drive module among the I second area drive modules is electrically connected to the ith global power line and the ith memory block, and the ith second area drive The module includes: M second region driving circuits, which are electrically connected to the i-th global power line, and an m-th second region driving circuit among the M second region driving circuits is electrically connected to the The mth gate control line, wherein the i-th first area driving module is located on one side of the i-th memory block, and the i-th second area driving module is located on the i-th memory The other side of the volume.
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* Cited by examiner, † Cited by third party
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US5619162A (en) * 1990-09-12 1997-04-08 Kabushiki Kaisha Toshiba Dram using word line potential circuit control
US20020018386A1 (en) * 1995-08-18 2002-02-14 Tsukasa Ooishi Semiconductor circuit device with reduced power consumption in slow operation mode
US20010014042A1 (en) * 1998-05-26 2001-08-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor device, semiconductor memory device and semiconductor integrated circuit device
US20060098523A1 (en) * 1998-06-29 2006-05-11 Fujitsu Limited Semiconductor memory device capable of driving non-selected word lines to first and second potentials
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