KR20120058380A - Nonvolatile semiconductor memory device and control method thereof - Google Patents

Abstract

PURPOSE: A nonvolatile semiconductor memory device and a controlling method thereof are provided to perform an erasing operation in a sub block by a potential difference between a body and a word line. CONSTITUTION: One end of a selection transistor in a drain side is connected to a first end of a memory string. One end of a selection transistor in a source side is connected to a second end of the memory string. A plurality of word lines(WL1-WL8) are commonly connected to a plurality of memory strings. A control circuit applies a first voltage to a bit line and a source line, applies a second voltage to a word line, and applies a third voltage to a selection gate line in the drain side and a selection gate line in the source side.

Description

Nonvolatile semiconductor memory device and control method thereof {NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF}

This application is based on Japanese Patent Application No. 2010-264872 (November 29, 2010), which claims its priority, the entire contents of which are incorporated herein by reference.

Embodiments described herein relate to a nonvolatile semiconductor memory device and a control method thereof.

Conventionally, LSIs have been formed by integrating devices in a two-dimensional plane on a silicon substrate. In order to increase the memory capacity of a memory, it is common to reduce the size of one element (miniaturize), but in recent years, the miniaturization thereof has become difficult and technically difficult. In order to miniaturize, the technology of photolithography needs to be improved, but the cost of the lithography process is increasing. In addition, even if miniaturization is achieved, it is expected to meet physical limitations such as breakdown voltage between the elements as long as the driving voltage and the like are not scaled. In addition, with the miniaturization, the distance between the memory elements becomes closer, so that the adverse effect of the capacitive coupling between the memory elements in operation increases. That is, there is a high possibility that operation as a device becomes difficult. Therefore, in recent years, many nonvolatile semiconductor memory devices (layered nonvolatile semiconductor memory devices) in which memory cells are three-dimensionally disposed in order to increase the degree of integration of memory have been proposed.

One conventional semiconductor memory device in which memory cells are three-dimensionally arranged is a semiconductor memory device using a transistor having a cylindrical structure. In a semiconductor memory device using a columnar transistor, a multi-layer polysilicon and a pillar-shaped pillar-shaped semiconductor serving as a gate electrode are provided. The columnar semiconductor is arranged to penetrate the polysilicon layer, and a memory cell is formed at the intersection thereof. In this memory cell, the columnar semiconductor functions as a channel (body) portion of the transistor. Around the columnar semiconductor, a plurality of charge accumulation layers are formed via a tunnel insulating layer and accumulate charges. In addition, a block insulating layer is formed around the charge storage layer. Thus, the structure containing polysilicon, a columnar semiconductor, a tunnel insulation layer, a charge accumulation layer, and a block insulation layer forms the memory string which connected the memory cells in series.

In a conventional semiconductor memory device in which such memory cells are three-dimensionally arranged, an erase operation is performed in units of memory blocks that are sets of memory strings in which word lines are commonly connected. In the conventional stacked semiconductor memory device, with the increase in the number of stacked layers, there is a problem that the number of word lines commonly connected to a plurality of memory strings in one memory block increases, and the number of memory cells included in one memory block increases. Therefore, there is a demand for a stacked semiconductor memory device capable of selectively erasing only a part of memory cells in a memory block, not in units of memory blocks.

An embodiment of the present invention provides a stacked nonvolatile semiconductor memory device capable of selectively performing an erase operation in a memory block, and a control method thereof.

The nonvolatile semiconductor memory device of the embodiment described below includes a memory cell array having a plurality of memory blocks. In each of the plurality of memory blocks, a plurality of memory strings formed by connecting a plurality of memory transistors arranged in a matrix and electrically rewritable in series are arranged. One end of the drain side select transistor is connected to the first end of the memory string, while one end of the source side select transistor is connected to the second end of the memory string. The plurality of word lines are arranged to be commonly connected to the plurality of memory strings arranged in one of the plurality of memory blocks. Further, a plurality of bit lines extend in the first direction, respectively, and are commonly connected to the other ends of the drain side selection transistors present in the plurality of memory blocks. The source line is connected to the other end of the source side select transistor. The drain side selection gate line is arranged with the second direction in the longitudinal direction so as to commonly connect the gates of the drain side selection transistors arranged in a second direction orthogonal to the first direction. The source side select gate line is disposed with the second direction in the longitudinal direction so as to commonly connect the gates of the source side select transistors arranged in the second direction. The control circuit controls voltages applied to the plurality of memory blocks.

Each of the plurality of memory strings includes a columnar portion extending in a direction perpendicular to the substrate, and is formed to surround a columnar semiconductor layer functioning as a body of the memory transistor, and a side surface of the columnar portion, and accumulate charge. And a word line conductive layer formed so as to surround the side surface of the columnar portion via the charge accumulation layer, and functioning as a gate of the memory transistor and the word line. A plurality of drain side select transistors commonly connected to one of said drain side select gate lines and one said source side select gate line and a plurality of said memory strings connected to a plurality of source side select transistors constitute a sub block. When the control circuit performs an erase operation for selectively erasing at least one subblock of the memory blocks, in the selected first subblock, the control circuit applies a first voltage to the bit line and the source line, while applying a first voltage to the word line. A second voltage smaller than one voltage is applied. The erase operation is performed by applying a third voltage lower than the first voltage to the drain select gate line and the source select gate line by a predetermined value. On the other hand, in the second sub-block present in the same memory block as the selected sub-block and not selected, the erase operation is performed by applying a fourth voltage approximately equal to the first voltage to the drain-side select gate line and the source-side select gate line. Do not do it.

According to the embodiment of the present invention, a stacked nonvolatile semiconductor memory device capable of selectively performing an erase operation in a memory block and a control method thereof can be provided.

1 is a circuit diagram showing an overall configuration of a nonvolatile semiconductor memory device according to the first embodiment.
FIG. 2 is a schematic perspective view of the memory cell array AR1 of FIG. 1.
FIG. 3A is an equivalent circuit diagram showing a circuit configuration of the memory cell array AR1 of FIG. 1.
3B is a schematic cross-sectional view of the memory block MB in the memory cell array AR1 of FIG. 1.
3C is a schematic cross-sectional view of another memory cell array.
4 is a schematic cross-sectional view of the memory unit MU in one memory block MB.
5 is a plan view of one memory block MB;
6 is a diagram showing an erase operation in the first embodiment;
Fig. 7 is a diagram showing an erase operation in the first embodiment.
8 is a diagram showing an erase operation in the first embodiment;
9A is an example of a charge pump circuit and a voltage value adjustment circuit suitable for generating various voltages of the first embodiment.
9B is an example of the row decoder 2A used in the first embodiment.
Fig. 10 is a circuit diagram of the entire configuration of a nonvolatile semiconductor memory device according to the second embodiment.
FIG. 11 is a schematic perspective view of the memory cell array AR1 of FIG. 10.
12 is a schematic cross-sectional view of one memory block MB of the memory cell array AR1 of FIG. 10.
Fig. 13 is a schematic cross-sectional view of one memory unit MU of one memory block MB.
Fig. 14 is a diagram showing an erase operation in the second embodiment.
Fig. 15A is a diagram showing an erase operation in the second embodiment.
Fig. 15B is a diagram showing an erase operation in the second embodiment.
Fig. 16A is a diagram showing an erase operation in a modification of the second embodiment.
FIG. 16B is a diagram showing an erase operation in a modification of the second embodiment. FIG.
17A is an example of a charge pump circuit and a voltage value adjustment circuit suitable for generating various voltages of the second embodiment.
17B is an example of the row decoder 2A used in the second embodiment.
18A is a circuit diagram of the entire configuration of a nonvolatile semiconductor memory device according to the third embodiment.
18B is an example of the row decoder 2A used in the third embodiment.
Fig. 19A is a circuit diagram of the entire configuration of a nonvolatile semiconductor memory device according to the fourth embodiment.
Fig. 19B is a circuit diagram of the overall configuration of a modification of the nonvolatile semiconductor memory device according to the fourth embodiment.
20 is a schematic perspective view of the memory cell array AR1 of FIG. 19.
21 is a schematic cross-sectional view of one memory block MB of memory cell array AR1 of FIG. 19;
Fig. 22A is a diagram showing the operation of the nonvolatile semiconductor memory device according to the fifth embodiment.
Fig. 22B is a view showing the operation of a modification of the nonvolatile semiconductor memory device according to the fifth embodiment.
Fig. 23 is an example of a charge pump circuit suitable for generating various voltages of the fifth embodiment.
24 is a circuit diagram of the entire configuration of a nonvolatile semiconductor memory device according to the sixth embodiment.
25 is a schematic perspective view of the memory cell array AR1 of FIG. 24.
FIG. 26 is a schematic cross-sectional view of the memory block MB in the memory cell array AR1 of FIG. 24.
27 is a diagram showing an erase operation in the sixth embodiment;
Fig. 28 is a diagram showing an erase operation in the sixth embodiment.
29 is an example of a charge pump circuit and a voltage value adjustment circuit suitable for generating various voltages according to a sixth embodiment.
30 is a circuit diagram of the entire configuration of a nonvolatile semiconductor memory device according to the seventh embodiment.
FIG. 31 is a schematic perspective view of the memory cell array AR1 of FIG. 30.
32 is a diagram showing an erase operation in the seventh embodiment;
33 is a diagram showing an erase operation in the seventh embodiment;

EMBODIMENT OF THE INVENTION Hereinafter, with reference to drawings, embodiment of the nonvolatile semiconductor memory device which concerns on this invention, and its control method is demonstrated.

[First Embodiment]

First, with reference to FIG. 1, the whole structure of the nonvolatile semiconductor memory device which concerns on 1st Embodiment is demonstrated. 1 is a circuit diagram of a nonvolatile semiconductor memory device according to the first embodiment.

As shown in FIG. 1, the nonvolatile semiconductor memory device according to the first embodiment includes the row decoders 2A and 2B, the sense amplifier circuit 3, and the column decoder 4 provided in the memory cell array AR1 and its periphery. ) And control circuit AR2.

As shown in FIG. 1, the memory cell array AR1 is configured by arranging a plurality of memory strings MS in which electrically rewritable memory transistors MTr1 to 8 (memory cells) are connected in series. The control circuit AR2 is comprised of various control circuits which control the voltage supplied to the gates of the memory transistors MTr (MTr1 to 8) and the like.

The row decoders 2A and 2B are disposed on the left and right sides of the memory cell array AR1, respectively, and drive the word line WL, the selection gate line SGD, SGS and the back gate line BG in accordance with the address signal from the control circuit AR2. The column decoder 4 selects an address for writing and reading in accordance with the address signal supplied from the control circuit AR4. The sense amplifier circuit 3 determines the data stored in the memory cell during the read operation. Further, the bit line BL and the source line SL are driven in accordance with the address signal supplied from the control circuit AR2 through the column decoder.

The control circuit AR2 includes a driver 201 for driving the word line WL, the selection gate line SGD, SGS, and the back gate line BL, a driver 202 for driving the bit line BL, the source line SL, and a power supply voltage. A charge pump circuit 203 and an address decoder 204 for boosting up are provided.

The control circuit AR2 performs an operation of writing data to the memory transistor MTr, an erase operation of erasing data of the memory transistor MTr, and an operation of reading data from the memory transistor MTr. In the write operation and the read operation, the voltage applied to the selected memory string MS is substantially the same as that of the conventional stacked flash memory.

The memory cell array AR1 has a memory block MB of m columns as shown in FIG. Each memory block MB has, for example, memory units MU arranged in a matrix form in n rows and 2 columns. The memory unit MU includes a memory string MS, a source side select transistor SSTr2 connected to the source side of the memory string MS, a drain side select transistor SDTr2 connected to the drain side of the memory string MS, and a back gate transistor BTr. In addition, in the example shown in FIG. 1, the 1st column of the memory unit MU is described as sub-block SB1, and the 2nd column is described as sub-block SB2. In FIG. 1, the case where two sub-blocks SB1 and SB2 exist in one memory block MB is explained, but it is not limited to this, Of course, three or more sub-blocks may be provided in one memory block MB. .

The m memory blocks MB share the same bit line BL. That is, the bit line BL extends in the column direction shown in FIG. 1 and is connected to a plurality of memory units MUs (drain-side selection transistors SDTr) arranged in line in the column direction among the m memory blocks MB. In each memory block MB, two memory units MU arranged in the column direction are commonly connected to the same bit line BL.

In each memory block MB, 2 x n memory units MU share a word line WL and a back gate line BG. In addition, the n memory units MU (that is, the memory units MU in one sub-block) arranged in the row direction share the selection gate line SGD and the selection gate line SGS. That is, the plurality of drain side select transistors SDTr and the plurality of source side select transistors SSTr connected in common to one drain side select gate line SGD and one source side select gate line SGS are connected to one Configure the sub block.

As shown in the schematic perspective view of FIG. 2, the memory cell array AR1 is configured by arranging memory transistors MTr for electrically storing data in a three-dimensional matrix shape. That is, the memory transistor MTr is arranged in a matrix shape in the horizontal direction and also in the stacking direction (the direction perpendicular to the substrate). The plurality of memory transistors MTr1 to 8 arranged in the stacking direction are connected in series and constitute the above-described memory string MS. To determine the selection / non-selection of the memory string MS, the drain side selection transistor SDTr2 is connected to one end of the memory string MS, and the source side selection transistor SSTr2 is connected to the other end. This memory string MS is arranged with the stacking direction in the longitudinal direction. In addition, the detailed laminated structure is demonstrated later.

Next, the circuit configuration of the memory cell array AR1 will be described in detail with reference to FIG. 3A. 3A is an equivalent circuit diagram of the memory cell array AR1.

The memory cell array AR1 has a plurality of bit lines BL and a plurality of memory blocks MB as shown in Fig. 3A. The bit lines BL are formed in a stripe shape arranged with a predetermined pitch in the row direction and extending in the column direction in the longitudinal direction. The memory block MB is provided repeatedly in the column direction with a predetermined pitch.

The memory block MB has a plurality of memory units MUs arranged in a matrix in the row direction and the column direction as shown in Fig. 3A. In the memory block MB, a plurality of memory units MUs connected in common are provided in one bit line BL. The memory unit MU has a memory string MS, a source side select transistor SSTr2 and a drain side select transistor SDTr2. The memory units MU are arranged in a matrix in the row direction and the column direction.

The memory string MS is composed of memory transistors MTr1 to 8 and back gate transistor BTr connected in series. The memory transistors MTr1 to 4 are connected in series in the stacking direction. The memory transistors MTr5 to 8 are similarly connected in series in the stacking direction. The threshold voltages of the memory transistors MTr1 to 8 are changed by changing the amount of charge accumulated in the charge storage layer. By changing the threshold voltage, data held by the memory transistors MTr1 to 8 can be rewritten. The back gate transistor BTr is connected between the lowermost memory transistor MTr4 and the memory transistor MTr5. Therefore, the memory transistors MTr1 to MTr8 and the back gate transistor BTr are connected in a U shape in a cross section along the column direction. The drain of the source side select transistor SSTr2 is connected to one end of the memory string MS (the source of the memory transistor MTr8). The source of the drain side selection transistor SDTr2 is connected to the other end of the memory string MS (drain of the memory transistor MTr1).

The gates of the 2xn memory transistors MTr1 in one memory block MB are commonly connected to one word line WL1 extending in the row direction. Similarly, the gates of the 2xn memory transistors MTr2 to 8 are commonly connected to one word line WL2 to 8 extending in the row direction, respectively. In addition, the gates of the 2xn back gate transistors BTr arranged in a matrix in the row direction and the column direction are commonly connected to the back gate line BG.

The gates of the n source side select transistors SSTr2 arranged in a row in the row direction are commonly connected to one source side select gate line SGS2 extending in the row direction. The source of the source side select transistor SSTr2 is connected to the source line SL extending in the row direction.

The gates of the n drain side select transistors SDTr2 arranged in a row in the row direction are commonly connected to one drain side select gate line SGD2 extending in the row direction. The drain of the drain side select transistor SDTr2 is connected to the bit line BL extending in the column direction.

Next, with reference to FIG. 3B, FIG. 4, and FIG. 5, the laminated structure of the nonvolatile semiconductor memory device which concerns on 1st Embodiment is demonstrated. 3B is a schematic cross-sectional view of the column direction of the memory block MB. 4 is a schematic sectional view of one memory unit MU, and FIG. 5 is a plan view of the memory block MB.

As shown in FIG. 3B, the memory cell array AR1 includes a back gate transistor layer 20, a memory transistor layer 30, a selection transistor layer 40, and a wiring layer 50 on the substrate 10. The back gate transistor layer 20 functions as a back gate transistor BTr. The memory transistor layer 30 functions as memory transistors MTr1 to 8 (memory string MS). The select transistor layer 40 functions as a source side select transistor SSTr2 and a drain side select transistor SDTr2. The wiring layer 50 functions as a source line SL and a bit line BL.

The back gate transistor layer 20 has a back gate conductive layer 21 as shown in FIG. 4. The back gate conductive layer 21 functions as a back gate line BG and functions as a gate of the back gate transistor BTr.

The back gate conductive layer 21 is formed to expand two-dimensionally in the row direction and the column direction parallel to the substrate 10. The back gate conductive layer 21 is divided for each memory block MB. The back gate conductive layer 21 is made of polysilicon (poly-Si).

The back gate conductive layer 20 has a back gate hole 22 as shown in FIG. The back gate hole 22 is formed to dig the back gate conductive layer 21. The back gate hole 22 is formed in the substantially rectangular shape which makes a column direction the longitudinal direction seen from the upper surface. The back gate hole 22 is formed in matrix form in a row direction and a column direction.

The memory transistor layer 30 is formed on the upper layer of the back gate conductive layer 20 as shown in FIG. 4. The memory transistor layer 30 has word line conductive layers 31a to 31d. The word line conductive layers 31a to 31d function as word lines WL1 to 8, respectively, and function as gates of the memory transistors MTr1 to 8, respectively.

The word line conductive layers 31a to 31d are laminated with an interlayer insulating layer (not shown). The word line conductive layers 31a to 31d are formed to have a predetermined pitch in the column direction and extend in the row direction in the longitudinal direction. The word line conductive layers 31a to 31d are made of polysilicon (poly-Si).

The memory transistor layer 30 has a memory hole 32 as shown in FIG. 3B. The memory holes 32 are formed to penetrate through the word line conductive layers 31a to 31d and an interlayer insulating layer (not shown). The memory holes 32 are formed to match near the end portions of the back gate holes 22 in the column direction.

3B shows an example in which two memory strings MS arranged in the bit line BL direction are commonly connected to the same word line wiring layers 31a to 31d, but are arranged in the bit line BL direction as shown in FIG. 3C. A configuration in which the memory string MS to be connected is connected to the word line wiring layers 31a to 31d separated from each other for each memory string MS can also be adopted.

In addition, the back gate transistor layer 20 and the memory transistor layer 30 have a memory gate insulating layer 33 and a memory semiconductor layer 34 as shown in FIG. The memory semiconductor layer 34 functions as a body of the memory transistors MTr1 to MTr8 (memory string MS).

As shown in FIG. 4, the memory gate insulating layer 33 is formed to have a predetermined thickness on the side surfaces of the back gate hole 22 and the memory hole 32. The memory gate insulating layer 33 has a block insulating layer 33a, a charge accumulation layer 33b, and a tunnel insulating layer 33c. As the charge storage layer 33b accumulates electric charges, the threshold voltages of the memory transistors MTr1 to 8 are changed, whereby data held by the memory transistor MTr can be rewritten.

As shown in FIG. 4, the block insulating layer 33a is formed on the side surfaces of the back gate hole 22 and the memory hole 32 with a predetermined thickness. The charge accumulation layer 33b is formed on the side surface of the block insulating layer 33a with a predetermined thickness. The tunnel insulating layer 33c is formed on the side surface of the charge storage layer 33b with a predetermined thickness. The block insulating layer 33a and the tunnel insulating layer 33c are made of silicon oxide (SiO ₂ ). The charge accumulation layer 33b is made of silicon nitride (SiN).

The memory semiconductor layer 34 is formed in contact with the side surface of the tunnel insulating layer 33c. The memory semiconductor layer 34 is formed to fill the back gate hole 22 and the memory hole 33. The memory semiconductor layer 34 is formed in a U shape when viewed in the row direction. The memory semiconductor layer 34 has a pair of columnar portions 34a extending in a direction perpendicular to the substrate 10 and a connection portion 34b connecting the lower ends of the pair of columnar portions 34a. The memory semiconductor layer 34 is made of polysilicon (poly-Si).

In other words, the configuration of the back gate transistor layer 20 is changed so that the memory gate insulating layer 33 is formed to surround the connection portion 34b. The back gate conductive layer 21 is formed to surround the connecting portion 34b via the memory gate insulating layer 33. In addition, in other words, the memory gate insulating layer 33 is formed so as to surround the columnar portion 34a. The word line conductive layers 31a to 31d are formed to surround the columnar portions 34a via the memory gate insulating layer 33.

The select transistor layer 40 has a source side conductive layer 45a and a drain side conductive layer 45b as shown in FIG. 3B. The source side conductive layer 45a functions as a source side selection gate line SGS2 and functions as a gate of the source side selection transistor SSTr2. The drain side conductive layer 45b functions as the drain side selection gate line SGD2 and functions as the gate of the drain side selection transistor SDTr2.

The source side conductive layer 45a is formed around the semiconductor layer 48a, and the drain side conductive layer 45b is the same layer as the source side conductive layer 45a, and is similarly formed around the semiconductor layer 48b. have. The source side conductive layer 45a and the drain side conductive layer 45b are made of polysilicon (poly-Si).

The select transistor layer 40 has a source side hole 46a and a drain side hole 46b as shown in FIG. The source side hole 46a is formed to penetrate the source side conductive layer 45a. The drain side hole 46b is formed to penetrate the drain side conductive layer 45b. The source-side hole 46a and the drain-side hole 46b are formed at positions where the memory holes 32 match with each other.

As shown in FIG. 4, the select transistor layer 40 includes a source side gate insulating layer 47a, a source side columnar semiconductor layer 48a, a drain side gate insulating layer 47b, and a drain side columnar semiconductor layer. Has (48b). The source side columnar semiconductor layer 48a functions as the body of the source side selection transistor SSTr2. The drain side columnar semiconductor layer 48b functions as the body of the drain side selection transistor SDTr2.

Further, the distance Dsm between the source side conductive layer 45a or the drain side conductive layer 45b and the word line conductive layer 31d is, for example, 2 compared to the distance Dmm between the word line conductive layers 31a to d. It has a distance of about three to three times. This is to prevent the erase operation. That is, in the erase operation, as described later, a high voltage is supplied to the source side conductive layer 45a or the drain side conductive layer 45b, while the ground voltage Vss is supplied to the word line conductive layers 31a to d. . In this case, the columnar portion 34b immediately below the source-side conductive layer 45a or the drain-side conductive layer 45b rises to the vicinity of the erase voltage Vera by capacitive coupling, but it is a word line conductive layer 31d. The potential of the columnar portion 34b immediately below) is approximately 0V. For this reason, if the distance between the source side conductive layer 45a or the drain side conductive layer 45b and the word line conductive layer 31d is short, it is just below the source side conductive layer 45a or the drain side conductive layer 45b. A strong electric field is generated between the pillar-shaped portion 48b and the pillar-shaped portion 34a directly below the word line conductive layer 31d, thereby generating a GIDL current, thereby causing data to be erased in the non-selected memory block. There is work to be done. Therefore, the distance Dsm between the source side conductive layer 45a or the drain side conductive layer 45b and the word line conductive layer 31d needs to be larger than the distance Dmm between the word line conductive layers 31a to d. .

As shown in FIG. 4, the wiring layer 50 is formed on the upper layer of the selection transistor layer 40. The wiring layer 50 has a source line layer 51 and a bit line layer 52. The source line layer 51 functions as a source line SL. The bit line layer 52 functions as a bit line BL.

The source line layer 51 is formed in the plate shape extended in a row direction. The source line layer 51 is formed in contact with the top surface of the pair of source-side columnar semiconductor layers 48a adjacent to the column direction. The bit line layer 52 is formed in a stripe shape in contact with the upper surface of the drain-side columnar semiconductor layer 48b and having a predetermined pitch in the row direction and extending in the column direction. The source line layer 51 and the bit line layer 52 are comprised with metals, such as tungsten (W), copper (Cu), and aluminum (Al).

Next, with reference to FIG. 5, the shape of word line conductive layers 31a-31d is demonstrated in detail. 5 is a top view illustrating the shape of the word line conductive layer 31a. Since the word line conductive layers 31b to 31d have substantially the same shape as the word line conductive layer 31a, only the word line conductive layer 31a is representatively shown in FIG.

As shown in Fig. 5, the word line conductive layer 31a is formed in the shape of a comb teeth in the vertical direction. The word line conductive layer 31a connects the plurality of straight portions 351a and 352a surrounding the plurality of columnar semiconductor layers 34a arranged in the row direction and the ends of the plurality of straight portions 351a and 352a. Straight portions 351b and 352b. In this manner, word lines connected to the memory strings MS arranged in the bit line BL direction are commonly connected to each memory block. This is because it is necessary to reduce the number of metal wirings for connecting the signals of the word line WL, the selection gate line SGD, SGS, and the back gate line BG to peripheral circuit portions such as the row decoder. In Fig. 5, reference numeral 34a 'denotes a dummy columnar semiconductor layer which is not used as the memory string MS. In addition, in the case of the structure like FIG. 3C, the dummy columnar semiconductor layer 34a 'is unnecessary.

Next, the erase operation in the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIGS. 6 to 8. 6 and 7 show voltages applied to respective units together with equivalent circuit diagrams of the memory cell array AR1. 8 is a timing chart showing timing of application of voltage. Here, it is assumed that an erase operation is performed in units of sub-blocks in which sub-block SB1 is selectively erased among two sub-blocks in one memory block MB. At this time, the sub-block SB2 is not to be erased, and the erasure of data in the memory cells is prohibited. The two sub-blocks SB1 and SB2 are all connected to the same bit line BL, source line SL, and word line WL, while the drain side select gate line SGD2 and the source side select gate line SGS2 are each individually. In addition, in the following description, the selection gate lines SGD2 and SGS2 in sub-block SB1 are called SGD21 and SGS21, and similarly, the selection gate lines SGD2 and SGS2 in sub-block SB2 are called SGD22 and SGS22.

In the sub-block SB1 selected as the erase target, as shown in Fig. 8, the bit line BL and the source line SL are set to the erase voltage Vera (around 20V) at time t1. On the other hand, the ground line Vss (0V) is supplied to the word line WL. The drain-side selection gate line SGD21 and the source-side selection gate line SGS21 are supplied with a voltage Vera-ΔV lower than the erase voltage Vera by a voltage ΔV (for example, 5 to 8V) at time t3, respectively. As a result, GIDL current (Gate Induced Drain Leakage Current) is generated at the end of the bit line BL side of the drain side selection transistor SDTr2 of the sub-block SB1 and the end of the source line SL side of the source side selection transistor SSTr2 (see FIG. 7). ), The erase voltage Vera supplied to the bit line BL and the source line SL is transferred to the body of the memory unit MU in the sub-block SB1. Thereby, the erase operation in the sub-block SB1 is performed by the potential difference between the voltage Vera of the body and the voltage Vss of the word line WL.

On the other hand, in the sub-block SB2 in which erasing is prohibited by non-selection, since the bit line BL and the source line SL are shared with the sub-block SB1, the bit line BL and the source line SL are set to the erase voltage Vera (about 20 V) at time t1. However, at time t2, the drain side selection gate line SGD22 and the source side selection gate line SGS22 are applied with a voltage Vera 'approximately equal to the erase voltage Vera, thereby, between the source line SL and the source side selection gate line SGS, and The high voltage is not applied between the bit line BL and the drain side select gate line SGD, thereby preventing the generation of the GIDL current.

9A is an example of a charge pump circuit and a voltage value adjustment circuit suitable for generating various voltages of the present embodiment. The oscillator 101 generates a clock signal, and the charge pump circuit 102 inputs the clock signal to boost the power supply voltage Vdd to the erase voltage Vera. The voltage values of the voltages Vera 'and Vera-ΔV are adjusted by the voltage value adjusting circuit 103 formed by serially connecting a transistor of a diode connection. In addition, the voltage determination circuit constituted by the differential amplifier 106 and the division resistors 107 and 108 determines whether or not the voltage Vera has risen to a predetermined value and is based on the output signal of the differential amplifier 106. The operation of the oscillator 101 is stopped.

In the selected memory block, the above-mentioned voltage is supplied to the selection gate lines SGD2 and SGS2. However, in the non-selection memory block, it is preferable to keep the selection gate lines SGD2 and SGS2 in a floating state. An example of the row decoder 2A for performing such voltage control is shown in Fig. 9B (the row decoder 2B also has a substantially similar configuration, so only the row decoder 2A will be described). This row decoder 2A has an address determination circuit 111 and a transfer transistor group 112. The address determination circuit 111 conducts the transfer transistor 112a for switching the supply of the voltage Vera 'or Vera-ΔV in the selection block based on the block address signal Block Adrs. On the other hand, in an unselected block, the voltage Vdd is supplied to the gate of the transfer transistor 112b which supplies the power supply voltage Vdd, and the selection gate lines SGD2 and SGS2 are charged to the power supply voltage Vdd-Vth. Subsequently, when the bit line BL and the source line SL rise to the voltage Vera, the voltages of the selection gate lines SGD2 and SGS2 rise due to capacitive coupling, so that the transfer transistor 112b is in a non-conductive state. As a result, the selection gate lines SGD2 and SGS2 are in a floating state.

[Second Embodiment]

Next, the nonvolatile semiconductor device according to the second embodiment will be described.

10 is a circuit diagram of the entire configuration of a nonvolatile semiconductor memory device according to the second embodiment. 11 is a schematic perspective view of the memory cell array AR1 of the nonvolatile semiconductor device according to the second embodiment. In addition, about the structure similar to 1st Embodiment, the same code | symbol is attached | subjected and the detailed description is abbreviate | omitted below.

In this embodiment, the memory unit MU includes other selection transistors SDTr1 and SSTr1 connected in series with the selection transistors SDTr2 and SSTr2 connected to the bit line BL and the source line SL. The selection transistors SDTr1 and SSTr1 are connected between the selection transistors SDTr2 and SSTr2 and the memory string MS. The two selection transistors connected in series as described above are provided to prevent the generation of the GIDL current in the unselected block due to the potential difference between the selection gate line SGD2 or the SGS2 and the word line WL as described above. Hereinafter, the selection transistors SDTr2 and SSTr2 are referred to as "second drain side selection transistor SDTRr2" and "second source selection transistor SSTr2", and the selection transistors SDTr1 and SSTr1 are referred to as "first drain side selection transistor SDTRr1" and "first Source side select transistor SSTr1 ".

As shown in Fig. 12, the first drain side selection transistor SDTr1 and the first source side selection transistor SSTr1 have a source side conductive layer 41a and a drain side conductive layer 41b, respectively. The source side conductive layer 41a functions as the source side selection gate line SGS1 of the first source side selection transistor SSTr1. The drain side conductive layer 41b functions as the drain side select gate line SGD1 of the drain side select transistor SDTr1.

As shown in FIG. 13, the source side conductive layer 41a is formed around the semiconductor layer 48a via the gate insulating film 43a, and the drain side conductive layer 41b is the source side conductive layer ( It is the same layer as 41a), and is similarly formed around the semiconductor layer 48b via the gate insulating film 43b. The source side conductive layer 41a and the drain side conductive layer 41b are made of polysilicon (poly-Si).

Next, the erase operation in the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIGS. 14, 15A, and 15B. 14 and 15A show voltages applied to respective units together with equivalent circuit diagrams of the memory cell array AR1. 15B is a timing chart showing timing of application of voltage. Here, of the two subblocks in one memory block MB, the subblock SB1 is to be erased, while the subblock SB2 is forbidden to erase. In addition, in the following description, the selection gate lines SGD2 and SGS2 in sub-block SB1 are called SGD21 and SGS21, and the selection gate lines SGD1 and SGS1 in sub-block SB1 are called SGD11 and SGS11. Similarly, the selection gate lines SGD2 and SGS2 in the sub block SB2 are referred to as SGD22 and SGS22, and the selection gate lines SGD1 and SGS1 in the sub block SB2 are referred to as SGD12 and SGS12.

In the sub-block SB1 selected as the erase target, the bit line BL and the source line SL are set to the erase voltage Vera (around 20V) at time t1. On the other hand, the ground line Vss (0V) is supplied to the word line WL. The second drain side selection gate line SGD21 and the second source side selection gate line SGS21 are supplied with a voltage Vera-ΔV lower than the erase voltage Vera by a voltage ΔV (for example, 5 to 8V) at time t3, respectively. . As a result, GIDL current (Gate Induced Drain Leakage Current) is generated at the end of the bit line BL side of the drain side selection transistor SDTr2 of the sub-block SB1 and the end of the source line SL side of the source side selection transistor SSTr2 (see Fig. 15A). ), The erase voltage Vera supplied to the bit line BL and the source line SL is transferred to the body of the memory unit MU in the sub-block SB1. Thereby, the erase operation in the sub-block SB1 is performed by the potential difference between the voltage Vera of the body and the voltage Vss of the word line WL. On the other hand, to the drain side selection gate line SGD11 and the source side selection gate line SGS11, a voltage Vmid (for example, about 10V) having a magnitude approximately halfway between the erase voltage Vera 'and the ground voltage Vss is supplied at time t3.

In sub-block SB2 in which erasing is prohibited by non-selection, a voltage Vera 'approximately equal to the erase voltage Vera is applied to the drain-side selection gate line SGD22 and the source-side selection gate line SGS22 at time t2, whereby generation of the GIDL current is prevented. It is prohibited. In addition, a voltage Vmid (for example, about 10V) having a magnitude approximately halfway between the erase voltage Vera 'and the ground voltage Vss is applied to the drain side selection gate line SGD12 and the source side selection gate line SGS12 at time t2. . As a result, since the difference in voltages applied between the plurality of adjacent wirings at a small wiring pitch becomes small, the possibility of generating a GIDL current can be reduced. In other words, it is possible to reduce the risk of occurrence of the erase in the non-selective subblock SB2.

16A and 16B, the voltages supplied to the selection gate lines SGD11 and SGS11 may be the voltage Vera-ΔV similarly to the selection gate lines SGD21 and SGS22.

17A is an example of the circuit for generating the above-mentioned voltage Vmid. The difference from the circuit of FIG. 9A is that the level shifter 111, the NMOS transistor 112, the division resistors 113 and 114, and the differential amplifier 115 are provided to generate the voltage Vmid. The NMOS transistor 112 is supplied with the voltage Vera 'at the drain, and the source is connected to one end of the division resistors 113 and 114. The voltage generated at the source is the voltage Vmid. The other ends of the split resistors 113 and 114 are grounded, and a connection node of the split resistors 113 and 114 is connected to one input terminal of the differential amplifier 115. The output terminal of the differential amplifier 115 is connected to the level shifter 111, and the output terminal of the level shifter 111 is connected to the gate of the NMOS transistor 112.

According to this circuit configuration, the voltage Vmid generated at the source of the NMOS transistor 112 is raised at approximately the same timing as the voltage Vera '. Then, the division resistors 113 and 114 and the differential amplifier 115 determine whether this voltage Vmid has reached the desired voltage. When the voltage Vmid reaches the desired voltage, the differential amplifier 115 switches the output signal bEN2 to "H". As a result, the output signal Vout of the level shifter 111 becomes "L", and the NMOS transistor 112 is switched to the non-conducting state (OFF). On the contrary, when the voltage Vmid falls below the desired voltage, the output signal Vout of the level shifter 111 becomes "H", and the NMOS transistor 112 is switched to the conduction state ON. By repeating this operation, the voltage Vmid is kept at a constant value.

17B shows an example of the row decoder 2A used in the present embodiment. The difference from FIG. 9B is that the transfer transistor 112c for supplying the voltage Vmid to the selection gate lines SGD11 and SGD12 is provided. Since the selection gate lines SGD11 and SGD12 do not need to control the selection / non-selection of the memory string MS, it is not necessary to provide a pull-down transistor corresponding to the transfer transistor 112b required for non-selection.

[Third embodiment]

Next, a nonvolatile semiconductor device according to the third embodiment will be described.

18A is a circuit diagram of the entire configuration of a nonvolatile semiconductor memory device according to the third embodiment. In the third embodiment, similarly to the second embodiment, the memory unit MU includes the drain side selection transistors SDTr1 and SSTr1 in addition to the second selection transistors SDTr2 and SSTr2. However, in this 3rd Embodiment, all the 1st drain side selection gate line SGD1 and the 1st source side selection gate line SGS1 are mutually connected between several sub-block SB in each block, and in this point, it is 2nd It is different from embodiment. Other configurations and various operations are substantially the same as in the above embodiment. By applying a voltage as shown in Figs. 15A and 15B, the erase operation similar to that of the other embodiment can be performed.

18B shows an example of the row decoder 2A used in the present embodiment. The difference from FIG. 17B is that only one transfer transistor 112c for supplying the voltage Vmid to the selection gate lines SGD11 and SGD12 is provided.

[Fourth Embodiment]

Next, the nonvolatile semiconductor device according to the fourth embodiment will be described.

19A is a circuit diagram of the entire configuration of a nonvolatile semiconductor memory device according to the fourth embodiment, and FIG. 19B is a modification thereof. 20 is a schematic perspective view of the memory cell array AR1. In the fourth embodiment, similarly to the first embodiment, one drain side select transistor SDTr and one source side select transistor SSTr are provided in one memory unit MU. However, this fourth embodiment differs from the first embodiment in that dummy memory transistors DMSS and DMDS are provided between the drain side selection transistor SDTr or the source side selection transistor SSTr and the memory transistor MTr. Although the dummy transistors DMSS and DMDS constitute a part of the memory string MS and have a structure similar to that of the ordinary memory transistor MTr, they are not used for data storage, and the threshold voltage is a constant value (for example, always Erasing level).

As shown in FIG. 21, the dummy transistor DMSS includes a memory gate insulating layer 33 and a columnar portion similar to the memory transistor MTr formed around the columnar portion 34a of the memory semiconductor layer 34. A dummy word line conductive layer 31e formed by sandwiching the memory gate insulating layer 33 around 34a is provided. The dummy word line conductive layer 31e is formed of polysilicon, for example, and functions as a dummy word line DWLS.

Similarly, the dummy transistor DMDS includes a memory gate insulating layer 33 formed around the columnar portion 34a of the memory semiconductor layer 34, and a memory gate insulating layer 33 around the columnar portion 34a. A dummy word line conductive layer 31e formed therebetween. The dummy word line conductive layer 31e functions as a dummy word line DWLD.

The erase operation of the fourth embodiment can be executed in substantially the same manner as in the second embodiment. That is, in the second embodiment, the voltages applied to the first drain side selection gate line SGD1 and the first source side selection gate line SGS1 are directly applied to the dummy word lines DWLD and DWLS, and the voltage applied to the other wiring is By the same procedure as in the second embodiment, the erase operation can be performed in the sub-block SB unit.

That is, in the case of the configuration of Fig. 19A, a voltage as shown in Figs. 15A and 16A may be applied to each unit. In the case where the dummy word lines DWLD and DWLS are commonly connected between the plurality of sub-blocks SB as in the configuration of FIG. 19B, a voltage as shown in FIG. 16A may be applied to each unit.

[Fifth Embodiment]

Next, a nonvolatile semiconductor device according to the fifth embodiment will be described.

Since the structure of an apparatus is substantially the same as 2nd Embodiment, description is abbreviate | omitted.

Also in the erasing operation, the voltage finally applied to each unit is the same as in the second embodiment. In this embodiment, however, as shown in Fig. 22A, the voltage of each part is raised to the voltage Vmid before the voltage is increased to, for example, the voltage Vera, Vera-ΔV, and the like, and then the target voltage Vera, Vera-ΔV. It differs from 2nd Embodiment in that it is made.

In addition, as shown in FIG. 22B, the voltages finally supplied to the selection gate lines SGD11 and SGS11 may be the voltage Vmid instead of the voltage Vera-ΔV.

23 is an example of a charge pump circuit that can be used in this embodiment. In this embodiment, since the generation timing of the voltage Vmid is arbitrary, as shown in FIG. 23, the voltage Vmid can be generated using the independent oscillator 101 'and the charge pump circuit 102'.

[Sixth Embodiment]

Next, the nonvolatile semiconductor device according to the sixth embodiment will be described with reference to FIGS. 24 to 25. 24 is a circuit diagram of the entire configuration of a nonvolatile semiconductor memory device according to the sixth embodiment. 25 and 26 are schematic perspective views and cross-sectional views of the memory cell array AR1 of the nonvolatile semiconductor device according to the sixth embodiment, respectively. In addition, about the structure similar to 1st, 2nd embodiment, the same code | symbol is attached | subjected and the detailed description is abbreviate | omitted below. 25 and 26 omit some of the structure of the memory cell array, but the structure of the memory cell array is the same as in the above-described embodiment.

In this embodiment, in addition to the second drain side selection transistor SDTr2 and the second source side selection transistor SSTr2, a plurality of (for example, two) first drain side selection transistors SDTr1, SDTr1 ', And a plurality of (for example, two) first source side select transistors SSTr1 and SSTr1 '. The selection transistors SDTr1 and SDTr1 'are connected in series between the selection transistor SDTr2 and the memory string MS. The selection transistors SSTr1 and SSTr1 'are connected in series between the selection transistor SSTr2 and the memory string MS. Since the structure of other parts is substantially the same as the structure (FIGS. 11, 12, 13) of 2nd Embodiment, the overlapping description is abbreviate | omitted.

Next, the erase operation in the nonvolatile semiconductor memory device according to the sixth embodiment will be described with reference to FIGS. 27 and 28. Here, similarly to the description in the second embodiment, the case where the sub-block SB1 is to be erased and the sub-block SB2 is prohibited to erase among the two sub-blocks in one memory block MB will be described. The selection gate lines SGD2 and SGS2 in the sub-block SB1 are referred to as SGD21 and SGS21, and the selection gate lines SGD1, SGS1, SGD1 'and SGS1' in the sub-block SB1 are referred to as SGD11, SGS11, SGD11 'and SGS11', respectively. Similarly, the selection gate lines SGD2 and SGS2 in the sub-block SB2 are referred to as SGD22 and SGS22, and the selection gate lines SGD1, SGS1, SGD1 'and SGS1' in the sub-block SB2 are referred to as SGD12, SGS12, SGD12 'and SGS12', respectively.

The voltage finally applied to each part for the erase operation is substantially the same as in the second embodiment. In this embodiment, however, similarly to the fifth embodiment, before the voltage of each unit is increased to, for example, the voltages Vera, Vera-ΔV, and Vera ', the magnitude of the erase voltage Vera' and the ground voltage Vss are approximately equal. The voltage is raised to the intermediate voltage Vmid1, and then to the target voltages Vera, Vera-ΔV, and Vera '. As in the second embodiment, it is also possible to omit the raising to the intermediate voltage Vmid1 and to perform the control of raising the target voltages Vera, Vera-ΔV, and Vera 'directly from the ground voltage.

One memory string MS of this embodiment has two first drain side select transistors SGD1 and SGD1 'connected in series, and has two first source side select transistors SGS1 and SGS1' connected in series.

In either of the selection sub-block SB1 and the non-selection sub-block SB2, the voltage Vmid1 is supplied to the first drain-side selection transistors SGD1 (SGD11, SGD12) and the first source-side selection transistors SGS1 (SGSS11, SGS12), The voltage Vmid2 (<Vmid1) smaller than this voltage Vmid1 is supplied to the drain side selection transistors SGD1 '(SGD11', SGD12 ') and the first source side selection transistors SGS1' (SGS11 ', SGS12') (see Fig. 28). Thereby, since the difference of the voltage applied between several wiring which adjoins by a small wiring pitch becomes smaller compared with embodiment mentioned above, the possibility of generating GIDL current can be made small.

29 is an example of a charge pump circuit that can be used in this embodiment. The circuit which generates voltage Vera, Vera ', and Vera- (DELTA) V shown in the upper direction of FIG. 29 is the same structure as FIG. 29 is a circuit for generating voltages Vmid1 and Vmid2. Since the same code | symbol is attached | subjected about the component same as the circuit of FIG. 23 below, detailed description is abbreviate | omitted. In the circuit below in FIG. 29, the level shifter circuit 111 ′, the NMOS transistor 112 ′, the division resistors 113 ′, 114 ′ and the differential amplifier circuit 115 ′ are used to generate the voltage Vmid2. Equipped. These are the same as the level shifter circuit 111, the NMOS transistor 112, the division resistors 113 and 114, and the differential amplifier circuit 115 shown in Fig. 17A, and thus detailed description thereof will be omitted.

In the above description, the configuration and operation when the first drain side selection transistor SDTr1 and the first source side selection transistor SSTr1 are each present (SDTr1 and SDTr1 ', SSTr1 and SSTr1') are described in detail. However, the number of the first drain side selection transistor SDTr1 and the first source side selection transistor SSTr1 need not be two, and may be three or more. N first drain side select transistors SDTr1 (1), SDTr1 (2),... When SDTr1 (n) is present, the voltage applied to the voltage Vmid1 applied to the gate SGD1 (1) of the selection transistor SDTr1 (1) is the largest value, and then the selection transistor SDTr farther from the bit line BL is The voltage Vmid applied to the gate is made small (Vmid1> Vmid2>…> Vmidi). The voltages applied to the gates of the first drain-side select transistor and the first source-side select transistor of the selection sub-block are supplied to Vmid1, Vmid2,... Instead of Vmidn, the voltage Vera-ΔV may be set as in the modification of the second embodiment (Fig. 16A).

[Seventh Embodiment]

Next, a nonvolatile semiconductor device according to the seventh embodiment will be described with reference to FIGS. 30 to 33. 30 is a circuit diagram of the entire configuration of a nonvolatile semiconductor memory device according to the seventh embodiment. 31 is a schematic perspective view of the memory cell array AR1 of the nonvolatile semiconductor device according to the seventh embodiment. In addition, about the structure similar to 1st, 2nd embodiment, the same code | symbol is attached | subjected and the detailed description is abbreviate | omitted below.

This embodiment is characterized in that, like the fourth embodiment, a dummy transistor is provided between the selection transistors SDTr2 and SSTr2 and the memory transistors MTr1 and MTr8. However, unlike the fourth embodiment, the plurality of (for example, two) dummy transistors are different from the fourth embodiment in that they are connected in series with one selection transistor SDTr2 (or SSTr2). Specifically, two dummy transistors DMDS2 and DMDS1 are connected in series with the drain-side selection transistor SDTr2. In addition, two dummy transistors DMSS2 and DMSS1 are connected in series with the source-side selection transistor SSTr2. The dummy transistor DMDS1 is connected in series with the memory transistor MTr8. The dummy transistor DMDS2 is connected in series with the dummy transistor DMDS1, and one end thereof is connected to the drain side select transistor SDTr2. The dummy transistor DMSS1 is connected in series with the memory transistor MTr1, the dummy transistor DMSS2 is connected in series with the dummy transistor DMSS1, and one end thereof is connected to the source side selection transistor SSTr2. Since the structure of other parts is substantially the same as the structure of 4th Embodiment, the overlapping description is abbreviate | omitted.

Next, the erase operation in the nonvolatile semiconductor memory device according to the seventh embodiment will be described with reference to FIGS. 32 and 33. Here, similarly to the description in the sixth embodiment, the case where the sub-block SB1 is to be erased and the sub-block SB2 is prohibited to erase among the two sub-blocks in one memory block MB will be described. 32, dummy transistors DMDS2, DMDS1, DMSS2, and DMSS1 in the sub-block SB1 are referred to as DMDS21, DMDS11, DMSS21, and DMSS11, respectively. The dummy transistors DMDS2, DMDS1, DMSS2, and DMSS1 in the sub-block SB2 are called DMDS22, DMDS12, DMSS22, and DMSS12, respectively.

The voltages finally applied to the bit lines BL, the source lines SL, the selection gate lines SGD2, and SGS2 for the erase operation are substantially the same as in the sixth embodiment. In addition, the voltages applied to the dummy word lines DWLD21, DWLS21, DWLD11, DWLS11, DWLD22, DWLS22, DWLD12, and DWLS12 of the dummy transistor are selected gate lines SGD11, SGS11, SGD11 ', SGS11', SGD12, It is equal to the voltage applied to SGS12, SGD12 ', SGS12'. Thereby, the effect similar to 6th Embodiment can be exhibited. In addition, the voltages applied to the dummy word lines DWLD21 and DWLS21 in the selected subblock SB1 may be set to the voltage Vera-ΔV instead of the voltage Vmid-1 as in the modification of the second embodiment (Fig. 16A).

The number of dummy transistors DMDS and DMSS need not be two, and the number of three or more dummy transistors may be the same as that of the selection transistors SDTr1 and SSTr1 in the sixth embodiment. At this time, as for the dummy transistors DMDS and DMSS closer to the bit line BL, the voltage Vmid applied to the gate is increased, and the distance is smaller as in the sixth embodiment. In addition, the charge pump circuit shown in FIG. 29 can be used for these erase operations.

While certain embodiments of the invention have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms. In addition, various omissions, substitutions and changes in the form of the method and system described herein can be made without departing from the spirit of the present invention. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the invention.

For example, in the above embodiment, an example in which all have a memory cell array AR1 in which U-shaped memory strings MS are arranged is described. However, the present invention is not limited thereto, and for example, a memory string in which all memory transistors are arranged in a straight line. (I-shape) may be used.

In addition, in the above embodiment, unlike the memory transistor MTr, the selection transistors SDTr and SSTr have no charge storage film 33b and are configured as transistors having a gate insulating film made of, for example, a single layer film of a silicon oxide film. However, the present invention is not limited to this. Like the memory transistor, the selection transistors SDTr and SSTr have a memory gate insulating layer 33 having a three-layer structure of a block insulating layer 33a, a charge storage layer 33b, and a tunnel insulating layer 33c. It may be.

Claims (20)

A memory cell array having a plurality of memory blocks;
A plurality of memory strings formed by serially connecting a plurality of memory transistors arranged in a matrix and electrically rewritable in each of the plurality of memory blocks;
A drain side selection transistor having one end connected to a first end of the memory string;
A source side select transistor having one end connected to a second end of the memory string;
A plurality of word lines arranged to be commonly connected to the plurality of memory strings arranged in one of the plurality of memory blocks;
A plurality of bit lines each extending in a first direction and connected to the other ends of the drain side selection transistors present in the plurality of memory blocks;
A source line connected to the other end of the source side select transistor,
A drain side select gate line arranged with the second direction in the longitudinal direction so as to commonly connect the gates of the drain side select transistors arranged in a second direction perpendicular to the first direction;
A source side select gate line arranged with the second direction in the longitudinal direction so as to commonly connect the gates of the source side select transistors arranged in the second direction;
A control circuit for controlling voltages applied to the plurality of memory blocks;
Each of the plurality of memory strings,
A columnar semiconductor layer including a columnar portion extending in a direction perpendicular to the substrate and functioning as a body of the memory transistor;
A charge accumulation layer formed to surround the side surface of the columnar portion and configured to accumulate charge;
A word line conductive layer formed to surround the side surface of the columnar portion via the charge storage layer, and functioning as a gate of the memory transistor and the word line;
A plurality of drain side select transistors commonly connected to one of the drain side select gate lines and one source side select gate line and a plurality of the memory strings connected to a plurality of source side select transistors constitute one sub block. and,
When the control circuit executes an erase operation for selectively erasing at least one sub block of the memory block,
In the selected first subblock,
A first voltage is applied to the bit line and the source line, while a second voltage smaller than the first voltage is applied to the word line.
An erase operation is applied to the drain side selection gate line and the source side selection gate line by applying a third voltage lower than the first voltage by a predetermined value;
In the second sub block existing in the same memory block as the selected sub block and deselected,
A nonvolatile semiconductor memory device, characterized in that the erase operation is not performed by applying a fourth voltage approximately equal to the first voltage to the drain side selection gate line and the source side selection gate line. The method of claim 1, wherein the third voltage is set to the extent to generate a GIDL current (Gate Induced Drain Leakage Current) by the potential difference with the first voltage,
And the fourth voltage is set to such an extent that generation of a GIDL current is prohibited by a potential difference with the first voltage. The drain drain selection transistor of claim 1, wherein the drain side selection transistor includes a first drain side selection transistor and a second drain side selection transistor connected in series with the first drain side selection transistor and one end of which is connected to the bit line. and,
The source side select transistor includes a first source side select transistor and a second source side select transistor connected in series with the first source side select transistor and one end thereof connected to the source line,
When the control circuit executes an erase operation for selectively erasing at least one sub block of the memory block,
In the first sub-block, the second drain side select gate line to which the gate of the second drain side select transistor is connected and the second source side select gate line to which the gate of the second source side select transistor are connected are provided. The fourth voltage is applied to the first drain side selection gate line to which the gate of the first drain side selection transistor is connected and the first source side selection gate line to which the gate of the first source side selection transistor is connected. Applying a fifth voltage approximately midway between the voltage and the second voltage,
In the second sub-block, the fourth voltage is applied to the second drain side selection gate line and the second source side selection gate line, while the first drain side selection gate line and the first source side selection are applied. And a fifth voltage is applied to a gate line. The method of claim 3, wherein the third voltage is set to the extent to generate a GIDL current (Gate Induced Drain Leakage Current) by the potential difference with the first voltage,
And the fourth voltage is set to such an extent that generation of a GIDL current is prohibited by a potential difference with the first voltage. The said first drain side selection gate line and said 1st source side selection gate line of each of a plurality of sub-blocks are a said 1st drain side selection gate line and a said 1st source side in another sub block. A nonvolatile semiconductor memory device commonly connected to a selection gate line. 6. The method of claim 5, wherein a plurality of the first drain side select transistors are connected in series to one second drain side select transistor, and a plurality of the first source side select transistors are connected in series to the one second source. Connected to the side select transistor,
When the control circuit executes an erase operation for selectively erasing at least one sub block of the memory block,
As for the first drain side selection transistor closer to the bit line, the voltage applied to the gate is set to a larger value than that of the first drain side selection transistor farther from the bit line than that.
The voltage of the first source side select transistor closer to the source line is set to a higher value than that of the first source side select transistor farther from the source line than that of the first source side select transistor. Nonvolatile semiconductor memory device. The drain drain select transistor of claim 1, wherein the drain drain select transistor is connected to a first end of the memory string and a second drain drain select transistor connected in series with the first drain select transistor. Including,
The source side select transistor includes the first source side select transistor connected to a second end of the memory string, and a second source side select transistor connected in series with the first source side select transistor,
When the control circuit executes an erase operation for selectively erasing at least one sub block of the memory block,
In the first sub-block, a first drain side selection gate line to which a gate of the first drain side selection transistor is connected, a second drain side selection gate line to which a gate of the second drain side selection transistor is connected, and the first sub block is connected. The third voltage is applied to a first source side select gate line to which a gate of the first source side select transistor is connected, and a second source side select gate line to which a gate of the second source side select transistor is connected;
In the second sub-block, the fourth voltage is applied to the second drain side selection gate line and the second source side selection gate line, while the first drain side selection gate line and the first source side selection are applied. And a fifth voltage is applied to a gate line. The method of claim 7, wherein the third voltage is set to generate a GIDL current (Gate Induced Drain Leakage Current) by a potential difference with the first voltage.
And the fourth voltage is set to such an extent that generation of a GIDL current is prohibited by a potential difference with the first voltage. A plurality of said first drain side select transistors are connected in series with respect to one said second drain side select transistor, and a plurality of said first source side select transistors are selected by one said second source side select. Connected in series with the transistor,
When the control circuit executes an erase operation for selectively erasing at least one sub block of the memory block,
The fifth drain applied to the gate is set to a larger value than that of the first drain-side select transistor closer to the bit line than the first drain-side select transistor farther from the bit line. ,
The fifth source voltage applied to the gate is set to a larger value than that of the first source side selection transistor closer to the source line than that of the first source side selection transistor closer to the source line. A nonvolatile semiconductor memory device, characterized in that. 2. The memory string of claim 1, wherein the memory string includes a first dummy transistor connected to the drain side select transistor and not used for data storage, and a second dummy transistor connected to the source side select transistor and not used for data storage. Equipped,
When the control circuit executes an erase operation for selectively erasing at least one sub block of the memory block,
In the first sub-block, the third voltage is applied to the drain side select gate line and the source side select gate line, while the first dummy word line and the second connected gate of the first dummy transistor are connected. A fifth voltage that is approximately halfway between the fourth voltage and the second voltage is applied to the second dummy word line to which the gate of the dummy transistor is connected;
In the second sub block, the fourth voltage is applied to the drain side selection gate line and the source side selection gate line, while the fifth voltage is applied to the first dummy word line and the second dummy word line. A nonvolatile semiconductor memory device, characterized in that. The method of claim 10, wherein the third voltage is set to the extent to generate a GIDL current (Gate Induced Drain Leakage Current) by the potential difference with the first voltage,
And the fourth voltage is set to such an extent that generation of a GIDL current is prohibited by a potential difference with the first voltage. The dummy word of claim 10, wherein the first dummy transistor and the second dummy transistor function as the columnar semiconductor layer, the charge accumulation layer, and the first dummy word line or the second dummy word line. A nonvolatile semiconductor memory device comprising a line conductive layer. The method of claim 1, wherein the memory string,
A third dummy transistor connected in series with the memory transistor and not used for data storage;
A fourth dummy transistor connected in series with the third dummy transistor and connected at one end thereof to the drain side select transistor and not used for data storage;
A fifth dummy transistor connected in series with the memory transistor and not used for data storage;
A sixth dummy transistor connected in series with the fifth dummy transistor, one end of which is connected to the source-side selection transistor and not used for data storage;
When the control circuit executes an erase operation for selectively erasing at least one sub block of the memory block,
In the first sub-block, the third voltage is applied to the fourth dummy word line to which the gate of the fourth dummy transistor is connected and the sixth dummy word line to which the gate of the sixth dummy transistor is connected. Applying a fifth voltage approximately halfway between the fourth voltage and the second voltage to the third dummy word line to which the gate of the third dummy transistor is connected and the fifth dummy word line to which the gate of the fifth dummy transistor is connected; ,
In the second sub block, the fourth voltage is applied to the fourth dummy word line and the sixth dummy word line, while the fifth voltage is applied to the third dummy word line and the fifth dummy word line. A nonvolatile semiconductor memory device, characterized in that applied. 15. The method of claim 13, wherein the third voltage is set to the extent to generate a GIDL current (Gate Induced Drain Leakage Current) by the potential difference with the first voltage,
And the fourth voltage is set to such an extent that generation of a GIDL current is prohibited by a potential difference with the first voltage. The method of claim 13, wherein the plurality of third dummy transistors are connected in series to one fourth dummy transistor, and the plurality of fifth dummy transistors are connected in series to one sixth dummy transistor,
When the control circuit executes an erase operation for selectively erasing at least one sub block of the memory block,
As for the third dummy transistor located closer to the bit line, the voltage applied to the gate is set to a larger value than that of the third dummy transistor farther from the bit line than that.
Non-volatile semiconductor, characterized in that the fifth dummy transistor located closer to the source line, the voltage applied to the gate is set to a larger value than the fifth dummy transistor located farther from the source line than that. store. The second dummy word line of each of a plurality of sub blocks is commonly connected to the first dummy word line and the second dummy word line of another sub block. Nonvolatile Semiconductor Memory. The nonvolatile semiconductor memory device according to claim 1, wherein a distance between said drain side selection gate line or said source side selection gate line and said word line is larger than a distance between said word lines. The control circuit of claim 1, wherein the control circuit is further configured to supply the fourth voltage and the second voltage before supplying a target voltage to the bit line, the source line, the drain side select gate line, or the source side select gate line. A nonvolatile semiconductor memory device configured to supply a fifth voltage of approximately intermediate. As a control method of a nonvolatile semiconductor memory device,
The nonvolatile semiconductor memory device,
A memory cell array having a plurality of memory blocks;
A plurality of memory strings formed by serially connecting a plurality of memory transistors arranged in a matrix and electrically rewritable in each of the plurality of memory blocks;
A drain side selection transistor having one end connected to a first end of the memory string;
A source side select transistor having one end connected to a second end of the memory string;
A plurality of word lines arranged to be commonly connected to the plurality of memory strings arranged in one of the plurality of memory blocks;
A plurality of bit lines each extending in a first direction and connected to the other ends of the drain side selection transistors present in the plurality of memory blocks;
A source line connected to the other end of the source side select transistor,
A drain side select gate line arranged with the second direction in the longitudinal direction so as to commonly connect the gates of the drain side select transistors arranged in a second direction perpendicular to the first direction;
A source side select gate line disposed with the second direction in a longitudinal direction so as to commonly connect the gates of the source side select transistors arranged in the second direction,
Each of the plurality of memory strings,
A columnar semiconductor layer including a columnar portion extending in a direction perpendicular to the substrate and functioning as a body of the memory transistor;
A charge accumulation layer formed to surround the side surface of the columnar portion and configured to accumulate charge;
A word line conductive layer formed to surround the side surface of the columnar portion via the charge storage layer, and functioning as a gate of the memory transistor and the word line;
A plurality of drain side select transistors commonly connected to one of the drain side select gate lines and one source side select gate line and a plurality of the memory strings connected to a plurality of source side select transistors constitute one sub block. and,
When performing an erase operation for selectively erasing at least one sub block of the memory blocks,
In the selected first sub block, a first voltage is applied to the bit line and the source line, while a second voltage smaller than the first voltage is applied to the word line, and the drain side selection gate line and the source are applied. An erase operation is applied to the side select gate line by applying a third voltage lower than the first voltage by a predetermined value.
In the second sub block existing in the same memory block as the selected sub block and non-selected, an erase operation is performed by applying a fourth voltage approximately equal to the first voltage to the drain side selection gate line and the source side selection gate line. The control method of the nonvolatile semiconductor memory device characterized by the above-mentioned. 20. The method of claim 19, wherein the third voltage is set to the extent to generate a GIDL current (Gate Induced Drain Leakage Current) by the potential difference with the first voltage,
And the fourth voltage is set to such an extent that generation of a GIDL current is prohibited by a potential difference with the first voltage.

Images