TWI684992B - On-die-termination circuit and control method for of the same - Google Patents

Abstract

An on-die-termination (ODT) circuit is connected to a memory module and includes a first transmission line, a first ODT, a second ODT, a first switch circuit, a third ODT, a fourth ODT, a second switch circuit, and an ODT control logic. The first ODT and the second ODT are coupled to a first node on the first transmission line. The first switch circuit includes a first switch and a second switch, and is driven according to the first control signal. The third ODT and the fourth ODT are coupled to a second node on the first transmission line. The second switch circuit includes a third switch and a fourth switch, and is driven according to the second control signal. The ODT control logic outputs the first control signal and the second control signal to control the first switch circuit and the second switch circuit to be turned on at different timings.

Description

Terminal resistance circuit and its control method

The invention relates to a terminal resistance circuit and a control method thereof, in particular to a terminal resistance circuit with a time-sharing conduction mechanism and a control method thereof.

A traditional dynamic random access memory (DRAM) module usually includes an on-die termination (ODT), which is used for impedance matching of signal lines and reduces signal distortion. Traditional termination resistors are usually coupled to a reference voltage, such as a ground voltage.

In the existing memory, when the controller reads, it will first open ODT (On-Die-Termination), so that the data signal pin DQ/DQS/DQS# of DDR3/LPDDR2/LPDDR3 stays at 1/2VDD standard DDR4 stops at VDD level and LPDDR4 stops at VSS level. When ODT is turned on, the voltage of the power node in the chip or the voltage of the ground node in the chip will jump due to the simultaneous driving current caused by the simultaneous opening.

Specifically, since there is a package power inductor between the external power node and the on-chip power node, and there is a package ground inductor between the external ground node and the on-chip ground node, the voltage difference is as follows (1) , (2): V-V'=Lp(di/dt)...... Equation (1)

G’-G=Lg(di/dt)... Equation (2)

Where V is the external power node potential, V'is the on-chip power node potential, G is the external ground node potential, G'is the on-chip ground node potential, Lp is the package power inductance value, Lg is the package ground inductance, and i is the current , T is the time. From the above, it can be seen that the voltage of the power node in the chip or the voltage of the ground node in the chip jumps due to the package power inductance and the package ground inductance during ODT startup, which affects the operation of the memory module.

Therefore, how to improve the design of the termination resistance circuit control mechanism to reduce the voltage jitter of the power node in the chip or the voltage jitter of the ground node in the chip, and overcome the above-mentioned defects, has become one of the important issues to be solved by this business.

The technical problem to be solved by the present invention is to provide a termination resistance circuit and its control method in view of the deficiencies of the prior art.

In order to solve the above technical problems, one of the technical solutions adopted by the present invention is to provide a termination resistor circuit connected to a memory module, which includes a first transmission line, a first termination resistor, a second termination resistor, a first Switching circuit, third terminal resistance, fourth terminal resistance, second switching circuit and terminal resistance control logic. The first transmission line is used to transmit data between the memory module and the first pad. The first termination resistor is coupled to the first node on the first transmission line. The second terminal resistor is coupled to the first node. The first switch circuit includes a first switch and a second switch, the first switch is coupled between the power node in the first chip and the first terminal resistor, and is driven according to the first control signal, and the second switch is coupled to the second The terminal resistance and the ground node in the first chip are driven according to the first control signal. The third termination resistor is coupled to the second node on the first transmission line. The fourth termination resistor is coupled to the second node. The second switch circuit includes a third switch and a fourth switch. The third switch is coupled between the power node in the second chip and the third terminal resistor, and is driven according to the second control signal. The fourth switch is coupled to the fourth Between the terminating resistor and the ground node in the second chip, and according to the Two control signals are driven. The terminal resistance control logic is configured to output the first control signal and the second control signal to control the first switch circuit and the second switch circuit to conduct at different time points.

In order to solve the above technical problems, another technical solution adopted by the present invention is to provide a control method for a termination resistor circuit, which is suitable for a memory module. The control method includes: setting a termination resistor circuit connected to the memory module The termination resistance circuit includes a first transmission line, a first termination resistance, a second termination resistance, a first switching circuit, a third termination resistance, a fourth termination resistance, a second switching circuit, and a termination resistance control logic. The first transmission line is used to transmit data between the memory module and the first pad. The first termination resistor is coupled to the first node on the first transmission line. The second terminal resistor is coupled to the first node. The first switch circuit includes a first switch and a second switch, the first switch is coupled between the power node in the first chip and the first terminal resistor, and is driven according to the first control signal, and the second switch is coupled to the second The terminal resistance and the ground node in the first chip are driven according to the first control signal. The third termination resistor is coupled to the second node on the first transmission line. The fourth termination resistor is coupled to the second node. The second switch circuit includes a third switch and a fourth switch. The third switch is coupled between the power node in the second chip and the third terminal resistor, and is driven according to the second control signal. The fourth switch is coupled to the fourth The terminal resistor and the ground node in the second chip are driven according to the second control signal. The terminal resistance control logic is configured to output the first control signal and the second control signal to control the first switch circuit and the second switch circuit to conduct at different time points. The control method further includes configuring the terminal resistance control logic to output the first control signal and the second control signal to control the first switch circuit and the second switch circuit to conduct at different time points.

In order to further understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and explanation only, and are not intended to limit the present invention.

1‧‧‧ Terminal resistance circuit

100‧‧‧Memory module

102‧‧‧Terminal resistance control logic

I, Ia, Ib ‧‧‧ total current

L1‧‧‧ First transmission line

L2‧‧‧Second transmission line

N1‧‧‧First node

N2‧‧‧The second node

N3‧‧‧The third node

N4‧‧‧The fourth node

N5‧‧‧ fifth node

N6‧‧‧Sixth node

ODT_S1‧‧‧First control signal

ODT_S2‧‧‧Second control signal

ODT_S3‧‧‧third control signal

ODT_S4‧‧‧ Fourth control signal

ODT_S5‧‧‧Fifth control signal

ODT_S6 The sixth control signal

PAD1‧‧‧First pad

PAD2‧‧‧Second pad

R11‧‧‧ First terminating resistor

R12‧‧‧Second termination resistor

R21‧‧‧Third termination resistor

R22‧‧‧Fourth terminating resistor

R31‧‧‧The fifth terminating resistor

R32‧‧‧The sixth terminating resistor

R41‧‧‧The seventh terminating resistor

R42‧‧‧Eighth terminating resistor

R51‧‧‧Ninth terminating resistor

R52‧‧‧Tenth terminal resistance

R61‧‧‧Eleventh termination resistor

R62‧‧‧Twelfth terminating resistor

S1‧‧‧ First switch circuit

S11‧‧‧ First switch

S12‧‧‧Second switch

S2‧‧‧ Second switch circuit

S21‧‧‧The third switch

S22‧‧‧The fourth switch

S3‧‧‧ Third switch circuit

S31‧‧‧ fifth switch

S32‧‧‧Sixth switch

S4‧‧‧ fourth switching circuit

S41‧‧‧The seventh switch

S42‧‧‧Eighth switch

S5‧‧‧ fifth switching circuit

S51‧‧‧Ninth switch

S52‧‧‧Tenth switch

S6‧‧‧Sixth switch circuit

S61‧‧‧Eleventh switch

S62‧‧‧The twelfth switch

T‧‧‧Time

V’‧‧‧Electrical node potential of the chip

VDD1‧‧‧ Power supply node in the first chip

VDD2‧‧‧Power supply node in the second chip

VDD3‧‧‧Power supply node in the third chip

VDD4 ‧‧‧ power supply node in the fourth chip

VDD5‧‧‧‧ Power supply node in the fifth chip

VDD6 power supply node in the sixth chip

VSS1‧‧‧Earth node in the first chip

VSS2‧‧‧Earth node in the second chip

VSS3‧‧‧Earth node in the third chip

VSS4‧‧‧Earth node in the fourth chip

VSS5‧‧‧Earth node in the fifth chip

VSS6‧‧‧Earth node in the sixth chip

FIG. 1 is a circuit diagram of a terminating resistance circuit according to the first embodiment of the present invention.

FIG. 2 is a graph of the total current of simultaneous conduction and time-sharing conduction and the potential of the power supply node in the chip versus time in the first embodiment of the present invention.

3 is a circuit diagram of a terminating resistance circuit according to a second embodiment of the present invention.

FIG. 4 is a graph of the total current of simultaneous conduction and time-sharing conduction and the potential of the power supply node in the chip versus time in the second embodiment of the present invention.

5 is a circuit diagram of a terminating resistance circuit according to a third embodiment of the present invention.

6 is a flowchart of a control method of a terminating resistance circuit according to a fourth embodiment of the invention.

The following are specific specific examples to illustrate the implementation of the "terminal resistance circuit and its control method" disclosed by the present invention. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments. Various details in this specification can also be based on different viewpoints and applications, and various modifications and changes can be made without departing from the concept of the present invention. In addition, the drawings of the present invention are merely schematic illustrations, and are not drawn according to actual sizes, and are declared in advance. The following embodiments will further describe the related technical content of the present invention, but the disclosed content is not intended to limit the protection scope of the present invention.

It should be understood that although terms such as “first”, “second”, and “third” may be used herein to describe various elements or signals, these elements or signals should not be limited by these terms. These terms are mainly used to distinguish one component from another component, or one signal from another signal. In addition, the term "or" as used herein may include any combination of any one or more of the associated listed items, depending on the actual situation.

[First embodiment]

Referring to FIG. 1, FIG. 1 is a terminal resistance circuit according to the first embodiment of the present invention. Circuit diagram. The first embodiment of the present invention provides a termination resistor circuit 1 connected to a memory module 100, which includes a first transmission line L1, a first termination resistor R11, a second termination resistor R12, a first switching circuit S1, and a third terminal The resistor R21, the fourth termination resistor R22, the second switching circuit S2, and the termination resistor control logic 102.

The first transmission line L1 is used to transmit data between the memory module 100 and the first pad PAD1. The first termination resistor R11 is coupled to the first node N1 on the first transmission line L1. The second termination resistor R12 is coupled to the first node N1. The first switch circuit S1 includes a first switch S11 and a second switch S12. The first switch S11 is coupled between the power supply node VDD1 and the first termination resistor S11 in the first chip, and is driven according to the first control signal ODT_S1. The two switches S12 are coupled between the second termination resistor R12 and the ground node VSS1 in the first chip, and are also driven according to the first control signal ODT_S1.

Preferably, the third termination resistor R21 is coupled to the second node N2 on the first transmission line L1. The fourth termination resistor R22 is coupled to the second node N2. The second switch circuit S2 includes a third switch S21 and a fourth switch S22. The third switch S21 is coupled between the power supply node VDD2 and the third termination resistor R21 in the second chip, and is driven according to the second control signal ODT_S2, and The fourth switch S22 is coupled between the fourth termination resistor R22 and the ground node VSS2 in the second chip, and is also driven according to the second control signal ODT_S2. The power node VDD1 in the first chip and the power node VDD2 in the second chip can be connected to the same power source, and the ground node VSS1 in the first chip and the ground node VSS2 in the second chip can be connected to the same ground terminal.

In addition, the terminal resistance circuit 1 further includes a terminal resistance control logic 102 configured to output the first control signal ODT_S1 and the second control signal ODT_S2 to control the first switch circuit S1 and the second switch circuit S2 to conduct at different time points. The first switching circuit S1 and the second switching circuit S2 may include, but are not limited to, a P-type metal oxide semiconductor field effect transistor (PMOSFET), an N-type metal oxide semiconductor field effect transistor (NMOSFET), and a transmission gate (Transmission) Gate).

In detail, the terminating resistor (ODT) control logic 102 can be configured with an external ODT pin. When an ODT enable signal is applied to an external ODT pin provided outside the memory chip, the ODT enable signal can be transmitted to The ODT control logic 102 provided inside the memory chip. The ODT control logic 102 can generate the first control signal ODT_S1 and the second control signal ODT_S2 according to the target resistance set in the extended mode register set (EMRS). The termination resistance control logic 102 may be, or be included in, a memory controller, which is a bus circuit controller used to manage and plan the transmission speed from the memory to the processor. The memory controller may be a single chip or integrated into a related large chip, which may be, for example, a microprocessor or a memory controller built in Northbridge.

When the first control signal ODT_S1 and the second control signal ODT_S2 are applied, the first switch circuit S1 and the second switch circuit S2 are driven according to the logic states of the first control signal ODT_S1 and the second control signal ODT_S2, and according to the predetermined termination resistance Value to terminate the first pad PAD1. Here, the DQ, DQS, /DQS and other pins of the memory module 100 can be terminated. The advantage of this method is that it can save the terminal resistors and other electronic components on the motherboard, so the manufacturing cost of the circuit board can be greatly reduced, and the design of the motherboard can be more concise. Furthermore, since idle memory chips can be quickly turned on and off, the power consumption when the memory is idle is greatly reduced. In addition, the termination from the inside of the chip will be more timely and effective than the termination from the motherboard, thereby reducing the latency of the memory delay. This also makes it possible to further increase the memory, for example to increase the operating frequency of DDR2, DDR3 (L), DDR4, LPDDR2/3/4 and other memory.

Please further refer to FIG. 2, which is a graph of the total current of simultaneous conduction and time-sharing conduction and the potential of the power supply node in the chip versus time in the first embodiment of the present invention. As shown in the figure, Ia represents the total current that the first switching circuit S1 and the second switching circuit S2 conduct simultaneously during the time 1T, and Ib represents the total current that the first switching circuit S1 and the second switching circuit S2 conduct during the time division 2T Current, V'is the potential of the power supply node in the chip. According to the above formulas (1) and (2), it can be seen that when the first termination resistance R11, the second termination resistance R12, the third termination resistance R21 and the fourth termination resistance R22 are grouped and turned on in time-sharing, it can be reduced The di/dt value when ODT is turned on, which further reduces the voltage jitter of the on-chip power node or the on-chip ground node formed by L(p/g)*di/dt, thereby maintaining the first transmission line L1 in the memory module Constant voltage during data transmission between 100 and the first pad PAD1. The conduction time of the first switch circuit S1 and the second switch circuit S2 may be adjusted, for example, the two may be a fixed time difference or different time differences.

[Second Embodiment]

Please refer to FIG. 3, which is a circuit diagram of a terminating resistor circuit according to a second embodiment of the present invention. The second embodiment of the present invention further provides a terminating resistance circuit 1, which is changed based on the terminating resistance circuit 1 of FIG. 1, and therefore repeated description is omitted. In this embodiment, the termination resistor circuit 1 further includes a fifth resistor R31, a sixth resistor R32, a third switch circuit S3, a seventh resistor R41, an eighth resistor R42, and a fourth switch circuit S4.

Further, the fifth resistor R31 is coupled to the third node N3 on the first transmission line L1, and the sixth resistor R32 is also coupled to the third node N3. The seventh resistor R41 is coupled to the fourth node N4 on the first transmission line L1, and the eighth resistor R42 is also coupled to the fourth node.

In addition, the termination resistance circuit 1 further includes a third switch circuit S3 and a fourth switch circuit S4. The third switch circuit S3 includes a fifth switch S31 and a sixth switch S32. The fifth switch S31 is coupled between the power node VDD3 and the fifth resistor R31 in the third chip, and is driven according to the third control signal ODT_S3. On the other hand, the sixth switch S32 is coupled between the sixth resistor R32 and the ground node VSS in the third chip, and is driven according to the third control signal ODT_S3.

The fourth switch circuit S4 includes a seventh switch S41 and an eighth switch S42. The seventh switch S41 is coupled between the power node VDD4 and the seventh resistor R41 in the fourth chip, and is driven according to the fourth control signal ODT_S4, and the eighth switch S42 is coupled between the eighth resistor R42 and the fourth chip ground The nodes VSS are also driven according to the fourth control signal ODT_S4.

The third switch circuit S3 and the fourth switch circuit S4 may include, but are not limited to, P-type gold It belongs to oxide semiconductor field effect transistor (PMOSFET), N-type metal oxide semiconductor field effect transistor (NMOSFET) and transmission gate (Transmission Gate).

The terminal resistance control logic 102 is further configured to output the third control signal ODT_S3 and the fourth control signal ODT_S4. Similarly, when the third control signal ODT_S3 and the fourth control signal ODT_S4 are applied, the third switch circuit S3 and the fourth switch circuit S4 are driven according to the logic states of the third control signal ODT_S3 and the fourth control signal ODT_S4, and according to the predetermined To terminate the first pad PAD1. Here, the DQ, DQS, /DQS and other pins of the memory module 100 can be terminated.

In this embodiment, the conduction time points of the first switch circuit S1, the second switch circuit S2, the third switch circuit S3, and the fourth switch circuit S4 may be operated in different groups. For example, the terminal resistance control logic 102 may be configured to control the first switch circuit S1, the second switch circuit S2, the third switch circuit S3, and the fourth switch circuit S4 to be turned on at different time points, that is, divided into four groups Turn on.

On the other hand, the termination resistance control logic 102 may be configured to control the first switch circuit S1 and the third switch circuit S3 to be turned on at the same time, and to control the second switch circuit S2 and the fourth switch circuit S4 to be turned on at the same time, That is, it is divided into two groups to conduct.

Please further refer to FIG. 4, which is a graph of the total current of simultaneous conduction and time-sharing conduction and the potential of the power supply node in the chip versus time in the second embodiment of the present invention. As shown in the figure, I represents the total current under various conditions. According to the above formulas (1) and (2), it can be seen that when the terminal resistances are grouped and turned on in time-sharing, the di/dt value when ODT is turned on can be reduced, and further formed by L(p/g)*di/dt The voltage of the power node in the chip or the voltage of the ground node in the chip jumps, thereby maintaining the constant voltage of the first transmission line L1 when transmitting data between the memory module 100 and the first pad PAD1.

Among them, the first switch circuit S1, the second switch circuit S2, the third switch circuit S3 and the fourth switch circuit S4 can be divided into two groups or four groups of conduction, and the first switch circuit S1, the second switch circuit S2, The conduction time of the third switch circuit S3 and the fourth switch circuit S4 is adjusted, for example, two It can be a fixed time difference or a different time difference, and because the larger the number of packets, the more time it will take to complete the ODT opening. Therefore, the user can design the memory chip and refer to the external power node and the on-chip power node The value of the package power inductance between the external ground node and the in-chip ground node between the package ground inductance value determines the required delay time and the number of packets.

[Third Embodiment]

Please refer to FIG. 5, which is a circuit diagram of a terminating resistor circuit according to a third embodiment of the present invention. The third embodiment of the present invention additionally provides a terminating resistance circuit 1, which is changed based on the terminating resistance circuit 1 of FIG. 1, and therefore repeated description is omitted. In this embodiment, the termination resistance circuit 1 further includes a second transmission line L2, a ninth resistance R51, a tenth resistance R52, a fifth switching circuit S5, an eleventh resistance R61, a twelfth resistance R62, and a sixth switching circuit S6 .

The second transmission line L2 is used to transmit data between the memory module 100 and the second pad PAD2. The ninth resistor R51 is coupled to the fifth node N5 on the second transmission line L2, and the tenth resistor R52 is also coupled to the fifth node N5. The eleventh resistor R61 is coupled to the sixth node N6 on the second transmission line L2, and the twelfth resistor R62 is also coupled to the sixth node N6.

The fifth switch circuit S5 includes a ninth switch S51 and a tenth switch S52. The ninth switch S51 is coupled between the power node VDD5 and the ninth resistor R51 in the fifth chip, and is driven according to the fifth control signal ODT_S5. The tenth switch S52 is coupled between the tenth resistor R52 and the ground node VSS5 in the fifth chip, and is also driven according to the fifth control signal ODT_S5.

On the other hand, the sixth switch circuit S6 includes an eleventh switch S61 and a twelfth switch S62. The eleventh switch S61 is coupled between the power supply node VDD6 and the eleventh resistor R61 in the sixth chip. Driven by the control signal ODT_S6. The twelfth switch S62 is coupled between the twelfth resistor R62 and the ground node VSS6 in the sixth chip, and is also driven according to the sixth control signal ODT_S6.

Here, the power node VDD1 in the first chip and the power node VDD2 in the second chip can be connected to the same power source, the power node VDD5 in the fifth chip and the power node VDD6 in the sixth chip can be connected to the same power source, and the first chip is grounded The node VSS1 and the ground node VSS2 in the second chip can be connected to the same ground, and the ground node VSS5 in the fifth chip and the ground node VSS6 in the sixth chip can be connected to the same ground.

The terminal resistance control logic 102 is further configured to output the fifth control signal ODT_S5 and the sixth control signal ODT_S6 to control the first switch circuit S1, the second switch circuit S2, the fifth switch circuit S5, and the sixth switch circuit S6 at Conducted at different times.

The fifth switching circuit S5 and the sixth switching circuit S6 may include, but are not limited to, a P-type metal oxide semiconductor field effect transistor (PMOSFET), an N-type metal oxide semiconductor field effect transistor (NMOSFET), and a transmission gate (Transmission) Gate).

Similarly, when the first control signal ODT_S1 and the second control signal ODT_S2 are applied, the first switch circuit S1 and the second switch circuit S2 are driven according to the logic states of the first control signal ODT_S1 and the second control signal ODT_S2, and according to the predetermined To terminate the first pad PAD1. When the fifth control signal ODT_S5 and the sixth control signal ODT_S6 are applied, the fifth switch circuit S5 and the sixth switch circuit S6 are driven according to the logic states of the fifth control signal ODT_S5 and the sixth control signal ODT_S6, and according to the predetermined terminal The resistance value terminates the second pad PAD2. Here, the DQ, DQS, /DQS and other pins of the memory module 100 can be terminated.

According to the above formulas (1) and (2), it can be seen that when the terminal resistances are grouped and turned on in time-sharing, the di/dt value when ODT is turned on can be reduced, and further formed by L(p/g)*di/dt The voltage of the power node in the chip or the voltage of the ground node in the chip jumps, thereby maintaining the constant voltage of the first transmission line L1 when transferring data between the memory module 100 and the first pad PAD1, and maintaining the second transmission line L2 in memory Constant voltage during data transmission between the body module 100 and the second pad PAD2.

It should be noted that in the above embodiments, the terminating resistors connected to each transmission line The number is not limited to the number provided in the embodiment.

[Fourth embodiment]

Please refer to FIG. 6, which is a flowchart of a method for controlling a terminating resistance circuit according to a fourth embodiment of the present invention. This embodiment provides a method for controlling a terminating resistance circuit, which is applicable to the above-described first to third embodiments, and is not limited to the sequence shown in the flowchart.

The control method of the terminal resistance circuit of the present invention is applicable to a memory module. The control method includes:

Step S100: Set a terminal resistance circuit connected to the memory module.

In detail, the termination resistance circuit may include the termination resistance circuits of the first to third embodiments described above, and therefore will not be repeated here.

Step S102: Determine a plurality of switches according to the voltage jump condition generated by the package power inductance value between the external power node of the chip and the power node inside the chip, and the package ground inductance value between the external ground node and the ground node of the chip Circuit grouping and conduction time.

Step S104: Configure the terminal resistance control logic to output a control signal to control the plurality of switch circuits to conduct at different time points according to the grouping method and conduction time of the plurality of switch circuits.

[Beneficial effect of embodiment]

One of the beneficial effects of the present invention is that the terminal resistance circuit and its control method provided by the present invention can reduce the current-to-time change value when the ODT is turned on by grouping each terminal resistance and performing time-division conduction control. Furthermore, the voltage of the power node in the chip or the voltage jump of the ground node in the chip formed by the package internal power inductance or the package internal ground node inductance is further reduced, thereby maintaining the constant voltage of each transmission line when transmitting data between the memory module and the pad .

In addition, a plurality of switching circuits can be divided into multiple groups for conducting control, and the conducting time of each switching circuit can be adjusted. And the user can design according to the memory chip, and refer to the package power inductance value between the external power node and the on-chip power node, and the external ground node The voltage jump caused by the package ground inductance value between the ground node in the chip determines the required delay time and the number of packets.

The content disclosed above is only a preferred and feasible embodiment of the present invention, and therefore does not limit the scope of the patent application of the present invention, so any equivalent technical changes made by using the description and drawings of the present invention are included in the application of the present invention. Within the scope of the patent.

1‧‧‧ Terminal resistance circuit

100‧‧‧Memory module

102‧‧‧Terminal resistance control logic

L1‧‧‧ First transmission line

N1‧‧‧First node

N2‧‧‧The second node

ODT_S1‧‧‧First control signal

ODT_S2‧‧‧Second control signal

PAD1‧‧‧First pad

R11‧‧‧ First terminating resistor

R12‧‧‧Second termination resistor

R21‧‧‧Third termination resistor

R22‧‧‧Fourth terminating resistor

S1‧‧‧ First switch circuit

S11‧‧‧ First switch

S12‧‧‧Second switch

S2‧‧‧ Second switch circuit

S21‧‧‧The third switch

S22‧‧‧The fourth switch

VDD1‧‧‧ Power supply node in the first chip

VDD2‧‧‧Power supply node in the second chip

VSS1‧‧‧Earth node in the first chip

VSS2‧‧‧Earth node in the second chip

Claims (10)

A terminal resistance circuit, connected to a memory module, includes: a first transmission line for transmitting data between the memory module and a first pad; a first termination resistor, coupled to A first node on the first transmission line; a second terminal resistor coupled to the first node; a first switch circuit including: a first switch coupled to a first on-chip power supply node and Between the first terminal resistors and driven according to a first control signal; and a second switch coupled between the second terminal resistor and a ground node in the first chip and according to the first control signal And drive; a third terminal resistor, coupled to a second node on the first transmission line; a fourth terminal resistor, coupled to the second node; a second switch circuit, including: a third switch , Coupled between a second chip power node and the third terminal resistor, and driven according to a second control signal; and a fourth switch, coupled to the fourth terminal resistor and a second chip Between ground nodes and driven according to the second control signal; and a termination resistance control logic configured to divide the first switch circuit and the second switch circuit into a plurality of groups and output the first control signal And the second control signal to control the first switch circuit and the second switch circuit to be turned on at different time points according to the groups. The termination resistance circuit as described in item 1 of the patent application scope, wherein the power node in the first chip is connected to the power node in the second chip, and the ground node in the first chip is connected to the ground node in the second chip. The terminating resistor circuit as described in item 1 of the scope of the patent application further includes: a fifth resistor coupled to a third node on the first transmission line; A sixth resistor, coupled to the third node; a third switch circuit, including: a fifth switch, coupled between a third on-chip power supply node and the fifth resistor, and according to a third Driven by a control signal; and a sixth switch, coupled between the sixth resistor and a ground node in a third chip, and driven according to the third control signal; a seventh resistor, coupled to the first A fourth node on the transmission line; an eighth resistor, coupled to the fourth node; and a fourth switch circuit, including: a seventh switch, coupled to a fourth on-chip power supply node and the seventh Between the resistors and driven according to a fourth control signal; and an eighth switch, coupled between the eighth resistor and a ground node in the fourth chip, and driven according to the fourth control signal, wherein the The termination resistance control logic is further configured to output the third control signal and the fourth control signal. The terminating resistance circuit as described in item 3 of the patent scope, wherein the terminating resistance control logic is configured to control the first switching circuit, the second switching circuit, the third switching circuit, and the fourth switching circuit at different times Point conduction. The terminating resistance circuit as described in item 3 of the patent application scope, wherein the terminating resistance control logic is configured to control the first switching circuit and the third switching circuit to be turned on at the same time, and to control the second switching circuit and the The fourth switch circuit is turned on at the same time. The terminating resistance circuit as described in item 3 of the patent application scope, wherein the first on-chip power node is connected to the second on-chip power node, the third on-chip power node and the fourth on-chip power node, and the The first on-chip ground node is connected to the second on-chip ground node, the third on-chip ground node, and the fourth on-chip ground node. The terminating resistor circuit as described in item 1 of the patent application scope further includes: a second transmission line for transmitting data between the memory module and a second pad; a ninth resistor, coupled to the A fifth node on the second transmission line; a tenth resistor, coupled to the fifth node; a fifth switch circuit, including: a ninth switch, coupled to a fifth on-chip power supply node and the first Between nine resistors and driven according to a fifth control signal; and a tenth switch coupled between the tenth resistor and a ground node in the fifth chip and driven according to the fifth control signal; one An eleventh resistor, coupled to a sixth node on the second transmission line; a twelfth resistor, coupled to the sixth node; and a sixth switch circuit, including: an eleventh switch, coupled Between a power node in the sixth chip and the eleventh resistor, and driven according to a sixth control signal; and a twelfth switch, coupled to the twelfth resistor and a ground node in the sixth chip And driven according to the sixth control signal, wherein the termination resistance control logic is further configured to output the fifth control signal and the sixth control signal to control the first switch circuit, the second switch circuit, The fifth switch circuit and the sixth switch circuit are turned on at different time points. The terminating resistance circuit as described in item 7 of the patent application scope, wherein the first on-chip power node is connected to the second on-chip power node, and the fifth on-chip power node is connected to the sixth on-chip power node, the The ground node in the first chip is connected to the ground node in the second chip, and the ground node in the fifth chip is connected to the ground node in the sixth chip. A control method for a terminal resistance circuit is applicable to a memory module. The control method includes: A terminal resistance circuit connected to the memory module is provided, which includes: a first transmission line for transmitting data between the memory module and a first pad; a first terminal resistance, coupled to A first node on the first transmission line; a second terminal resistor coupled to the first node; a first switch circuit including: a first switch coupled to a first on-chip power supply node and Between the first terminal resistors, and driven according to a first control signal; and a second switch, coupled between the second terminal resistor and a ground node in the first chip, and according to the first control signal Drive; a third terminal resistor, coupled to a second node on the first transmission line; a fourth terminal resistor, coupled to the second node; a second switch circuit, including: a third switch , Coupled between a second chip power node and the third terminal resistor, and driven according to a second control signal; and a fourth switch, coupled to the fourth terminal resistor and a second chip Between ground nodes and driven according to the second control signal; configuring a termination resistance control logic to divide the first switch circuit and the second switch circuit into a plurality of groups, and output the first control signal and the second The control signal controls the first switch circuit and the second switch circuit to be turned on at different time points according to the groups. The control method of the terminating resistance circuit as described in item 9 of the patent scope, wherein the power node in the first chip is connected to the power node in the second chip, and the ground node in the first chip is connected to the second chip Ground node.

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