KR20060062551A - Delay circuit for on-die termination - Google Patents

Abstract

The present invention discloses a delay circuit for on-die termination. The delay circuit for on-die termination includes delay increasing fuses, and when the delay increasing fuses are cut, delays the clock signal by a first delay time, and transmits the clock signal when the first fuses are not cut. At least one delay increasing circuit for transmitting the signal as it is, and the delay reducing fuses, the clock signal is passed as is when the delay reducing fuses are cut, the second delay if the fuses are not cut And at least one delay reduction circuit for delayed transmission by time. Thus, delay circuits for on die termination allow for adaptively variable delay components through a fuse or mode register set. Accordingly, the delay time can be adaptively changed according to the process change of the semiconductor memory device, and the on-die termination AC parameter specification is recommended.

Description

Delay circuit for On-Die Termination

1 is a partial block diagram of a semiconductor memory device having an on die termination circuit according to the prior art.

2 illustrates a delay circuit for on die termination according to a first embodiment of the present invention.

3 illustrates a delay circuit for on die termination according to a second embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a delay circuit for on-die termination that variably delays an internal clock signal of a delay-locked loop (DLL) and then applies it to an on-die termination driver.

As the semiconductor memory devices become faster, the swing width of signals interfaced between the semiconductor memory devices is gradually decreasing. The reason is to minimize the delay time for signal transmission.

However, as the swing width of the signal decreases, the influence on external noise increases, and the reflection of the signal due to impedance mismatching at the interface stage is also critical.

These impedance mismatches are caused by external noise, fluctuations in power supply voltage, changes in operating temperature, or changes in manufacturing processes. When impedance mismatches occur, high-speed data transfer is difficult and output data may be distorted. .

Therefore, when the distorted output signal is transmitted, problems such as setup / hold fail or input level judgment error may frequently occur at the receiving end.

In particular, in electronic products employing dynamic random access memory (DRAM), the frequency of the signal bus has been remarkably increased to realize high speed operation. Accordingly, various researches have been conducted on bus termination techniques to solve the impedance mismatching problem and minimize the distortion of signal integrity. In one of those studies, the use of On-Die Termination (ODT) rather than Mother Board Termination (MBT), especially in electronic systems with stub bus structures It is known to be more advantageous in terms of signal integrity.

In this case, the on-die termination refers to a termination structure in which bus termination is performed at an I / O port of a memory mounted in a memory module. In turn, the on-die termination is an impedance matching circuit, also referred to as on-chip termination, which is employed near pads in integrated circuit chips.

In semiconductor memory devices, such as DDR (Double Data Rate) type synchronous DRAM (SDRAM), a typical on-die termination for impedance matching involves connecting a resistor having a fixed resistance value to a pad. Is achieved.

FIG. 1 is a block diagram of a semiconductor memory device including the on die termination circuit. The semiconductor memory device including the on die termination circuit includes a DLL 1, a delay circuit for on die termination 2, An ODT gate 3 and an ODT driver 4 are provided.

The DLL 1 generates an internal clock signal CLK, and the on-die termination delay circuit 2 has a delay component having a fixed value, and delays the clock signal CLK by a predetermined time according to the delay component. Generates an on-die termination clock signal (ODT_CLK), and the ODT gate (3) receives an on-die termination comment (PODT) transmitted from an internal circuit (not shown) to the on-die termination clock signal (ODT_CLK). In synchronization, the on-die termination output up and down signals ODT_UP and ODT_DN are generated, and the on-die termination driver 4 performs a termination operation in response to the on-die termination up and down signals ODT_UP and ODT_DN.

As described above, the conventional semiconductor memory device determines the operation time of the on-die termination driver 4 through the delay circuit 2 for the on-die termination.

However, the on-die termination delay circuit 2 has only a fixed delay component (for example, a fixed resistance value), and thus cannot support various termination operations due to process changes. That is, when the delay component of the on-die termination delay circuit 2 is previously set to a default value, it is difficult to adjust the delay time in various ways according to the change of the process environment.

Accordingly, in the conventional delay circuit 2 for on-die termination, there is a need to manufacture a new mask having a new delay component in order to newly adjust the delay time.

In addition, on-die termination alternating current (AC) parameter specification is recommended in high-speed semiconductor memory devices, and on-die termination measures are required to satisfy this comfortably.

The high-speed semiconductor memory features adaptive on-die termination techniques to ensure that the on-die termination (AC) parameter specification is met, as well as the termination operation optimized according to the process environment can be performed under external or internal control. More and more necessary in the device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a delay circuit for on-die termination in which a delay component is changed using a fuse or a mode register set, and the delay time can be easily changed through the variable delay component.

The delay circuit for on-die termination according to the first aspect of the present invention for achieving the above object is provided with a delay increasing fuse, and when the delay increasing fuses are cut off, the clock signal is delayed and transmitted by a first delay time. And at least one delay increasing circuit which transfers the clock signal as it is, when the first fuses are not cut, and delay reducing fuses, and when the delay reducing fuses are cut. It is provided as it is, characterized in that it comprises at least one delay reducing circuit for delayed transmission by the second delay time when the fuse is not cut.

The delay circuit for on-die termination according to the second aspect of the present invention for achieving the above object transmits the clock signal by delaying the clock signal by a first delay time when the control signal is in the first state, and when the control signal is in the second state, At least one delay increasing circuit for transmitting the clock signal as it is, and if the control signal is in the first state, the clock signal is transmitted as it is; if the control signal is in the second state, the clock signal is delayed by a second delay time as it is. At least one delay reduction circuit for transmitting.

Hereinafter, a delay circuit for on-die termination of the present invention will be described with reference to the accompanying drawings.

2 is a diagram illustrating a delay circuit for on die termination according to a first embodiment of the present invention.

Continuing with reference to the drawings, the delay circuit 20 for on die termination includes a plurality of delay increasing circuits 21 and 23 and a plurality of delay reducing circuits 22 and 24, and each delay increasing circuit 21 includes: Pull-up resistor 212 located between inverter 211, inverter 211 and power supply voltage VDD, fuse 213 for pull-up resistor parallel to pull-up resistor 212, inverter 211 and ground voltage ( A pull-down resistor 214 positioned between VSS and a pull-down resistor fuse 215 parallel to the pull-down resistor 214, and the delay reduction circuit 22 includes a node N1 of a current path and a power supply voltage ( PMOS capacitor 221 and PMOS capacitor fuse 222 connected in series between VDD, NMOS capacitor 223 and NMOS capacitor connected in series between node N1 of the current path and ground voltage VSS It consists of a fuse 224.

In this case, the fuses 213, 215, 222, 223, 233, 235, 242, and 243 are physically cut by the user. That is, it is physically programmed by the user.

Hereinafter, the function of each component will be described.

The inverter 211 of the delay increasing circuit 21 outputs the clock signal CLK by inverting the pull-up resistor 212 or the pull-down when the pull-up resistor fuse 213 or the pull-down resistor fuse 215 is cut. When the power supply voltage VDD and the ground voltage VSS passed through the resistor 214 are applied, the inversion operation is performed. When the pull-up resistor fuse 213 or the pull-down resistor fuse 215 is not cut, the pull-up resistor is used. The inverting operation is performed by receiving the power supply voltage VDD and the ground voltage VSS passing through the fuse 213 or the fuse 215 for the pull-down resistor.

Therefore, the response speed of the inverter 211 when the pull-up resistor fuse 213 or the pull-down resistor fuse 215 is cut is when the pull-up resistor fuse 213 or the pull-down resistor fuse 215 is not cut. It becomes slow compared to the response speed of the inverter 211.

That is, the delay increasing circuit 21 slows the response speed of the inverter 211 by cutting the fuses 213 and 215, thereby increasing the delay time of the clock signal CLK.                     

The delay reduction circuit 22 is connected to the node N1 of the current path, and when the PMOS capacitor fuse 222 or the NMOS capacitor fuse 223 is cut, the delay reduction circuit 22 is connected to the node N1 of the current path. The connection to the PMOS NMOS capacitor 221 or the NMOS capacitor 224 is blocked. When the PMOS capacitor fuse 222 or the NMOS capacitor fuse 223 is not cut, the node N1 and the PMOS capacitor 221 or the NMOS capacitor 224 are connected to each other.

When the clock signal CLK transitions from the high level to the low level, the PMOS capacitor 221 connected to the node N1 is turned on to charge a predetermined amount of charge in accordance with the clock signal CLK, and the NMOS capacitor 224. ) Is turned on when the clock signal CLK transitions from a low level to a high level, thereby charging a predetermined amount of charges according to the clock signal CLK. That is, when the PMOS NMOS capacitor 221 or the NMOS capacitor 224 is connected to the node N1 of the current path, the transition speed of the clock signal CLK is slowed, and thus the signal transfer speed is also slowed. .

Accordingly, the delay reduction circuit 22 cuts the fuses 222 and 223 to disconnect the node N1 of the current path and the delay component, that is, the PMOS NMOS capacitor 221 or the NMOS capacitor 224. It cuts off, thereby reducing the delay time of the clock signal CLK.

Hereinafter, a method of adjusting the delay time of the delay circuit 20 for on die termination will be described.

At this time, the on-die termination delay circuit 20 is composed of two delay increasing circuits 21 and 23 and two delay reducing circuits 22 and 24 each having a predetermined delay component. 21 denotes the first delay time T1 when the fuses are cut, and the first delay reduction circuit 22 uses the second delay time T2 when the fuses are not cut. 23 assumes that the third delay time T3 is delayed when the fuses are cut, and the second delay increasing circuit 24 delays the fourth delay time T4 when the fuses are not cut.

First, a case where a signal is applied to the delay circuit 20 for on-die termination in which no fuses are cut is as follows.

When the clock signal CLK is input, the inverter 211 of the first delay increasing circuit 21 receives the power supply voltage VDD and the ground voltage VSS through the fuse 213 for the pull-up resistor and the fuse 215 for the pull-down resistor. ), And transfers the input clock signal CLK without a delay equal to the first delay time T1. The first delay reduction circuit 22 delays the clock signal CLK applied to the node 1 N1 by the second delay time T2 through the PMOS NMOS capacitor 221 and the NMOS capacitor 224. After delivery.

The inverter 231 of the second delay increasing circuit 23 receives the power supply voltage VDD and the ground voltage VSS through the fuses 233 and 235 for the pull-up and pull-down resistors, and input the clock signal CLK. Is transmitted without a delay equal to the third delay time T3, and the second delay reduction circuit 24 supplies the PMOS and NMOS capacitors 241 and 244 to the clock signal CLK applied to the node 2 N2. Delay by the fourth delay time (T4) through the transfer.

Accordingly, the on-die termination delay circuit 20, in which no fuse is cut, receives the clock signal CLK delayed by the second delay time and the fourth delay time T2 + T4, that is, the on-die termination clock signal ODT_CLK. Occurs.

Subsequently, a case where a signal is applied to the delay circuit 20 for on-die termination by cutting the fuses 213, 215, 233, and 235 of the first and second delay increasing circuits 21 and 23 is as follows. .

When the clock signal CLK is input, the first delay increasing circuit 21 receives the power supply voltage VDD and the ground voltage VSS through the pull-up resistor 212 and the pull-down resistor 214, and inputs the clock signal. Delays CLK by the first delay time T1 and delivers it. The first delay reduction circuit 22 further extends the clock signal CLK applied to the node 1 N1 by the second delay time T2 through the PMOS NMOS capacitor 221 and the NMOS capacitor 224. Delay and deliver.

The clock signal CLK is applied to the third delay time T3 by receiving the power supply voltage VDD and the ground voltage VSS passing through the pull-up resistor 232 and the pull-down resistor 234 of the second delay increasing circuit 23. Delay as much as) Finally, the second delay reduction circuit 24 further delays the clock signal CLK applied to the node 2 N2 by the fourth delay time T4 through the PMOS and NMOS capacitors 241 and 244. To pass.

That is, the delay circuit 20 for the on die termination may have the first, second, third, and fourth delay times T1 + T2 + T3 + T4 when the fuses of the delay increase circuits 21 and 23 are cut. A delayed clock signal CLK, that is, a clock signal ODT_CLK for on die termination is generated.

Therefore, the delay time when the fuses of the delay increasing circuits 21 and 23 are cut is increased by the first and third delay time T1 + T3 compared to the delay time when the fuses of the delay increasing circuits are not cut. .

On the other hand, when a signal is applied to the cut-off delay circuit 20 for the on-die termination of the fuses 222, 223, 242, and 243 of the first and second delay reduction circuits 22 and 24, as follows. same.

When the clock signal CLK is input, the inverter 211 of the first delay increasing circuit 21 receives the power supply voltage VDD and the ground voltage VSS through the fuse 213 for the pull-up resistor or the fuse 215 for the pull-down resistor. ), The input clock signal CLK is transmitted without delay as much as the first delay time T1, and the first delay reduction circuit 22 also transfers the clock signal CLK applied to the node 1 N1. Pass it as it is.

The inverter 231 of the second delay increasing circuit 23 receives the power supply voltage VDD and the ground voltage VSS through the fuses 233 and 235 for the pull-up and pull-down resistors, and input the clock signal CLK. Is transmitted without a delay equal to the third delay time T3, and the second delay reduction circuit 24 also transmits the clock signal CLK applied to the node 2 N2 as it is.

That is, the delay circuit 20 for the on die termination may include the first, the second, the third, and the fourth when the fuses 222, 223, 242, and 243 of the delay reduction circuits 22 and 24 are cut. A clock signal CLK that does not have a delay time equal to the delay times T1, T2, T3, and T4, that is, a clock signal ODT_CLK for on die termination is generated.

Therefore, the delay time when the fuses of the delay increase circuit are cut is reduced by the second and fourth delay time T2 + T4 compared to the delay time when the fuses of the delay increase circuit are not cut.                     

In the above description, the delay circuit 20 for on die termination has two delay increasing circuits and two delay reducing circuits. However, in practical applications, the number of delay increasing circuits and delay reducing circuits may be determined by the user or design needs. Naturally, it can be changed in various ways.

In addition, in the above description, the pull-up resistor fuse 213 and the pull-down resistor fuse 215 of the delay increasing circuit, the PMOS capacitor fuse 222 and the NMOS capacitor fuse 223 of the delay reducing circuit are simultaneously cut. Although the delay time is adjusted, it is natural that the actual application may cut the fuses 213, 215, 222, and 223 independently to adjust the delay time.

3 shows a delay circuit 30 for on die termination according to a second embodiment of the present invention.

Subsequently, with reference to the drawings, the delay circuit 30 for on die termination may include a plurality of delay reduction circuits 31, a delay increase circuit 32, a delay decrease circuit 31, and a plurality of delay increase circuits 32. Delay control circuits 33A, 33B.

The delay increasing circuit 31 receives an inverter 311 that receives and inverts a control signal, a first NAND gate 312 and a first NAND gate NAND combining an output signal of the inverter 311 and a clock signal CLK. A delay circuit 313 for delaying the output signal of 312 by a predetermined time, a second NAND gate 314 for NAND combining a control signal and a clock signal CLK, and an output signal and a second signal of the first NAND gate 312; And a third NAND gate 315 for NAND combining the output signal of the NAND gate 314.                     

The delay reduction circuit 32 includes an inverter 321 which receives a control signal and inverts it, a fourth NAND gate 322 NAND combining an output signal of the inverter 321 and a clock signal CLK, and a control signal and a clock signal ( A fifth NAND gate 323 for NAND combining CLK, a delay circuit 324 for delaying the output signal of the fourth NAND gate 323 by a predetermined time, and an output signal and a delay circuit of the fourth NAND gate 323 ( And a sixth NAND gate 325 for NAND combining the output signal of 324.

The delay control circuit 33A is a PMOS transistor 33A_2 connected in series between a fuse 33A_1 connected to a power supply voltage VDD, a fuse 33A_1 and a ground voltage VSS, and turned on or off according to a reset signal RESET. ) And a latch 33A_4 for latching signals generated through the PMOS transistor 33A_2 and the NMOS transistor 33A_3.

Hereinafter, the function of each component will be described.

The delay reduction circuit 31 transfers the clock signal CLK, but when a high level control signal is received from the delay control circuit 33A, the delay reduction circuit 31 transfers the input clock signal CLK without a delay. When the control signal is received, the input clock signal CLK is delayed by a delay time corresponding to the delay component of the delay circuit 313 and then transmitted.

The delay increasing circuit 32 transfers the clock signal CLK. When the high level control signal is received from the delay control circuit 33B, the delay increasing circuit 32 delays the delay time corresponding to the delay component of the delay circuit 324 and then transfers it. When the low level control signal is received, the input clock signal CLK is transferred without a delay.                     

The delay control circuit 33A receives the reset signal RESET of the semiconductor memory device, generates a low level control signal when the fuse 33A_1 is not cut, and high level when the fuse 33A_1 is cut. To generate a control signal.

Here, the reset signal RESET is a signal applied to reset the semiconductor memory device. The reset signal RESET is a pulse signal that is generally maintained at a high level and has a low level only when a reset operation is requested. In view of the fact that most of the operation of the present invention is performed in the normal operation mode, it is assumed that the reset signal RESET is always in a high level state.

Hereinafter, a method of adjusting the delay time of the delay circuit 30 for on die termination will be described.

At this time, the on-die termination delay circuit 30 is composed of a delay reducing circuit 31 and a delay increasing circuit 32, and the delay circuit 313 of the delay reducing circuit 31 has a first delay time T1. It is assumed that the delay circuits 324 of the delay reduction circuit 32 respectively delay by the second delay time T2.

First, an operation method of the delay circuit 30 for on die termination when the plurality of delay control circuits 33A and 33B is not fuse-cutted will be described below.

Accordingly, the plurality of delay control circuits 33A and 33B generate a low level control signal.

The inverter 311 of the delay reduction circuit 31 inverts the low level control signal, and the first NAND gate 312 NAND combines the high level signal and the clock signal CLK output from the inverter 311. The clock signal CLK is inverted, and the delay circuit 313 delays the output signal of the first NAND gate 312 by the first delay time T1 and transmits the delayed signal. The second NAND gate 314 generates a high level signal by NAND combining a low level control signal and a clock signal CLK.

Accordingly, the third NAND gate 315 is delayed by the high level signal applied from the second NAND gate 314 and the first delay time T1 applied from the delay circuit 313, and the inverted clock signal CLK is applied. NAND is combined to generate a clock signal delayed by the first delay time T1.

The inverter 321 of the delay increasing circuit 32 inverts the low level control signal, and the fourth NAND gate 322 is transmitted from the high level signal output from the inverter 321 and the delay reduction circuit 31. The NAND combination of the delayed clock signals is inverted.

The fifth NAND gate 323 NAND combines the low level control signal with the delayed clock signal transmitted from the delay reduction circuit 31 to generate a high level signal, and the delay circuit 324 generates the fifth NAND gate 323. Delays the high level signal by a second delay time T2 and then transfers the signal.

Accordingly, the sixth NAND gate 325 NAND combines the high level signal output from the delay circuit 324 and the delayed and inverted clock signal CLK transmitted from the fifth NAND gate 323, thereby providing a first delay time ( Generates a clock signal delayed by T1).

Accordingly, the delay circuit 30 for on die termination when the fuses 33A_1 and 33B_1 of the plurality of delay control circuits 33A and 33B are not cut may be a clock signal CLK delayed by a first delay time T1. Generates a clock signal (ODT_CLK) for on-die termination.

Next, an operation method of the on-die termination delay circuit 30 when the fuse 33A_1 of the delay control circuit 33A corresponding to the delay reduction circuit 31 is cut will be described.

Accordingly, the delay control circuit 33A corresponding to the delay reducing circuit 31 generates a high level control signal, and the delay control circuit 33B corresponding to the delay increasing circuit 32 generates a low level control signal. do.

The inverter 311 of the delay reduction circuit 31 inverts the high level control signal, and the first NAND gate 312 NAND combines the low level signal and the clock signal CLK output from the inverter 311. , The high level signal is generated, and the delay circuit 313 delays the high level signal by the first delay time T1 and then transfers the high level signal. The second NAND gate 314 inverts the clock signal CLK by NAND combining the high level control signal and the clock signal CLK.

Accordingly, the third NAND gate 315 NAND combines the inverted clock signal CLK applied from the second NAND gate 314 and a high level signal applied from the delay circuit 313 to combine the clock signal CLK. Occurs. That is, the clock signal CLK does not have a separate delay time.

In addition, the delay increasing circuit 32 operates in the same manner as when the plurality of delay control circuits 33A and 33B are not fuse cut, respectively, so as not to delay the clock signal CLK.

Therefore, when the fuse 33A_1 of the delay control circuit 33A corresponding to the delay reduction circuit 31 is cut, the clock signal CLK is not separately delayed. That is, the delay time of the on-die termination delay circuit 30 is reduced by the first delay time T1.

On the other hand, the operation method of the on-die termination delay circuit 30 when the fuse 33B_1 of the delay control circuit 33B corresponding to the delay increasing circuit 32 is cut will be described.

The plurality of delay control circuits 33A and 33B of the delay reduction circuit 31 are operated in the same manner as in the case where they are not fuse cut to delay the clock signal CLK by the first delay time T1.

The inverter 321 of the delay increasing circuit 32 inverts the high level control signal, and the fourth NAND gate 322 is delayed of the low level signal and the delay reducing circuit 31 output from the inverter 321. The NAND combination of the clock signals generates a high level signal.

The fifth NAND gate 323 NAND combines the high level control signal and the delayed clock signal of the delay reduction circuit 31 to invert the clock signal CLK, and the delay circuit 324 performs the fourth NAND gate 322. Delays the output signal by a second delay time T2.

Accordingly, the sixth NAND gate 325 is a high level signal applied from the fifth NAND gate 323 and a clock signal CLK delayed and inverted by the first and second delay times T1 + T2 from the delay circuit 324. ) Is generated by a NAND combination, and generates a clock signal delayed by the first and second delay times T1 + T2.

Accordingly, by cutting the fuse 33B_1 of the delay control circuit 33B corresponding to the delay increasing circuit 32, the delay circuit 30 for on die termination is delayed by the first and second delay times T1 + T2. Generates a clock signal. That is, the delay time of the on-die termination delay circuit 30 is increased by the second delay time T2.

In FIG. 3, the delay circuit 30 for the on die termination is provided with a delay increasing circuit and a delay reducing circuit one by one. However, in actual applications, the number of delay increasing circuits and delay reducing circuits may vary depending on user or design needs. Of course, you can change it.

In addition, in the present invention, the control signal is generated through the delay control circuit, but if necessary, it is possible to generate the control signals having the same function as in FIG. 3 by using a mode register set (MRS). Of course.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art various modifications and changes to the present invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

The delay circuit for on-die termination of the present invention allows for adaptively varying delay components through fuses or mode register sets. Accordingly, the delay time can be adaptively changed according to the process change of the semiconductor memory device, and the on-dimination AC parameter specification is recommended, and this can be satisfactorily satisfied.

Claims (11)

At least one delay increasing circuit having delay increasing fuses and increasing a delay time of a clock signal according to whether the delay increasing fuses are cut; And And at least one delay reducing circuit for reducing delay time of the clock signal according to whether the delay increasing fuses are cut. The method of claim 1, wherein the delay increasing circuit An inverter for inverting the clock signal; A pullup resistor located between the inverter and a power supply voltage; A pull-down resistor located between the inverter and the ground voltage; A first delay increasing fuse parallel to the pull-up resistor to apply a power supply voltage to the inverter through the pull-up resistor when the fuse is cut and to apply the power supply voltage to the inverter when the fuse is not cut; And A second delay increasing fuse which is parallel to the pull-down resistor and applies a ground voltage to the inverter through the pull-down resistor when the fuse is cut, and applies a ground voltage to the inverter when the fuse is not cut. A delay circuit for on die termination, characterized in that provided. The method of claim 1, wherein the delay reduction circuit A first capacitor connected with a power supply voltage; A second capacitor connected with the ground voltage; A first delay reduction fuse connected in series between said first capacitor and a transmission node; And And a second delay reduction fuse connected in series between said second capacitor and a transmission node. The method of claim 1, wherein the delay circuit for on die termination And connecting the at least one delay increasing circuit and the at least one delay reducing circuit in series. At least one delay reduction circuit for reducing a delay time of the clock signal when the control signal is in a first state; And And at least one delay increasing circuit for increasing a delay time of a clock signal when the control signal is in the first state. The method of claim 5, wherein the delay reduction circuit is A first inverter receiving the control signal and inverting the control signal; A first logic gate NAND combining the output signal of the first inverter and the clock signal; A first delay circuit for delaying an output signal of the first logic gate by a predetermined time; A second logic gate NAND combining the control signal and the clock signal; And And a third logic gate for NAND combining the output signal of the first delay circuit and the output signal of the second logic gate. 6. The circuit of claim 5, wherein the delay increasing circuit is A second inverter receiving the control signal and inverting the control signal; A fourth logic gate NAND combining the output signal of the inverter and the clock signal; A fifth logic gate NAND combining the control signal and the clock signal; And A second delay circuit for delaying an output signal of the fifth logic gate by a predetermined time; And a sixth logic gate for NAND combining the output signal of the fourth logic gate and the output signal of the second delay circuit. The method of claim 5, wherein the control signal A delay circuit for on-die termination, which is generated by a mode register set. The method of claim 5, wherein the delay circuit for on-die termination A control signal having a first state in response to a reset signal of the semiconductor memory device when the fuse is cut, and in response to the reset signal when the fuse is not cut, a second state is generated in response to the reset signal. And at least two delay control circuits for generating a control signal. The method of claim 9, wherein the delay control circuit is A fuse connected to the supply voltage; Transistors connected in series between the fuse and the ground voltage and turned on or off according to the reset signal to generate an output signal; And And a latch for latching an output signal output from the transistors. The method of claim 5, wherein the delay circuit for on-die termination And connecting the at least one delay increasing circuit and the at least one delay reducing circuit in series.

Images