TWI684768B - Phase detection method and phase detection circuit - Google Patents
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Abstract
本發明涉及一種相位檢測方法及其相位檢測電路,尤指一種透過簡單電路,於取得相同頻率、且具相位差的輸入訊號與輸出訊號後產生一新的倍頻訊號,供與一相位相同、且頻率相同之參考訊號比較,進一步並透過過濾倍頻訊號與參考訊號的相位差是否在可接受範圍內,判斷其相位是否正確,同時完成時脈週期的量測,藉以解決如DLL/DL電路僅能進行時脈週期測試的問題,進一步能做90度之相位移測試,可以有效的提升檢測的準確率,同時能運行時的檢測,而能快速的測試。 The invention relates to a phase detection method and a phase detection circuit, in particular to a simple circuit that generates a new frequency-multiplied signal after obtaining an input signal and an output signal with the same frequency and having a phase difference for the same phase, And the reference signal with the same frequency is compared, and further, by filtering whether the phase difference between the multiplier signal and the reference signal is within an acceptable range, it is judged whether the phase is correct, and at the same time, the measurement of the clock cycle is completed, so as to solve such as DLL/DL circuit Only the problem of clock cycle test can be carried out, and the phase shift test of 90 degrees can be further performed, which can effectively improve the accuracy of detection, and can also be detected at runtime and can be quickly tested.
Description
本發明係隸屬相位檢測之技術領域,具體而言係指一種相位檢測方法及其相位檢測電路,藉以能在運行時可以快速的自動測試,並檢測其時脈及相位的準確率。 The invention belongs to the technical field of phase detection, and specifically refers to a phase detection method and a phase detection circuit, so that it can quickly and automatically test during operation, and detect the accuracy of its clock and phase.
按,由於半導體裝置線路的尺寸微細化和複雜度均越來越驚人,使得半導體裝置之深次微米和奈米設計中出現了新的缺陷類型,因此僅開發和使用功能性向量已經無法滿足對產品測試的實際需求。如要維持半導體裝置能達到要求的品質等級,需對於半導體裝置進行更多型態的測試,甚至需要對於該半導體裝置在製作完成後,需要進行全面性的測試,以確保該半導體裝置的良率;以半導體裝置而言,其延遲鎖相電路【Delay Locked Loop,以下簡稱DLL】/延遲線電路【Delay line,以下簡稱DL】是一種用來延遲輸入訊號,以產生預期要的相位移輸出訊號的電路,而在現今半導體裝置之動態隨機存取記憶體【Dynamic RAM,以下簡稱DRAM】與快閃記憶體【NAND flash】的主控端都需要DLL/DL電路來相位移雙向資料控制引腳【Bi-directional Data Strobe,以下簡稱DQS】做為雙倍資料率同步動態隨機存取記憶體【Double Data Rate,以下簡稱DDR】模式下的數據取樣訊 號;然而目前並無教示或建議於運行時可以全面性進行的相位檢測方案,而相近似的方案僅僅是在檢測確定該半導體裝置的DLL/DL電路能在輸入端輸入訊號的時脈週期下,其輸出端能產生相同週期的訊號,並不能確定該訊號的相位移是否為90度;換言之,現有技術只能量測該輸出訊號的時脈週期是否等於輸入週期,故只能確定DLL/DL電路有輸出時脈,並無法量測出其是否相位移90度,而半導體裝置之DLL/DL電路的關鍵功能是要做相位移,因此若不能量測其相位移,也就不能確定該DLL/DL電路功能的正確性,而如何解決前述問題,係業界的重要課題,也是本發明所探討者。 As the size and complexity of semiconductor device circuits are becoming more and more amazing, new types of defects have appeared in the deep submicron and nanometer designs of semiconductor devices. Therefore, the development and use of functional vectors cannot meet the The actual needs of product testing. In order to maintain the required quality level of the semiconductor device, more types of tests need to be performed on the semiconductor device, and even after the semiconductor device is completed, a comprehensive test is required to ensure the yield of the semiconductor device For semiconductor devices, its delay locked circuit [Delay Locked Loop, hereinafter referred to as DLL]/delay line circuit [Delay line, hereinafter referred to as DL] is a kind of delay input signal used to generate the expected phase shift output signal Circuit, and the DRAM/Dynamic RAM (Dynamic RAM, hereinafter referred to as DRAM) and the flash memory [NAND flash] of the current semiconductor devices require DLL/DL circuit to phase shift the bidirectional data control pins [Bi-directional Data Strobe, hereinafter referred to as DQS] as double data rate synchronous dynamic random access memory [Double Data Rate, hereinafter referred to as DDR] mode data sampling However, there is currently no teaching or suggestion for a phase detection scheme that can be carried out comprehensively at runtime, and the similar scheme is only to detect the clock cycle of the DLL/DL circuit of the semiconductor device that can input the signal at the input terminal , The output of which can produce a signal with the same period, and it is not certain whether the phase shift of the signal is 90 degrees; in other words, the prior art can only measure whether the clock period of the output signal is equal to the input period, so only the DLL/ The DL circuit has an output clock and cannot measure whether it is 90 degrees out of phase, and the key function of the DLL/DL circuit of a semiconductor device is to do phase shift. Therefore, if the phase shift cannot be measured, it cannot be determined. The correctness of the function of the DLL/DL circuit, and how to solve the aforementioned problems, is an important issue in the industry and is also discussed in the present invention.
於是,本發明即基於上述需求與問題深入探討,並藉由本發明人多年從事相關開發的經驗,而積極尋求解決之道,經不斷努力之研究與發展,終於成功的發展出一種相位檢測方法及其相位檢測電路,其能有效解決現有無法有效量測相位移所造成的不便與困擾。 Therefore, the present invention is based on the in-depth discussion of the above needs and problems, and through the inventors’ years of experience in related development, and actively seeking solutions, after continuous research and development, finally developed a phase detection method and The phase detection circuit can effectively solve the inconvenience and trouble caused by the existing inability to effectively measure the phase displacement.
因此,本發明之主要目的係在提供一種相位檢測方法及其相位檢測電路,藉以解決DLL/DL電路僅能進行時脈週期測試的問題,進一步能做90度之相位移測試,且能提升檢測的準確率。 Therefore, the main object of the present invention is to provide a phase detection method and a phase detection circuit, thereby solving the problem that the DLL/DL circuit can only perform clock cycle test, and further can perform a phase shift test of 90 degrees, and can improve detection Accuracy.
又,本發明之主要目的係在提供一種相位檢測方法及其相位檢測電路,其能運行時的檢測,而能有效、且快速的測 試。 Moreover, the main object of the present invention is to provide a phase detection method and a phase detection circuit that can detect during operation, and can effectively and quickly measure test.
為此,本發明主要係透過下列的技術手段,來具體實現上述的各項目的與效能,供一測試機台量測一半導體裝置之一待測電路的時脈週期及/或相位移,其包含有;一倍頻電路,其中具有兩輸入端,其中一輸入端可與一待測電路之輸入端並聯,供接收一輸入訊號輸入,而倍頻電路的另一輸入端係與前該測電路之輸出端連接,供接收一經待測電路而產生一具有相位差之輸出訊號輸入,且該倍頻電路可將該輸入訊號與該輸出訊號結合後產生一組二倍倍頻訊號;一比較電路,其具有兩輸入端,其中一輸入端連接該倍頻電路之輸出端,供接收該倍頻訊號,而另一輸入端則可供輸入一參考訊號,令該比較電路可比較二個輸入訊號的相位差異;一突波過濾器,其具有一連接比較電路輸出端之輸入端,該突波過濾器可以透過預設的容許值將經過比較電路輸入的比較訊號過濾掉其超出容許值的訊號突波;一判讀輸出器,其具有一連接該突波過濾器輸出端之輸入端,令其依規則判讀結果,並回報測試機台。 Therefore, the present invention mainly implements the above-mentioned objects and performance through the following technical means, for a testing machine to measure the clock cycle and/or phase shift of a circuit to be tested of a semiconductor device, which Including; a frequency multiplier circuit, which has two input terminals, one of which can be connected in parallel with the input terminal of a circuit under test for receiving an input signal input, and the other input terminal of the frequency multiplier circuit is the same as the previous test The output terminal of the circuit is connected for receiving an output signal input with a phase difference generated by the circuit under test, and the frequency multiplier circuit can combine the input signal with the output signal to generate a set of double frequency multiplier signals; a comparison The circuit has two input terminals, one of which is connected to the output terminal of the frequency doubling circuit for receiving the frequency doubling signal, and the other input terminal is for inputting a reference signal, so that the comparison circuit can compare the two inputs The phase difference of the signal; a surge filter with an input connected to the output of the comparison circuit. The surge filter can filter out the comparison signal input by the comparison circuit beyond the allowable value through the preset allowable value. Signal surge; an interpretation output, which has an input connected to the output of the surge filter, so that it can interpret the results according to the rules and report back to the testing machine.
藉此,透過前述技術手段的具體實現,使本發明能透過電路極為簡單的相位檢測電路,供於取得相同頻率、且具相位差的輸入訊號與輸出訊號後產生一新的倍頻訊號,供與一相位相同、且頻率相同之參考訊號比較,進一步並透過過濾倍頻訊號與參考訊號的相位差是否在可接受範圍內,判斷其相位是否正確,同時完成時脈週期的量測,藉以解決如DLL/DL電路僅能進 行時脈週期測試的問題,進一步能做90度之相位移測試,可以有效的提升檢測的準確率,且在運行時能檢測,進而快速的測試,並能增加其附加價值,也能提高其經濟效益。 Thus, through the specific implementation of the aforementioned technical means, the present invention can be used to obtain a new frequency-multiplied signal after obtaining an input signal and an output signal with the same frequency and a phase difference through a very simple phase detection circuit. Compare with a reference signal with the same phase and the same frequency, and further determine whether the phase is correct by filtering whether the phase difference between the multiplier signal and the reference signal is within the acceptable range, and at the same time complete the measurement of the clock cycle to solve Such as DLL/DL circuit can only enter The problem of running the clock cycle test can further do a phase shift test of 90 degrees, which can effectively improve the accuracy of the detection, and can be detected during operation, and thus rapid testing, and can increase its added value and can also improve its Economic benefits.
為使 貴審查委員能進一步了解本發明的構成、特徵及其他目的,以下乃舉本發明之若干較佳實施例,並配合圖式詳細說明如后,供讓熟悉該項技術領域者能夠具體實施。 In order to enable your review committee to further understand the structure, features and other purposes of the present invention, the following are some preferred embodiments of the present invention, and the detailed description in conjunction with the drawings as follows, for those familiar with the technical field to be able to implement .
(10)‧‧‧相位檢測電路 (10)‧‧‧phase detection circuit
(12)‧‧‧倍頻電路 (12)‧‧‧ Frequency multiplier circuit
(14)‧‧‧比較電路 (14)‧‧‧Comparison circuit
(16)‧‧‧突波過濾器 (16)‧‧‧Surge filter
(18)‧‧‧判讀輸出器 (18)‧‧‧Interpretation output
(20)‧‧‧待測電路 (20)‧‧‧ circuit under test
第一圖:係本發明之相位檢測電路的架構示意圖,供說明其主要配置狀態。 The first figure is a schematic diagram of the structure of the phase detection circuit of the present invention, for illustrating its main configuration state.
第二圖:係本發明之相位檢測電路實際應用於一半導體裝置之DLL/DL電路時的架構示意圖。 Figure 2 is a schematic diagram of the phase detection circuit of the present invention when it is actually applied to a DLL/DL circuit of a semiconductor device.
第三圖:係本發明之相位檢測方法的流程示意圖。 The third figure is a schematic flow chart of the phase detection method of the present invention.
第四圖:係本發明於實際運作時的時序示意圖,供說明其量測合格的狀態。 The fourth figure: it is a time sequence diagram of the present invention in actual operation, for explaining the measurement qualified state.
第五圖:係本發明於實際運作時的另一時序示意圖,供說明其量測不合格的狀態。 Fifth figure: It is another time sequence diagram of the present invention in actual operation, to illustrate the state of measurement failure.
本發明之一種相位檢測方法及其相位檢測電路的構成,係如第一、二圖所示,其中第一圖係本發明相位檢測電路的架構、第二圖應用本發明相位檢測電路於實際應用的架構。如圖所示,該相位檢測電路(10)係包含有一倍頻電路(12)、一接於輸出端之比較電路(14)、一接於比較電路(14)輸出端之突波過濾器(16)【Glitch Filter】及一設於突波過濾器(16)輸出端之判讀輸出器(18)【Result report】; 其中該倍頻電路(12)具有兩輸入端,供取得二輸入訊號。其中一輸入端可與一待測電路(20)【如DLL/DL電路】之輸入端並聯【如第二圖所示】,供接收一輸入訊號【DLY_input】輸入。而倍頻電路(12)的另一輸入端係與前述待測電路(20)之輸出端【如第二圖所示】連接,供接收一經待測電路(20)而產生一具有相位差【Phase】之輸出訊號【DLY_output】輸入,以利用該倍頻電路(12)的簡單電路將前述二個輸入訊號結合後產生一新的倍頻訊號,若輸入該倍頻電路(12)之輸入訊號【DLY_input】與輸出訊號【DLY_output】的二輸入訊號的相位差為90度時,則該倍頻電路(12)會產生一個新的相位與輸出訊號【DLY_output】接近之二倍倍頻訊號【clock_2x】。 A phase detection method and a phase detection circuit of the present invention are shown in the first and second figures, wherein the first figure is the architecture of the phase detection circuit of the present invention, and the second figure applies the phase detection circuit of the present invention to practical applications Architecture. As shown in the figure, the phase detection circuit (10) includes a frequency multiplier circuit (12), a comparison circuit (14) connected to the output terminal, and a surge filter connected to the output terminal of the comparison circuit (14) 16) [Glitch Filter] and a judgment output device (18) [Result report] provided at the output end of the surge filter (16); The frequency multiplier circuit (12) has two input terminals for obtaining two input signals. One of the input terminals can be connected in parallel with the input terminal of a circuit under test (20) [such as DLL/DL circuit] [as shown in the second figure] for receiving an input signal [DLY_input] input. The other input terminal of the frequency multiplier circuit (12) is connected to the output terminal of the circuit under test (20) [as shown in the second figure] for receiving a phase difference produced by the circuit under test (20) [ Phase] output signal [DLY_output] input, using the simple circuit of the frequency multiplier circuit (12) to combine the two input signals to generate a new frequency multiplier signal, if the input signal of the frequency multiplier circuit (12) is input When the phase difference between the two input signals of [DLY_input] and the output signal [DLY_output] is 90 degrees, the frequency multiplier circuit (12) will generate a new double frequency multiplier signal [clock_2x] that is close to the output signal [DLY_output] ].
而該比較電路(14)具有兩輸入端。其中一輸入端連接前述倍頻電路(12)之輸出端,供接收該倍頻電路(12)輸出之二倍倍頻訊號【clock_2x】。另一輸入端則可供輸入一參考訊號【reference_clock】,以利用該比較電路(14)進一步比較二個輸入訊號的相位差異。另該突波過濾器(16)之輸入端係連接前述比較電路(14)之輸出端,用以透過預設的容許值將該經過比較電路(14)輸入的比較訊號過濾掉其未超出容許值的訊號突波【Glitch】。再者,該判讀輸出器(18)的輸入端係連接前述之突波過濾器(16)的輸出端,用以依預設的規則判讀結果,例如當突波過濾器(16)過濾時其訊號突波在容許值範圍內時,則輸出一無突波的過濾訊號【如第三圖所示】,供該判讀輸出器(18)讀取後判讀為合格,該判讀輸出器(18)並將該合格結果收集後由輸出端輸出回報給測試機台。反之當突波過濾器(16)過濾時 其訊號突波超出容許值範圍時,則輸出一具突波的過濾訊號【如第四圖所示】,供該判讀輸出器(18)讀取後判讀為不合格,該判讀輸出器(18)並將該不合格結果收集後由輸出端輸出回報給測試機台。 The comparison circuit (14) has two input terminals. One of the input terminals is connected to the output terminal of the frequency multiplier circuit (12) for receiving the double frequency multiplier signal [clock_2x] output by the frequency multiplier circuit (12). The other input terminal can be used to input a reference signal [reference_clock], so as to further compare the phase difference of the two input signals by using the comparison circuit (14). In addition, the input terminal of the surge filter (16) is connected to the output terminal of the aforementioned comparison circuit (14), and is used to filter the comparison signal input through the comparison circuit (14) through the preset allowable value, which does not exceed the allowable Signal glitch of value [Glitch]. Furthermore, the input terminal of the interpretation output device (18) is connected to the output terminal of the aforementioned surge filter (16), which is used to interpret the result according to a preset rule, for example, when the surge filter (16) filters When the signal surge is within the allowable value range, a filtered signal without glitches [as shown in the third figure] is output for the interpretation output device (18) to read and pass, and the interpretation output device (18) After collecting the qualified results, the output terminal outputs and returns to the testing machine. Conversely, when the surge filter (16) filters When the signal surge exceeds the allowable value range, a filtered signal with a surge [as shown in the fourth figure] is output for the interpretation output (18) to read as unqualified, and the interpretation output (18 ) After collecting the unqualified result, the output terminal will output and report back to the testing machine.
藉此,組構成一種電路簡單、且量測準確率高之相位檢測電路。 Thereby, a phase detection circuit with simple circuit and high measurement accuracy is formed.
第三圖所示為本發明相位檢測方法的流程圖。第四、五圖顯示根據這些實施例之不同狀態的時序圖。 The third figure shows a flowchart of the phase detection method of the present invention. The fourth and fifth figures show timing diagrams of different states according to these embodiments.
(a)、步驟S101、取得二個輸入訊號。一個是從外部電路直接而來的輸入訊號。另一個是該輸入訊號通過一待測電路後產生具相位差之訊號。準備一個欲輸入待測電路(20)之DLL/DL電路頻率為F的時脈輸入訊號【DLY_input】。準備一個將該輸入訊號輸入至該相位檢測電路(10)後產生相位移後的時脈輸出訊號【DLY_output】。若待測電路(20)之DLL/DL電路正常運作時為90度相位差,則該輸出訊號為該輸入訊號的90度相位,並將該輸入訊號與該輸出訊號同時輸入該相位檢測電路(10)之倍頻電路(12)。 (a) Step S101: Obtain two input signals. One is the input signal directly from the external circuit. The other is that the input signal generates a signal with a phase difference after passing through a circuit to be tested. Prepare a clock input signal [DLY_input] with the frequency F of the DLL/DL circuit to be input to the circuit under test (20). Prepare a clock output signal [DLY_output] after the input signal is input to the phase detection circuit (10) to generate a phase shift. If the DLL/DL circuit of the circuit under test (20) has a 90-degree phase difference during normal operation, the output signal is the 90-degree phase of the input signal, and the input signal and the output signal are simultaneously input to the phase detection circuit ( 10) Frequency multiplication circuit (12).
(b)、步驟S102、結合該輸入訊號及該具相位差之訊號產生一倍頻訊號:透過該倍頻電路(12)將前述的輸入訊號與該具相位差之訊號結合,若如前述該輸出訊號與該輸入訊號為90度相位差時,則產生一個二倍頻【2xF】、且相位與輸入訊號接近的二倍倍頻訊號【clock_2x】。 (b) Step S102: Combine the input signal and the signal with phase difference to generate a frequency doubling signal: combine the aforementioned input signal with the signal with phase difference through the frequency doubling circuit (12), as described above When the output signal is 90 degrees out of phase with the input signal, a double frequency signal [2xF] with a phase close to the input signal is generated [clock_2x].
(c)、步驟S103、比較該倍頻訊號與一頻率及相位與該倍頻訊號相同之參考訊號。準備一與倍頻訊號頻率及相位相 同之參考訊號【Reference_clock】,並透過該相位檢測電路(10)之比較電路(14)把倍頻電路(12)輸出之倍頻訊號與該參考訊號相比。 (c) Step S103: Compare the frequency-doubled signal with a reference signal whose frequency and phase are the same as the frequency-doubled signal. Prepare a phase with the frequency and phase of the multiplier signal The same reference signal [Reference_clock], and the frequency multiplier signal output from the frequency multiplier circuit (12) is compared with the reference signal through the comparison circuit (14) of the phase detection circuit (10).
(d)、步驟S104、過濾參考訊號與倍頻訊號之相位差是否在接受範圍內。根據預設的突波容許值,透過該相位檢測電路(10)之突波過濾器(16)過濾該參考訊號與該倍頻訊號的相位差是否在可接受的範圍內。若輸入訊號與輸出訊號為90度相位差,則如第四圖所示,倍頻訊號與參考訊號應該是相等,或產生可接受的訊號突波【如第四圖之Sig_diff】。於過濾後形成無突波訊號【如第四圖之Sig_filter】。反之,當倍頻訊號與參考訊號不相等,則產生超出可接受的訊號突波【如第五圖之Sig_diff】,並於過濾後形成序列突波訊號【如第五圖之Sig_filter】。 (d) Step S104: Whether the phase difference between the filtered reference signal and the multiplier signal is within the acceptance range. According to the preset surge allowable value, whether the phase difference between the reference signal and the frequency doubling signal is filtered through the surge filter (16) of the phase detection circuit (10) is within an acceptable range. If the input signal and the output signal are 90 degrees out of phase, as shown in the fourth figure, the multiplier signal and the reference signal should be equal, or an acceptable signal surge [such as Sig_diff in the fourth figure] should be generated. After filtering, a surge-free signal is formed [Sig_filter in the fourth image]. Conversely, when the frequency-multiplied signal is not equal to the reference signal, a signal surge beyond acceptable [Sig_diff in the fifth figure] is generated, and after filtering, a sequence surge signal [Sig_filter in the fifth figure] is formed.
(e)、步驟S105、回報過濾後的結果。該相位檢測電路(10)之判讀輸出器(18)於取得突波過濾器(16)的過濾訊號後,如過濾後的訊號為無突波訊號【如第四圖之Sig_filter】,則判斷為合格。反之,如過濾後的訊號為突波訊號【如第五圖之Sig_filter】,則判斷為不合格。該判讀輸出器(18)將前述合格或不合格的訊號回報給該測試機台,然後結束整個相位檢測的量測流程。 (e) Step S105: Report the filtered result. After the judging output device (18) of the phase detection circuit (10) obtains the filtering signal of the surge filter (16), if the filtered signal is a non-surge signal [such as Sig_filter in the fourth figure], it is judged as qualified. Conversely, if the filtered signal is a surge signal [Sig_filter in the fifth figure], it is judged as unqualified. The interpretation output device (18) returns the aforementioned qualified or unqualified signal to the testing machine, and then ends the entire phase detection measurement process.
經由上述的說明,本發明透過電路極為簡單的相位檢測電路(10)從外部電路取得輸入訊號,使該輸入訊號通過待測電路後產生有相同頻率且具相位差的訊號,結合這兩個訊號而產生一新的倍頻訊號。把倍頻訊號與一相位及頻率相同之參考訊 號相比。進一步透過過濾倍頻訊號與參考訊號的相位差是否在可接受範圍內,判斷其相位是否正確,同時完成時脈週期的量測,藉以解決如DLL/DL電路僅能進行時脈週期測試的問題,進一步能做90度之相位移測試,可以有效的提升檢測的準確率,同時能運行時的檢測,而能快速的測試,故可大幅增進其實用性。 Through the above description, the present invention obtains an input signal from an external circuit through a very simple phase detection circuit (10), so that the input signal passes through the circuit under test to generate a signal with the same frequency and a phase difference, combining these two signals A new frequency doubling signal is generated. Reference signal with the same phase and frequency as the frequency doubling signal No. Further, by filtering whether the phase difference between the frequency-doubled signal and the reference signal is within an acceptable range, it is judged whether the phase is correct, and at the same time, the measurement of the clock cycle is completed, thereby solving the problem that the DLL/DL circuit can only perform the clock cycle test. In addition, it can further do a phase shift test of 90 degrees, which can effectively improve the accuracy of detection, at the same time, it can be tested at runtime, and can be tested quickly, so it can greatly improve its practicality.
綜上所述,可以理解到本發明為一創意極佳之發明創作,除了有效解決先前技藝所面臨的問題,更大幅增進功效,且在相同的技術領域中未見相同或近似的產品創作或公開使用,同時具有功效的增進,故本發明已符合發明專利有關「新穎性」與「進步性」的要件,乃依法提出發明專利之申請。 In summary, it can be understood that the present invention is an invention with excellent creativity, in addition to effectively solving the problems faced by the previous art, greatly improving the efficiency, and in the same technical field, there is no same or similar product creation or It is open for use and has an improvement in efficacy. Therefore, the present invention has met the requirements for "novelty" and "progressiveness" of the invention patent, and an application for an invention patent is filed according to law.
(10)‧‧‧相位檢測電路 (10)‧‧‧phase detection circuit
(12)‧‧‧倍頻電路 (12)‧‧‧ Frequency multiplier circuit
(14)‧‧‧比較電路 (14)‧‧‧Comparison circuit
(16)‧‧‧突波過濾器 (16)‧‧‧Surge filter
(18)‧‧‧判讀輸出器 (18)‧‧‧Interpretation output
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CN101867368A (en) * | 2009-04-20 | 2010-10-20 | 索尼公司 | Clock data recovery circuit and multiplied-frequency clock generation circuit |
CN104579325A (en) * | 2013-10-10 | 2015-04-29 | 瑞昱半导体股份有限公司 | Data receiving device and method |
TWI504152B (en) * | 2008-09-16 | 2015-10-11 | Synopsys Inc | High speed pll clock multiplier |
EP3190704B1 (en) * | 2016-01-06 | 2018-08-01 | Nxp B.V. | Digital phase locked loops |
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TWI504152B (en) * | 2008-09-16 | 2015-10-11 | Synopsys Inc | High speed pll clock multiplier |
CN101867368A (en) * | 2009-04-20 | 2010-10-20 | 索尼公司 | Clock data recovery circuit and multiplied-frequency clock generation circuit |
CN104579325A (en) * | 2013-10-10 | 2015-04-29 | 瑞昱半导体股份有限公司 | Data receiving device and method |
EP3190704B1 (en) * | 2016-01-06 | 2018-08-01 | Nxp B.V. | Digital phase locked loops |
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