TWI684768B - Phase detection method and phase detection circuit - Google Patents

Abstract

The invention relates to a phase detection method and a phase detection circuit, in particular to a simple circuit that generates a new frequency-multiplied signal after obtaining an input signal and an output signal with the same frequency and having a phase difference for the same phase, And the reference signal with the same frequency is compared, and further, by filtering whether the phase difference between the multiplier signal and the reference signal is within an acceptable range, it is judged whether the phase is correct, and at the same time, the measurement of the clock cycle is completed, so as to solve such as DLL/DL circuit Only the problem of clock cycle test can be carried out, and the phase shift test of 90 degrees can be further performed, which can effectively improve the accuracy of detection, and can also be detected at runtime and can be quickly tested.

Description

Phase detection method and phase detection circuit

The invention belongs to the technical field of phase detection, and specifically refers to a phase detection method and a phase detection circuit, so that it can quickly and automatically test during operation, and detect the accuracy of its clock and phase.

As the size and complexity of semiconductor device circuits are becoming more and more amazing, new types of defects have appeared in the deep submicron and nanometer designs of semiconductor devices. Therefore, the development and use of functional vectors cannot meet the The actual needs of product testing. In order to maintain the required quality level of the semiconductor device, more types of tests need to be performed on the semiconductor device, and even after the semiconductor device is completed, a comprehensive test is required to ensure the yield of the semiconductor device For semiconductor devices, its delay locked circuit [Delay Locked Loop, hereinafter referred to as DLL]/delay line circuit [Delay line, hereinafter referred to as DL] is a kind of delay input signal used to generate the expected phase shift output signal Circuit, and the DRAM/Dynamic RAM (Dynamic RAM, hereinafter referred to as DRAM) and the flash memory [NAND flash] of the current semiconductor devices require DLL/DL circuit to phase shift the bidirectional data control pins [Bi-directional Data Strobe, hereinafter referred to as DQS] as double data rate synchronous dynamic random access memory [Double Data Rate, hereinafter referred to as DDR] mode data sampling However, there is currently no teaching or suggestion for a phase detection scheme that can be carried out comprehensively at runtime, and the similar scheme is only to detect the clock cycle of the DLL/DL circuit of the semiconductor device that can input the signal at the input terminal , The output of which can produce a signal with the same period, and it is not certain whether the phase shift of the signal is 90 degrees; in other words, the prior art can only measure whether the clock period of the output signal is equal to the input period, so only the DLL/ The DL circuit has an output clock and cannot measure whether it is 90 degrees out of phase, and the key function of the DLL/DL circuit of a semiconductor device is to do phase shift. Therefore, if the phase shift cannot be measured, it cannot be determined. The correctness of the function of the DLL/DL circuit, and how to solve the aforementioned problems, is an important issue in the industry and is also discussed in the present invention.

Therefore, the present invention is based on the in-depth discussion of the above needs and problems, and through the inventors’ years of experience in related development, and actively seeking solutions, after continuous research and development, finally developed a phase detection method and The phase detection circuit can effectively solve the inconvenience and trouble caused by the existing inability to effectively measure the phase displacement.

Therefore, the main object of the present invention is to provide a phase detection method and a phase detection circuit, thereby solving the problem that the DLL/DL circuit can only perform clock cycle test, and further can perform a phase shift test of 90 degrees, and can improve detection Accuracy.

Moreover, the main object of the present invention is to provide a phase detection method and a phase detection circuit that can detect during operation, and can effectively and quickly measure test.

Therefore, the present invention mainly implements the above-mentioned objects and performance through the following technical means, for a testing machine to measure the clock cycle and/or phase shift of a circuit to be tested of a semiconductor device, which Including; a frequency multiplier circuit, which has two input terminals, one of which can be connected in parallel with the input terminal of a circuit under test for receiving an input signal input, and the other input terminal of the frequency multiplier circuit is the same as the previous test The output terminal of the circuit is connected for receiving an output signal input with a phase difference generated by the circuit under test, and the frequency multiplier circuit can combine the input signal with the output signal to generate a set of double frequency multiplier signals; a comparison The circuit has two input terminals, one of which is connected to the output terminal of the frequency doubling circuit for receiving the frequency doubling signal, and the other input terminal is for inputting a reference signal, so that the comparison circuit can compare the two inputs The phase difference of the signal; a surge filter with an input connected to the output of the comparison circuit. The surge filter can filter out the comparison signal input by the comparison circuit beyond the allowable value through the preset allowable value. Signal surge; an interpretation output, which has an input connected to the output of the surge filter, so that it can interpret the results according to the rules and report back to the testing machine.

Thus, through the specific implementation of the aforementioned technical means, the present invention can be used to obtain a new frequency-multiplied signal after obtaining an input signal and an output signal with the same frequency and a phase difference through a very simple phase detection circuit. Compare with a reference signal with the same phase and the same frequency, and further determine whether the phase is correct by filtering whether the phase difference between the multiplier signal and the reference signal is within the acceptable range, and at the same time complete the measurement of the clock cycle to solve Such as DLL/DL circuit can only enter The problem of running the clock cycle test can further do a phase shift test of 90 degrees, which can effectively improve the accuracy of the detection, and can be detected during operation, and thus rapid testing, and can increase its added value and can also improve its Economic benefits.

In order to enable your review committee to further understand the structure, features and other purposes of the present invention, the following are some preferred embodiments of the present invention, and the detailed description in conjunction with the drawings as follows, for those familiar with the technical field to be able to implement .

(10)‧‧‧phase detection circuit

(12)‧‧‧ Frequency multiplier circuit

(14)‧‧‧Comparison circuit

(16)‧‧‧Surge filter

(18)‧‧‧Interpretation output

(20)‧‧‧ circuit under test

The first figure is a schematic diagram of the structure of the phase detection circuit of the present invention, for illustrating its main configuration state.

Figure 2 is a schematic diagram of the phase detection circuit of the present invention when it is actually applied to a DLL/DL circuit of a semiconductor device.

The third figure is a schematic flow chart of the phase detection method of the present invention.

The fourth figure: it is a time sequence diagram of the present invention in actual operation, for explaining the measurement qualified state.

Fifth figure: It is another time sequence diagram of the present invention in actual operation, to illustrate the state of measurement failure.

A phase detection method and a phase detection circuit of the present invention are shown in the first and second figures, wherein the first figure is the architecture of the phase detection circuit of the present invention, and the second figure applies the phase detection circuit of the present invention to practical applications Architecture. As shown in the figure, the phase detection circuit (10) includes a frequency multiplier circuit (12), a comparison circuit (14) connected to the output terminal, and a surge filter connected to the output terminal of the comparison circuit (14) 16) [Glitch Filter] and a judgment output device (18) [Result report] provided at the output end of the surge filter (16); The frequency multiplier circuit (12) has two input terminals for obtaining two input signals. One of the input terminals can be connected in parallel with the input terminal of a circuit under test (20) [such as DLL/DL circuit] [as shown in the second figure] for receiving an input signal [DLY_input] input. The other input terminal of the frequency multiplier circuit (12) is connected to the output terminal of the circuit under test (20) [as shown in the second figure] for receiving a phase difference produced by the circuit under test (20) [ Phase] output signal [DLY_output] input, using the simple circuit of the frequency multiplier circuit (12) to combine the two input signals to generate a new frequency multiplier signal, if the input signal of the frequency multiplier circuit (12) is input When the phase difference between the two input signals of [DLY_input] and the output signal [DLY_output] is 90 degrees, the frequency multiplier circuit (12) will generate a new double frequency multiplier signal [clock_2x] that is close to the output signal [DLY_output] ].

The comparison circuit (14) has two input terminals. One of the input terminals is connected to the output terminal of the frequency multiplier circuit (12) for receiving the double frequency multiplier signal [clock_2x] output by the frequency multiplier circuit (12). The other input terminal can be used to input a reference signal [reference_clock], so as to further compare the phase difference of the two input signals by using the comparison circuit (14). In addition, the input terminal of the surge filter (16) is connected to the output terminal of the aforementioned comparison circuit (14), and is used to filter the comparison signal input through the comparison circuit (14) through the preset allowable value, which does not exceed the allowable Signal glitch of value [Glitch]. Furthermore, the input terminal of the interpretation output device (18) is connected to the output terminal of the aforementioned surge filter (16), which is used to interpret the result according to a preset rule, for example, when the surge filter (16) filters When the signal surge is within the allowable value range, a filtered signal without glitches [as shown in the third figure] is output for the interpretation output device (18) to read and pass, and the interpretation output device (18) After collecting the qualified results, the output terminal outputs and returns to the testing machine. Conversely, when the surge filter (16) filters When the signal surge exceeds the allowable value range, a filtered signal with a surge [as shown in the fourth figure] is output for the interpretation output (18) to read as unqualified, and the interpretation output (18 ) After collecting the unqualified result, the output terminal will output and report back to the testing machine.

Thereby, a phase detection circuit with simple circuit and high measurement accuracy is formed.

The third figure shows a flowchart of the phase detection method of the present invention. The fourth and fifth figures show timing diagrams of different states according to these embodiments.

(a) Step S101: Obtain two input signals. One is the input signal directly from the external circuit. The other is that the input signal generates a signal with a phase difference after passing through a circuit to be tested. Prepare a clock input signal [DLY_input] with the frequency F of the DLL/DL circuit to be input to the circuit under test (20). Prepare a clock output signal [DLY_output] after the input signal is input to the phase detection circuit (10) to generate a phase shift. If the DLL/DL circuit of the circuit under test (20) has a 90-degree phase difference during normal operation, the output signal is the 90-degree phase of the input signal, and the input signal and the output signal are simultaneously input to the phase detection circuit ( 10) Frequency multiplication circuit (12).

(b) Step S102: Combine the input signal and the signal with phase difference to generate a frequency doubling signal: combine the aforementioned input signal with the signal with phase difference through the frequency doubling circuit (12), as described above When the output signal is 90 degrees out of phase with the input signal, a double frequency signal [2xF] with a phase close to the input signal is generated [clock_2x].

(c) Step S103: Compare the frequency-doubled signal with a reference signal whose frequency and phase are the same as the frequency-doubled signal. Prepare a phase with the frequency and phase of the multiplier signal The same reference signal [Reference_clock], and the frequency multiplier signal output from the frequency multiplier circuit (12) is compared with the reference signal through the comparison circuit (14) of the phase detection circuit (10).

(d) Step S104: Whether the phase difference between the filtered reference signal and the multiplier signal is within the acceptance range. According to the preset surge allowable value, whether the phase difference between the reference signal and the frequency doubling signal is filtered through the surge filter (16) of the phase detection circuit (10) is within an acceptable range. If the input signal and the output signal are 90 degrees out of phase, as shown in the fourth figure, the multiplier signal and the reference signal should be equal, or an acceptable signal surge [such as Sig_diff in the fourth figure] should be generated. After filtering, a surge-free signal is formed [Sig_filter in the fourth image]. Conversely, when the frequency-multiplied signal is not equal to the reference signal, a signal surge beyond acceptable [Sig_diff in the fifth figure] is generated, and after filtering, a sequence surge signal [Sig_filter in the fifth figure] is formed.

(e) Step S105: Report the filtered result. After the judging output device (18) of the phase detection circuit (10) obtains the filtering signal of the surge filter (16), if the filtered signal is a non-surge signal [such as Sig_filter in the fourth figure], it is judged as qualified. Conversely, if the filtered signal is a surge signal [Sig_filter in the fifth figure], it is judged as unqualified. The interpretation output device (18) returns the aforementioned qualified or unqualified signal to the testing machine, and then ends the entire phase detection measurement process.

Through the above description, the present invention obtains an input signal from an external circuit through a very simple phase detection circuit (10), so that the input signal passes through the circuit under test to generate a signal with the same frequency and a phase difference, combining these two signals A new frequency doubling signal is generated. Reference signal with the same phase and frequency as the frequency doubling signal No. Further, by filtering whether the phase difference between the frequency-doubled signal and the reference signal is within an acceptable range, it is judged whether the phase is correct, and at the same time, the measurement of the clock cycle is completed, thereby solving the problem that the DLL/DL circuit can only perform the clock cycle test. In addition, it can further do a phase shift test of 90 degrees, which can effectively improve the accuracy of detection, at the same time, it can be tested at runtime, and can be tested quickly, so it can greatly improve its practicality.

In summary, it can be understood that the present invention is an invention with excellent creativity, in addition to effectively solving the problems faced by the previous art, greatly improving the efficiency, and in the same technical field, there is no same or similar product creation or It is open for use and has an improvement in efficacy. Therefore, the present invention has met the requirements for "novelty" and "progressiveness" of the invention patent, and an application for an invention patent is filed according to law.

(10)‧‧‧phase detection circuit

(12)‧‧‧ Frequency multiplier circuit

(14)‧‧‧Comparison circuit

(16)‧‧‧Surge filter

(18)‧‧‧Interpretation output

Claims (7)

A phase detection circuit for a testing machine to measure the clock cycle and/or phase shift of a circuit to be tested of a semiconductor device, which includes; a frequency multiplier circuit with two input terminals, one of which can be connected to The input terminal of a circuit under test is connected in parallel for receiving an input signal input, and the other input terminal of the frequency multiplier circuit is connected to the output terminal of the previous circuit under test for receiving a signal with a phase difference generated by the circuit under test And the frequency multiplier circuit can combine the input signal with the signal with phase difference to generate a frequency multiplier signal; a comparison circuit has two input terminals, one of which is connected to the output terminal of the frequency multiplier circuit. Receiving the frequency-multiplied signal, the other input can receive a reference signal, the comparison circuit can compare the input signal with the signal with phase difference; a surge filter with an input connected to the output of the comparison circuit At the end, the surge filter can filter the comparison signal input by the comparison circuit through the preset allowable value, and the signal surge that does not exceed the allowable value is filtered out, wherein the allowable value is adjustable; a judgment output device, which has a Connect the input of the output of the surge filter, so that it can interpret the results according to the rules and report back to the testing machine. The phase detection circuit as described in item 1 of the patent application range, wherein the semiconductor device may be a dynamic random access memory. The phase detection circuit as described in item 1 of the patent application range, wherein the semiconductor device may be a flash memory. The phase detection circuit as described in item 1 or 2 or 3 of the patent application scope, wherein the circuit to be tested of the semiconductor device may be a delay-phase locked circuit. The phase detection circuit as described in item 1 or 2 or 3 of the patent application range, wherein the circuit to be tested of the semiconductor device may be a delay line circuit. The phase detection circuit as described in item 1 of the patent application scope, wherein the input signal is combined with a signal with a phase difference to generate a double frequency signal with the same phase as the input signal. A phase detection method for a testing machine to measure the clock cycle and/or phase shift of a circuit to be tested of a semiconductor device, which includes the following steps: obtaining two signals, one of which is from an external circuit Input signal, another signal is a signal with phase difference generated by the input signal passing through a circuit to be tested; combining the input signal and the signal with phase difference to generate a doubled frequency doubler with the same phase as the input signal Signal; compare the multiplier signal with a reference signal with the same frequency and phase; filter whether the phase difference between the reference signal and the multiplier signal is within the accepted range; and report the filtered result.

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