TWI684314B - Pwm/pfm dual mode charging system - Google Patents

Pwm/pfm dual mode charging system Download PDF

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TWI684314B
TWI684314B TW108115134A TW108115134A TWI684314B TW I684314 B TWI684314 B TW I684314B TW 108115134 A TW108115134 A TW 108115134A TW 108115134 A TW108115134 A TW 108115134A TW I684314 B TWI684314 B TW I684314B
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voltage
current
transistor
signal
charge
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TW108115134A
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TW202042476A (en
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王朝欽
侯宗佑
劉冠賢
林裕城
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國立中山大學
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Abstract

A PWM/PFM dual mode charging system includes a conversion circuit, a current sensor, a constant current mode control unit, a constant voltage mode control unit and a OR gate. The conversion circuit is configured to charge a battery module. The current is configured to sense a current level of the conversion circuit and output a sensing voltage. The constant current mode control unit receives the sensing voltage and outputs a PWM signal. The constant voltage mode control unit outputs a PFM signal. The OR gate receives the PWM signal and the PFM signal and outputs a control signal for controlling the conversion circuit.

Description

PWM/PFM雙模式充電系統PWM/PFM dual-mode charging system

本發明是關於一種充電系統,特別是關於一種PWM/PFM雙模式充電系統。The invention relates to a charging system, in particular to a PWM/PFM dual-mode charging system.

隨著電動汽機車及可攜式個人裝置的快速發展,電動汽機車及可攜式個人裝置所使用之儲能裝置對於電力容量的需求越來越大,其中,鋰電池因為具有高能量密度的優點而被廣泛使用,此外,為了提供快速、穩定及高效率的充電,充電的控制方法也相當受到重視。一般而言,鋰電池的充電曲線可區分為三個階段,首先,在預充電階段以微小的電流進行充電,以避免對低電壓之電池造成傷害;接著當鋰電池的電壓上升至一準位時,切換至定電流模式進行充電,以最大的電流對鋰電池進行充電而加快充電速度;最後當鋰電池的電壓達到滿額電壓時,切換至定電壓模式進行充電,以緩慢遞減的電流對鋰電池充電,避免鋰電池被過度充電。其中,較為常見的充電系統為切換式電源轉換電路搭配PWM(Pulse Width Modulation)的控制達成三階段的充電,在定電流模式下可將其視為重載,在定電壓模式下則可將其視為輕載,雖然以PWM進行控制可在定電流模式下達到高效率的電源轉換,但單純使用PWM在定電壓模式下進行控制並無法達到高效率。With the rapid development of electric steam locomotives and portable personal devices, the energy storage devices used in electric steam locomotives and portable personal devices have an increasing demand for power capacity. Among them, lithium batteries have high energy density. The advantages are widely used. In addition, in order to provide fast, stable and high-efficiency charging, charging control methods have also received considerable attention. Generally speaking, the charging curve of a lithium battery can be divided into three stages. First, the small current is charged in the pre-charging stage to avoid damage to the low-voltage battery; then when the voltage of the lithium battery rises to a level At the time, switch to constant current mode for charging, charge the lithium battery with the maximum current to speed up the charging speed; finally, when the voltage of the lithium battery reaches the full voltage, switch to constant voltage mode for charging, and charge the lithium battery with a slowly decreasing current Charge the battery to prevent the lithium battery from being overcharged. Among them, the more common charging system is a switching power conversion circuit with PWM (Pulse Width Modulation) control to achieve three-stage charging, which can be regarded as a heavy load in a constant current mode, and can be used in a constant voltage mode Regarded as light load, although PWM control can achieve high efficiency power conversion in constant current mode, but simply using PWM to control in constant voltage mode cannot achieve high efficiency.

本發明的主要目的在於提供具有雙模式充電控制之充電系統,能在定電流模式下以PWM(Pulse-width modulation)進行電源轉換之控制,並在定電壓模式下以PFM(Pulse-frequency modulation)進行電源轉換之控制,以克服先前技術中單純透過PWM進行控制而在定電壓模式下有著效率低的問題,且本發明僅透過一個或閘即達成PWM及PFM兩種模式的結合,可有效地減少模式切換時的損耗並提高整體效率。The main objective of the present invention is to provide a charging system with dual-mode charging control, which can perform power conversion control by PWM (Pulse-width modulation) in constant current mode and PFM (Pulse-frequency modulation) in constant voltage mode The control of power conversion is performed to overcome the problem of low efficiency in the constant voltage mode simply controlled by PWM in the prior art, and the present invention achieves the combination of PWM and PFM modes through only one OR gate, which can effectively Reduce losses during mode switching and increase overall efficiency.

本發明之一種PWM/PFM雙模式充電系統包含一轉換電路、一電流感測器、一定電流模式控制單元、一定電壓模式控制單元及一或閘,其中該轉換電路具有一第一功率開關、一第二功率開關及一充放電單元,該充放電單元電性連接該第一功率開關及該第二功率開關,該轉換電路用以對一電池模組充電,其中該電池模組具有一電池電壓。該電流感測器耦接該充放電單元,該電流感測器用以感測該充放電單元之一電流的大小,且該電流感測器輸出一感測電壓,該定電流模式控制單元電性連接該電流感測器以接收該感測電壓,該定電流模式控制單元根據該電流感測器之該感測電壓、一限制電壓及一漣波電壓輸出一脈衝寬度調變訊號。該定電壓模式控制單元根據該電池電壓、一滿額電壓及一時脈訊號輸出一脈衝頻率調變訊號。該或閘電性連接該定電流模式控制單元及該定電壓模式控制單元以接收該脈衝寬度調變訊號及該脈衝頻率調變訊號,該或閘輸出一控制訊號以控制該轉換電路之該第一功率開關及該第二功率開關。A PWM/PFM dual-mode charging system of the present invention includes a conversion circuit, a current sensor, a certain current mode control unit, a certain voltage mode control unit, and an OR gate, wherein the conversion circuit has a first power switch, a A second power switch and a charge-discharge unit, the charge-discharge unit is electrically connected to the first power switch and the second power switch, the conversion circuit is used to charge a battery module, wherein the battery module has a battery voltage . The current sensor is coupled to the charge-discharge unit. The current sensor is used to sense a current of the charge-discharge unit. The current sensor outputs a sense voltage. The constant current mode controls the electrical property of the unit The current sensor is connected to receive the sensing voltage, and the constant current mode control unit outputs a pulse width modulation signal according to the sensing voltage of the current sensor, a limiting voltage, and a ripple voltage. The constant voltage mode control unit outputs a pulse frequency modulation signal according to the battery voltage, a full voltage and a clock signal. The OR gate is electrically connected to the constant current mode control unit and the constant voltage mode control unit to receive the pulse width modulation signal and the pulse frequency modulation signal, and the OR gate outputs a control signal to control the first of the conversion circuit A power switch and the second power switch.

本發明藉由該定電流模式控制單元及該定電壓模式控制單元達成PWM/PFM雙模式的充電控制,並僅透過單一個該或閘達成兩個模式之間的切換,可再進一步地減少模式切換時可能產生的損耗,提高該PWM/PFM雙模式充電系統的整體充電效率。 The present invention achieves PWM/PFM dual-mode charging control by the constant current mode control unit and the constant voltage mode control unit, and only achieves the switching between the two modes through a single OR gate, which can further reduce the mode The loss that may occur during switching improves the overall charging efficiency of the PWM/PFM dual-mode charging system.

請參閱第1圖,其為本發明之一實施例,一PWM/PFM雙模式充電系統100的功能方塊圖,該PWM/PFM雙模式充電系統100具有一轉換電路110、一電流感測器120、一定電流模式控制單元130、一定電壓模式控制單元140及一或閘150。該轉換電路110接收一輸入電壓Vin並將其進行轉換為合適之電流或電壓對一電池模組B充電,該電流感測器120耦接該轉換電路110以感測其電流大小,且該電流感測器120輸出一感測電壓Vsense。該定電流模式控制單元130電性連接該電流感測器120以接收該感測電壓Vsense,該定電流模式控制單元130另接 收一限制電壓Vlimit及一漣波電壓Vramp,且該定電流模式控制單元130根據該感測電壓Vsense、該限制電壓Vlimit及該漣波電壓Vramp輸出一脈衝寬度調變訊號PWM。該定電壓模式控制單元140根據該電池模組B之一電池電壓VBAT、一滿額電壓Vfull及一時脈訊號Clk輸出一脈衝頻率調變訊號PFM,該或閘150電性連接該定電流模式控制單元130及該定電壓模式控制單元140以接收該脈衝寬度調變訊號PWM及該脈衝頻率調變訊號PFM,該或閘150輸出一控制訊號SC至該轉換電路110並控制該轉換電路110,使該轉換電路110能在各個充電階段下以合適的電流或電壓對該電池模組B進行充電,其中各電路單元的詳細電路及作動方式詳述於下。 Please refer to FIG. 1, which is a functional block diagram of a PWM/PFM dual-mode charging system 100 according to an embodiment of the invention. The PWM/PFM dual-mode charging system 100 has a conversion circuit 110 and a current sensor 120 , A certain current mode control unit 130, a certain voltage mode control unit 140, and an OR gate 150. The switching circuit 110 receives an input voltage V in and will be converted into an appropriate current or voltage of a battery module B is charged, the current sensor 120 is coupled to the switching circuit 110 to sense its current size, and the The current sensor 120 outputs a sense voltage V sense . The constant current mode control unit 130 is electrically connected to the current sensor 120 to receive the sense voltage V sense , the constant current mode control unit 130 further receives a limit voltage V limit and a ripple voltage V ramp , and the constant The current mode control unit 130 outputs a pulse width modulation signal PWM according to the sense voltage V sense , the limit voltage V limit and the ripple voltage V ramp . The constant voltage mode control unit 140 outputs a pulse frequency modulation signal PFM according to a battery voltage V BAT of the battery module B, a full voltage V full and a clock signal Clk, and the OR gate 150 is electrically connected to the constant current mode the control unit 130, and the constant voltage mode control unit 140 to receive the pulse width modulation signal PWM and the pulse frequency modulation signal PFM, the oR gate 150 outputs a control signal S C to the switching circuit 110 and controls the switching circuit 110 , So that the conversion circuit 110 can charge the battery module B with a suitable current or voltage at each charging stage. The detailed circuit and operation mode of each circuit unit are described in detail below.

請參閱第1及2圖,在本實施例中,該轉換電路110為一切換式電源轉換架構,該轉換電路110具有一第一功率開關111、一第二功率開關112、一充放電單元113、一非交疊電路114、一零電流偵測電路115及一高準位位移器116。其中,該第一功率開關111為一P型功率電晶體,該第二功率開關112為一N型功率電晶體,該第一功率開關111之源極接收該輸入電壓Vin,該第一功率開關111之汲極電性連接一節點VX,該第一功率開關111之閘極接收一第一控制訊號SC1。該第二功率開關112之汲極電性連接該節點VX,該第二功率開關112之源極接地,該第二功率開關112之閘極接收一第二控制訊號SC2。該充放電單元113具有一電感113a、一電阻113b及一電容113c,該電感113a之兩端分別電性連接該節點VX及該電池模組B,該電阻113b之兩端分別電性連接該電池模組B及該電容113c之一端,該電容113c之另一端接地。該非交疊電路114電性連接該或閘150以接收該控制訊號SC,且該非交疊電路114將該控制訊號SC分為該第一控制訊號SC1及該第二控制訊號SC2。該零電流偵測電路115電性連接該非交疊電路114,以將該第二控制訊號SC2傳送至該第二功率開關112。該高準位位移器116電性連接該非交疊電 路114,以提昇該第一控制訊號SC1的準位並傳送至該第一功率開關111。該轉換電路110藉由該第一控制訊號SC1及該第二控制訊號SC2控制該第一功率開關111及該第二功率開關112之責任週期(Duty cycle),而將該輸入電壓Vin轉換為合適之電流或電壓對該電池模組B充電。 Please refer to FIGS. 1 and 2. In this embodiment, the conversion circuit 110 is a switching power conversion architecture. The conversion circuit 110 has a first power switch 111, a second power switch 112, and a charge-discharge unit 113 , A non-overlapping circuit 114, a zero current detection circuit 115 and a high level shifter 116. The first power switch 111 is a P-type power transistor, the second power switch 112 is an N-type power transistor, the source of the first power switch 111 receives the input voltage V in , and the first power The drain of the switch 111 is electrically connected to a node V X , and the gate of the first power switch 111 receives a first control signal S C1 . The drain of the second power switch 112 is electrically connected to the node V X , the source of the second power switch 112 is grounded, and the gate of the second power switch 112 receives a second control signal S C2 . The charging and discharging unit 113 has an inductor 113a, a resistor 113b, and a capacitor 113c. Both ends of the inductor 113a are electrically connected to the node V X and the battery module B, respectively, and both ends of the resistor 113b are electrically connected to the One end of the battery module B and the capacitor 113c, and the other end of the capacitor 113c are grounded. 114 of the non-overlap circuit electrically connected to the OR gate 150 receives the control signal S C, the non-overlap circuit 114 and the control signal S C is divided into the first control signal S C1 and the second control signal S C2. The zero current detection circuit 115 is electrically connected to the non-overlapping circuit 114 to transmit the second control signal SC 2 to the second power switch 112. The high level shifter 116 is electrically connected to the non-overlapping circuit 114 to raise the level of the first control signal S C1 and transmit it to the first power switch 111. The conversion circuit 110 controls the duty cycle of the first power switch 111 and the second power switch 112 by the first control signal S C1 and the second control signal S C2 , and the input voltage V in Convert to a suitable current or voltage to charge the battery module B.

請參閱第2及3圖,該電流感測器120用以感測該充放電單元113之該電感113a的電流大小,以得知該電感113a的電流是否已經大於一預定值而判斷該轉換電路110是否切換至定電流模式。請參閱第3圖,在本實施例中,該電流感測器120具有一負載121、一第一電流鏡122、一第二電流鏡123及一電流電壓轉換迴路124。該負載121具有一第一電晶體121a及一第二電晶體121b,該第一電流鏡122具有一第三電晶體122a及一第四電晶體122b,該第二電流鏡123具有一第五電晶體123a、一第六電晶體123b及一第七電晶體123c,該第一電晶體121a、該第三電晶體122a及該第五電晶體123a構成一第一電流迴路L1,該第二電晶體121b、該第四電晶體122b及該第六電晶體123b構成一第二電流迴路L2,該第七電晶體123c用以複製電流至該第一電流迴路L1及該第二電流迴路L2,使該第一電流迴路L1及該第二電流迴路L2的電流與該第七電晶體123c的電流相同,且由於該第一電流迴路L1及該第二電流迴路L2的路徑相同,因此,節點VY與節點VZ的電壓相同。此外,該第一電流迴路L1電性連接該電感113a而由該電感113a擷取部份之電流,該電流電壓轉換迴路124電性連接該第二電晶體121b以由該第二電流迴路L2擷取一偵測電流並將其轉換為該感測電壓Vsense,其中,藉由該第一電晶體121a之寬度比為該第二電晶體121b之寬度比的K倍,該第二電晶體121b可以複製K分之一倍的該第一電晶體121a之電流並由該電流電壓轉換迴路124轉換為該感測電壓Vsense,而可藉由該感測電壓Vsense的電位偵測該電感113a的電流大小。 Please refer to FIG. 2 and FIG. 3, the current sensor 120 is used to sense the current size of the inductor 113a of the charge-discharge unit 113 to know whether the current of the inductor 113a has been greater than a predetermined value to determine the conversion circuit 110 Whether to switch to constant current mode. Please refer to FIG. 3. In this embodiment, the current sensor 120 has a load 121, a first current mirror 122, a second current mirror 123 and a current-voltage conversion circuit 124. The load 121 has a first transistor 121a and a second transistor 121b, the first current mirror 122 has a third transistor 122a and a fourth transistor 122b, and the second current mirror 123 has a fifth transistor The crystal 123a, a sixth transistor 123b and a seventh transistor 123c, the first transistor 121a, the third transistor 122a and the fifth transistor 123a constitute a first current loop L1, the second transistor 121b, the fourth transistor 122b and the sixth transistor 123b constitute a second current loop L2, and the seventh transistor 123c is used to replicate the current to the first current loop L1 and the second current loop L2, so that the The currents of the first current loop L1 and the second current loop L2 are the same as the current of the seventh transistor 123c, and since the paths of the first current loop L1 and the second current loop L2 are the same, the node V Y is The voltage at node V Z is the same. In addition, the first current loop L1 is electrically connected to the inductor 113a to extract part of the current from the inductor 113a, and the current-voltage conversion loop 124 is electrically connected to the second transistor 121b to be extracted by the second current loop L2 Take a detection current and convert it to the sense voltage V sense , where the width ratio of the first transistor 121a is K times the width ratio of the second transistor 121b, the second transistor 121b The current of the first transistor 121a can be duplicated by a factor of K and converted into the sense voltage V sense by the current-voltage conversion circuit 124, and the inductor 113a can be detected by the potential of the sense voltage V sense The size of the current.

請參閱第2及4圖,該定電流模式控制單元130具有一第一比較器131、一充放電選擇電路132、一充電電容133、一第二比較器134、一延遲器135及一低準位位移器136。該第一比較器131電性連接該電流感測器120及該低準位位移器136,以由該電流感測器120接收該感測電壓Vsense,並由該低準位位移器136接收該限制電壓Vlimit,該第一比較器131比對該感測電壓Vsense及該限制電壓Vlimit的電位大小並輸出一第一比較訊號comp1。該充放電選擇電路132電性連接該第一比較器131以接收該第一比較訊號comp1,該充電電容133電性連接該充放電選擇電路132,其中,該充放電選擇電路132根據該第一比較訊號comp1選擇性地對該充電電容133充電或放電,使該充電電容133之一電容電壓VCC上升或下降。該第二比較器134電性連接該充電電容133,該第二比較器134比對該充電電容133之該電容電壓VCC及該漣波電壓Vramp的電位大小而輸出該脈衝寬度調變訊號PWM。該延遲器135接收反相之該脈衝寬度調變訊號PWM進行延遲,該低準位位移器136接收該延遲器135輸出之一延遲訊號Sdelay進行準位位移,且該低準位位移器136輸出該限制電壓Vlimit至該第一比較器131。 Please refer to FIGS. 2 and 4, the constant current mode control unit 130 has a first comparator 131, a charge and discharge selection circuit 132, a charging capacitor 133, a second comparator 134, a delay 135 and a low level Bit shifter 136. The first comparator 131 is electrically connected to the current sensor 120 and the low level shifter 136, so that the current sensor 120 receives the sensing voltage V sense and is received by the low level shifter 136 For the limit voltage V limit , the first comparator 131 compares the potential levels of the sense voltage V sense and the limit voltage V limit and outputs a first comparison signal comp1. The charge-discharge selection circuit 132 is electrically connected to the first comparator 131 to receive the first comparison signal comp1, and the charge capacitor 133 is electrically connected to the charge-discharge selection circuit 132, wherein the charge-discharge selection circuit 132 is based on the first The comparison signal comp1 selectively charges or discharges the charging capacitor 133 so that a capacitor voltage V CC of the charging capacitor 133 rises or falls. The second comparator 134 is electrically connected to the charging capacitor 133, and the second comparator 134 outputs the pulse width modulation signal according to the potential levels of the capacitor voltage V CC and the ripple voltage V ramp of the charging capacitor 133 PWM. The delayer 135 receives the inverted PWM signal PWM for delay, the low level shifter 136 receives a delay signal S delay output from the delay 135 for level shifting, and the low level shifter 136 The limit voltage V limit is output to the first comparator 131.

請參閱第4圖,該充放電選擇電路132具有一第一開關132a、一第二開關132b及一反相器132c,該第一開關132a之閘極電性連接該第一比較器131以接收該第一比較訊號comp1並受該第一比較訊號comp1控制,該第二開關132b之閘極經由該反相器132c接收反相之該第一比較訊號comp1並受反相之該第一比較訊號comp1控制,在本實施例中,該第一開關132a及該第二開關132b皆為NMOS電晶體,由於受到互為反相之訊號控制,該第一開關132a導通時,該第二開關132b截止,而該第一開關132a截止時,該第二開關132b導通。其中,當該感測電壓Vsense小於該限制電壓Vlimit時,該第一比較器131輸出之該第一比較訊號comp1為高電位,導通該第一開關132a並截止該第二開關132b,此時一充電電流I C經由該第一開關132a對該充電電容133充電,使該充電電容133的該電容電壓V cc緩慢上升。相對地,當該感測電壓V sense大於該限制電壓V limit時,該第一比較器131輸出之第一比較訊號comp1為低電位,而截止該第一開關132a並導通該第二開關132b,此時該第二開關132b提供一放電電流I DISS對該充電電容133放電,使該充電電容133的該電容電壓V CC上升速度放緩或是下降,接著再透過該第二比較器134比對該充電電容133的該電容電壓V CC與該漣波電壓V ramp的大小後即可輸出責任週期(Duty cycle)可變之該脈衝寬度調變訊號PWM,而可藉由該脈衝寬度調變訊號PWM的控制讓該充放電單元113的輸出電流維持在定電流。 Referring to FIG. 4, the charge-discharge selection circuit 132 has a first switch 132a, a second switch 132b, and an inverter 132c. The gate of the first switch 132a is electrically connected to the first comparator 131 to receive The first comparison signal comp1 is controlled by the first comparison signal comp1, the gate of the second switch 132b receives the inverted first comparison signal comp1 through the inverter 132c and receives the inverted first comparison signal Comp1 control. In this embodiment, both the first switch 132a and the second switch 132b are NMOS transistors. Due to the signal control of opposite phases to each other, when the first switch 132a is turned on, the second switch 132b is turned off When the first switch 132a is turned off, the second switch 132b is turned on. When the sense voltage V sense is less than the limit voltage V limit , the first comparison signal comp1 output by the first comparator 131 is at a high level, turning on the first switch 132a and turning off the second switch 132b. when a charging current I C of the first switch 132a of the capacitor 133 is charged via the charging, the capacitor voltage V cc so that the charging capacitor 133 rises slowly. In contrast, when the sense voltage V sense is greater than the limit voltage V limit , the first comparison signal comp1 output by the first comparator 131 is at a low level, and the first switch 132a is turned off and the second switch 132b is turned on. At this time, the second switch 132b provides a discharge current I DISS to discharge the charging capacitor 133, so that the rising speed of the capacitor voltage V CC of the charging capacitor 133 is slowed or decreased, and then compared by the second comparator 134 After the magnitudes of the capacitor voltage V CC and the ripple voltage V ramp of the charging capacitor 133, the pulse width modulation signal PWM with a variable duty cycle can be output, and the pulse width modulation signal can be modulated by the pulse width The PWM control keeps the output current of the charging and discharging unit 113 at a constant current.

請參閱第2及5圖,該定電壓模式控制單元140具有一第三比較器141、一正反器142及一定電壓控制或閘143,該第三比較器141接收該電池模組B之該電池電壓V BAT及該滿額電壓V full,其中該滿額電壓V full是藉由該電池模組B的額定電壓進行設定,該第三比較器141比對該電池電壓V BAT及該滿額電壓V full的電位大小並輸出一第三比較訊號comp3。該正反器142之輸入端電性連接第三比較器141以接收該第三比較訊號comp3,該正反器142之時脈輸入端接收該時脈訊號Clk,且該正反器142根據該第三比較訊號comp3及該時脈訊號Clk輸出一正反器輸出訊號S FF,該定電壓控制或閘143電性連接該正反器142,且該定電壓控制或閘143根據該正反器輸出訊號S FF及該時脈訊號Clk輸出該脈衝頻率調變訊號PFM。 Referring to FIGS. 2 and 5, the constant voltage mode control unit 140 has a third comparator 141, a flip-flop 142, and a certain voltage control or gate 143. The third comparator 141 receives the battery module B The battery voltage V BAT and the full voltage V full , wherein the full voltage V full is set by the rated voltage of the battery module B, the third comparator 141 compares the battery voltage V BAT with the full voltage V full And output a third comparison signal comp3. The input terminal of the flip-flop 142 is electrically connected to the third comparator 141 to receive the third comparison signal comp3, the clock input terminal of the flip-flop 142 receives the clock signal Clk, and the flip-flop 142 is based on the The third comparison signal comp3 and the clock signal Clk output a flip-flop output signal S FF , the constant voltage control or gate 143 is electrically connected to the flip-flop 142, and the constant voltage control or gate 143 is based on the flip-flop The output signal S FF and the clock signal Clk output the pulse frequency modulation signal PFM.

請參閱第2及5圖,當該電池模組B之該電池電壓V BAT尚未達到該滿額電壓V full前,該第三比較器141輸出之該第三比較訊號comp3為低電位,使得該定電壓控制或閘143輸出之該脈衝頻率調變訊號PFM的電位變化與該時脈訊號Clk相同,而由於該時脈訊號Clk的責任週期很小,因此,該或閘150接收該脈衝寬度調變訊號PWM及該脈衝頻率調變訊號PFM後,該脈衝頻率調變訊號PFM會被該脈衝寬度調變訊號PWM遮蔽,使得該控制訊號S C的電位變化與該脈衝寬度調變訊號PWM相同。而當該電池模組B之該電池電壓V BAT達到該滿額電壓V full時,該第三比較器141輸出之該第三比較訊號comp3為高電位,使得該正反器輸出訊號S FF為較長的邏輯1訊號而遮蔽該時脈訊號Clk,讓該定電壓控制或閘143輸出之該脈衝頻率調變訊號PFM也為較長的邏輯1訊號,該或閘150接收該脈衝寬度調變訊號PWM及該脈衝頻率調變訊號PFM後,該脈衝寬度調變訊號PWM會被該脈衝頻率調變訊號PFM遮蔽,使得該控制訊號S C的電位變化與該脈衝頻率調變訊號PFM相同,藉此,本發明可以僅透過單一個該或閘150達成充電系統於雙模式之間的切換,而減少兩個模式之間切換可能產生的損失並提高整體效率。 Please refer to FIGS. 2 and 5, before the battery voltage V BAT of the battery module B has not reached the full voltage V full , the third comparison signal comp3 output by the third comparator 141 is at a low potential, making the constant The potential change of the pulse frequency modulation signal PFM output by the voltage control or gate 143 is the same as the clock signal Clk, and since the duty cycle of the clock signal Clk is very small, the OR gate 150 receives the pulse width modulation and the PWM signal of the PFM pulse frequency modulation signal, the pulse frequency modulation signal is masked to the PFM pulse width modulation signal PWM, so that the same with the pulse width modulation signal PWM control signal S C to the potential change. When the battery voltage V BAT of the battery module B reaches the full voltage V full , the third comparison signal comp3 output by the third comparator 141 is at a high level, so that the flip-flop output signal S FF is The long logic 1 signal shields the clock signal Clk, so that the pulse frequency modulation signal PFM output by the constant voltage control or gate 143 is also a longer logic 1 signal, and the OR gate 150 receives the pulse width modulation signal after the PWM and PFM pulse frequency modulation signal, the pulse width modulation signal PWM is a pulse frequency modulation signal of the PFM shield, so that the same frequency of the pulse modulation signal of the PFM control signal S C of the potential change, thereby In the present invention, only one OR gate 150 can be used to switch between two modes of the charging system, thereby reducing the possible loss caused by switching between the two modes and improving the overall efficiency.

請參閱第2及6圖,該非交疊電路114電性連接該或閘150以接收該控制訊號S C,且該非交疊電路114分別輸出該第一控制訊號S C1及該第二控制訊號S C2至該第一功率開關111及該第二功率開關112,其中,該非交疊電路114透過兩個反相器串使得該第一控制訊號S C1開啟該第一功率開關111的時間長於該第二控制訊號S C2關閉該第二功率開關112的時間,讓該第一功率開關111及該第二功率開關112的切換時間交錯,以避免該第一功率開關111及該第二功率開關112同時導通使該輸入電壓V in經由該第一功率開關111及該第二功率開關112接地產生大電流,造成功率損耗或是功率開關的燒毀的問題發生。 See FIGS. 2 and 6, the non-overlap 114 electrically connected to the OR gate circuit 150 to receive the control signal S C, and the non-overlap circuit 114 outputs the first control signal S a C1 and the second control signal S C2 to the first power switch 111 and the second power switch 112, wherein the non-overlapping circuit 114 makes the first control signal S C1 turn on the first power switch 111 longer than the first through the two inverter strings Two control signals S C2 turn off the time of the second power switch 112, so that the switching times of the first power switch 111 and the second power switch 112 are staggered to avoid the simultaneous operation of the first power switch 111 and the second power switch 112 the conducting a large input voltage V in the second current switch 111 and power switch 112 is grounded via the first power, the power loss caused problems burning occurs or the power switch.

請參閱第2及7圖,為了避免該第二功率開關112產生逆電流,該PWM/PFM雙模式充電系統100藉由該零電流偵測電路115偵測該節點V X的電壓,而能在該節點V X的電壓為零時關閉該第二功率開關112。在本實施例中,該零電流偵測電路115電性連接該第二功率開關112及該非交疊電路114,使得該非交疊電路114輸出之該第二控制訊號SC2經由該零電流偵測電路115傳送至該第二功率開關112,該零電流偵測電路115具有一正反器115a、一及閘115b及一比較器115c,該比較器115c電性連接該節點VX,並將節點VX的電壓與接地之零電位進行比較,該正反器115a之一重置端電性連接該比較器115c,該及閘115b電性連接該正反器115a及該非交疊電路114,其中,當該節點VX的電壓降至零時重置該正反器115a,使得該及閘115b輸出低電位而立即關閉該第二功率開關112,而避免該第二功率開關112產生逆電流。 Please refer to FIGS. 2 and 7, in order to avoid the reverse current generated by the second power switch 112, the PWM/PFM dual-mode charging system 100 detects the voltage of the node V X by the zero current detection circuit 115, and can When the voltage of the node V X is zero, the second power switch 112 is turned off. In the present embodiment, the zero current detection circuit 115 is electrically connected to the second power switch 112 and the non-overlap circuit 114, 114 so that the output of the non-overlap circuit of the second control signal S C2 of the zero current detection via The circuit 115 is transmitted to the second power switch 112. The zero current detection circuit 115 has a flip-flop 115a, a gate 115b and a comparator 115c. The comparator 115c is electrically connected to the node V X and connects the node The voltage of V X is compared with the zero potential of ground. One reset terminal of the flip-flop 115a is electrically connected to the comparator 115c, and the gate 115b is electrically connected to the flip-flop 115a and the non-overlapping circuit 114, wherein When the voltage of the node V X drops to zero, the flip-flop 115a is reset, so that the gate 115b outputs a low potential and immediately closes the second power switch 112, so as to prevent the second power switch 112 from generating a reverse current.

請參閱第2及8圖,為本實施例之一三角波及時脈產生器160的電路圖,其中該三角波及時脈產生器160具有一電容161、一電晶體串162及一邏輯電路163。該電晶體串162產生一偏壓電流對該電容161充電使該電容161的電壓上升,而當該電容161的電壓大於該邏輯電路163接收之一高電位位準VH時,該邏輯電路163之一第四比較器163a輸出低電位,使該邏輯電路163輸出之該時脈訊號Clk為高電位,此時該時脈訊號Clk會關閉該電晶體串162之一PMOS電晶體162a並開啟一NMOS電晶體162b,讓該電容161快速放電而電壓下降,當該電容161的電壓小於該邏輯電路163接收之一低電位位準VL時,該邏輯電路163之一第五比較器163b輸出低電位,使該邏輯電路163輸出之該時脈訊號Clk為低電位,開啟該電晶體串162之該PMOS電晶體162a並關閉該NMOS電晶體162b,而重新對該電容161充電並反覆上述之充電、放電步驟,而由該電容161輸出該漣波電壓Vramp,並由該邏輯電路163輸出該時脈訊號Clk。此外,該邏輯電路163還另接收一重置訊號R,以對該三角波及時脈產生器160進行重置。 Please refer to FIGS. 2 and 8 for a circuit diagram of a triangular wave and clock generator 160 according to this embodiment. The triangular wave and clock generator 160 has a capacitor 161, a transistor string 162 and a logic circuit 163. The transistor string 162 generates a bias current to charge the capacitor 161 so that the voltage of the capacitor 161 rises, and when the voltage of the capacitor 161 is greater than a high potential level VH received by the logic circuit 163, the logic circuit 163 A fourth comparator 163a outputs a low potential, so that the clock signal Clk output by the logic circuit 163 is a high potential. At this time, the clock signal Clk turns off one of the PMOS transistors 162a of the transistor string 162 and turns on The NMOS transistor 162b allows the capacitor 161 to quickly discharge and the voltage drops. When the voltage of the capacitor 161 is less than a low potential level V L received by the logic circuit 163, a fifth comparator 163b of the logic circuit 163 outputs low Potential, making the clock signal Clk output by the logic circuit 163 low, turning on the PMOS transistor 162a of the transistor string 162 and turning off the NMOS transistor 162b, and recharging the capacitor 161 and repeating the above charging In the discharging step, the ripple voltage V ramp is output by the capacitor 161, and the clock signal Clk is output by the logic circuit 163. In addition, the logic circuit 163 also receives a reset signal R to reset the triangle wave and the clock generator 160.

本發明藉由該定電流模式控制單元130及該定電壓模式控制單元 140達成PWM/PFM雙模式的充電控制而避免定電壓模式下發生低效率的問題,並僅透過單一個該或閘150即達成兩個模式之間的切換,可減少切換模式時的損耗,提高該PWM/PFM雙模式充電系統100整體的充電效率。 The present invention uses the constant current mode control unit 130 and the constant voltage mode control unit 140 Achieve PWM/PFM dual-mode charging control to avoid the problem of low efficiency in constant voltage mode, and achieve switching between the two modes by only one OR gate 150, which can reduce the loss when switching modes and improve The overall charging efficiency of the PWM/PFM dual-mode charging system 100.

本發明之保護範圍當視後附之申請專利範圍所界定者為準,任何熟知此項技藝者,在不脫離本發明之精神和範圍內所作之任何變化與修改,均屬於本發明之保護範圍。 The scope of protection of the present invention shall be subject to the scope defined in the attached patent application. Any changes and modifications made by those who are familiar with this skill without departing from the spirit and scope of the present invention shall fall within the scope of protection of the present invention. .

100‧‧‧PWM/PFM雙模式充電系統 100‧‧‧PWM/PFM dual-mode charging system

110‧‧‧轉換電路 110‧‧‧ Conversion circuit

111‧‧‧第一功率開關 111‧‧‧ First power switch

112‧‧‧第二功率開關 112‧‧‧The second power switch

113‧‧‧充放電單元 113‧‧‧Charge and discharge unit

113a‧‧‧電感 113a‧‧‧Inductance

113b‧‧‧電阻 113b‧‧‧Resistance

113c‧‧‧電容 113c‧‧‧Capacitance

114‧‧‧非交疊電路 114‧‧‧Non-overlapping circuit

115‧‧‧零電流偵測電路 115‧‧‧ Zero current detection circuit

115a‧‧‧正反器 115a‧‧‧Pros and cons

115b‧‧‧及閘 115b‧‧‧ and gate

115c‧‧‧比較器 115c‧‧‧Comparator

116‧‧‧高準位位移器 116‧‧‧High level shifter

120‧‧‧電流感測器 120‧‧‧current sensor

121‧‧‧負載 121‧‧‧Load

121a‧‧‧第一電晶體 121a‧‧‧First transistor

121b‧‧‧第二電晶體 121b‧‧‧Second transistor

122‧‧‧第一電流鏡 122‧‧‧First Current Mirror

122a‧‧‧第三電晶體 122a‧‧‧third transistor

122b‧‧‧第四電晶體 122b‧‧‧The fourth transistor

123‧‧‧第二電流鏡 123‧‧‧second current mirror

123a‧‧‧第五電晶體 123a‧‧‧Fifth transistor

123b‧‧‧第六電晶體 123b‧‧‧The sixth transistor

123c‧‧‧第七電晶體 123c‧‧‧The seventh transistor

130‧‧‧定電流模式控制單元 130‧‧‧ Constant current mode control unit

131‧‧‧第一比較器131‧‧‧ First comparator

132‧‧‧充放電選擇電路132‧‧‧ Charge and discharge selection circuit

132a‧‧‧第一開關132a‧‧‧First switch

132b‧‧‧第二開關132b‧‧‧Second switch

132c‧‧‧反相器132c‧‧‧Inverter

133‧‧‧充電電容133‧‧‧Charging capacitor

134‧‧‧第二比較器134‧‧‧ Second Comparator

135‧‧‧延遲器135‧‧‧delay

136‧‧‧低準位位移器136‧‧‧Low level shifter

140‧‧‧定電壓模式控制單元140‧‧‧ Constant voltage mode control unit

141‧‧‧第三比較器141‧‧‧The third comparator

142‧‧‧正反器142‧‧‧Pros and cons

143‧‧‧定電壓控制或閘143‧‧‧ Constant voltage control or gate

150‧‧‧或閘150‧‧‧ or gate

160‧‧‧三角波及時脈產生器160‧‧‧triangle wave and clock generator

161‧‧‧電容161‧‧‧Capacitance

162‧‧‧電晶體串162‧‧‧Transistor string

162a‧‧‧PMOS電晶體162a‧‧‧PMOS transistor

162b‧‧‧NMOS電晶體162b‧‧‧NMOS transistor

163‧‧‧邏輯電路163‧‧‧Logic circuit

163a‧‧‧第四比較器163a‧‧‧The fourth comparator

163b‧‧‧第五比較器163b‧‧‧Fifth comparator

VX、VY、VZ‧‧‧節點V X , V Y , V Z ‧‧‧ nodes

VBAT‧‧‧電池電壓V BAT ‧‧‧ Battery voltage

Vsense‧‧‧感測電壓V sense ‧‧‧ sense voltage

PWM‧‧‧脈衝寬度調變訊號PWM‧‧‧Pulse width modulation signal

PFM‧‧‧脈衝頻率調變訊號PFM‧‧‧Pulse frequency modulation signal

SC‧‧‧控制訊號S C ‧‧‧Control signal

SC1‧‧‧第一控制訊號S C1 ‧‧‧ First control signal

SC2‧‧‧第二控制訊號S C2 ‧‧‧ Second control signal

Vlimit‧‧‧限制電壓V limit ‧‧‧Limit voltage

comp1‧‧‧第一比較訊號comp1‧‧‧First comparison signal

Vfull‧‧‧滿額電壓V full ‧‧‧ full voltage

comp3‧‧‧第三比較訊號comp3‧‧‧The third comparison signal

Clk‧‧‧時脈訊號Clk‧‧‧clock signal

SFF‧‧‧正反器輸出訊號S FF ‧‧‧ flip-flop output signal

Vramp‧‧‧漣波電壓V ramp ‧‧‧ ripple voltage

VCC‧‧‧電容電壓V CC ‧‧‧ capacitor voltage

B‧‧‧電池模組B‧‧‧Battery module

L1‧‧‧第一電流迴路L1‧‧‧ First current loop

L2‧‧‧第二電流迴路L2‧‧‧second current loop

Sdelay‧‧‧延遲訊號S delay ‧‧‧ Delay signal

IC‧‧‧充電電流I C ‧‧‧ Charging current

IDISS‧‧‧放電電流I DISS ‧‧‧ Discharge current

Vin‧‧‧輸入電壓V in ‧‧‧ input voltage

R‧‧‧重置訊號R‧‧‧Reset signal

VH‧‧‧高電位位準V H ‧‧‧High potential level

VL‧‧‧低電位位準V L ‧‧‧ Low level

第1圖:依據本發明之一實施例,一種PWM/PFM雙模式充電系統的功能方塊圖。 Figure 1: A functional block diagram of a PWM/PFM dual-mode charging system according to an embodiment of the present invention.

第2圖:依據本發明之一實施例,該PWM/PFM雙模式充電系統的電路圖。 Figure 2: According to one embodiment of the present invention, the circuit diagram of the PWM/PFM dual-mode charging system.

第3圖:依據本發明之一實施例,一電流感測器的電路圖。 Figure 3: A circuit diagram of a current sensor according to an embodiment of the invention.

第4圖:依據本發明之一實施例,一定電流模式控制單元的電路圖。 Fig. 4: A circuit diagram of a constant current mode control unit according to an embodiment of the invention.

第5圖:依據本發明之一實施例,一定電壓模式控制單元的電路圖。 Fig. 5: A circuit diagram of a certain voltage mode control unit according to an embodiment of the present invention.

第6圖:依據本發明之一實施例,一非交疊電路的電路圖。 Fig. 6: A circuit diagram of a non-overlapping circuit according to an embodiment of the invention.

第7圖:依據本發明之一實施例,一零電流偵測電路的電路圖。 Fig. 7: A circuit diagram of a zero current detection circuit according to an embodiment of the invention.

第8圖:依據本發明之一實施例,一三角波及時脈產生器的電路圖。 Figure 8: A circuit diagram of a triangle wave and clock generator according to an embodiment of the invention.

100‧‧‧PWM/PFM雙模式充電系統 100‧‧‧PWM/PFM dual-mode charging system

110‧‧‧轉換電路 110‧‧‧ Conversion circuit

120‧‧‧電流感測器 120‧‧‧current sensor

130‧‧‧定電流模式控制單元 130‧‧‧ Constant current mode control unit

140‧‧‧定電壓模式控制單元 140‧‧‧ Constant voltage mode control unit

150‧‧‧或閘 150‧‧‧ or gate

Vin‧‧‧輸入電壓 V in ‧‧‧ input voltage

B‧‧‧電池模組 B‧‧‧Battery module

SC‧‧‧控制訊號 S C ‧‧‧Control signal

PWM‧‧‧脈衝寬度調變訊號 PWM‧‧‧Pulse width modulation signal

PFM‧‧‧脈衝頻率調變訊號 PFM‧‧‧Pulse frequency modulation signal

Vsense‧‧‧感測電壓 V sense ‧‧‧ sense voltage

Vlimit‧‧‧限制電壓 V limit ‧‧‧Limit voltage

Vramp‧‧‧漣波電壓 V ramp ‧‧‧ ripple voltage

Vfull‧‧‧滿額電壓 V full ‧‧‧ full voltage

VBAT‧‧‧電池電壓 V BAT ‧‧‧ Battery voltage

Clk‧‧‧時脈訊號 Clk‧‧‧clock signal

Claims (10)

一種PWM/PFM雙模式充電系統,其包含: 一轉換電路,具有一第一功率開關、一第二功率開關及一充放電單元,該充放電單元電性連接該第一功率開關及該第二功率開關,該轉換電路用以對一電池模組充電,其中該電池模組具有一電池電壓; 一電流感測器,耦接該充放電單元,該電流感測器用以感測該充放電單元之一電流的大小,且該電流感測器輸出一感測電壓; 一定電流模式控制單元,電性連接該電流感測器以接收該感測電壓,該定電流模式控制單元根據該電流感測器之該感測電壓、一限制電壓及一漣波電壓輸出一脈衝寬度調變訊號; 一定電壓模式控制單元,根據該電池電壓、一滿額電壓及一時脈訊號輸出一脈衝頻率調變訊號;以及 一或閘,電性連接該定電流模式控制單元及該定電壓模式控制單元以接收該脈衝寬度調變訊號及該脈衝頻率調變訊號,該或閘輸出一控制訊號以控制該轉換電路之該第一功率開關及該第二功率開關。 A PWM/PFM dual-mode charging system, including: A conversion circuit has a first power switch, a second power switch and a charge and discharge unit, the charge and discharge unit is electrically connected to the first power switch and the second power switch, the conversion circuit is used to Group charging, wherein the battery module has a battery voltage; A current sensor coupled to the charge-discharge unit, the current sensor is used to sense a current of the charge-discharge unit, and the current sensor outputs a sense voltage; A certain current mode control unit is electrically connected to the current sensor to receive the sensing voltage, and the constant current mode control unit outputs a pulse according to the sensing voltage of the current sensor, a limiting voltage and a ripple voltage Width modulation signal; The constant voltage mode control unit outputs a pulse frequency modulation signal according to the battery voltage, a full voltage and a clock signal; and An OR gate, electrically connected to the constant current mode control unit and the constant voltage mode control unit to receive the pulse width modulation signal and the pulse frequency modulation signal, the OR gate outputs a control signal to control the conversion circuit The first power switch and the second power switch. 如申請專利範圍第1項所述之PWM/PFM雙模式充電系統,其中該定電流模式控制單元具有一第一比較器、一充放電選擇電路、一充電電容及一第二比較器,該第一比較器接收該感測電壓及該限制電壓,且該第一比較器根據該感測電壓及該限制電壓輸出一第一比較訊號,該充放電選擇電路電性連接該第一比較器,該充電電容電性連接該充放電選擇電路,其中該充放電選擇電路根據該第一比較訊號選擇性地對該充電電容充電或放電,該第二比較器電性連接該充電電容,該第二比較器根據該充電電容之一電容電壓及該漣波電壓輸出該脈衝寬度調變訊號。The PWM/PFM dual-mode charging system as described in item 1 of the patent scope, wherein the constant current mode control unit has a first comparator, a charge and discharge selection circuit, a charging capacitor and a second comparator, the first A comparator receives the sense voltage and the limit voltage, and the first comparator outputs a first comparison signal according to the sense voltage and the limit voltage, and the charge-discharge selection circuit is electrically connected to the first comparator, the The charge capacitor is electrically connected to the charge-discharge selection circuit, wherein the charge-discharge selection circuit selectively charges or discharges the charge capacitor according to the first comparison signal, the second comparator is electrically connected to the charge capacitor, and the second comparison The device outputs the pulse width modulation signal according to a capacitor voltage of the charging capacitor and the ripple voltage. 如申請專利範圍第2項所述之PWM/PFM雙模式充電系統,其中該定電流模式控制單元具有一延遲器及一低準位位移器,該延遲器接收反相之該脈衝寬度調變訊號進行延遲,該低準位位移器電性連接該延遲器以接收該延遲器輸出之一延遲訊號進行準位位移,且該低準位位移器輸出該限制電壓。The PWM/PFM dual-mode charging system as described in item 2 of the patent application scope, wherein the constant current mode control unit has a delay and a low level shifter, the delay receives the inverted pulse width modulation signal For delay, the low-level shifter is electrically connected to the delayer to receive a delay signal output by the delayer for level shifting, and the low-level shifter outputs the limiting voltage. 如申請專利範圍第2項所述之PWM/PFM雙模式充電系統,其中該充放電選擇電路具有一第一開關及一第二開關,該第一開關接收該第一比較訊號並受該第一比較訊號控制,該第二開關接收反相之該第一比較訊號並受反相之該第一比較訊號控制,其中該第一開關導通時提供一充電電流對該充電電容充電,該第二開關導通時提供一放電電流對該充電電容放電。The PWM/PFM dual-mode charging system as described in item 2 of the patent scope, wherein the charge-discharge selection circuit has a first switch and a second switch, the first switch receives the first comparison signal and receives the first comparison signal Controlled by a comparison signal, the second switch receives the inverted first comparison signal and is controlled by the inverted first comparison signal, wherein the first switch provides a charging current to charge the charging capacitor when the first switch is turned on, and the second switch When turned on, a discharge current is provided to discharge the charging capacitor. 如申請專利範圍第4項所述之PWM/PFM雙模式充電系統,其中該充放電選擇電路具有一反相器,該第二開關經由該反相器耦接該第一比較器,以由該反相器接收反相之該第一比較訊號。The PWM/PFM dual-mode charging system as described in item 4 of the patent application scope, wherein the charge-discharge selection circuit has an inverter, and the second switch is coupled to the first comparator via the inverter, so that the The inverter receives the inverted first comparison signal. 如申請專利範圍第2項所述之PWM/PFM雙模式充電系統,其中該定電壓模式控制單元具有一第三比較器、一正反器及一定電壓控制或閘,該第三比較器接收該電池電壓及該滿額電壓,該第三比較器根據該電池電壓及該滿額電壓輸出一第三比較訊號,該正反器電性連接第三比較器,且該正反器根據該第三比較訊號及該時脈訊號輸出一正反器輸出訊號,該定電壓控制或閘電性連接該正反器,且該定電壓控制或閘根據該正反器輸出訊號及該時脈訊號輸出該脈衝頻率調變訊號。The PWM/PFM dual-mode charging system as described in item 2 of the patent application scope, wherein the constant voltage mode control unit has a third comparator, a flip-flop and a certain voltage control or gate, and the third comparator receives the The battery voltage and the full voltage, the third comparator outputs a third comparison signal according to the battery voltage and the full voltage, the flip-flop is electrically connected to the third comparator, and the flip-flop is based on the third comparison signal And the clock signal outputs a flip-flop output signal, the constant voltage control or gate is electrically connected to the flip-flop, and the constant voltage control or gate outputs the pulse frequency according to the flip-flop output signal and the clock signal Modulation signal. 如申請專利範圍第1項所述之PWM/PFM雙模式充電系統,其另包含一三角波及時脈產生器,該三角波及時脈產生器具有一電容、一電晶體串及一邏輯電路,該電晶體串電性連接該電容,且該電晶體串用以選擇性地對該電容充電或放電,使該電容產生該漣波電壓,該邏輯電路電性連接該電容,且該邏輯電路根據該電容之該漣波電壓、一高準位位準及一低準位位準輸出該時脈訊號,該時脈訊號用以控制該電晶體串對該電容充電或放電。The PWM/PFM dual-mode charging system as described in item 1 of the patent application scope further includes a triangular wave and clock generator with a capacitor, a transistor string and a logic circuit, the transistor string The capacitor is electrically connected, and the transistor string is used to selectively charge or discharge the capacitor, so that the capacitor generates the ripple voltage, the logic circuit is electrically connected to the capacitor, and the logic circuit is based on the capacitance of the capacitor The ripple voltage, a high level and a low level output the clock signal. The clock signal is used to control the transistor string to charge or discharge the capacitor. 如申請專利範圍第1項所述之PWM/PFM雙模式充電系統,其中該電流感測器具有一負載、一第一電流鏡、一第二電流鏡及一電流電壓轉換迴路,該負載具有一第一電晶體及一第二電晶體,該第一電流鏡具有一第三電晶體及一第四電晶體,該第二電流鏡具有一第五電晶體及一第六電晶體,該第一電晶體、該第三電晶體及該第五電晶體構成一第一電流迴路,該第二電晶體、該第四電晶體及該第六電晶體構成一第二電流迴路,該電流電壓轉換迴路電性連接該第二電晶體以由該第二電流迴路擷取一偵測電流並將其轉換為該感測電壓,其中該第一電晶體之寬度比為該第二電晶體之寬度比的K倍。The PWM/PFM dual-mode charging system as described in item 1 of the patent scope, wherein the current sensor has a load, a first current mirror, a second current mirror, and a current-voltage conversion loop, and the load has a first A transistor and a second transistor, the first current mirror has a third transistor and a fourth transistor, the second current mirror has a fifth transistor and a sixth transistor, the first transistor The crystal, the third transistor, and the fifth transistor constitute a first current loop, the second transistor, the fourth transistor, and the sixth transistor constitute a second current loop, and the current-voltage conversion loop electrically The second transistor is connected to the second current loop to capture a detection current and convert it into the sensing voltage, wherein the width ratio of the first transistor is the width ratio of the second transistor K Times. 如申請專利範圍第1項所述之PWM/PFM雙模式充電系統,其中該轉換電路具有一非交疊電路,該非交疊電路電性連接該或閘以接收該控制訊號,且該非交疊電路分別輸出一第一控制訊號及一第二控制訊號至該第一功率開關及該第二功率開關,其中該第一控制訊號及該第二控制訊號可讓該第一功率開關及該第二功率開關的切換時間交錯。The PWM/PFM dual-mode charging system as described in item 1 of the patent scope, wherein the conversion circuit has a non-overlapping circuit, the non-overlapping circuit is electrically connected to the OR gate to receive the control signal, and the non-overlapping circuit Respectively output a first control signal and a second control signal to the first power switch and the second power switch, wherein the first control signal and the second control signal enable the first power switch and the second power The switching times of the switches are staggered. 如申請專利範圍第9項所述之PWM/PFM雙模式充電系統,其中該轉換電路具有一零電流偵測電路,該零電流偵測電路電性連接該第二功率開關及該非交疊電路,其中該第二控制訊號經由該零電流偵測電路傳送至該第二功率開關。The PWM/PFM dual-mode charging system as described in item 9 of the patent scope, wherein the conversion circuit has a zero current detection circuit, the zero current detection circuit is electrically connected to the second power switch and the non-overlapping circuit, The second control signal is transmitted to the second power switch through the zero current detection circuit.
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