TWI681528B - Redistribution structure and manufacturing method thereof - Google Patents
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本發明是有關於半導體晶片封裝領域,且特別是有關於一種重佈線結構及其製造方法。The invention relates to the field of semiconductor wafer packaging, and in particular to a redistribution structure and a manufacturing method thereof.
為了使得電子產品能達到輕薄短小的設計,半導體封裝技術亦跟著日益進展,以發展出符合小體積、重量輕、高密度以及在市場上具有高競爭力等要求的產品。舉例來說,半導體封裝技術的態樣之一是在晶片上形成重佈線層(redistribution layer,RDL),而輸入/輸出(input/output,I/O)焊球可以藉由重佈線層與晶片電性連接。經由此種半導體封裝技術,晶片上的I/O焊墊可被重新佈置而覆蓋比晶片面積更大的區域。然而,目前隨著晶片尺寸的縮小以及I/O數量的增加,使得晶片上的重佈線層的配置變得越來越複雜,設置於重佈線層內導線之線寬及線距(line/space)也越來越細微,造成重佈線層中的傳輸訊號存有一定程度的損耗,且不能加以忽視。In order to enable electronic products to achieve light, thin, and short designs, semiconductor packaging technology has also evolved to develop products that meet the requirements of small size, light weight, high density, and high competitiveness in the market. For example, one of the aspects of semiconductor packaging technology is to form a redistribution layer (RDL) on the wafer, and input/output (I/O) solder balls can be used by the redistribution layer and the chip Electrical connection. With this semiconductor packaging technology, the I/O pads on the wafer can be rearranged to cover a larger area than the wafer area. However, at present, as the size of the wafer shrinks and the number of I/Os increases, the configuration of the redistribution layer on the wafer becomes more and more complicated, and the line width and line spacing of the wires disposed in the redistribution layer ) Is becoming more and more subtle, causing a certain degree of loss in the transmission signal in the rewiring layer, which cannot be ignored.
此外,隨著傳輸訊號的頻率上升,電流的分佈就會愈往導線的周緣表面集中,導致導線的中心部位幾乎沒有電流流過,進而使得電流輸送量減少,此現象稱為集膚效應(skin effect)。在集膚效應的影響下,高頻運作時容易造成訊號傳遞的訊號延遲與干擾,進而降低半導體封裝產品的效能。In addition, as the frequency of the transmitted signal rises, the distribution of current will be concentrated toward the peripheral surface of the wire, resulting in almost no current flowing through the center of the wire, thereby reducing the amount of current delivery. This phenomenon is called the skin effect (skin effect) effect). Under the influence of skin effect, high-frequency operation is likely to cause signal delay and interference of signal transmission, thereby reducing the performance of semiconductor packaging products.
承上所述,如何改善重佈線層中導線之設計,以減少集膚效應所造成線路訊號傳輸的損耗,是本領域技術人員亟需努力的目標。As mentioned above, how to improve the design of the wires in the redistribution layer to reduce the loss of line signal transmission caused by the skin effect is a goal urgently needed by those skilled in the art.
本發明提供一種重佈線結構及其製造方法,能夠提升線路表面的電導率,降低因集膚效應所導致訊號傳輸的損耗。The invention provides a rewiring structure and a manufacturing method thereof, which can increase the electrical conductivity of the surface of the circuit and reduce the loss of signal transmission due to the skin effect.
本發明提供一種重佈線結構,適於設置於晶片上並電性連接於晶片的接墊。重佈線結構包括介電層以及堆疊導電層。介電層配置於晶片上且具有暴露出接墊的凹槽。堆疊導電層配置於介電層上並覆蓋凹槽的側壁與連接側壁的底面,以電性連接晶片的接墊。堆疊導電層包括第一導電層、第二導電層以及第三導電層。第一導電層配置於介電層的凹槽中,第二導電層疊置於第一導電層上,第三導電層疊置於第二導電層上。第三導電層的電導率大於第二導電層的電導率,且第三導電層的電阻率介於約3x10 -8Ohm·m至1.5x10 -8Ohm·m之間。 The invention provides a redistribution structure, which is suitable for being arranged on a wafer and electrically connected to the pad of the wafer. The rewiring structure includes a dielectric layer and stacked conductive layers. The dielectric layer is disposed on the wafer and has a groove exposing the pad. The stacked conductive layer is disposed on the dielectric layer and covers the side walls of the groove and the bottom surface connecting the side walls to electrically connect the pads of the chip. The stacked conductive layer includes a first conductive layer, a second conductive layer, and a third conductive layer. The first conductive layer is disposed in the groove of the dielectric layer, the second conductive stack is placed on the first conductive layer, and the third conductive stack is placed on the second conductive layer. The conductivity of the third conductive layer is greater than the conductivity of the second conductive layer, and the resistivity of the third conductive layer is between about 3x10 -8 Ohm·m to 1.5x10 -8 Ohm·m.
本發明的一種重佈線結構的製造方法,重佈線結構適於設置於晶片上並電性連接於晶片的接墊。重佈線結構的製造方法至少包括以下步驟。形成介電層於晶片上,其中介電層具有暴露出接墊的凹槽,其中凹槽具有側壁與連接側壁的底面。形成堆疊導電層於介電層上並覆蓋凹槽的側壁與底面,以電性連接晶片的接墊,其步驟包括形成第一導電層於凹槽中、形成第二導電層於第一導電層上以及形成第三導電層於第二導電層上。第三導電層的電導率大於第二導電層的電導率,且第三導電層的電阻率介於約3x10 -8Ohm·m至1.5x10 -8Ohm·m之間。 According to the manufacturing method of the rewiring structure of the present invention, the rewiring structure is suitable for being disposed on the wafer and electrically connected to the pads of the wafer. The manufacturing method of the rewiring structure includes at least the following steps. A dielectric layer is formed on the wafer, wherein the dielectric layer has a groove exposing the pad, wherein the groove has a side wall and a bottom surface connecting the side wall. Forming a stacked conductive layer on the dielectric layer and covering the sidewalls and bottom surface of the groove to electrically connect the pads of the wafer, the steps of which include forming a first conductive layer in the groove and forming a second conductive layer on the first conductive layer Forming and forming a third conductive layer on the second conductive layer. The conductivity of the third conductive layer is greater than the conductivity of the second conductive layer, and the resistivity of the third conductive layer is between about 3x10 -8 Ohm·m to 1.5x10 -8 Ohm·m.
基於上述,本發明藉由在晶片接墊上配置堆疊導電層,且在堆疊導電層中的最外層配置電導率較高的導電材料,以提升重佈線結構中表面的電導率,降低因集膚效應所導致訊號傳輸的損耗。Based on the above, the present invention disposes stacked conductive layers on the wafer pads, and arranges the outermost layer of the stacked conductive layers with conductive materials with higher conductivity to improve the surface conductivity of the rewiring structure and reduce the skin effect The resulting loss of signal transmission.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.
圖1是依照本發明的一實施例的一種半導體結構俯視示意圖。半導體結構10包括晶片100以及配置於晶片100上的重佈線路結構200。晶片100包括配置於晶片100的主動面(如圖2A所示的100a)上的多個接墊110。在一些實施例中,晶片100可以包含多個電子元件(未繪示),例如電晶體、二極體、電容或電感等。這些電子元件例如是以層疊的方式設置於晶片100中。晶片100可以包括矽、砷化鎵或其他基板材料,並在基板材料上形成多個接墊110做為電性連接點,以提供導電線路進行電性連接,使訊號可以在這些電子元件之間傳輸。在一些實施例中,在晶片100的主動面上還可以配置保護層(如圖2A所示的120)以保護層晶片100的接墊110。舉例來說,重佈線路結構200可以配置在這些層疊的電子元件之間來電性連接上下層的電子元件。重佈線路結構200可以包括連接於接墊110上的部份以及走線部分。以下闡述關於重佈線路結構200中連接於接墊110上的部份的製造方法的細節。FIG. 1 is a schematic top view of a semiconductor structure according to an embodiment of the invention. The
圖2A至圖2G是依照本發明的一實施例的一種重佈線結構的製造方法的剖面示意圖。請參照圖2A,形成介電層210於晶片100上,藉以將設置於晶片100上的接墊110進行區隔,避免後續形成導電層時造成接墊110短路。介電層210可以形成在晶片100的保護層120上。保護層120的材料包括聚苯并噁唑(polybenzoxazole;PBO)、聚醯亞胺(polyimide;PI)、苯並環丁烯(benzocyclobutene;BCB)或其他適合的聚合材料。保護層120具有開口120a暴露出部分的接墊110。形成在保護層120上的介電層210可以具有頂表面210a以及對應於開口120a的凹槽212。介電層210的凹槽212可以是對應於保護層120的開口120a以暴露出接墊110。介電層210可以包括單層或多層的絕緣材料。在一些實施例中,當設置於晶片100上的接墊110數量眾多時,可以形成多層結構的介電層210將重佈線層200中的線路分層區隔。2A to 2G are schematic cross-sectional views of a method for manufacturing a redistribution structure according to an embodiment of the invention. Referring to FIG. 2A, a
在晶片100的主動面100a上依序形成第一介電材料214以及第二介電材料216時,可以利用旋轉塗佈(spin-on coating)、化學氣相沉積(chemical vapor deposition;CVD)或其他適合的製程。本實施例所繪示的介電層210的層數僅為說明之用,實際上介電層210的數量及厚度可依照設計需求而改變,並不以此為限。第一介電材料214以及第二介電材料216可以是相同或相似的材料,例如聚醯亞胺(polyimide)、聚苯噁唑(polybenzoxazole,PBO)、苯並環丁烯(benzocyclobutene,BCB)或其他適合的高分子材料。接著,可以利用微影製程(photolithography process)及/或蝕刻製程(etching process)或其他適合的製程,移除部分的介電層210,以圖案化介電層210,例如在接墊110上方形成介電層210的凹槽212,以暴露出底層的接墊110。When the first
凹槽212具有側壁212a與連接於側壁212a的底面212b,且凹槽212的底面212b暴露出接墊110。在一些實施例中,凹槽212可以是上寬下窄的錐狀,例如凹槽212的頂部尺寸D1(如直徑)大於底部尺寸D2(如直徑)。在一些實施例中,多層介電材料所構成的側壁212a可以是不切齊的。介電層的側壁212a可以是呈階梯狀,如圖2A所示。在介電層210是包括多層介電材料的其他實施例中,由多層介電材料所構成的側壁212a也可以是切齊的或者大致上地垂直於底面212b。The
請參照圖2B,在形成介電層210之後,可選擇性地將晶種層(seed layer)220形成於晶片100的接墊110上,並覆蓋介電層210的凹槽212的側壁212a與底面212b。可以藉由濺鍍製程(sputtering process)、物理氣相沉積製程(Physical Vapor Deposition,PVD)或其他適合的製程以形成晶種層220在介電層210上,並共形地(conformally)覆蓋凹槽212的側壁212a與底面212b以及介電層210的頂表面210a。晶種層220的材料例如包括銅、鈦、氮化鈦、鈦與銅的組合或其類似的導電材料,以電性連接晶片100的接墊110。Referring to FIG. 2B, after the
請參照圖2C,在形成晶種層220之後,可以形成光阻層PR於晶種層220上。光阻層PR可以具有開口OP。舉例來說,光阻層PR的開口OP可以對應於介電層210的凹槽212,以暴露出位於凹槽212的側壁212a與底面212b上的晶種層220。光阻層PR可以包括感光性的樹脂材料。舉例來說,可以將乾膜光阻(dry film photoresist)材料或液體光阻(liquid photoresist)材料形成在晶種層220上。接著,利用微影及/或蝕刻製程或其他適合的製程,以圖案化光阻材料來形成具有開口OP的光阻層PR。在一些實施例中,光阻層PR的開口尺寸D3(例如直徑)可以大於凹槽212頂部尺寸D1。2C, after forming the
請參照圖2D,以光阻層PR作為罩幕,形成堆疊導電層230在介電層210上以及對應於凹槽212的開口OP中,以覆蓋被光阻層PR的開口OP所暴露的晶種層220。舉例來說,依序堆疊地形成第一導電層232、第二導電層234以及第三導電層236於晶種層220上。可以藉由適當的沉積製程,例如電鍍法、無電鍍法或其類似的製法,將第一導電層232形成在介電層210的凹槽212中,以覆蓋於晶種層220上。接著,將第二導電層234形成在第一導電層232上。隨後,將第三導電層236形成在第二導電層234上。在一些實施例中,第一導電層232、第二導電層234以及第三導電層236可以是與晶種層220共形地形成。堆疊導電層230可以藉由調整沉積製程的時間來控制各個導電層的厚度,堆疊導電層230的厚度增加,可以降低高頻的電阻率。也可以依照最外層第三導電層236的電導率搭配產品實際操作的速度來決定導電層的厚度,然本發明的實施例並不限制導電層的厚度。2D, using the photoresist layer PR as a mask, a stacked
在一些實施例中,第一導電層232、第二導電層234以及第三導電層236可以分別包含不同的材料。舉例來說,位於最外層的第三導電層236的電阻率(electric resistivity)介於約3x10
-8Ohm·m至約1.5x10
-8Ohm·m之間。第三導電層236的電導率(electric conductivity)可以大於第二導電層234的電導率。在一些實施例中,在堆疊導電層230中,第一導電層232的電導率最大,其次為第三導電層236,而位於第一導電層232與第三導電層236之間的第二導電層234的電導率可以是三者之中最小。
In some embodiments, the first
舉例來說,第一導電層232可以是銅、銅合金或其他適合的導電材料。第二導電層234可以選用能夠增強第一導電層232與第三導電層236之間結合性的導電材料,例如鎳、鎳合金或其他適合的導電材料。第三導電層236可以是具有較第二導電層234的電導率更高的材料,例如是金或其他適合的導電材料。藉由在堆疊導電層230的最外層(例如第三導電層236)配置具有較高電導率的材料可以提升重佈線結構200中導電線路表面的電導率,藉此降低在高頻時因集膚效應所產生的高電阻率,同時避免訊號傳輸的損耗。再者,由於最外層的第三導電層236具有良好的電導率,其有利於後續製程,例如藉由打線製程以透過重佈線路結構200將晶片100與其他電子元件電性連接。For example, the first
在一些實施例中,在形成堆疊導電層230的製程完成後,堆疊導電層230可以不填滿光阻層PR的開口OP。也就是說,在開口OP內,堆疊導電層230中每一導電層的剖面形狀可以呈凹形。堆疊導電層230中具有溝槽230a。溝槽230a的深度可以視導電層沉積製程的參數與設計需求而定,本發明的實施例並不限制溝槽230a的深度。在其他實施例中,堆疊導電層230中的各導電層依序堆疊,在形成最外層的第三導電層236之後,第三導電層236頂表面大致上為平坦的表面,即第三導電層236的表面不存在溝槽230a。In some embodiments, after the process of forming the stacked
請參照圖2E及圖2F,在形成堆疊導電層230後,可以移除光阻層PR。例如透過剝離製程(stripping process)來移除光阻層PR。接著,在移除光阻層PR後,可以透過例如蝕刻製程或其他適合的製程來移除被光阻層PR覆蓋的晶種層220,以暴露出介電層210的頂表面210a,如圖2F所示。2E and 2F, after forming the stacked
請參照圖2G,在移除光阻層PR與被光阻層PR覆蓋的晶種層220之後,在介電層210的頂表面210a上形成絕緣層240,以包覆並保護堆疊導電層230。在堆疊導電層230的表面具有溝槽230a的實施例中,絕緣層240可以填滿溝槽230a。絕緣層240的材料例如包括聚醯亞胺(polyimide)、聚苯噁唑(polybenzoxazole,PBO)、苯並環丁烯(benzocyclobutene,BCB)或其他適合的絕緣材料。在形成絕緣層240之後,重佈線路結構200的製程大致上完成。2G, after removing the photoresist layer PR and the
圖3A是依照本發明的一實施例的一種重佈線結構的剖面示意圖(例如是沿著圖1中的A-A線的剖面示意圖),圖3B是依照圖3A的重佈線結構的俯視示意圖。本實施例的重佈線結構300與圖2F的結構相似,其中相同的元件以相同的標號表示,於此不再贅述。請參照圖3A與圖3B,本實施例的重佈線結構300與圖2F的結構的差異例如在於,可以進一步將位於介電層210的頂表面210a所在平面上的堆疊導電層230移除,以使堆疊導電層230的表面平整化。3A is a schematic cross-sectional view of a redistribution structure according to an embodiment of the present invention (for example, a schematic cross-sectional view along line A-A in FIG. 1), and FIG. 3B is a schematic top view of the redistribution structure according to FIG. 3A. The
舉例來說,在移除位於介電層210的頂表面210a所在平面上的堆疊導電層230之後,重佈線結構300中的介電層210的頂表面210a共面(coplanar)於晶種層220的頂表面220a以及堆疊導電層230的頂表面230b。堆疊導電層230的頂表面230b包括部分的第三導電層236、部分的第二導電層234以及部分的第一導電層232。最外圈的第一導電層232環繞第二導電層234,且第二導電層234環繞最內圈的第三導電層236。在一些實施例中,晶種層220可以圍繞堆疊導電層230,且溝槽230a例如是位於被最內圈的第三導電層236所環繞的區域中。須說明的是,圖3B中所繪示的堆疊導電層230與晶種層220的圖案僅為示例,可依據實際設計需求而進行調整,本發明的實施例並不以此為限。在其他實施例中,可以在堆疊導電層230的頂表面230b上形成如圖2G所示的絕緣層240,以保護堆疊導電層230。For example, after removing the stacked
綜上所述,本發明藉由在晶片接墊上配置堆疊導電層,且在堆疊導電層中的最外層配置電導率較高的導電材料,以提升重佈線結構中表面的電導率,以降低因集膚效應所導致訊號傳輸的損耗。再者,由於堆疊導電層的最外層具有良好的電導率,其有利於後續透過重佈線路結構將晶片與其他電子元件電性連接的製程。In summary, in the present invention, a stacked conductive layer is disposed on the wafer pad, and a conductive material with higher conductivity is disposed on the outermost layer of the stacked conductive layer to improve the surface conductivity of the rewiring structure to reduce the Loss of signal transmission caused by skin effect. Furthermore, since the outermost layer of the stacked conductive layers has good conductivity, it is advantageous for the subsequent process of electrically connecting the chip to other electronic components through the redistribution circuit structure.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.
10‧‧‧半導體結構10‧‧‧Semiconductor structure
100‧‧‧晶片100‧‧‧chip
100a‧‧‧主動面100a‧‧‧Active face
110‧‧‧接墊110‧‧‧Pad
120‧‧‧保護層120‧‧‧Protective layer
120a、OP‧‧‧開口120a, OP‧‧‧ opening
200、300‧‧‧重佈線路結構200, 300‧‧‧ heavy wiring structure
210‧‧‧介電層210‧‧‧dielectric layer
210a、220a、230b‧‧‧頂表面210a, 220a, 230b ‧‧‧ top surface
212‧‧‧凹槽212‧‧‧groove
212a‧‧‧側壁212a‧‧‧Side wall
212b‧‧‧底面212b‧‧‧Bottom
214‧‧‧第一介電材料214‧‧‧First dielectric material
216‧‧‧第二介電材料216‧‧‧Second dielectric material
220‧‧‧晶種層220‧‧‧Seed layer
230‧‧‧堆疊導電層230‧‧‧Stacked conductive layers
230a‧‧‧溝槽230a‧‧‧groove
232‧‧‧第一導電層232‧‧‧The first conductive layer
234‧‧‧第二導電層234‧‧‧Second conductive layer
236‧‧‧第三導電層236‧‧‧third conductive layer
240‧‧‧絕緣層240‧‧‧Insulation
D1‧‧‧頂部尺寸D1‧‧‧Top size
D2‧‧‧底部尺寸D2‧‧‧Bottom size
D3‧‧‧開口尺寸D3‧‧‧Opening size
PR‧‧‧光阻層PR‧‧‧Photoresist layer
圖1是依照本發明的一實施例的一種半導體結構俯視示意圖。 圖2A至圖2G是依照本發明的一實施例的一種重佈線結構的製造方法的剖面示意圖。 圖3A是依照本發明的一實施例的一種重佈線結構的剖面示意圖。 圖3B是依照圖3A的重佈線結構的俯視示意圖。FIG. 1 is a schematic top view of a semiconductor structure according to an embodiment of the invention. 2A to 2G are schematic cross-sectional views of a method for manufacturing a redistribution structure according to an embodiment of the invention. 3A is a schematic cross-sectional view of a redistribution structure according to an embodiment of the invention. 3B is a schematic top view of the rewiring structure according to FIG. 3A.
100‧‧‧晶片 100‧‧‧chip
110‧‧‧接墊 110‧‧‧Pad
120‧‧‧保護層 120‧‧‧Protective layer
200‧‧‧重佈線路結構 200‧‧‧ heavy wiring structure
210‧‧‧介電層 210‧‧‧dielectric layer
210a‧‧‧頂表面 210a‧‧‧Top surface
220‧‧‧晶種層 220‧‧‧Seed layer
230‧‧‧堆疊導電層 230‧‧‧Stacked conductive layers
232‧‧‧第一導電層 232‧‧‧The first conductive layer
234‧‧‧第二導電層 234‧‧‧Second conductive layer
236‧‧‧第三導電層 236‧‧‧third conductive layer
240‧‧‧絕緣層 240‧‧‧Insulation
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US20130244419A1 (en) * | 2008-09-29 | 2013-09-19 | Samsung Electronics Co., Ltd. | Inter connection structure including copper pad and pad barrier layer, semiconductor device and electronic apparatus including the same |
TW201426965A (en) * | 2012-12-28 | 2014-07-01 | Taiwan Semiconductor Mfg | Semiconductor die package and package on package device |
TW201639103A (en) * | 2015-04-16 | 2016-11-01 | 台灣積體電路製造股份有限公司 | Semiconductor devices and method of forming the same |
TW201804589A (en) * | 2016-07-29 | 2018-02-01 | 台灣積體電路製造股份有限公司 | Package structure and method of forming the same |
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US20130244419A1 (en) * | 2008-09-29 | 2013-09-19 | Samsung Electronics Co., Ltd. | Inter connection structure including copper pad and pad barrier layer, semiconductor device and electronic apparatus including the same |
TW201426965A (en) * | 2012-12-28 | 2014-07-01 | Taiwan Semiconductor Mfg | Semiconductor die package and package on package device |
TW201639103A (en) * | 2015-04-16 | 2016-11-01 | 台灣積體電路製造股份有限公司 | Semiconductor devices and method of forming the same |
TW201804589A (en) * | 2016-07-29 | 2018-02-01 | 台灣積體電路製造股份有限公司 | Package structure and method of forming the same |
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