TWI681528B - Redistribution structure and manufacturing method thereof - Google Patents

Abstract

A redistribution structure adapted to being disposed on a chip and electrically connected to a contact pad of the chip and including a dielectric layer and a stack conductive layer is provided. The dielectric layer disposed on the chip and has recess exposing the contact pad. The stack conductive layer disposed on the dielectric layer covers a side wall of the recess and a bottom surface connected to the side wall to electrically connect the contact pad. The stack conductive layer includes a first conductive layer disposed in the recess, a second conductive layer stacked on the first conductive layer and a third conductive layer stacked on the second conductive layer. The electric conductivity of the third conductive layer is greater than that of the second conductive layer. The electric resistivity of the third conductive layer ranges from about 3x10 ^-8Ohm·m to 1.5x10 ^-8Ohm·m. A manufacturing method of a redistribution structure is also provided.

Description

Rewiring structure and its manufacturing method

The invention relates to the field of semiconductor wafer packaging, and in particular to a redistribution structure and a manufacturing method thereof.

In order to enable electronic products to achieve light, thin, and short designs, semiconductor packaging technology has also evolved to develop products that meet the requirements of small size, light weight, high density, and high competitiveness in the market. For example, one of the aspects of semiconductor packaging technology is to form a redistribution layer (RDL) on the wafer, and input/output (I/O) solder balls can be used by the redistribution layer and the chip Electrical connection. With this semiconductor packaging technology, the I/O pads on the wafer can be rearranged to cover a larger area than the wafer area. However, at present, as the size of the wafer shrinks and the number of I/Os increases, the configuration of the redistribution layer on the wafer becomes more and more complicated, and the line width and line spacing of the wires disposed in the redistribution layer ) Is becoming more and more subtle, causing a certain degree of loss in the transmission signal in the rewiring layer, which cannot be ignored.

In addition, as the frequency of the transmitted signal rises, the distribution of current will be concentrated toward the peripheral surface of the wire, resulting in almost no current flowing through the center of the wire, thereby reducing the amount of current delivery. This phenomenon is called the skin effect (skin effect) effect). Under the influence of skin effect, high-frequency operation is likely to cause signal delay and interference of signal transmission, thereby reducing the performance of semiconductor packaging products.

As mentioned above, how to improve the design of the wires in the redistribution layer to reduce the loss of line signal transmission caused by the skin effect is a goal urgently needed by those skilled in the art.

The invention provides a rewiring structure and a manufacturing method thereof, which can increase the electrical conductivity of the surface of the circuit and reduce the loss of signal transmission due to the skin effect.

The invention provides a redistribution structure, which is suitable for being arranged on a wafer and electrically connected to the pad of the wafer. The rewiring structure includes a dielectric layer and stacked conductive layers. The dielectric layer is disposed on the wafer and has a groove exposing the pad. The stacked conductive layer is disposed on the dielectric layer and covers the side walls of the groove and the bottom surface connecting the side walls to electrically connect the pads of the chip. The stacked conductive layer includes a first conductive layer, a second conductive layer, and a third conductive layer. The first conductive layer is disposed in the groove of the dielectric layer, the second conductive stack is placed on the first conductive layer, and the third conductive stack is placed on the second conductive layer. The conductivity of the third conductive layer is greater than the conductivity of the second conductive layer, and the resistivity of the third conductive layer is between about 3x10 ^-8 Ohm·m to 1.5x10 ^-8 Ohm·m.

According to the manufacturing method of the rewiring structure of the present invention, the rewiring structure is suitable for being disposed on the wafer and electrically connected to the pads of the wafer. The manufacturing method of the rewiring structure includes at least the following steps. A dielectric layer is formed on the wafer, wherein the dielectric layer has a groove exposing the pad, wherein the groove has a side wall and a bottom surface connecting the side wall. Forming a stacked conductive layer on the dielectric layer and covering the sidewalls and bottom surface of the groove to electrically connect the pads of the wafer, the steps of which include forming a first conductive layer in the groove and forming a second conductive layer on the first conductive layer Forming and forming a third conductive layer on the second conductive layer. The conductivity of the third conductive layer is greater than the conductivity of the second conductive layer, and the resistivity of the third conductive layer is between about 3x10 ^-8 Ohm·m to 1.5x10 ^-8 Ohm·m.

Based on the above, the present invention disposes stacked conductive layers on the wafer pads, and arranges the outermost layer of the stacked conductive layers with conductive materials with higher conductivity to improve the surface conductivity of the rewiring structure and reduce the skin effect The resulting loss of signal transmission.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

FIG. 1 is a schematic top view of a semiconductor structure according to an embodiment of the invention. The semiconductor structure 10 includes a wafer 100 and a redistribution circuit structure 200 disposed on the wafer 100. The wafer 100 includes a plurality of pads 110 disposed on the active surface of the wafer 100 (100a shown in FIG. 2A). In some embodiments, the wafer 100 may include multiple electronic components (not shown), such as transistors, diodes, capacitors, or inductors. These electronic components are provided in the wafer 100 in a stacked manner, for example. The chip 100 may include silicon, gallium arsenide or other substrate materials, and a plurality of pads 110 are formed on the substrate material as electrical connection points to provide conductive lines for electrical connection so that signals can be between these electronic components transmission. In some embodiments, a protective layer (such as 120 shown in FIG. 2A) may be disposed on the active surface of the wafer 100 to protect the pad 110 of the wafer 100. For example, the redistribution circuit structure 200 can be configured between these stacked electronic components to electrically connect the upper and lower electronic components. The redistribution circuit structure 200 may include a portion connected to the pad 110 and a wiring portion. The details of the method for manufacturing the portion of the redistribution circuit structure 200 connected to the pad 110 are described below.

2A to 2G are schematic cross-sectional views of a method for manufacturing a redistribution structure according to an embodiment of the invention. Referring to FIG. 2A, a dielectric layer 210 is formed on the wafer 100, so as to separate the pads 110 disposed on the wafer 100 to avoid short circuiting of the pads 110 during the subsequent formation of the conductive layer. The dielectric layer 210 may be formed on the protective layer 120 of the wafer 100. The material of the protective layer 120 includes polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB) or other suitable polymer materials. The protective layer 120 has a pad 110 with an opening 120a exposing a portion. The dielectric layer 210 formed on the protective layer 120 may have a top surface 210a and a groove 212 corresponding to the opening 120a. The groove 212 of the dielectric layer 210 may be an opening 120 a corresponding to the protective layer 120 to expose the pad 110. The dielectric layer 210 may include a single layer or multiple layers of insulating material. In some embodiments, when there are a large number of pads 110 disposed on the wafer 100, a dielectric layer 210 with a multi-layer structure may be formed to separate the circuits in the redistribution layer 200 in layers.

When the first dielectric material 214 and the second dielectric material 216 are sequentially formed on the active surface 100a of the wafer 100, spin-on coating, chemical vapor deposition (CVD), or Other suitable processes. The number of dielectric layers 210 shown in this embodiment is for illustrative purposes only. In fact, the number and thickness of the dielectric layers 210 can be changed according to design requirements, and are not limited thereto. The first dielectric material 214 and the second dielectric material 216 may be the same or similar materials, such as polyimide, polybenzoxazole (PBO), and benzocyclobutene (BCB) Or other suitable polymer materials. Then, a part of the dielectric layer 210 may be removed by using a photolithography process and/or an etching process or other suitable processes to pattern the dielectric layer 210, for example, formed on the pad 110 The groove 212 of the dielectric layer 210 exposes the bottom pad 110.

The groove 212 has a side wall 212a and a bottom surface 212b connected to the side wall 212a, and the bottom surface 212b of the groove 212 exposes the pad 110. In some embodiments, the groove 212 may have a tapered shape with an upper width and a lower width. For example, the top dimension D1 (eg, diameter) of the groove 212 is greater than the bottom dimension D2 (eg, diameter). In some embodiments, the sidewalls 212a formed by multiple layers of dielectric materials may not be aligned. The sidewall 212a of the dielectric layer may be stepped, as shown in FIG. 2A. In other embodiments where the dielectric layer 210 includes multiple layers of dielectric materials, the side wall 212a composed of multiple layers of dielectric materials may also be cut or substantially perpendicular to the bottom surface 212b.

Referring to FIG. 2B, after the dielectric layer 210 is formed, a seed layer 220 may be selectively formed on the pad 110 of the wafer 100 and cover the sidewall 212a of the groove 212 of the dielectric layer 210 and底面212b. The seed layer 220 may be formed on the dielectric layer 210 by a sputtering process, a physical vapor deposition process (PVD), or other suitable processes, and conformally cover the recess The side wall 212a and the bottom surface 212b of the groove 212 and the top surface 210a of the dielectric layer 210. The material of the seed layer 220 includes, for example, copper, titanium, titanium nitride, a combination of titanium and copper, or a similar conductive material, and is electrically connected to the pad 110 of the wafer 100.

2C, after forming the seed layer 220, a photoresist layer PR may be formed on the seed layer 220. The photoresist layer PR may have an opening OP. For example, the opening OP of the photoresist layer PR may correspond to the groove 212 of the dielectric layer 210 to expose the seed layer 220 on the sidewall 212a and the bottom surface 212b of the groove 212. The photoresist layer PR may include a photosensitive resin material. For example, a dry film photoresist material or a liquid photoresist material may be formed on the seed layer 220. Next, a photoresist layer PR having an opening OP is formed by patterning the photoresist material using a lithography and/or etching process or other suitable processes. In some embodiments, the opening size D3 (eg, diameter) of the photoresist layer PR may be greater than the top size D1 of the groove 212.

2D, using the photoresist layer PR as a mask, a stacked conductive layer 230 is formed on the dielectric layer 210 and in the opening OP corresponding to the groove 212 to cover the crystal exposed by the opening OP of the photoresist layer PR Seed layer 220. For example, the first conductive layer 232, the second conductive layer 234, and the third conductive layer 236 are sequentially stacked on the seed layer 220. The first conductive layer 232 can be formed in the groove 212 of the dielectric layer 210 by an appropriate deposition process, such as an electroplating method, an electroless plating method, or the like, to cover the seed layer 220. Next, the second conductive layer 234 is formed on the first conductive layer 232. Subsequently, the third conductive layer 236 is formed on the second conductive layer 234. In some embodiments, the first conductive layer 232, the second conductive layer 234, and the third conductive layer 236 may be conformally formed with the seed layer 220. The stacked conductive layer 230 can control the thickness of each conductive layer by adjusting the time of the deposition process. As the thickness of the stacked conductive layer 230 increases, the high-frequency resistivity can be reduced. The thickness of the conductive layer may also be determined according to the conductivity of the outermost third conductive layer 236 and the actual operation speed of the product. However, the embodiment of the present invention does not limit the thickness of the conductive layer.

In some embodiments, the first conductive layer 232, the second conductive layer 234, and the third conductive layer 236 may include different materials, respectively. For example, the electrical resistivity of the third conductive layer 236 located at the outermost layer is between about 3x10 ^-8 Ohm·m to about 1.5x10 ^-8 Ohm·m. The electric conductivity of the third conductive layer 236 may be greater than the electric conductivity of the second conductive layer 234. In some embodiments, in the stacked conductive layer 230, the first conductive layer 232 has the highest conductivity, followed by the third conductive layer 236, and the second conductive layer between the first conductive layer 232 and the third conductive layer 236 The conductivity of the layer 234 may be the smallest of the three.

For example, the first conductive layer 232 may be copper, copper alloy, or other suitable conductive materials. The second conductive layer 234 may be a conductive material that can enhance the bonding between the first conductive layer 232 and the third conductive layer 236, such as nickel, nickel alloy, or other suitable conductive materials. The third conductive layer 236 may be a material having a higher electrical conductivity than the second conductive layer 234, such as gold or other suitable conductive materials. By configuring a material with a higher conductivity on the outermost layer of the stacked conductive layer 230 (for example, the third conductive layer 236), the conductivity of the surface of the conductive circuit in the redistribution structure 200 can be improved, thereby reducing The high resistivity produced by the effect, while avoiding the loss of signal transmission. Furthermore, since the outermost third conductive layer 236 has good electrical conductivity, it is advantageous for subsequent processes, for example, a wire bonding process to electrically connect the chip 100 to other electronic components through the redistribution circuit structure 200.

In some embodiments, after the process of forming the stacked conductive layer 230 is completed, the stacked conductive layer 230 may not fill the opening OP of the photoresist layer PR. That is, in the opening OP, the cross-sectional shape of each conductive layer in the stacked conductive layer 230 may be concave. The stacked conductive layer 230 has a trench 230a therein. The depth of the trench 230a may depend on the parameters and design requirements of the conductive layer deposition process. The embodiments of the present invention do not limit the depth of the trench 230a. In other embodiments, the conductive layers in the stacked conductive layer 230 are sequentially stacked. After the outermost third conductive layer 236 is formed, the top surface of the third conductive layer 236 is substantially flat, that is, the third conductive layer The groove 230a does not exist on the surface of 236.

2E and 2F, after forming the stacked conductive layer 230, the photoresist layer PR may be removed. For example, the photoresist layer PR is removed through a stripping process. Then, after removing the photoresist layer PR, the seed layer 220 covered by the photoresist layer PR can be removed through, for example, an etching process or other suitable processes to expose the top surface 210a of the dielectric layer 210, as shown in FIG. 2F.

2G, after removing the photoresist layer PR and the seed layer 220 covered by the photoresist layer PR, an insulating layer 240 is formed on the top surface 210a of the dielectric layer 210 to cover and protect the stacked conductive layer 230 . In the embodiment where the surface of the stacked conductive layer 230 has the trench 230a, the insulating layer 240 may fill the trench 230a. The material of the insulating layer 240 includes, for example, polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), or other suitable insulating materials. After forming the insulating layer 240, the process of redistributing the wiring structure 200 is substantially completed.

3A is a schematic cross-sectional view of a redistribution structure according to an embodiment of the present invention (for example, a schematic cross-sectional view along line A-A in FIG. 1), and FIG. 3B is a schematic top view of the redistribution structure according to FIG. 3A. The redistribution structure 300 of this embodiment is similar to the structure of FIG. 2F, wherein the same elements are denoted by the same reference numerals, and will not be repeated here. 3A and 3B, the difference between the rewiring structure 300 of this embodiment and the structure of FIG. 2F is, for example, that the stacked conductive layer 230 on the plane where the top surface 210a of the dielectric layer 210 is located can be further removed to The surface of the stacked conductive layer 230 is flattened.

For example, after removing the stacked conductive layer 230 on the plane where the top surface 210a of the dielectric layer 210 is located, the top surface 210a of the dielectric layer 210 in the redistribution structure 300 is coplanar with the seed layer 220 And the top surface 230b of the stacked conductive layer 230. The top surface 230b of the stacked conductive layer 230 includes a part of the third conductive layer 236, a part of the second conductive layer 234, and a part of the first conductive layer 232. The first conductive layer 232 of the outermost circle surrounds the second conductive layer 234, and the second conductive layer 234 surrounds the third conductive layer 236 of the innermost circle. In some embodiments, the seed layer 220 may surround the stacked conductive layer 230, and the trench 230a is, for example, located in an area surrounded by the innermost third conductive layer 236. It should be noted that the patterns of the stacked conductive layer 230 and the seed layer 220 shown in FIG. 3B are only examples, and can be adjusted according to actual design requirements. The embodiments of the present invention are not limited thereto. In other embodiments, an insulating layer 240 as shown in FIG. 2G may be formed on the top surface 230 b of the stacked conductive layer 230 to protect the stacked conductive layer 230.

In summary, in the present invention, a stacked conductive layer is disposed on the wafer pad, and a conductive material with higher conductivity is disposed on the outermost layer of the stacked conductive layer to improve the surface conductivity of the rewiring structure to reduce the Loss of signal transmission caused by skin effect. Furthermore, since the outermost layer of the stacked conductive layers has good conductivity, it is advantageous for the subsequent process of electrically connecting the chip to other electronic components through the redistribution circuit structure.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

10‧‧‧Semiconductor structure

100‧‧‧chip

100a‧‧‧Active face

110‧‧‧Pad

120‧‧‧Protective layer

120a, OP‧‧‧ opening

200, 300‧‧‧ heavy wiring structure

210‧‧‧dielectric layer

210a, 220a, 230b ‧‧‧ top surface

212‧‧‧groove

212a‧‧‧Side wall

212b‧‧‧Bottom

214‧‧‧First dielectric material

216‧‧‧Second dielectric material

220‧‧‧Seed layer

230‧‧‧Stacked conductive layers

230a‧‧‧groove

232‧‧‧The first conductive layer

234‧‧‧Second conductive layer

236‧‧‧third conductive layer

240‧‧‧Insulation

D1‧‧‧Top size

D2‧‧‧Bottom size

D3‧‧‧Opening size

PR‧‧‧Photoresist layer

FIG. 1 is a schematic top view of a semiconductor structure according to an embodiment of the invention. 2A to 2G are schematic cross-sectional views of a method for manufacturing a redistribution structure according to an embodiment of the invention. 3A is a schematic cross-sectional view of a redistribution structure according to an embodiment of the invention. 3B is a schematic top view of the rewiring structure according to FIG. 3A.

100‧‧‧chip

110‧‧‧Pad

120‧‧‧Protective layer

200‧‧‧ heavy wiring structure

210‧‧‧dielectric layer

210a‧‧‧Top surface

220‧‧‧Seed layer

230‧‧‧Stacked conductive layers

232‧‧‧The first conductive layer

234‧‧‧Second conductive layer

236‧‧‧third conductive layer

240‧‧‧Insulation

Claims (10)

A redistribution structure suitable for being placed on a wafer and electrically connected to pads of the wafer. The redistribution structure includes: a dielectric layer disposed on the wafer and having a recess exposing the pad A groove, wherein the groove has a side wall and a bottom surface connected to the side wall; and a stacked conductive layer is disposed on the dielectric layer and covers the side wall and the bottom surface of the groove to electrically connect the groove The pads of the wafer, the stacked conductive layer includes: a first conductive layer disposed in the groove of the dielectric layer; a second conductive layer stacked on the first conductive layer; And a third conductive layer stacked on the second conductive layer, wherein the conductivity of the third conductive layer is greater than that of the second conductive layer, and the resistivity of the third conductive layer is between About 3x10 ^-8 Ohm. m to 1.5x10 ^-8 Ohm. Between m, wherein the first conductive layer in the trace portion of the redistribution structure surrounds the second conductive layer and the second conductive layer surrounds the third conductive layer. The redistribution structure as described in item 1 of the patent application range, wherein the materials of the first conductive layer, the second conductive layer, and the third conductive layer are different from each other, and the The electrical conductivity is greater than the electrical conductivity of the third conductive layer. The redistribution structure as described in item 1 of the patent application scope further includes: a seed layer, which is arranged on the pad of the wafer and covers the groove The side wall and the bottom surface, and the seed layer is located between the pad and the stacked conductive layer, wherein the stacked conductive layer conformally covers the seed layer. The redistribution structure as described in item 1 of the patent application scope further includes: an insulating layer disposed on the dielectric layer and covering the stacked conductive layer, wherein a surface of the stacked conductive layer has grooves , And the insulating layer fills the trench. The redistribution structure according to item 1 of the patent application scope, wherein the top surface of the dielectric layer is coplanar with the top surface of the stacked conductive layer, and the top surface of the stacked conductive layer includes a part of The first conductive layer, the portion of the second conductive layer surrounded by the portion of the first conductive layer, and the portion of the third conductive layer surrounded by the portion of the second conductive layer. A method for manufacturing a rewiring structure suitable for being disposed on a wafer and electrically connected to pads of the wafer. The method for manufacturing a rewiring structure includes: forming a dielectric layer on the wafer , Wherein the dielectric layer has a groove exposing the pad, wherein the groove has a side wall and a bottom surface connecting the side wall; and forming a stacked conductive layer on the dielectric layer and covering the recess The side wall and the bottom surface of the groove to electrically connect the pad of the wafer include: forming a first conductive layer in the groove; forming a second conductive layer on the first conductive layer And forming a third conductive layer on the second conductive layer, wherein the conductivity of the third conductive layer is greater than that of the second conductive layer, and the resistivity of the third conductive layer is between about 3x10 ^-8 Ohm. m to 1.5x10 ^-8 Ohm. Between m, wherein the first conductive layer in the trace portion of the redistribution structure surrounds the second conductive layer and the second conductive layer surrounds the third conductive layer. The method for manufacturing a redistribution structure as described in item 6 of the patent application scope further includes: before forming the stacked conductive layer, forming a seed layer on the pad of the wafer and covering the groove The side wall and the bottom surface; and forming a photoresist layer on the seed layer, wherein the photoresist layer has an opening corresponding to the groove, and the opening of the photoresist layer exposes a portion of the The seed layer; and after forming the photoresist layer, forming the stacked conductive layer on the seed layer exposed by the opening of the photoresist layer to cover the portion of the seed layer The seed layer. The method for manufacturing a redistribution structure as described in item 7 of the patent application scope further includes: after forming the stacked conductive layer, removing the photoresist layer and the seed crystal under the photoresist layer Layer to expose the top surface of the dielectric layer. The method for manufacturing a rewiring structure as described in item 8 of the patent application range, wherein after forming the stacked conductive layer, the surface of the stacked conductive layer has There is a trench, and after removing the seed layer, the manufacturing method of the redistribution structure further includes: forming an insulating layer on the top surface of the dielectric layer to cover the stacked conductive layer, and The insulating layer fills the trench. The method for manufacturing a redistribution structure as described in item 8 of the scope of the patent application further includes: after forming the stacked conductive layer, removing the stacked conductive on the plane of the top surface of the dielectric layer A layer such that the top surface of the dielectric layer is coplanar with the top surface of the stacked conductive layer, wherein the top surface of the stacked conductive layer includes a portion of the first conductive layer, the Part of the second conductive layer surrounded by the first conductive layer, and part of the third conductive layer surrounded by the second conductive layer.

Images