TWI679740B - Lead frame array for carrying chips and led package structure with multiple chips - Google Patents

Abstract

A leadframe array for mounting a chip includes a plurality of leadframes, and a center of each leadframe forms a functional area; any four of the leadframes adjacent to each other form a cross-shaped cutting path; There are two pairs of connecting bridge groups between adjacent lead frames, which respectively cross the cutting path, and each two adjacent lead frames are connected by a connecting bridge group; each connecting bridge group has an inner connecting bridge, a An oblique connection bridge and an outer connection bridge; the four inner connection bridges together form a closed central hole area, and the central hole area is located at the center of four adjacent lead frames. The invention also provides a multi-chip light emitting diode packaging structure, which includes a lead frame cut from a lead frame array.

Description

Lead frame array for mounting chip and multi-chip light emitting diode packaging structure

The present invention relates to a lead frame array and a light emitting diode packaging structure having the lead frame, and particularly to a metal lead frame array for carrying a chip, which is packaged to form a light emitting diode packaging structure.

In the prior art, a lead frame for mounting a chip is usually manufactured from a metal sheet to form an array. After die bonding, wire bonding, and resin packaging, etc., it is cut through ( Saw) and cut the interconnected parts of the lead frame.

Each lead frame has metal pieces with different polarities. However, the metal pieces of different lead frames also need to be properly connected by connecting bridges to avoid islanding situations caused by the continuous sheet cutting process. In addition, due to the development of miniaturization of the lead frame, the connecting bridge connecting the metal sheet needs to be properly arranged, otherwise the burrs generated after cutting may cause the lead frame to short circuit.

Furthermore, the strength of the connection between the lead frames also needs to be considered to avoid the problem of lead frame deviation during the injection process of the resin-encapsulated plastic.

The technical problem to be solved by the present invention is to provide a lead frame array for mounting a chip, which can well connect the lead frames adjacent to each other, and solve the problem of continuous cutting process. Possible islanding problems, and increase the connection strength between lead frames to ensure the stability of plastic injection.

In order to solve the above technical problem, according to one aspect of the present invention, a lead frame array for mounting a chip is provided. The lead frame array includes a plurality of lead frames, and a center of each of the lead frames forms a functional area. A cross-shaped cutting track is formed between the lead frames; two pairs of connecting bridge groups are arranged between any four of the lead frames adjacent to each other, and each of the two adjacent The lead frames are each connected by one of the connecting bridge groups; each of the connecting bridge groups has an inner connecting bridge, an oblique connecting bridge, and an outer connecting bridge; four of the inner connecting bridges surround each other to form a joint. A closed central hole region, the central hole region being located at the center of four lead frames adjacent to each other; the four oblique connecting bridges are correspondingly located at the four inner connecting bridges and the four outer sides Connect between bridges.

In addition, the technical problem to be solved by the present invention is to provide a multi-chip light emitting diode packaging structure, solve the problem of islanding that may occur during the continuous cutting process, and ensure the stability of plastic injection to increase the yield of the product.

The invention has the following beneficial effects: the invention can solve the problem of islands that may occur in the process of continuous cutting, and increase the connection strength between lead frames to ensure the stability of plastic injection.

In order to further understand the technology, methods and effects adopted by the present invention to achieve the intended purpose, please refer to the following detailed description and drawings of the present invention. It is believed that the purpose, features and characteristics of the present invention can be deepened and specific It is understood, however, the drawings are provided for reference and description only, and are not intended to limit the present invention.

1R‧‧‧ Lead Frame Array

10‧‧‧ lead frame

12‧‧‧ carrier substrate

100‧‧‧light emitting diode package structure

120‧‧‧ divided passage

122‧‧‧Semi-blind depression

124‧‧‧Semi-blind ladder structure

19‧‧‧ Connected bridge set

190‧‧‧Central hole area

191‧‧‧ inside connection bridge

192‧‧‧ oblique connection bridge

193‧‧‧outside connecting bridge

191a, 192a, 193a‧‧‧Guide

S1, S2‧‧‧‧cut road

20‧‧‧ insulated package

22‧‧‧Reflection

222‧‧‧arc

223‧‧‧Covered extension structure

224‧‧‧ insulation partition

226‧‧‧peripheral extension

23‧‧‧Polarity identification structure

30‧‧‧Chip

40‧‧‧Transparent Filler

C‧‧‧ Center

F‧‧‧function area

T1, T2 ‧‧‧ intersection

R‧‧‧arc radius

W‧‧‧Side Length

θ‧‧‧ angle

FIG. 1 is a front plan view of a lead frame array for mounting a wafer according to the present invention.

2 is a bottom plan view of a lead frame array for mounting a wafer according to the present invention.

3 is a bottom perspective view of a lead frame array for mounting a wafer according to the present invention.

FIG. 4 is a perspective view of the lead frame array package of the present invention that has not been cut yet.

FIG. 5 is a perspective view of a multi-chip light emitting diode package structure according to the present invention.

FIG. 6 is a right side view of the multi-chip light emitting diode packaging structure of the present invention.

FIG. 7 is a top view of a multi-chip light emitting diode package structure according to the present invention.

FIG. 8 is a bottom view of the multi-chip light emitting diode package structure of the present invention.

FIG. 9 is a cross-sectional view of the present invention along the line IX-IX in FIG. 7.

Fig. 10 is a cross-sectional view of the present invention taken along the line X-X in Fig. 7.

Please refer to FIG. 1 and FIG. 2, which are a front plan view and a bottom plan view of a lead frame array for mounting a chip according to the present invention. The present invention provides a lead frame array 1R for mounting a chip, which includes a plurality of lead frames 10. In this embodiment, four lead frames 10 are used as an array unit to describe the detailed structure, but the number of lead frames 10 is not limited thereto. The structure of other positions of the lead frame 10 can be deduced by analogy.

A functional area F is formed in the center of each lead frame 10. The functional area F refers to an area that can be used to carry a chip and provide related functions, such as a light-emitting chip to provide a light-emitting function. A cross-shaped cutting track S1, S2 is formed between any four of the lead frames 10 adjacent to each other. The four lead frames 10 adjacent to each other are separated by the cutting lines S1 and S2 to form four quadrants.

As shown in FIG. 1, in this embodiment, there are a total of two pairs of connecting bridge groups 19 between any four adjacent lead frames 10. Two pairs of connecting bridge groups 19 traverse the cutting lanes S1 and S2, respectively. Each two adjacent lead frames 10 are connected by a connecting bridge group 19; each connecting bridge group 19 has an inner connecting bridge 191, an oblique connecting bridge 192, and an outer connecting bridge 193. The four inner connecting bridges 191 collectively form a closed central hole area 190. The central hole area 190 is located at the center of four adjacent lead frames 10 and is substantially square. As shown in FIG. 1 and FIG. 2, the central hole area 190 is approximately quadrangular, and the four connecting bridge groups 19 are respectively located above, below, left, and right of the central hole area 190. Corresponding positions of the four diagonally connected bridges 192 Between the four inner connecting bridges 191 and the four outer connecting bridges 193, each of the connecting bridge groups 19 is roughly arranged in an N or Z shape. The lead frame array 1R of the present invention effectively solves the problem of islands that may occur during the continuous cutting process by the two pairs of connecting bridge groups 19 and the closed central hole area 190 structure. The Z-shaped (or N-shaped) connecting bridge group 19 can effectively increase the strength of the connection between the lead frame arrays 1R to ensure the stability of plastic injection.

The arrangement of all the connecting bridge groups 19 in this embodiment is the same. The N-shape is the same as the Z-shape, only because of different viewing angles. As shown in FIG. 1, the connecting bridge groups 19 located on both sides of the central hole area 190 are substantially N-shaped, and the connecting bridge groups 19 located above and below the central hole area 190 are substantially Z-shaped.

Please refer to the connecting bridge group 19 in the lower part of FIG. 1. In this embodiment, the oblique connecting bridge 192 of each connecting bridge group 19 forms an acute angle θ with the inner connecting bridge 191 and the outer connecting bridge 193 respectively. Furthermore, the inner connecting bridges 191 and the outer connecting bridges 193 are substantially perpendicular to the cutting lanes S1 and S2, and may also be referred to as vertical connecting bridges. The inner connecting bridges 191 and the outer connecting bridges 193 located on opposite sides of the central hole area 190 are parallel to each other.

Each lead frame 10 of this embodiment has four carrier substrates 12, each of which is substantially square, and the four carrier substrates 12 form a cross-shaped separation channel 120. Each of the carrier substrates 12 is connected to one The inner connecting bridge 191, an oblique connecting bridge 192, and an outer connecting bridge 193. The two ends of each diagonal connection bridge 192 are respectively connected to the corners of the two carrier substrates 12, and the ends of the inner connection bridge 191 and the outer connection bridge 193 are substantially perpendicularly connected to the sides of the carrier substrate 12.

It is to be noted that, any one end of each oblique connection bridge 192 in this embodiment is not connected to any end of the inner connection bridge 191 and is not connected to any end of the outer connection bridge 193. Thereby, after the lead frame array 1R is cut along the cutting lines S1 and S2, the remaining diagonal connection bridges 192, the inner connection bridges 191, and the outer connection bridges 193 can be well separated. In this embodiment, the diagonal connection after cutting is preferred. The free ends of the bridge 192, the inner connecting bridge 191 and the outer connecting bridge 193 can be equally spaced apart. Through the above structural design, this embodiment is not affected by cutting tolerances.

In this embodiment, the lead frame 10 and the insulating packaging material can be better combined. The lead frame array 1R has a front surface (as shown in FIG. 1) and a bottom surface opposite to the front side (as shown in FIG. 2). Referring to FIG. 1, on the front side of each lead frame 10, a half blind recess 122 is formed on an outer corner of each carrier substrate 12. The "semi-blind" refers to removing a part of the thickness of the metal sheet in a half etching manner, and generally about half of the thickness is removed. Each carrier substrate 12 has four semi-blind recesses 122 distributed at four outer corners. The semi-blind recessed portion 122 of this embodiment extends from a corner of the front surface of the carrier substrate 12 toward the center of the carrier substrate 12. Each semi-blind recessed portion 122 occupies approximately a quarter of the area of the carrier substrate 12. More specifically, each semi-blind depression 122 extends into the functional area F of the lead frame 10.

Please refer to FIG. 2 and FIG. 3. In this embodiment, a half blind step structure 124 is formed along the partition channel 120 on the inner side of each carrier substrate 12 near the bottom surface. In the etching process of this embodiment, it is preferable to etch a part of the thickness of the connecting bridge group 19 together. In other words, the thicknesses of the inner connecting bridge 191, the diagonal connecting bridge 192, and the outer connecting bridge 193 are substantially equal to the semi-blind depression. The thickness of the portion 122. In other words, the thickness of all the connecting bridge groups 19 is smaller than the thickness of the carrier substrate 12. Therefore, the present embodiment can reduce the burrs generated during the cutting process of the connecting bridge group 19.

In this embodiment, after the die-bonding (which may include wire bonding if necessary), when packaging, the connection bridge group 19 on each side of the lead frame 10 has three connection bridges, which can increase the connection strength between the carrier substrates 12. After the lead frame array 1R of FIG. 1 is packaged, as shown in FIG. 4, it is cut along the cutting lines S1 and S2, as shown in FIG. 5, to form a light emitting diode package structure 100 with multiple chips, or light emitting diode for short.体 包装 结构 100。 Body packaging structure 100. The light-emitting diode package structure 100 includes a lead frame 10, an insulating package 20, a plurality of wafers 30, and a light-transmissive filler 40. The lead frame 10 includes four load-bearing substrates 12, each of which can be equipped with red, green, and blue light emitting chips, such as a red light wavelength of 620 to 630nm, green light wavelength 520 to 535nm, blue light wavelength 447 to 472nm. However, this embodiment is not limited to this, and can be designed according to requirements. The light emitting chips can be lighted independently or mixed together to form white light. Additionally, the bonding wires in FIG. 4 and FIG. 7 of the present invention are indicated by dashed lines, which means that wafers that do not require bonding, such as flip-chip wafers, can be omitted. The invention is not limited to horizontal wafers. The carrier substrate 12 is exposed on the bottom surface of the insulating package 20 as an electrode (as shown in FIG. 8). Each supporting substrate 12 extends three guide legs 191a, 192a, 193a outward along the same plane. More specifically, the two sides of each carrier substrate 12 extend three guide legs outward along the same plane, and these guide legs are the remaining inner connecting bridge 191, the oblique connecting bridge 192, and the outer connections remaining after cutting. The bridge 193 is exposed outside the insulating package 20. Two of the guide pins have the same polarity. A plurality of wafers 30 are placed on the front of the lead frame 10. The insulating package 20 covers a plurality of wafers 30 and the lead frame 10. The insulating package 20 may be an epoxy material, such as an epoxy molding compound (EMC) packaging material. The insulating package 20 has a concave reflecting portion 22. The light-transmitting filler 40 is filled in the reflecting portion 22.

Please refer to FIG. 5 and FIG. 6. In the multi-chip light emitting diode package structure 100 of this embodiment, the reflective portion 22 has two sets of opposite arc surfaces 222 connected to each other to form four intersections (T1, T2), of which four The arc radii R of the arc surfaces 222 are equal to each other and are not located at the same center. Each of the three intersections T1 forms a rounded corner, and one of the intersections T2 has a polarity identification structure 23. The polarity identification structure 23 may be, for example, a notched shape. However, the present invention is not limited to this, as long as the polarity identification structure 23 is different from the shape of the intersection T1. In this embodiment, the identification of the direction of the light emitting diode packaging structure 100 is provided by the difference in geometry at the intersection T2, which can solve the design bottleneck of the small-sized mold core.

Please refer to FIGS. 7 to 9. The reflective portion 22 of this embodiment has been specially designed. Specifically, the insulating package 20 is square. Assuming that the length of each side is W, the centers C of the four arc surfaces 222 are respectively Located between the four sides of the insulating package 20, the arc radius R is smaller than the side length W of the insulating package 20. The range of the arc radius R is The semi-blind recessed portion 122 is exposed, but not all of the semi-blind recessed portion 122 are exposed. The four intersections (T1, T2) are all located within the range of the semi-blind recessed portion 122, so that the insulating package 20 and the transparent filling material 40 is combined in the semi-blind recess 122 to provide a stronger bonding force with the lead frame 10. In other words, viewed from FIG. 5, the arc radius R is equal to the insulating package 20 minus a predetermined length, which is longer than half the length of the vertical connection bridge (inner connection bridge 191 or outer connection bridge 193) and smaller than the vertical connection bridge. The length is the sum of the width of the semi-blind depression 122. Taking a specific example of this embodiment, a side length W of the insulating package 20 is about 1.2 mm, and the predetermined length is 0.1 mm.

The arc surface 222 of the present invention is not limited to the circular arc described above, and may be an elliptical or parabolic arc surface. The advantages of the above-mentioned geometric shape of the reflecting portion 22 are better than those of the conventional circular reflecting portion or the square reflecting portion. The functional area formed by the reflective portion 22 in this embodiment is larger than the functional area formed by the circular reflective portion, or the solid crystal area is large. The reflection effect of the reflection portion 22 in this embodiment is better than that of the square reflection portion. The functional area formed by the reflective portion 22 in this embodiment has at most approximately 90% of the area of the light emitting diode packaging structure 100.

As shown in FIG. 7, FIG. 9, and FIG. 10, the insulating package 20 of this embodiment is filled with four semi-blind recesses 122. Wherein, the insulating package 20 is formed with cladding extension structures 223 at the four intersections (T1, T2) and the front surfaces of the four carrier substrates 12, and the cladding extension structures 223 extend downward from the inside of the upper half of the reflective portion 22 and Fill each semi-blind depression 122. In addition, as shown in FIG. 7, a cross-shaped partition channel 120 is formed between the four carrier substrates 12. Each of the supporting substrates 12 forms a half blind step structure 124 along the cross-shaped partitioning channel 120 on the inner side near the bottom surface, as shown in FIGS. 9 and 10. The insulating package 20 is filled between two adjacent semi-blind stepped structures 124 to form an insulating partition 224. From the perspective of the cross-section, the insulating partition 224 has a narrow upper half and a wide lower half. The advantage of such a structural design is that when the insulative package 20 is incorporated in the semi-blind stepped structure 124, the distance from the outside to the reflective portion 22 can be increased, in other words, the intrusion of external moisture into the light-emitting diode package structure 100 can be slowed down. Within unit. This can increase the reliability and life of the product. In addition, the insulating package 20 also extends from the outside of the reflective portion 22 to the periphery of the bottom surfaces of the four carrier substrates 12 to form a peripheral extension portion 226. The peripheral extension portion 226 is aligned with the bottom surface of the carrier substrate 12.

In summary, the features and functions of the present invention are that two pairs of Z-shaped (or N-shaped) connecting bridge groups are connected between any four adjacent lead frames 10 and jointly form a closed center hole. The region 190 can not only effectively solve the problem of islands that may occur during the continuous cutting process, but also increase the connection strength between the lead frames 10 to ensure the stability of plastic injection. The lead frame 10 is partially etched to form a semi-blind structure. The semi-blind recess 122 can increase the bonding strength of the strong insulating package 20 and the lead frame 10. The semi-blind step structure 124 formed along the cross-shaped partition channel 120 can reduce water. Gas invasion. The reflecting portion 22 is formed by connecting two sets of opposite curved surfaces 222 to each other, which can provide not only a larger functional area but also a good reflection effect. The corners of the reflecting portion 22 are used to identify the direction of the light emitting diode package structure 100 based on the difference in geometric shapes.

The above are only the preferred and feasible embodiments of the present invention, and any equivalent changes and modifications made in accordance with the scope of patent application of the present invention shall fall within the scope of the present invention.

Claims (12)

A lead frame array for carrying a chip includes: a plurality of lead frames, each of which has a functional area formed in the center; and a cross-shaped cutting track formed between any four of the lead frames adjacent to each other; There are two pairs of connecting bridge groups between any four of the lead frames adjacent to each other, which respectively traverse the cutting path, and each two adjacent lead frames are connected by one connecting bridge group; each Each of the connecting bridge groups has an inner connecting bridge, an oblique connecting bridge, and an outer connecting bridge. The four inner connecting bridges together form a closed central hole area. The central hole area is located at four The centers of the lead frames adjacent to each other; the four diagonal connection bridges are correspondingly located between the four inner connection bridges and the four outer connection bridges. The lead frame array for mounting a chip according to claim 1, wherein the inner connecting bridges and the outer connecting bridges are perpendicular to the cutting path, and the inner connecting bridges located on opposite sides of the central hole area These outer connecting bridges are parallel to each other. The lead frame array for mounting a wafer according to claim 1, wherein each of the lead frames has four carrier substrates, and a cross-shaped partition channel is formed between the four carrier substrates, wherein each of the carrier substrates Each is connected with one of the inner connecting bridge, one of the diagonal connecting bridge and one of the outer connecting bridge. The lead frame array for mounting a chip according to claim 3, wherein the thickness of the connecting bridge groups is smaller than the thickness of the carrier substrate. The lead frame array for mounting a chip according to claim 4, wherein each of the diagonal connection bridges connects two corners of the carrier substrate, and the ends of the inner connection bridges and the ends of the outer connection bridges are connected to each other. The side of the carrier substrate is described. The lead frame array for mounting a chip according to claim 3, wherein the lead frame array has a front surface and a bottom surface opposite to the front surface, and on each of the front surfaces of each of the lead frames, Each of the outer corners of the carrier substrate forms a half blind recess. The lead frame array for mounting a wafer according to claim 6, wherein each of the carrier substrates has a half-stepped structure along its inner side of the bottom surface along the partition channel. A multi-chip light-emitting diode packaging structure includes: a plurality of chips; a lead frame including four carrier substrates, and the sides of each of the carrier substrates extend outward along the same plane by three guide pins, and the wires The frame has a front surface and a bottom surface opposite to the front surface, wherein a plurality of the wafers are placed on the front surface of the lead frame; an insulating package covering a plurality of the wafers and the lead frame, so The insulating package has a concave reflecting portion; and a light-transmitting filling material is filled on the reflecting portion; wherein a plurality of the guide pins of the lead frame are exposed to the insulating package, wherein the Three of the lead pins are exposed on each side of the insulating package and two of the lead pins have the same polarity. The multi-chip light emitting diode package structure according to claim 8, wherein the reflecting portion has two groups of opposite arc surfaces connected to each other to form four intersections, wherein the arc radii of the four arc surfaces are equal to each other and do not Located at the same center. The multi-chip light emitting diode package structure according to claim 9, wherein each of the three intersections forms a rounded corner, and one of the intersections has a polarity identification structure. The multi-chip light emitting diode package structure according to claim 9, wherein the insulating package has a square shape, and the centers of the four arc surfaces are located in the middle of the four sides of the insulating package, respectively. The radius is smaller than the side length of the insulating package. The multi-chip light emitting diode package structure according to claim 9, wherein the insulating package is formed from the reflective portion to four of the intersections and four front faces of the carrier substrate Wrapped extension structure.