TWI679690B - Manufacturing method of semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device includes forming a stacked structure on a semiconductor substrate, and forming a plurality of first spacers on the stacked structure. Then, an intermediate layer is formed on the stacked structure to completely cover the first gap wall, and then a plurality of second gap walls are formed on the intermediate layer, wherein the second gap wall and the first gap wall have several overlapping portions, and The second gap wall serves as an etching mask, and the intermediate layer and the first gap wall are etched, leaving the first gap wall at the overlapping portion. After removing the second gap wall and the intermediate layer, a mask layer is formed on the stacked structure to cover the first gap wall of the overlapping portion, and the top of the first gap wall is exposed by etching back the mask layer, and then moved Remove the first gap wall. The mask layer is used as an etching mask to etch at least one layer in the stacked structure.

Description

Manufacturing method of semiconductor element

The present invention relates to a semiconductor element technology, and more particularly, to a method for manufacturing a semiconductor element.

In order to improve the degree of accumulation and miniaturization of semiconductor memory, in recent years, Dynamic Random Access Memory (DRAM) has been developed. The dynamic random access memory has a storage node for storing carriers, and a stitching process is usually used to manufacture the openings that subsequently form the storage nodes.

However, the opening formed by the above method is defined by two lithography processes. The mask layer used in the first lithography process is usually thin, and the margin in the etching process is too low, resulting in inaccurate subsequent processes. And even closed mouth. In addition, due to the current exposure accuracy, there may also be problems with the size, shape or position of the openings. All of the above defects will affect the subsequently formed components, resulting in poor component yield. Therefore, how to meet the needs of accumulation and miniaturization while improving process margins and preventing closed mouth has become a major challenge for researchers in this field.

The invention provides a method for manufacturing a semiconductor device, which can accurately produce an opening of a storage node without closing.

A method of manufacturing a semiconductor device according to the present invention includes the following steps. A semiconductor substrate is provided. A stacked structure is formed on the semiconductor substrate. The stacked structure is composed of a plurality of layers, and the two layers in contact with each other in the plurality of layers have different etching rates. A plurality of first partition walls are formed on the stacked structure. An intermediate layer is formed on the stacked structure to completely cover several first spacers. A plurality of second spacers are formed on the intermediate layer, and there are several overlapping portions between the plurality of second spacers and the plurality of first spacers. The second gap walls are used as the etching mask, the intermediate layer and the first gap walls are etched, and the first gap walls at the overlapping portions are left. Remove several second spacers and intermediate layers. A cover layer is formed on the stacked structure to cover a plurality of first gap walls of the overlapping portion. The mask layer is etched back to expose the tops of the plurality of first spacers. Remove several first spacers. The mask layer is used as an etching mask to etch at least one of a plurality of layers of the stacked structure.

In an embodiment of the present invention, the method for forming the first spacer comprises: forming a first material layer having a plurality of first linear patterns on a stacked structure; and conformally depositing a second material layer on a semiconductor substrate. To cover the top and sides of the first line patterns; isotropically etch the second material layer to form a plurality of first spacers on the sides of the first line patterns; and remove the first material layer .

In an embodiment of the present invention, the first material layer is a single-layer or multi-layer structure.

In an embodiment of the present invention, a material of the second material layer includes silicon oxide or silicon nitride.

According to an embodiment of the present invention, the isotropic etching method includes wet etching.

In an embodiment of the present invention, the method for forming the second spacer includes: forming a third material layer having a plurality of second linear patterns on the intermediate layer; and conformally depositing a fourth material layer on the semiconductor substrate. To cover the top and sides of the plurality of second linear patterns; to etch the fourth material layer isotropically to form a plurality of second spacers on the sides of the plurality of second linear patterns; and to remove the third material layer.

In an embodiment of the present invention, the third material layer is a single-layer or multi-layer structure.

In an embodiment of the invention, a material of the fourth material layer includes silicon oxide or silicon nitride.

According to an embodiment of the present invention, the isotropic etching method includes wet etching.

In an embodiment of the present invention, the intermediate layer is a single-layer or multi-layer structure.

In an embodiment of the present invention, a width of each of the second gap walls is greater than a width of each of the first gap walls.

Based on the above, in the method for manufacturing a semiconductor device according to the present invention, a plurality of first gap walls and a plurality of second gap walls having a plurality of overlapping portions are formed on a stacked structure, and a plurality of second gaps are formed. The wall is used as an etching mask, and several first gap walls are left in the overlapped portion. The remaining first gap walls define the positions where the openings are to be formed, so the margin of the etching process can be increased and the openings can be accurately controlled. Size, shape, or location, to avoid closed mouth, thereby improving the yield of semiconductor devices.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

The following describes some embodiments in detail with the accompanying drawings, but the embodiments provided are not intended to limit the scope covered by the present invention. In addition, the drawings are for illustration purposes only, and are not drawn to the original dimensions. In order to facilitate understanding, the same elements in the following description will be described with the same symbols. In addition, the terms "including", "including", "having", etc. used in the text are all open terms; that is, including but not limited to. Moreover, the directional terms mentioned in the text, such as "up" and "down", are only directions for referring to the drawings. Therefore, the directional terms used are used for illustration, not for limiting the present invention.

Hereinafter, a manufacturing process of a semiconductor device according to an embodiment of the present invention will be described, but the present invention is not limited to the following embodiments.

FIG. 1A is a schematic top view of a manufacturing process of a semiconductor device according to an embodiment; FIG. 1B is a schematic cross-sectional view taken along a line I-I in FIG. 1A.

Referring to FIG. 1A and FIG. 1B, a semiconductor substrate 100 is first provided. For example, the semiconductor substrate 100 is, for example, a silicon substrate or other suitable semiconductor substrates, but the present invention is not limited thereto. In this embodiment, a stacked structure 102 is formed on the semiconductor substrate 100, wherein the stacked structure 102 is composed of several film layers, and the two layers in contact with each other in the film layers preferably have different etching rates. For example, the material of the film layer in the stacked structure 102 may include, but is not limited to, boro-phospho-silicate-glass (BPSG), silicon oxide layer (SiO ₂ ), silicon nitride layer (SiN), Polycrystalline silicon layer, silicon oxide layer formed from tetraethoxysilane (TEOS) source, amorphous carbon layer (aC), anti-reflective coating (ARC), anti-reflective coating containing silicon, etc. In other words, the number of layers of the film layer included in the stacked structure 102 and the materials thereof may be based on the design requirements of the process, and a variety of different materials with high etching selection ratios are used, which is not limited in the present invention.

Next, a first material layer 106 having a plurality of first linear patterns 104 is formed on the stacked structure 102. For example, the first material layer 106 may be a single layer or a multilayer structure. In this embodiment, the first material layer 106 is exemplified as a multi-layer structure, wherein the material in contact with the stacked structure 102 may be a material layer capable of increasing adhesion, and the material not in contact with the stacked structure 102 may have high Etch another material layer with a selectivity ratio. In other embodiments, the first material layer 106 may also have a single-layer structure, but the present invention is not limited thereto.

2A and 2B are schematic top and cross-sectional views of the next step of FIGS. 1A and 1B.

Please refer to FIG. 2A and FIG. 2B. In order to form a plurality of first spacers on the stacked structure 102, a second material layer 108 may be conformally deposited on the semiconductor substrate 100 to cover the first linear pattern 104. Top 104a and side 104b. For example, the method for forming the second material layer 108 is, for example, a chemical vapor deposition method or an atomic layer coating method. The material of the second material layer 108 includes silicon oxide or silicon nitride, but the invention is not limited thereto.

3A and 3B are schematic top and cross-sectional views of the next step of FIGS. 2A and 2B.

Referring to FIGS. 3A and 3B, the second material layer 108 is etched isotropically to form a plurality of first spacers 110 on the side surfaces 104 b (see FIG. 2B) of the plurality of first line patterns 104. For example, the isotropic etching method is, for example, wet etching, but the present invention is not limited thereto. Next, the first material layer 106 is removed, leaving a first spacer 110 on the stacked structure 102. In this embodiment, the plurality of first spacers 110 are arranged on the stacked structure 102 in parallel at a certain distance, for example, but the invention is not limited thereto. In other embodiments, the first material layers 106 of the first linear pattern 104 in other arrangements may be formed according to the process design requirements, and the first spacers 110 in other arrangements may be formed by the above method, such as two The closer first gap walls 110 are a group, and the distance between each group is far, but the invention is not limited thereto.

4A and 4B are schematic top and cross-sectional views of the next step of FIGS. 3A and 3B.

Referring to FIGS. 4A and 4B, an intermediate layer 112 is formed on the stacked structure 102 to completely cover a plurality of first spacers 110. For example, the intermediate layer 112 has a single-layer or multi-layer structure. In this embodiment, the intermediate layer 112 is exemplified as a multi-layered structure. The material in contact with the first spacer 110 may be a material layer that can increase adhesion or high fluidity, and the material not in contact with the first spacer 110 may be The material of the first spacer 110 has another material layer with a high etching selectivity. In other embodiments, the intermediate layer 112 may also have a single-layer structure, but the invention is not limited thereto.

5A and 5B are schematic top and cross-sectional views of the next step of FIGS. 4A and 4B. For easy understanding, the position of the first partition wall 110 in FIG. 5B is indicated by a dotted line.

Referring to FIGS. 5A and 5B, a third material layer 116 having a plurality of second linear patterns 114 is formed on the intermediate layer 112. For example, the third material layer 116 has a single-layer or multi-layer structure. In this embodiment, the third material layer 116 is exemplified as a multi-layered structure, in which the material in contact with the intermediate layer 112 may be a material layer capable of increasing adhesion, and the material not in contact with the intermediate layer 112 may have a high material Etch another material layer with a selectivity ratio. In other embodiments, the third material layer 116 may also have a single-layer structure, but the invention is not limited thereto. On the other hand, the materials of the first material layer 106 and the third material layer 116 may be the same or different. The second linear patterns 114 are arranged on the intermediate layer 112 in parallel with each other, for example. The extending direction of the second linear pattern 114 intersects, for example, the extending direction of the first linear pattern 104. For example, there is an angle θ between the extending direction of the second linear pattern 114 and the extending direction of the first linear pattern 104, where the angle θ is, for example, -40 ° to 40 °, but the invention is not limited thereto.

6A and 6B are schematic top and cross-sectional views of the next step of FIGS. 5A and 5B.

Referring to FIGS. 6A and 6B, in order to form a plurality of second spacers on the intermediate layer 112, a fourth material layer 118 may be conformally deposited on the semiconductor substrate 100 to cover the tops of the plurality of second linear patterns 114. 114a and side 114b. For example, the method for forming the fourth material layer 118 is, for example, a chemical vapor deposition method or an atomic layer coating method. The material of the fourth material layer 118 includes silicon oxide or silicon nitride. The materials of the second material layer 108 and the fourth material layer 118 may be the same or different. In addition, the thicknesses of the second material layer 108 and the fourth material layer 118 may also be different. For example, the thickness of the fourth material layer 118 is greater than the thickness of the second material layer 108 to facilitate subsequent etching processes, but the present invention is not limited thereto. . The thickness of the fourth material layer 118 may also be the same as the thickness of the second material layer 108.

7A and 7B are schematic top and cross-sectional views of the next step of FIGS. 6A and 6B.

Referring to FIGS. 7A and 7B, the fourth material layer 118 is etched isotropically to form a plurality of second spacers 120 on the side surfaces 114 b (see FIG. 6B) of the plurality of second line patterns 114. For example, the isotropic etching method is, for example, wet etching, but the present invention is not limited thereto.

Then, the third material layer 116 is removed. Therefore, a plurality of second spacers 120 are formed on the intermediate layer 112. In the present embodiment, since the extending direction of the second linear pattern 114 and the extending direction of the first linear pattern 104 are at an angle θ, for example, the second gaps 120 and the first gaps 110 intersect with each other. The portion will have several overlapping portions 122. Accordingly, the required (storage node) opening position can be accurately controlled in subsequent processes.

8A and 8B are schematic top and cross-sectional views of the next step of FIGS. 7A and 7B.

Please refer to FIG. 8A and FIG. 8B, and use the second spacer wall 120 in FIG. 7A and FIG. 7B as an etching mask to etch the intermediate layer 112 and several first spacer walls 110 in FIG. The first gap wall 110 of the portion 122 is then removed from the second gap wall 120 and the intermediate layer 112.

In this embodiment, if the width W2 of each second gap wall 120 is greater than the width W1 of each first gap wall 110 (see FIG. 7B), the first gap wall 110 of the overlapping portion 122 can be effectively protected from Being etched, and ensuring that the size, shape or position of the first gap wall 110 of the overlapping portion 122 is not affected by the etching process, which can improve errors caused by lower exposure accuracy, thereby improving component yield and electrical performance .

9A and 9B are schematic top and cross-sectional views of the next step of FIGS. 8A and 8B.

Referring to FIGS. 9A and 9B, a cover layer 124 is formed on the stacked structure 102 to cover the first gap wall 110 of the overlapping portion 122. In this embodiment, the surface 124 a of the cover layer 124 is higher than the top portion 110 a of the first spacer 110, for example.

10A and 10B are schematic top and cross-sectional views of the next step of FIGS. 9A and 9B.

Referring to FIG. 10A and FIG. 10B, the cover curtain layer 124 is etched back to expose the top 110 a of the first spacer 110. In this embodiment, the surface 126 a of the mask layer 126 after the mask layer 124 is etched back is, for example, lower than the top portion 110 a of the first spacer 110. In another embodiment, the surface 126 a of the cover layer 126 is, for example, coplanar with the top portion 110 a of the first spacer 110. That is, as long as the top 110 a of the first spacer 110 can be exposed after the mask layer 124 is etched back.

11A and 11B are schematic top and cross-sectional views of the next step of FIGS. 10A and 10B.

Please refer to FIGS. 11A and 11B to remove the first spacer 110. Therefore, a plurality of openings 128 are formed in the mask layer 126 to expose the top surface 102 a of the stacked structure 102.

12A and 12B are schematic top and cross-sectional views of the next step of FIGS. 11A and 11B.

12A and 12B, at least one layer of the stacked structure 102 is etched by using the mask layer 126 as an etching mask. In other words, the stacked structure 102 forms a plurality of openings 130 near the top surface 102a. Through the above process, a plurality of openings 130 can be accurately manufactured without closing, so the problems encountered in forming existing processes such as DRAM storage node openings can be improved, and the yield of semiconductor devices can be improved.

In summary, according to the present invention, the method for manufacturing a semiconductor device includes forming a plurality of first spacers and a plurality of second spacers with a plurality of overlapping portions on each other on a stacked structure, and using a plurality of second spacers. The gap wall is used as an etching mask, leaving several overlapping gaps and other processes. Therefore, it can increase the margin of the etching process and accurately control the size, shape or position of the opening, and avoid the occurrence of closedness, thereby improving the semiconductor device. Yield.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

100‧‧‧ semiconductor substrate

102‧‧‧ stacked structure

102a‧‧‧Top

104‧‧‧The first linear pattern

104a, 114a, 110a‧‧‧Top

104b, 114b‧‧‧ side

106‧‧‧First material layer

108‧‧‧Second material layer

110‧‧‧ the first gap

112‧‧‧ middle layer

114‧‧‧ Second linear pattern

116‧‧‧third material layer

118‧‧‧ fourth material layer

120‧‧‧Second wall

122‧‧‧ Overlapping

124, 126‧‧‧ Overlay

124a, 126a‧‧‧ surface

128, 130‧‧‧ opening

W1, W2‧‧‧Width

θ‧‧‧ angle

FIGS. 1A, 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, and 12A illustrate a manufacturing process of a semiconductor device according to an embodiment of the present invention Top view schematic. 1B, 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, and 12B are respectively FIG. 1A, FIG. 2A, FIG. 3A, FIG. 4A, and FIG. 5A, FIG. 6A, FIG. 7A, FIG. 8A, FIG. 9A, FIG. 10A, FIG. 11A and FIG.

Claims (10)

A method for manufacturing a semiconductor element includes: providing a semiconductor substrate; forming a stacked structure on the semiconductor substrate, the stacked structure is composed of a plurality of layers, and two layers in contact with each other in the plurality of layers have different etchings Rate; forming a plurality of first spacers on the stacked structure, wherein a method of forming the plurality of first spacers includes: forming a first material layer having a plurality of first linear patterns on the stacked structure ; Conformally depositing a second material layer on the semiconductor substrate to cover the top and sides of the plurality of first linear patterns; isotropically etching the second material layer so that the plurality of first Forming the plurality of first spacers on the side of a linear pattern; and removing the first material layer; forming an intermediate layer on the stacked structure to completely cover the plurality of first spacers; A plurality of second gap walls are formed on the intermediate layer, wherein the plurality of second gap walls and the plurality of first gap walls have a plurality of overlapping portions; The gap wall serves as an etching mask, and the intermediate layer and the plurality of first gap walls are etched, and the plurality of first gap walls at the overlapping portion are left; the plurality of second gap walls and the The intermediate layer; forming a mask layer on the stacked structure to cover the plurality of first gap walls of the overlapping portion; and etching back the mask layer to expose the plurality of first gaps The top of the wall; removing the plurality of first gap walls; and using the mask layer as an etching mask to etch at least one of the plurality of layers of the stacked structure. The method for manufacturing a semiconductor device according to item 1 of the scope of patent application, wherein the first material layer has a single-layer or multi-layer structure. The method for manufacturing a semiconductor device according to item 1 of the scope of patent application, wherein a material of the second material layer includes silicon oxide or silicon nitride. The method for manufacturing a semiconductor device according to item 1 of the scope of patent application, wherein the method of isotropic etching includes wet etching. The method for manufacturing a semiconductor device according to item 1 of the scope of patent application, wherein the method of forming the plurality of second spacers includes: forming a third material layer having a plurality of second linear patterns on the intermediate layer; A fourth material layer is conformally deposited on the semiconductor substrate to cover the top and sides of the plurality of second line patterns; the fourth material layer is isotropically etched to the plurality of second line patterns The side of the pattern forms a plurality of second spacers; and the third material layer is removed. The method for manufacturing a semiconductor device according to item 5 of the scope of patent application, wherein the third material layer has a single-layer or multi-layer structure. The method for manufacturing a semiconductor device according to item 5 of the scope of patent application, wherein a material of the fourth material layer includes silicon oxide or silicon nitride. The method for manufacturing a semiconductor device according to item 5 of the scope of patent application, wherein the method of isotropic etching includes wet etching. The method for manufacturing a semiconductor device according to item 1 of the scope of patent application, wherein the intermediate layer has a single-layer or multi-layer structure. The method for manufacturing a semiconductor element according to item 1 of the scope of patent application, wherein a width of each of the second spacers is larger than a width of each of the first spacers.