TWI679628B - Display apparatus and method of driving light emitting block thereof - Google Patents

Abstract

A display device and a driving method of a light emitting block thereof. The display device includes a plurality of light-emitting blocks. Each light-emitting block includes a latch circuit, a selection circuit, a voltage output circuit, a data transistor, a driving transistor, a capacitor, and a light-emitting diode. The latch circuit latches a plurality of digital control signals corresponding to the data voltage. The selection circuit provides a plurality of selection signals according to the latched digital control signals. The voltage output circuit provides a driving voltage according to a selection signal, in which the voltage of the reaction data decreases and the driving voltage also decreases. The data transistor receives data voltage and displacement signals. The driving transistor is coupled between the data transistor, the driving voltage and the light emitting diode. The capacitor is coupled between the control terminal and the second terminal of the driving transistor.

Description

Display device and driving method of light emitting block thereof

The present invention relates to a display device, and more particularly, to a display device and a method for driving a light emitting block thereof.

In display technology, light-emitting diodes are continuously miniaturized to provide more applications. In the display device, the light emitting diode may be applied as a backlight module providing a backlight, or may be directly applied as a display interface for displaying an image. However, in order to make the backlight module or display interface more versatile, reducing the power consumption of the backlight module or display interface is an important issue.

The invention provides a display device and a driving method of a light emitting block thereof, which can save power consumption, but still maintain a desired light emitting brightness of a light emitting diode.

The display device of the present invention includes a plurality of light-emitting blocks. Each light-emitting block includes a latch circuit, a selection circuit, a voltage output circuit, a data transistor, a driving transistor, a capacitor, and a light-emitting diode. The latch circuit receives a plurality of data corresponding to the data voltage. Digital control signals and displacement signals, and latch these digital control signals according to the displacement signals. The selection circuit is coupled to the latch circuit to receive the latched digital control signals and provide a plurality of selection signals. The selection circuit enables one of the selection signals according to the latched digital control signals. The voltage output circuit is coupled to the selection circuit to receive these selection signals and provide a driving voltage, wherein the driving voltage is controlled by these selection signals, and the driving voltage also decreases as the data voltage decreases. The data transistor has a first terminal for receiving a data voltage, a control terminal for receiving a displacement signal, and a second terminal. The driving transistor has a first terminal receiving a driving voltage, a control terminal coupled to a second terminal of the data transistor, and a second terminal. The capacitor is coupled between the control terminal of the driving transistor and the second terminal of the driving transistor. The light emitting diode is coupled between the second terminal of the driving transistor and the system low voltage.

The driving method of the present invention is used to drive a plurality of light-emitting blocks of a display device. Each of these light-emitting blocks has a light-emitting diode, and the driving method includes the following steps. The data voltage is received to determine the light emitting current flowing through the light emitting diode by the driving voltage. A plurality of digital control signals corresponding to the data voltage are received to adjust the driving voltage. The driving voltage is also reflected as the data voltage decreases.

Based on the above, the display device and the driving method of the light-emitting block of the embodiment of the present invention receive a plurality of digital control signals corresponding to the data voltage to adjust the driving voltage, and the driving voltage also decreases as the data voltage decreases . Therefore, when the light-emitting gray-scale value of the light-emitting block is lower, more power can be saved, but the light-emitting brightness of the light-emitting diode is still maintained.

In order to make the above features and advantages of the present invention more comprehensible, the following enumerated The embodiments will be described in detail with the accompanying drawings.

10, 20‧‧‧ display device

11‧‧‧Displacement control circuit

13‧‧‧ data supply circuit

15‧‧‧light-emitting block

21‧‧‧Display Panel

100, 15‧‧‧ light-emitting blocks

110‧‧‧ latch circuit

111, 113, 115‧‧‧

120‧‧‧Selection circuit

130‧‧‧Voltage output circuit

210‧‧‧Displacement register

220‧‧‧input register

230‧‧‧Data latch

240‧‧‧ quasi-displacement device

250‧‧‧ Digital Analog Converter

260‧‧‧Buffer

AND1‧‧‧First and Gate

AND2‧‧‧Second and Gate

C1‧‧‧capacitor

CLK‧‧‧clock signal

DLX‧‧‧Display Information

Id‧‧‧ Luminous current

INT‧‧‧First inverter

LED1‧‧‧light-emitting diode

LEN‧‧‧ Latch enable signal

LHS‧‧‧Horizontal Signal Cable

M0 ~ M7‧‧‧‧Switching transistor

NOR1‧‧‧First reverse OR gate

NOR2‧‧‧Second reverse OR gate

PX‧‧‧LCD Pixel

~

‧‧‧信號 S0 ~ S2

~

‧‧‧signal

S111 ~ S116, S120, S130‧‧‧curve

Sdit, Sdit0 ~ Sdit2‧‧‧ Digital control signal

SET‧‧‧Set signal

SR_1 ~ SR_3, SR_n‧‧‧shift signal

STR‧‧‧Trigger signal

TD1‧‧‧Data Transistor

TD2‧‧‧Drive Transistor

TG11 ~ TG14, TG21 ~ TG28, TG31 ~ TG38, TG41 ~ TG48‧‧‧Transmission gate

VD1‧‧‧Drive voltage

VDATA‧‧‧Data voltage

VDD‧‧‧System high voltage

VDD_max‧‧‧Maximum driving voltage level

VDD0 ~ VDD7‧‧‧Drive level

VDX‧‧‧ Analog Drive Voltage

VG1, VS1‧‧‧‧Voltage

VLS‧‧‧Vertical Signal Cable

Vref‧‧‧Reference voltage

VSS‧‧‧System Low Voltage

VTm‧‧‧ Changed threshold voltage

XDB‧‧‧ Blue display data

XDG‧‧‧ green display data

XDR‧‧‧red display data

Y0 ~ Y7‧‧‧Selection signal

S710, S720‧‧‧ steps

FIG. 1A is a system schematic diagram of a light-emitting block according to an embodiment of the present invention.

FIG. 1B is a characteristic diagram of a driving transistor of a light-emitting block according to an embodiment of the present invention.

FIG. 2 is a schematic circuit diagram of a light-emitting block according to an embodiment of the present invention.

FIG. 3A is a simulation diagram of a driving voltage changing with a data voltage according to an embodiment of the present invention.

FIG. 3B is a simulation diagram of the driving voltage being a fixed voltage according to an embodiment of the present invention.

FIG. 4 is a system diagram of a display device according to an embodiment of the invention.

FIG. 5 is a system schematic diagram of a data providing circuit according to an embodiment of the present invention.

FIG. 6 is a system diagram of a display device according to another embodiment of the present invention.

FIG. 7 is a flowchart of a driving method of a light emitting block of a display device according to an embodiment of the invention.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that, such as those defined in commonly used dictionaries Terms should be construed to have meanings consistent with their meanings in the context of the related art and the present invention, and will not be construed as idealized or overly formal meanings unless explicitly defined as such herein.

It should be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, and / or sections, and / Or in part should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element," "component," "region," "layer," or "portion" discussed below may be referred to as a second element, component, region, layer, or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms, including "at least one", unless the content clearly indicates otherwise. "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It should also be understood that when used in this specification, the terms "including" and / or "including" designate the stated features, regions, wholes, steps, operations, presence of elements and / or components, but do not exclude one or more The presence or addition of other features, areas as a whole, steps, operations, elements, components, and / or combinations thereof.

FIG. 1A is a system schematic diagram of a light-emitting block according to an embodiment of the present invention. Please refer to FIG. 1A. In this embodiment, the light-emitting block 100 is a light-emitting circuit configured in a display device and can be used as a pixel of a display panel or a backlight module. The light-emitting block 100 includes at least a latch circuit 110, a selection circuit 120, and a voltage output circuit 130. The data transistor TD1, the driving transistor TD2, the capacitor C1, and the light-emitting diode LED1. The light-emitting diode LED1 is, for example, a sub-millimeter light-emitting diode, but the embodiment of the present invention is not limited thereto.

The latch circuit 110 receives a plurality of digital control signals Sdit and displacement signals SR_n corresponding to the data voltage VDATA, and latches the digital control signals Sdit according to the displacement signal SR_n, where n is a positive integer. The selection circuit 120 is coupled to the latch circuit 110 to receive the latched digital control signals (such as signals S0 ~ S2) and provide multiple selection signals (such as Y0 ~ Y2). The selection circuit 120 is based on the latched digital signals. Control signals (such as signals S0 ~ S2) enable one of these selection signals (such as signals Y0 ~ Y2).

The voltage output circuit 130 is coupled to the selection circuit 120 to receive these selection signals (such as Y0 ~ Y2) and provide a driving voltage VD1. The data transistor TD1 has a first terminal receiving a data voltage VDTAT, a control terminal receiving a displacement signal SR_n, and a second terminal. The driving transistor TD2 has a first terminal receiving the driving voltage VD1, a control terminal coupled to the second terminal of the data transistor TD1, and a second terminal. The capacitor C1 is coupled between the control terminal of the driving transistor TD2 and the second terminal of the driving transistor TD2. The light emitting diode LED1 is coupled between the second terminal of the driving transistor TD2 and the system low voltage VSS.

In this embodiment, the driving voltage VD1 is controlled by a selection signal (such as Y0 ~ Y2) to determine its voltage level, that is, the data voltage VDATA is reduced, and the driving voltage VD1 is also decreased as it is. In other words, when the light-emitting current Id flowing through the light-emitting diode LED1 remains unchanged, the lower the data voltage VDATA (visible The lower the corresponding grayscale value), the lower the driving voltage VD1; the higher the data voltage VDATA (which can be considered as the corresponding higher grayscale value), the higher the driving voltage VD1.

Since the light-emitting current Id is unchanged, the light-emitting brightness of the light-emitting diode LED1 is not affected, but as the driving voltage VD1 decreases, the overall power consumption of the light-emitting block 100 will decrease.

FIG. 1B is a characteristic diagram of a driving transistor of a light-emitting block according to an embodiment of the present invention. Please refer to FIG. 1A and FIG. 1B, where the curve S120 separates the linear region and the saturation region of the driving transistor TD2, and the driving transistor TD2 mainly operates in the saturation region. Curves S111 to S116 show the curves of the data voltage VDATA (ie, each gray level value) as a function of the driving voltage VD1. The curve S111 corresponds to a gray level value of 128, and the curve S116 corresponds to a gray level value of 255, for example. Generally speaking, the driving voltage VD1 is a fixed value, and in order to be applicable to all grayscale values (such as the curves S111 to S116), the driving voltage VD1 is set to the maximum driving voltage level VDD_max.

In this embodiment, the response data voltage VDATA (ie, the gray level value) decreases, and the driving voltage VD1 also decreases to a minimum driving voltage level that keeps the light emitting current Id flowing through the light emitting diode LED1 constant. Bit (that is, the intersecting point of the corresponding grayscale value curves S112-S116 and curve S120). That is, when the data voltage VDATA (ie, the gray level value) is not the maximum value, the driving voltage VD1 can be set to the curve S120 and the maximum driving voltage level VDD_max with the corresponding gray level value curve (such as S112 ~ S116) The higher the gray level value, the higher the driving voltage VD1 may be.

Further, as shown by the curve S130, in order to avoid the driving voltage VD1 jumping to the left of the curve S120 due to the characteristics of the driving transistor TD2, that is, the light emitting current Id flowing through the light emitting diode LED1 is excessively reduced, which affects the light emission. The luminous brightness of the diode LED1 can reflect the decrease of the data voltage VDATA, and the driving voltage VD1 also decreases to the minimum driving voltage level (that is, the intersection point of the corresponding grayscale value curves S112 ~ S116 and curve S120) plus Incremental voltage ΔV (equivalent to shifting curve S120 to the right by incremental voltage ΔV).

At this time, since the driving voltage VD1 is set to the maximum driving voltage level VDD_max at most, in addition to the maximum gray level value, the driving voltage VD1 of some gray levels is set to the maximum driving voltage level VDD_max, and other gray levels The driving voltage VD1 is set to be less than the maximum driving voltage level VDD_max. For example, when the data voltage VDATA is between the change threshold voltage VTm and the maximum grayscale voltage (that is, the corresponding curve S111), the driving voltage VD1 is maintained at the maximum driving voltage level VDD_max. And, the larger the incremental voltage ΔV, the lower the change threshold voltage VTm.

FIG. 2 is a schematic circuit diagram of a light-emitting block according to an embodiment of the present invention. Please refer to FIG. 1A and FIG. 2. In this embodiment, the number of digital control signals Sdit is 3 as an example (taking digital control signals Sdit0 to Sdit2 as an example), that is, the digital control signal Sdit is a 3-bit signal, where The number of the digital control signals Sdit corresponds to the number of bits of the grayscale value range of the data voltage VDATA, that is, the number of bits of the digital control signal Sdit may be less than or equal to the number of bits of the grayscale value range of the data voltage VDATA. In addition, the digital control signal Sdit may be a plurality of highest bits in the data voltage VDATA.

、

、

)，其中信號S0~S2可視為經栓鎖後的數位控制信號Sdit0~Sdit2，並且信號

、

、

則是信號S0~S2的反相信號。 The latching circuit 110 includes a plurality of latching units (such as 111, 113, and 115). Each of the latching circuits 110 receives digital control signals Sdit0 to Sdit2, and one of the digital control signals Sdit0 to Sdit2 is provided as the signals S0 to S2 and Corresponding inverted digital control signal (e.g. signal

,

,

), Where the signals S0 ~ S2 can be regarded as the digital control signals Sdit0 ~ Sdit2 after being locked, and the signals

,

,

It is the inverted signal of the signals S0 ~ S2.

Each latching unit (eg, 111, 113, 115) includes a first inverter INT, a first AND gate AND1, a second and gate AND2, a first OR gate NOR1, and a second OR gate NOR2. The first inverter INT has an input terminal and an output terminal for receiving a corresponding digital control signal (such as Sdit0 ~ Sdit2). The first AND gate AND1 has a first input terminal coupled to the output terminal of the first inverter INT, a second input terminal and an output terminal that receive the displacement signal SR_n. The second AND gate AND2 has a first input terminal for receiving a corresponding digital control signal (such as Sdit0 ~ Sdit2), a second input terminal and an output terminal for receiving the displacement signal SR_n.

、

、

)的輸出端。依據上述，栓鎖單元111接收位移信號SR_n及數位控制信號Sdit0，以提供信號S0及

；栓鎖單元113接收位移信號SR_n及數位控制信號Sdit1，以提供信號S1及

；栓鎖單元115接收位移信號SR_n及數位控制信號Sdit2，以提供 信號S2及

。 The first OR gate NOR1 has a first input terminal, a second input terminal coupled to the output terminals of the first AND gate AND1, and an output terminal that provides corresponding signals (such as signals S0 ~ S2). The second NOR gate NOR2 has a first input terminal coupled to the output of the second NOR gate AND2, a second input terminal coupled to the output of the first NOR gate NOR1, and a second input coupled to the first NOR gate NOR1. And provide corresponding signals (such as signals

,

,

) Output. According to the above, the latching unit 111 receives the displacement signal SR_n and the digital control signal Sdit0 to provide the signals S0 and

; The latch unit 113 receives the displacement signal SR_n and the digital control signal Sdit1 to provide the signals S1 and

; The latching unit 115 receives the displacement signal SR_n and the digital control signal Sdit2 to provide the signals S2 and

.

、

、

中的一個，以決定為導通或截止。並且，部份的傳輸閘(如TG11~TG14、TG21~TG28、TG31~TG38及TG41~TG48)串接於致能電壓準位(在此以系統低電壓VSS為例)與對應的選擇信號(如Y0~Y7)之間，部份的傳輸閘(如TG11~TG14、TG21~TG28、TG31~TG38及TG41~TG48)個別耦接於傳輸閘(如TG11~TG14、TG21~TG28、TG31~TG38及TG41~TG48)的其中之一的輸出端與禁能電壓準位(在此以系統高電壓VDD為例)之間。 The selection circuit 120 includes transmission gates TG11 to TG14, TG21 to TG28, TG31 to TG38, and TG41 to TG48, and transmission gates TG11 to TG14, TG21 to TG28, TG31 to TG38, and TG41 to TG48. Individual self-lock circuits 110 receive corresponding signals S0 ~ S2 one and signal

,

,

One of them is decided to be on or off. In addition, some transmission gates (such as TG11 ~ TG14, TG21 ~ TG28, TG31 ~ TG38, and TG41 ~ TG48) are connected in series to the enable voltage level (here, the system low voltage VSS is taken as an example) and the corresponding selection signal ( (Such as Y0 ~ Y7), some transmission gates (such as TG11 ~ TG14, TG21 ~ TG28, TG31 ~ TG38, and TG41 ~ TG48) are individually coupled to the transmission gates (such as TG11 ~ TG14, TG21 ~ TG28, TG31 ~ TG38). And TG41 ~ TG48) between the output terminal and the disabled voltage level (here, the system high voltage VDD is taken as an example).

的負控制端及輸出端。傳輸閘TG12具有接收系統高電壓VDD的輸入端、接收信號

的正控制端、接收信號S2的負控制端及耦接傳輸閘TG11的輸出端的輸出端。傳輸閘TG13具有接收系統低電壓VSS的輸入端、接收信號

的正控制端、接收信號S2的負控制端及輸出端。傳輸閘TG14具有接收系統高電壓VDD的輸入端、接收信號S2的正控制端、接收信號

的負控制端及耦接傳輸閘TG13的輸出端的輸出端。 The transmission gate TG11 has an input terminal for receiving the system low voltage VSS, a positive control terminal for receiving the signal S2, and a receiving signal.

Negative control terminal and output terminal. The transmission gate TG12 has an input terminal for receiving the high voltage VDD of the system, and a receiving signal

Positive control terminal, negative control terminal of receiving signal S2, and output terminal coupled to output terminal of transmission gate TG11. The transmission gate TG13 has an input terminal for receiving the system low voltage VSS, and receives a signal

Positive control terminal, negative control terminal and output terminal of receiving signal S2. The transmission gate TG14 has an input terminal for receiving the system high voltage VDD, a positive control terminal for receiving the signal S2, and a receiving signal.

And an output terminal coupled to the output terminal of the transmission gate TG13.

的負控制端及輸出端。傳輸 閘TG22具有接收系統高電壓VDD的輸入端、接收信號

的正控制端、接收信號S1的負控制端及耦接傳輸閘TG21的輸出端的輸出端。傳輸閘TG23具有耦接傳輸閘TG11的輸出端的輸入端、接收信號

的正控制端、接收信號S1的負控制端及輸出端。傳輸閘TG24具有接收系統高電壓VDD的輸入端、接收信號S1的正控制端、接收信號

的負控制端及耦接傳輸閘TG23的輸出端的輸出端。 The transmission gate TG21 has an input terminal coupled to the output terminal of the transmission gate TG11, a positive control terminal for receiving the signal S1, and a reception signal.

Negative control terminal and output terminal. The transmission gate TG22 has an input terminal for receiving the high voltage VDD of the system, and a receiving signal

Positive control terminal, negative control terminal of receiving signal S1, and output terminal coupled to output terminal of transmission gate TG21. The transmission gate TG23 has an input terminal coupled to an output end of the transmission gate TG11, and receives a signal.

Positive control terminal, negative control terminal and output terminal of receiving signal S1. The transmission gate TG24 has an input terminal for receiving the system high voltage VDD, a positive control terminal for receiving the signal S1, and a receiving signal.

And an output terminal coupled to the output terminal of the transmission gate TG23.

的負控制端及輸出端。傳輸閘TG26具有接收系統高電壓VDD的輸入端、接收信號

的正控制端、接收信號S1的負控制端及耦接傳輸閘TG25的輸出端的輸出端。傳輸閘TG27具有耦接傳輸閘TG13的輸出端的輸入端、接收信號

的正控制端、接收信號S1的負控制端及輸出端。傳輸閘TG28具有接收系統高電壓VDD的輸入端、接收信號S1的正控制端、接收信號

的負控制端及耦接傳輸閘TG27的輸出端的輸出端。 The transmission gate TG25 has an input terminal coupled to the output terminal of the transmission gate TG13, a positive control terminal for receiving the signal S1, and a receiving signal.

Negative control terminal and output terminal. The transmission gate TG26 has an input terminal for receiving the high voltage VDD of the system, and a receiving signal

Positive control terminal, negative control terminal of receiving signal S1, and output terminal coupled to output terminal of transmission gate TG25. The transmission gate TG27 has an input terminal coupled to an output end of the transmission gate TG13, and receives a signal.

Positive control terminal, negative control terminal and output terminal of receiving signal S1. The transmission gate TG28 has an input terminal for receiving the system high voltage VDD, a positive control terminal for receiving the signal S1, and a receiving signal.

The negative control terminal and the output terminal coupled to the output terminal of the transmission gate TG27.

的負控制端及提供選擇信號Y7的輸出端。傳輸閘TG32具有接收系統高電壓VDD的輸入端、接收信號

的正控制端、接收信號S0的負控制端及耦接傳輸閘TG31的輸出端的輸出端。傳輸閘TG33具有耦接傳輸閘TG21的輸出端的輸入端、接收信號

的正控制端、接收信號S0的負控制 端及提供選擇信號Y6的輸出端。傳輸閘TG34具有接收系統高電壓VDD的輸入端、接收信號S0的正控制端、接收信號

的負控制端及耦接傳輸閘TG33的輸出端的輸出端。 The transmission gate TG31 has an input terminal coupled to the output terminal of the transmission gate TG21, a positive control terminal receiving the signal S0, and a receiving signal.

Negative control terminal and an output terminal providing a selection signal Y7. The transmission gate TG32 has an input terminal for receiving the high voltage VDD of the system, and a receiving signal

The positive control terminal, the negative control terminal receiving the signal S0, and the output terminal coupled to the output terminal of the transmission gate TG31. The transmission gate TG33 has an input terminal coupled to the output end of the transmission gate TG21, and receives a signal.

Positive control terminal, negative control terminal receiving signal S0, and output terminal providing selection signal Y6. The transmission gate TG34 has an input terminal for receiving the system high voltage VDD, a positive control terminal for receiving the signal S0, and a receiving signal.

The negative control terminal and the output terminal coupled to the output terminal of the transmission gate TG33.

的負控制端及提供選擇信號Y5的輸出端。傳輸閘TG36具有接收系統高電壓VDD的輸入端、接收信號

的正控制端、接收信號S0的負控制端及耦接傳輸閘TG35的輸出端的輸出端。傳輸閘TG37具有耦接傳輸閘TG23的輸出端的輸入端、接收信號

的正控制端、接收信號S0的負控制端及提供選擇信號Y4的輸出端。傳輸閘TG38具有接收系統高電壓VDD的輸入端、接收信號S0的正控制端、接收信號

的負控制端及耦接傳輸閘TG37的輸出端的輸出端。 The transmission gate TG35 has an input terminal coupled to the output terminal of the transmission gate TG23, a positive control terminal receiving the signal S0, and a receiving signal.

Negative control terminal and an output terminal providing a selection signal Y5. The transmission gate TG36 has an input terminal for receiving the high voltage VDD of the system, and a receiving signal

The positive control terminal, the negative control terminal receiving the signal S0, and the output terminal coupled to the output terminal of the transmission gate TG35. The transmission gate TG37 has an input terminal coupled to the output end of the transmission gate TG23, and receives a signal.

Positive control terminal, negative control terminal receiving signal S0, and output terminal providing selection signal Y4. The transmission gate TG38 has an input terminal for receiving the system high voltage VDD, a positive control terminal for receiving the signal S0, and a receiving signal.

The negative control terminal and the output terminal coupled to the output terminal of the transmission gate TG37.

的負控制端及提供選擇信號Y3的輸出端。傳輸閘TG42具有接收系統高電壓VDD的輸入端、接收信號

的正控制端、接收信號S0的負控制端及耦接傳輸閘TG41的輸出端的輸出端。傳輸閘TG43具有耦接傳輸閘TG25的輸出端的輸入端、接收信號

的正控制端、接收信號S0的負控制端及提供選擇信號Y2的輸出端。傳輸閘TG44具有接收系統高電壓VDD的輸入端、接收信號S0的正控制端、接收信號

的負控制端及耦接傳輸閘TG43的輸出端的輸出端。 The transmission gate TG41 has an input terminal coupled to the output terminal of the transmission gate TG25, a positive control terminal receiving the signal S0, and a receiving signal.

Negative control terminal and an output terminal providing a selection signal Y3. The transmission gate TG42 has an input terminal for receiving the high voltage VDD of the system, and a receiving signal

The positive control terminal, the negative control terminal receiving the signal S0, and the output terminal coupled to the output terminal of the transmission gate TG41. The transmission gate TG43 has an input terminal coupled to the output end of the transmission gate TG25, and receives a signal.

Positive control terminal, negative control terminal receiving signal S0, and output terminal providing selection signal Y2. The transmission gate TG44 has an input terminal for receiving the system high voltage VDD, a positive control terminal for receiving the signal S0, and a receiving signal.

And an output terminal coupled to the output terminal of the transmission gate TG43.

的負控制端及提供選擇信號Y1的輸出端。傳輸閘TG46具有接收系統高電壓VDD的輸入端、接收信號

的正控制端、接收信號S0的負控制端及耦接傳輸閘TG45的輸出端的輸出端。傳輸閘TG47具有耦接傳輸閘TG27的輸出端的輸入端、接收信號

的正控制端、接收信號S0的負控制端及提供選擇信號Y0的輸出端。傳輸閘TG48具有接收系統高電壓VDD的輸入端、接收信號S0的正控制端、接收信號

的負控制端及耦接傳輸閘TG47的輸出端的輸出端。 The transmission gate TG45 has an input terminal coupled to the output terminal of the transmission gate TG27, a positive control terminal for receiving the signal S0, and a receiving signal.

Negative control terminal and an output terminal providing a selection signal Y1. The transmission gate TG46 has an input terminal for receiving the high voltage VDD of the system, and a receiving signal

The positive control terminal, the negative control terminal of the receiving signal S0, and the output terminal coupled to the output terminal of the transmission gate TG45. The transmission gate TG47 has an input terminal coupled to the output end of the transmission gate TG27, and receives a signal.

Positive control terminal, negative control terminal receiving signal S0, and output terminal providing selection signal Y0. The transmission gate TG48 has an input terminal for receiving the system high voltage VDD, a positive control terminal for receiving the signal S0, and a receiving signal.

The negative control terminal and the output terminal coupled to the output terminal of the transmission gate TG47.

The voltage output circuit 130 includes seven switching transistors M0 to M7, each of which has a first terminal for receiving one of a plurality of driving levels (VDD0 to VDD7) and one of receiving a selection signal (such as Y0 to Y7). The control terminal and a second terminal coupled to the driving voltage VD1.

According to the above, if the digital control signals Sdit2 ~ Sdit0 are "111" in sequence, the transmission gates TG11, TG14, TG21, TG24, TG25, TG28, TG31, TG34, TG35, TG38, TG41, TG44, TG45 and TG48 will be turned on, The remaining transmission gates will appear to be closed. Therefore, the system low voltage VSS will be transmitted to the selection signal Y7 through the conductive transmission gates TG11, TG21, and TG31, so that the selection signal Y7 is the enabled level, and the remaining selection signals Y0 to Y6 are disabled levels. Then, the switching transistor M7 is turned on, and the remaining switching transistors M0 to M6 are turned off. Therefore, the driving level VDD7 (for example, 8 volts) is provided to the driving transistor TD2 as the driving voltage VD1.

If the digital control signals Sdit2 ~ Sdit0 are "110" in sequence, the transmission gates TG11, TG14, TG21, TG24, TG25, TG28, TG32, TG33, TG36, TG37, TG42, TG43, TG46 and TG47 will be turned on, and the remaining transmission gates will be turned off. Therefore, the system low voltage VSS will be transmitted to the selection signal Y6 through the conductive transmission gates TG11, TG21 and TG33, so that the selection signal Y6 is the enable level, and the remaining selection signals Y0 ~ Y5, Y7 are the disable level. Then, the switching transistor M6 is turned on, and the remaining switching transistors M0 to M5 and M7 are turned off. Therefore, the driving level VDD6 (for example, 7 volts) is provided to the driving transistor TD2 as the driving voltage VD1. The rest of the state can be deduced by analogy, and will not be repeated here.

、

、

)。 In this embodiment, the latch units 111, 113, and 115 are exemplified by RS flip-flops, but the embodiment of the present invention is not limited thereto. In addition, a transmission gate (such as TG11 ~ TG14, TG21 ~ TG28, TG31 ~ TG38, and TG41 ~ TG48) connected in series between the enable voltage level (such as the system low voltage VSS) and the corresponding selection signal (such as Y0 ~ Y7). The number corresponds to the number of digital control signals (such as Sdit0 ~ Sdit2), and is connected in series between the transmission gate (such as TG11) between the enable voltage level (such as the system low voltage VSS) and the corresponding selection signal (such as Y1 ~ Y7). ~ TG14, TG21 ~ TG28, TG31 ~ TG38, and TG41 ~ TG48) individually receive latch signals (such as signals S0 ~ S2, corresponding to different digital control signals (such as Sdit0 ~ Sdit2)).

,

,

).

FIG. 3A is a simulation diagram of a driving voltage changing with a data voltage according to an embodiment of the present invention. FIG. 3B is a simulation diagram of the driving voltage being a fixed voltage according to an embodiment of the present invention. Please refer to FIGS. 1A, 3A and 3B. In this embodiment, the voltage VG1 is the gate voltage (corresponding to the data voltage VDATA) of the driving transistor TD2, and the voltage VS1 is the source voltage of the driving transistor TD2. It can be seen from FIGS. 3A and 3B that when the voltage VG1 is 1.45 or 3.46 volts (V), the driving voltage VD1 can be greatly reduced, but the light-emitting current Id changes only slightly. Therefore, in the case of a low gray level, the driving voltage VD1 can be reduced to reduce power consumption, but the light emitting brightness of the light emitting diode LED1 can still be maintained to a certain extent.

FIG. 4 is a system diagram of a display device according to an embodiment of the invention. Referring to FIG. 4, in this embodiment, the display device 10 includes at least a displacement control circuit 11, a data providing circuit 13, a light-emitting block 15, a plurality of vertical signal lines LVS, and a plurality of horizontal signal lines LHS, among which the light-emitting block 15 Please refer to the light emitting block 100 shown in FIG. 1A. The displacement control circuit 11 is used to provide a plurality of displacement signals (such as SR_1 ~ SR_3), and the data providing circuit 13 is used to provide a data voltage VDATA and a plurality of digital control signals Sdit.

The light-emitting block 15 is coupled to a plurality of corresponding horizontal signal lines LHS, and is coupled to the displacement control circuit 11 through the corresponding horizontal signal lines LHS to receive corresponding displacement signals (such as SR_1 ~ SR_3). On the other hand, the light-emitting block 15 is coupled to the corresponding plurality of vertical signal lines LVS, and is coupled to the data providing circuit 13 through the corresponding plurality of vertical signal lines LVS to receive the corresponding data voltage VDATA and the corresponding plurality Digital control signal Sdit.

The light-emitting block 15 stores the corresponding data voltage VDATA received according to the corresponding displacement signal (such as SR_1 ~ SR_3), and simultaneously locks the received digital control signals Sdit. The light-emitting block 15 determines the brightness of light emission according to the stored data voltage VDATA, and the light-emitting block 15 can reduce power consumption through the latched digital control signals Sdit. In this embodiment, the light-emitting blocks 15 directly provide light for forming a color image.

FIG. 5 is a system schematic diagram of a data providing circuit according to an embodiment of the present invention. Please refer to FIGS. 4 and 5. In this embodiment, the data providing circuit 13 includes a shift register 210, an input register 220, a data latch 230, a quasi-shifter 240, a digital analog converter 250 and Buffer 260. The displacement register 210 receives the setting signal SET and the clock signal CLK to provide a plurality of trigger signals STR that are sequentially enabled according to the setting signal SET and the clock signal CLK. The input register 220 is coupled to the displacement register 210 to receive a plurality of sequentially enabled trigger signals STR and receive a plurality of display data (such as red display data XDR, green display data XDG, and blue display data XDB). . Then, the input register 220 sequentially latches and outputs the display data (such as the red display data XDR, the green display data XDG, and the blue display data XDB) according to a plurality of sequentially enabled trigger signals STR.

The data latch 230 is coupled to the input register 220 and receives the latch enable signal LEN so as to latch and output display data received from the input register 220 according to the latch enable signal LEN (such as red display data XDR, Green display data XDG and blue display data XDB). The quasi-displacer 240 is coupled to the data latch 230 to receive display data (such as red display data XDR, green display data XDG, and blue display data XDB) from the data latch 230, and provide a quasi-displacement bit. The subsequent display data DLX and a plurality of digital control signals Sdit may be formed by directly outputting display data (such as red display data XDR, green display data XDG, and blue display data XDB).

The digital analog converter 250 is coupled to the quasi-shifter 240 to receive the quasi-shifted display data DLX, and to receive a plurality of reference voltages Vref to display the display data. After the DLX is converted to the analog level (that is, the voltage level), the analog driving voltage VDX is provided. The buffer 260 is coupled to the digital-to-analog converter 250 to receive the analog driving voltage VDX and provide the data voltage VDATA accordingly.

FIG. 6 is a system diagram of a display device according to another embodiment of the present invention. 4 and FIG. 6, the display device 20 is substantially the same as the display device 10. The difference is that the display device 20 further includes a display panel 21. The display panel 21 is configured with a plurality of liquid crystal pixels PX arranged in an array, and each light-emitting block 15 overlaps a portion of these liquid crystal pixels PX to provide display light to the overlapping liquid crystal pixels PX. In this embodiment, the display panel 21 and the light-emitting block 15 can share the displacement control circuit 11.

FIG. 7 is a flowchart of a driving method of a light emitting block of a display device according to an embodiment of the invention. Please refer to FIG. 7. In this embodiment, the driving method is used to drive a plurality of light-emitting blocks of the display device. Each of these light-emitting blocks has a light-emitting diode. The driving method includes the following steps. In step S710, the data voltage is received to determine a light emitting current flowing through the light emitting diode by the driving voltage. In step S720, a plurality of digital control signals corresponding to the data voltage are received to adjust the driving voltage, wherein the driving voltage is also reflected as the data voltage decreases. The sequence of steps S710 and S720 is for illustration, and the embodiment of the present invention is not limited thereto. For details of steps S710 and S720, reference may be made to the embodiments in FIGS. 1A, 1B, 2, 3A, 3B, and 4-6, and details are not described herein again.

In summary, the display device and the method for driving the light-emitting block according to the embodiments of the present invention receive a plurality of digital control signals corresponding to the data voltage to adjust the driver. The driving voltage and the voltage of the reaction data decrease, and the driving voltage also decreases. Therefore, when the light-emitting gray-scale value of the light-emitting block is lower, more power can be saved, but the light-emitting brightness of the light-emitting diode is still maintained.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims (20)

A display device includes: a plurality of light-emitting blocks, each of which includes: a latch circuit that receives a plurality of digital control signals and a displacement signal corresponding to a data voltage, and latches the displacement signal according to the displacement signal. A plurality of digital control signals; a selection circuit coupled to the latching circuit to receive the latched digital control signals and providing a plurality of selection signals, wherein the selection circuit is based on the latched digital control signals. One of the selection signals; a voltage output circuit coupled to the selection circuit to receive the selection signals and provide a driving voltage, wherein the driving voltage is controlled by the selection signals and reflects the data As the voltage decreases, the driving voltage also decreases. A data transistor has a first terminal that receives the data voltage, a control terminal and a second terminal that receives the displacement signal, and a driving transistor that receives the data. A first terminal of the driving voltage, a control terminal and a second terminal coupled to the second terminal of the data transistor; a capacitor coupled to the control terminal of the driving transistor Between the terminal and a second terminal of the driving transistor; and the second end and a light emitting diode, coupled to the driving transistor with a low voltage between the systems. The display device according to item 1 of the scope of patent application, wherein the driving voltage is also reduced to a minimum voltage that keeps a light-emitting current flowing through the light-emitting diode constant as the voltage of the data decreases. Level. The display device according to item 2 of the scope of patent application, wherein the driving voltage is also reduced to the minimum voltage level plus an incremental voltage as the voltage of the data decreases. The display device according to item 3 of the scope of patent application, wherein when the data voltage is between a change threshold voltage and a maximum grayscale voltage, the driving voltage is maintained at a maximum driving voltage. The display device according to item 4 of the scope of patent application, wherein as the incremental voltage is larger, the change threshold voltage is lower. The display device according to item 1 of the scope of patent application, wherein the latch circuit includes a plurality of latch units, each of which receives the digital control signals to provide one of the digital control signals and a corresponding inverted digital control signal. The display device according to item 6 of the scope of patent application, wherein the latch units include: a first inverter having an input end and an output end receiving one of the digital control signals; a first A sum gate having a first input end coupled to the output end of the first inverter, a second input end and an output end receiving the displacement signal; a second sum gate having receiving the digital controls A first input terminal of one of the signals, a second input terminal and an output terminal receiving the displacement signal; a first inverse OR gate having a first coupled to the output terminal of the first and gate An input terminal, a second input terminal, and an output terminal providing one of the digital control signals; a second inverting OR gate having a first input terminal, a coupling coupled to the output terminal of the second and gate; A second input terminal connected to the output terminal of the first OR gate and an output terminal coupled to the second input terminal of the first OR gate and provides a corresponding inverted digital control signal. The display device according to item 1 of the scope of patent application, wherein the selection circuit includes a plurality of transmission gates, and individually receives one of the digital control signals and a corresponding inverted digital control signal to determine whether to turn on or off, Some of the transmission gates are connected in series between the uniform energy voltage level and the corresponding selection signal, and some of the transmission gates are individually coupled to an output terminal and an disabled voltage level of one of the transmission gates. between. The display device according to item 8 of the scope of patent application, wherein the number of transmission gates connected in series between the enable voltage level and the corresponding selection signal corresponds to the number of digital control signals. The display device according to item 8 of the scope of patent application, wherein the transmission gates connected in series between the uniform energy voltage level and the corresponding selection signal individually receive different digital control signals. The display device according to item 1 of the scope of patent application, wherein the voltage output circuit includes a plurality of switching transistors, each of which has a first terminal for receiving one of a plurality of driving levels, and one of which receives the selection signals. A control terminal and a second terminal coupled to the driving voltage. The display device according to item 1 of the scope of patent application, wherein the number of the digital control signals corresponds to a one-bit number of a grayscale value range of the data voltage. The display device according to item 1 of the scope of patent application, wherein the digital control signals and the data voltage are provided by a data providing circuit. The display device according to item 1 of the patent application scope further includes a liquid crystal display panel having a plurality of liquid crystal pixels, and each of the light-emitting blocks overlaps with a portion of the liquid crystal pixels to provide display light to the overlap. Of those LCD pixels. The display device according to item 1 of the scope of patent application, wherein the light-emitting blocks directly provide light for forming a color image. The display device according to item 1 of the scope of patent application, wherein the light emitting diode is a one-millimeter light emitting diode. A driving method for driving a plurality of light-emitting blocks of a display device. Each of the light-emitting blocks has a light-emitting diode. The driving method includes: receiving a data voltage to determine a driving voltage flowing through a light-emitting diode. A light-emitting current of the polar body; receiving a plurality of digital control signals corresponding to a data voltage to adjust the driving voltage, wherein the driving voltage is also decreased as a result of the decrease in the data voltage. The driving method according to item 17 of the scope of patent application, wherein the driving voltage is also reduced to a minimum voltage level that keeps a light-emitting current flowing through the light-emitting diode constant as the data voltage decreases. . The driving method according to item 17 of the scope of patent application, wherein the driving voltage is also reduced to a minimum voltage level that keeps a light-emitting current flowing through the light-emitting diode constant as the data voltage decreases. Add an incremental voltage. The driving method according to item 19 of the application, wherein when the data voltage is between a change threshold voltage and a maximum grayscale voltage, the driving voltage is maintained at a maximum driving voltage, and when the incremental voltage is more The larger, the lower the change threshold voltage.