CN109979410B

CN109979410B - Display device and driving method of light emitting region thereof

Info

Publication number: CN109979410B
Application number: CN201910405925.7A
Authority: CN
Inventors: 林峻锋; 洪凯尉; 杨创丞; 林逸承; 李明贤
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2018-10-25
Filing date: 2019-05-15
Publication date: 2021-05-18
Anticipated expiration: 2039-05-15
Also published as: CN109979410A; TWI679628B; TW202016915A

Abstract

A display device and a method for driving a light emitting region thereof. The display device includes a plurality of light emitting regions. Each light emitting region includes a latch circuit, a selection circuit, a voltage output circuit, a data transistor, a driving transistor, a capacitor, and a light emitting diode. The latch circuit latches a plurality of digital control signals corresponding to the data voltages. The selection circuit provides a plurality of selection signals according to the latched digital control signals. The voltage output circuit provides a driving voltage according to the selection signal, wherein the driving voltage is reduced along with the reduction of the data voltage. The data transistor receives a data voltage and a displacement signal. The driving transistor is coupled among the data transistor, the driving voltage and the light emitting diode. The capacitor is coupled between the control end and the second end of the driving transistor.

Description

Display device and driving method of light emitting region thereof

Technical Field

The present invention relates to a display device, and more particularly, to a display device and a method for driving a light emitting region thereof.

Background

In display technology, light emitting diodes are continuously miniaturized to provide more applications. In a display device, the light emitting diode may be applied as a backlight module for providing backlight, or may be directly applied as a display interface for displaying an image. However, in order to make the backlight module or the display interface have higher versatility, reducing the power consumption of the backlight module or the display interface is an important issue.

Disclosure of Invention

The invention provides a display device and a driving method of a light emitting region thereof, which can save power consumption and still maintain the expected light emitting brightness of a light emitting diode.

The display device of the present invention includes a plurality of light emitting regions. Each light emitting region includes a latch circuit, a selection circuit, a voltage output circuit, a data transistor, a driving transistor, a capacitor, and a light emitting diode. The latch circuit receives a plurality of digital control signals and displacement signals corresponding to the data voltages and latches the digital control signals according to the displacement signals. The selection circuit is coupled to the latch signal to receive the latched digital control signals and provide a plurality of selection signals, wherein the selection circuit enables one of the selection signals according to the latched digital control signals. The voltage output circuit is coupled to the selection circuit to receive the selection signals and provide a driving voltage, wherein the driving voltage is controlled by the selection signals and reflects a drop of the data voltage, and the driving voltage also drops along with the drop. The data transistor has a first terminal for receiving a data voltage, a control terminal for receiving a displacement signal, and a second terminal. The driving transistor has a first terminal for receiving a driving voltage, a control terminal coupled to the second terminal of the data transistor, and a second terminal. The capacitor is coupled between the control end of the driving transistor and the second end of the driving transistor. The light emitting diode is coupled between the second end of the driving transistor and the system low voltage.

The driving method of the present invention is used for driving a plurality of light emitting areas of a display device, wherein the light emitting areas are respectively provided with a light emitting diode, and the driving method comprises the following steps. The data voltage is received to determine the light emitting current flowing through the light emitting diode by the driving voltage. Receiving a plurality of digital control signals corresponding to the data voltages to adjust the driving voltages, wherein the driving voltages are decreased in response to a decrease in the data voltages.

In view of the above, the display device and the driving method of the light emitting region thereof according to the embodiments of the invention receive a plurality of digital control signals corresponding to the data voltage to adjust the driving voltage, and the driving voltage is decreased in response to the decrease of the data voltage. Therefore, when the light-emitting gray-scale value of the light-emitting region is lower, more power can be saved, and the light-emitting brightness of the light-emitting diode can be still maintained.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1A is a system diagram of a light emitting region according to an embodiment of the invention.

Fig. 1B is a characteristic diagram of a driving transistor of a light-emitting region according to an embodiment of the invention.

Fig. 2 is a circuit diagram of a light emitting region according to an embodiment of the invention.

FIG. 3A is a simulation diagram of the driving voltage variation with the data voltage according to an embodiment of the invention.

FIG. 3B is a simulation diagram illustrating a driving voltage being a fixed voltage according to an embodiment of the invention.

FIG. 4 is a system diagram of a display device according to an embodiment of the invention.

FIG. 5 is a system diagram of a data providing circuit according to an embodiment of the invention.

FIG. 6 is a system diagram of a display device according to another embodiment of the invention.

Fig. 7 is a flowchart illustrating a driving method of a light emitting region of a display device according to an embodiment of the invention.

Description of reference numerals:

10. 20: display device

11: displacement control circuit

13: data supply circuit

15: light emitting area

21: display panel

100. 15: light emitting area

110: latch circuit

111. 113, 115: latch unit

120: selection circuit

130: voltage output circuit

210: shift temporary storage

220: input temporary storage

230: data latch

240: level shifter

250: digital-to-analog converter

260: buffer device

AND 1: a first AND gate

AND 2: second AND gate

C1: capacitor with a capacitor element

CLK: clock signal

DLX: displaying data

Id: luminous current

INT: a first inverter

LED 1: light emitting diode

And (3) LEN: latch enable signal

LHS: horizontal signal line

M0-M7: switching transistor

NOR 1: a first NOR gate

NOR 2: second NOR gate

PX: liquid crystal pixel

S0～S2、

Signal

S111 to S116, S120, and S130: curve line

Sdit, Sdit 0-Sdit 2: digital control signal

SET: setting signal

SR _1 to SR _3, SR _ n: displacement signal

STR: trigger signal

TD 1: data transistor

TD 2: driving transistor

TG 11-TG 14, TG 21-TG 28, TG 31-TG 38 and TG 41-TG 48: transmission gate

VD 1: driving voltage

VDATA: data voltage

VDD: high voltage of system

VDD _ max: maximum drive voltage level

VDD 0-VDD 7: drive level

VDX: analog driving voltage

VG1, VS 1: voltage of

VLS: vertical signal line

Vref: reference voltage

VSS: low voltage of system

VTm: varying the threshold voltage

XDB: blue display data

XDG: green display data

XDR: red display data

Y0-Y7: selection signal

S710 and S720: step (ii) of

Detailed Description

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element," "component," "region," "layer" or "portion" discussed below could be termed a second element, component, region, layer or portion without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms, including "at least one", unless the content clearly indicates otherwise. "or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions integers, steps, operations, elements, components, and/or groups thereof.

Fig. 1A is a system diagram of a light emitting region according to an embodiment of the invention. Referring to fig. 1A, in the present embodiment, a light emitting region 100 is configured in a display device and can be used as a pixel of a display panel or a light emitting circuit of a backlight module. The light emitting region 100 includes at least a latch circuit 110, a selection circuit 120, a voltage output circuit 130, a data transistor TD1, a driving transistor TD2, a capacitor C1, and a light emitting diode LED 1. The LED1 is, for example, a sub-millimeter LED, but the embodiment of the invention is not limited thereto.

The latch circuit 110 receives a plurality of digital control signals Sdit and a shift signal SR _ n corresponding to the data voltage VDATA, and latches the digital control signals Sdit according to the shift signal SR _ n, where n is a positive integer. The selection circuit 120 is coupled to the latch circuit 110 for receiving the latched digital control signals (e.g., signals S0-S2) and providing a plurality of selection signals (e.g., Y0-Y2), wherein the selection circuit 120 enables one of the selection signals (e.g., signals Y0-Y2) according to the latched digital control signals (e.g., signals S0-S2).

The voltage output circuit 130 is coupled to the selection circuit 120 to receive the selection signals (e.g., Y0-Y2) and provide the driving voltage VD 1. The data transistor TD1 has a first terminal for receiving the data voltage VDTAT, a control terminal for receiving the shift signal SR _ n, and a second terminal. The driving transistor TD2 has a first terminal receiving the driving voltage VD1, a control terminal coupled to the second terminal of the data transistor TD1, and a second terminal. The capacitor C1 is coupled between the control terminal of the driving transistor TD2 and the second terminal of the driving transistor TD 2. The light emitting diode LED1 is coupled between the second terminal of the driving transistor TD2 and the system low voltage VSS.

In the embodiment, the driving voltage VD1 is controlled by the selection signal (e.g., Y0-Y2) to determine its voltage level, i.e., the driving voltage VD1 decreases with the decrease of the data voltage VDATA. In other words, the lower the data voltage VDATA (which can be considered as the lower the corresponding gray-scale value), the lower the driving voltage VD1 is while the light-emitting current Id flowing through the light-emitting diode LED1 is kept constant; the higher the data voltage VDATA (which can be considered as the higher the corresponding gray scale value), the higher the driving voltage VD 1.

Since the light-emitting current Id is constant, the light-emitting luminance of the light-emitting diode LED1 is not affected, but the overall power consumption of the light-emitting region 100 decreases as the drive voltage VD1 decreases.

Fig. 1B is a characteristic diagram of a driving transistor of a light-emitting region according to an embodiment of the invention. Referring to fig. 1A and fig. 1B, the curve S120 separates the linear region and the saturation region of the driving transistor TD2, and the driving transistor TD2 mainly operates in the saturation region. Curves S111-S116 show the variation of each data voltage VDATA (i.e. each gray-scale value) with the driving voltage VD1, wherein the curve S111 corresponds to the gray-scale value 128, for example, and the curve S116 corresponds to the gray-scale value 255, for example. Generally, the driving voltage VD1 is a fixed value, and the driving voltage VD1 is set to the maximum driving voltage level VDD _ max in order to be applied to all gray levels (as shown by the curves S111-S116).

In the present embodiment, in response to the decrease of the data voltage VDATA (i.e., the gray-scale value), the driving voltage VD1 is also decreased to be greater than or equal to the minimum driving voltage level (i.e., the corresponding intersection point of the gray-scale curves S112-S116 and the curve S120) for maintaining the light-emitting current Id flowing through the LED 1. That is, when the data voltage VDATA (i.e., the gray-scale values) is not at the maximum value, the driving voltage VD1 can be set between the curve S120 and the maximum driving voltage level VDD _ max along with the corresponding gray-scale value curve (e.g., S112 to S116), and the driving voltage VD1 can be constant or higher as the gray-scale value is higher.

Further, as shown in the curve S130, in order to avoid the driving voltage VD1 jumping to the left side of the curve S120 due to the characteristic problem of the driving transistor TD2, i.e. the light emitting current Id flowing through the light emitting diode LED1 is excessively decreased to affect the light emitting brightness of the light emitting diode LED1, the driving voltage VD1 may also be added with the incremental voltage Δ V (which is equivalent to shifting the curve S120 to the right by the incremental voltage Δ V) as the driving voltage VD1 decreases to the minimum driving voltage level (i.e. the corresponding intersection point of the gray-level curves S112 to S116 and the curve S120) in response to the decrease of the data voltage VDATA.

At this time, since the driving voltage VD1 is set to the maximum driving voltage level VDD _ max at most, the driving voltage VD1 of some gray-scale values is set to the maximum driving voltage level VDD _ max in addition to the maximum gray-scale value, and the driving voltage VD1 of other gray-scale values is set to be less than the maximum driving voltage level VDD _ max. For example, when the data voltage VDATA is between the variation threshold voltage VTm and the maximum gray scale voltage (i.e., corresponding to the curve S111), the driving voltage VD1 is maintained at the maximum driving voltage level VDD _ max. The larger the incremental voltage Δ V is, the lower the fluctuation threshold voltage VTm is.

Fig. 2 is a circuit diagram of a light emitting region according to an embodiment of the invention. Referring to fig. 1A and fig. 2, in the present embodiment, the number of the digital control signal Sdit is taken as an example 3 (taking the digital control signals Sdit 0-Sdit 2 as examples), that is, the digital control signal Sdit is a 3-bit signal, wherein the number of the digital control signal Sdit corresponds to the number of bits of the gray scale range of the data voltage VDATA, that is, the number of the bits of the digital control signal Sdit may be less than or equal to the number of the bits of the gray scale range of the data voltage VDATA. Also, the digital control signal Sdit may be a plurality of most significant bits in the data voltage VDATA.

The latch circuit 110 includes a plurality of latch units (e.g., 111, 113, 115) respectively receiving the digital control signals Sdit 0-Sdit 2 to respectively provide one of the latched digital control signals Sdit 0-Sdit 2 as signals S0-S2 and corresponding inverted digital control signals (e.g., signals

) Wherein the signals S0-S2 can be regarded as the latched digital control signals Sdit 0-Sdit 2, and the signals

It is the inverse of signals S0-S2.

Each latch unit (e.g., 111, 113, 115) includes a first inverter INT, a first AND-gate AND1, a second AND-gate AND2, a first NOR gate NOR1, AND a second NOR gate NOR 2. The first inverter INT has an input terminal and an output terminal for receiving a corresponding digital control signal (e.g., Sdit 0-Sdit 2). The first AND gate 1 has a first input terminal coupled to the output terminal of the first inverter INT, a second input terminal receiving the shift signal SR _ n, AND an output terminal. The second AND gate AND2 has a first input terminal for receiving a corresponding digital control signal (e.g., Sdit 0-Sdit 2), a second input terminal for receiving the shift signal SR _ n, AND an output terminal.

The first NOR gate NOR1 has a first input coupled to the output of the first AND gate AND1, a second input, AND an output for providing corresponding signals (e.g., signals S0-S2). The second NOR gate NOR2 has a first input coupled to the output of the second AND gate NOR2, a second input coupled to the output of the first NOR gate NOR1, AND a second input coupled to the output of the first NOR gate NOR1 AND providing a corresponding signal (e.g., a signal

) To the output terminal of (a). According to the above, the latch unit 111 receives the shift signal SR _ n and the digital control signal Sdit0 to provide signals S0 and S

The latch unit 113 receives the shift signal SR _ n and the digital control signal Sdit1 to provide signals S1 and S

The latch unit 115 receives the shift signal SR _ n and the digital control signal Sdit2 to provide signals S2 and S

The selection circuit 120 includes transmission gates TG 11-TG 14,TG 21-TG 28, TG 31-TG 38 and TG 41-TG 48, transmission gates TG 11-TG 14, TG 21-TG 28, TG 31-TG 38 and TG 41-TG 48 respectively receive one of corresponding signals S0-S2 and the signal from the latch circuit 110

To be determined as on or off. In addition, some of the transmission gates (e.g., TG 11-TG 14, TG 21-TG 28, TG 31-TG 38, and TG 41-TG 48) are connected in series between an enable voltage level (taking the system low voltage VSS as an example) and a corresponding selection signal (e.g., Y0-Y7), and some of the transmission gates (e.g., TG 11-TG 14, TG 21-TG 28, TG 31-TG 38, and TG 41-TG 48) are respectively coupled between an output end of one of the transmission gates (e.g., TG 11-TG 14, TG 21-TG 28, TG 31-38, and TG 41-TG 48) and a disable voltage level (taking the system high voltage VDD as an example).

The transmission gate TG11 has an input terminal for receiving system low voltage VSS, a positive control terminal for receiving signal S2, and a received signal

Negative control terminal and output terminal. The transmission gate TG12 has an input terminal for receiving the system high voltage VDD, and a received signal

A negative control terminal receiving the signal S2, and an output terminal coupled to the output terminal of the transmission gate TG 11. The transmission gate TG13 has an input terminal for receiving system low voltage VSS, and a receiving signal

A positive control terminal receiving signal S2, and an output terminal. The transmission gate TG14 has an input terminal for receiving the system high voltage VDD, a positive control terminal for receiving the signal S2, and a received signal

And an output terminal coupled to the output terminal of the transmission gate TG 13.

The transmission gate TG21 has an input terminal coupled to the output terminal of the transmission gate TG11Positive control terminal of received signal S1, and received signal

Negative control terminal and output terminal. The transmission gate TG22 has an input terminal for receiving the system high voltage VDD, and a received signal

A negative control terminal receiving the signal S1, and an output terminal coupled to the output terminal of the transmission gate TG 21. The transmission gate TG23 has an input terminal coupled to the output terminal of the transmission gate TG11, and receives a signal

A positive control terminal receiving signal S1, and an output terminal. The transmission gate TG24 has an input terminal for receiving the system high voltage VDD, a positive control terminal for receiving the signal S1, and a received signal

And an output terminal coupled to the output terminal of the transmission gate TG 23.

The transmission gate TG25 has an input terminal coupled to the output terminal of the transmission gate TG13, a positive control terminal for receiving the signal S1, and a receiving signal

Negative control terminal and output terminal. The transmission gate TG26 has an input terminal for receiving the system high voltage VDD, and a received signal

A negative control terminal receiving the signal S1, and an output terminal coupled to the output terminal of the transmission gate TG 25. The transmission gate TG27 has an input terminal coupled to the output terminal of the transmission gate TG13, and receives a signal

A positive control terminal receiving signal S1, and an output terminal. The transmission gate TG28 has an input terminal for receiving the system high voltage VDD, a positive control terminal for receiving the signal S1, and a received signal

And an output terminal coupled to the output terminal of the transmission gate TG 27.

The transmission gate TG31 has an input terminal coupled to the output terminal of the transmission gate TG21, a positive control terminal for receiving the signal S0, and a receiving signal

And an output providing a select signal Y7. The transmission gate TG32 has an input terminal for receiving the system high voltage VDD, and a received signal

A negative control terminal receiving the signal S0, and an output terminal coupled to the output terminal of the transmission gate TG 31. The transmission gate TG33 has an input terminal coupled to the output terminal of the transmission gate TG21, and receives a signal

A negative control terminal receiving the signal S0, and an output terminal providing the select signal Y6. The transmission gate TG34 has an input terminal for receiving the system high voltage VDD, a positive control terminal for receiving the signal S0, and a received signal

And an output terminal coupled to the output terminal of the transmission gate TG 33.

The transmission gate TG35 has an input terminal coupled to the output terminal of the transmission gate TG23, a positive control terminal for receiving the signal S0, and a receiving signal

And an output providing a select signal Y5. The transmission gate TG36 has an input terminal for receiving the system high voltage VDD, and a received signal

A negative control terminal receiving the signal S0, and an output terminal coupled to the output terminal of the transmission gate TG 35. Transmission gate TG37 has an input terminal coupled to the output terminal of transmission gate TG23, and receives a signal

A negative control terminal receiving the signal S0, and an output terminal providing the select signal Y4. The transmission gate TG38 has an input terminal for receiving the system high voltage VDD, a positive control terminal for receiving the signal S0, and a received signal

And an output terminal coupled to the output terminal of the transmission gate TG 37.

The transmission gate TG41 has an input terminal coupled to the output terminal of the transmission gate TG25, a positive control terminal for receiving the signal S0, and a receiving signal

And an output providing a select signal Y3. The transmission gate TG42 has an input terminal for receiving the system high voltage VDD, and a received signal

A negative control terminal receiving the signal S0, and an output terminal coupled to the output terminal of the transmission gate TG 41. The transmission gate TG43 has an input terminal coupled to the output terminal of the transmission gate TG25, and receives a signal

A negative control terminal receiving the signal S0, and an output terminal providing the select signal Y2. The transmission gate TG44 has an input terminal for receiving the system high voltage VDD, a positive control terminal for receiving the signal S0, and a received signal

And an output terminal coupled to the output terminal of the transmission gate TG 43.

The transmission gate TG45 has an input terminal coupled to the output terminal of the transmission gate TG27, a positive control terminal for receiving the signal S0, and a receiving signal

And an output providing a select signal Y1. The transmission gate TG46 has an input terminal for receiving the system high voltage VDD, and a received signal

A negative control terminal receiving the signal S0, and an output terminal coupled to the output terminal of the transmission gate TG 45. The transmission gate TG47 has an input terminal coupled to the output terminal of the transmission gate TG27, and receives a signal

A negative control terminal receiving the signal S0, and an output terminal providing the select signal Y0. The transmission gate TG48 has an input terminal for receiving the system high voltage VDD, a positive control terminal for receiving the signal S0, and a received signal

And an output terminal coupled to the output terminal of the transmission gate TG 47.

The voltage output circuit 130 includes seven switching transistors M0-M7, each having a first terminal receiving one of a plurality of driving levels (VDD 0-VDD 7), a control terminal receiving one of selection signals (e.g., Y0-Y7), and a second terminal coupled to a driving voltage VD 1.

According to the above, if the digital control signals Sdit 2-Sdit 0 are "111" in sequence, the transmission gates TG11, TG14, TG21, TG24, TG25, TG28, TG31, TG34, TG35, TG38, TG41, TG44, TG45 and TG48 are turned on, and the rest of the transmission gates are turned off. Therefore, the system low voltage VSS is transmitted to the selection signal Y7 through the turned-on transmission gates TG11, TG21 and TG31, so that the selection signal Y7 is enabled, and the remaining selection signals Y0 to Y6 are disabled. Then, the switch transistor M7 is turned on, and the remaining switch transistors M0-M6 are turned off, so that the driving level VDD7 (e.g., 8 volts) is provided to the driving transistor TD2 as the driving voltage VD 1.

If the digital control signals Sdit 2-Sdit 0 are "110" in sequence, the transmission gates TG11, TG14, TG21, TG24, TG25, TG28, TG32, TG33, TG36, TG37, TG42, TG43, TG46 and TG47 are turned on, and the rest of the transmission gates are turned off. Therefore, the system low voltage VSS is transmitted to the selection signal Y6 through the turned-on transmission gates TG11, TG21 and TG33, so that the selection signal Y6 is at an enable level, and the remaining selection signals Y0 to Y5 and Y7 are at a disable level. Then, the switch transistor M6 is turned on, and the remaining switch transistors M0-M5, M7 are turned off, so that the driving level VDD6 (e.g., 7 volts) is provided to the driving transistor TD2 as the driving voltage VD 1. The rest states are analogized, and the description is omitted here.

In the embodiment, the

latch units

111, 113, and 115 are RS flip-flops as an example, but the embodiment of the invention is not limited thereto. In addition, the number of the transmission gates (such as TG 11-TG 14, TG 21-TG 28, TG 31-TG 38 and TG 41-TG 48) connected in series between the enable voltage level (such as system low voltage VSS) and the corresponding selection signal (such as Y0-Y7) corresponds to the number of the digital control signals (such as Sdit 0-Sdit 2), and the transmission gates (such as TG 11-TG 14, TG 21-TG 28, TG 31-TG 38 and TG 41-TG 48) connected in series between the enable voltage level (such as system low voltage VSS) and the corresponding selection signal (such as Y1-Y7) respectively receive the latch signals (such as TG 0-S2, TG 5842, TG 31-TG 38 and TG 41-Sdit 2) corresponding to different digital control signals (such as Sdit 0-Sdit 2),

)。

FIG. 3A is a simulation diagram of the driving voltage variation with the data voltage according to an embodiment of the invention. FIG. 3B is a simulation diagram illustrating a driving voltage being a fixed voltage according to an embodiment of the invention. Referring to fig. 1A, fig. 3A and fig. 3B, in the present embodiment, the voltage VG1 is the gate voltage (corresponding to the data voltage VDATA) of the driving transistor TD2, and the voltage VS1 is the source voltage of the driving transistor TD 2. As can be seen from fig. 3A and 3B, when the voltage VG1 is 1.45 or 3.46 volts (V), the driving voltage VD1 can be greatly reduced, but the light-emitting current Id only fluctuates slightly. Therefore, in the case of low gray scale, the driving voltage VD1 can be reduced to reduce power consumption, but the brightness of the light emitting diode LED1 can still be maintained to some extent.

FIG. 4 is a system diagram of a display device according to an embodiment of the invention. Referring to fig. 4, in the present embodiment, the display device 10 at least includes a displacement control circuit 11, a data providing circuit 13, a light emitting region 15, a plurality of vertical signal lines LVS and a plurality of horizontal signal lines LHS, wherein the light emitting region 15 can refer to the light emitting region 100 shown in fig. 1A. The shift control circuit 11 is configured to provide a plurality of shift signals (e.g., SR _1 to SR _3), and the data providing circuit 13 is configured to provide a data voltage VDATA and a plurality of digital control signals Sdit.

The light emitting regions 15 are coupled to the corresponding horizontal signal lines LHS, and are coupled to the shift control circuit 11 through the corresponding horizontal signal lines LHS to receive the corresponding shift signals (e.g., SR _1 to SR _ 3). On the other hand, the light emitting region 15 is coupled to the plurality of vertical signal lines LVS and is coupled to the data providing circuit 13 through the plurality of vertical signal lines LVS, so as to receive the corresponding data voltage VDATA and the corresponding plurality of digital control signals Sdit.

The light emitting region 15 stores the received corresponding data voltage VDATA according to the corresponding shift signals (e.g., SR _1 to SR _3), and latches the received digital control signals Sdit. The light emitting region 15 determines the luminance of light emission according to the stored data voltage VDATA, and the light emitting region 15 can reduce power consumption by the latched digital control signals Sdit. In the present embodiment, the light-emitting regions 15 directly provide light for forming color images.

FIG. 5 is a system diagram of a data providing circuit according to an embodiment of the invention. Referring to fig. 4 and 5, in the present embodiment, the data providing circuit 13 includes a shift register 210, an input register 220, a data latch 230, a level shifter 240, a digital-to-analog converter 250 and a buffer 260. The shift register 210 receives the SET signal SET and the clock signal CLK to provide a plurality of trigger signals STR that are sequentially enabled according to the SET signal SET and the clock signal CLK. The input register 220 is coupled to the shift register 210 for receiving the plurality of trigger signals STR that are sequentially enabled, and for receiving a plurality of display data (e.g., red display data XDR, green display data XDG, and blue display data XDB). Then, the input register 220 latches and outputs the display data (e.g., red display data XDR, green display data XDG, and blue display data XDB) in sequence according to the plurality of trigger signals STR that are enabled in sequence.

The data latch 230 is coupled to the input register 220 and receives the latch enable signal LEN to latch and output the display data (e.g., the red display data XDR, the green display data XDG, and the blue display data XDB) received from the input register 220 according to the latch enable signal LEN. The level shifter 240 is coupled to the data latch 230 to receive the display data (e.g., the red display data XDR, the green display data XDG, and the blue display data XDB) from the data latch 230 and provide the level-shifted display data DLX and a plurality of digital control signals Sdit, wherein the digital control signals Sdit may be formed by directly outputting the display data (e.g., the red display data XDR, the green display data XDG, and the blue display data XDB).

The digital-to-analog converter 250 is coupled to the level shifter 240 to receive the level-shifted display data DLX and to receive a plurality of reference voltages Vref to convert the display data DLX into an analog level (i.e., a voltage level) and then provide an analog driving voltage VDX. The buffer 260 is coupled to the digital-to-analog converter 250 for receiving the analog driving voltage VDX and providing the data voltage VDATA accordingly.

FIG. 6 is a system diagram of a display device according to another embodiment of the invention. Referring to fig. 4 and 6, the display device 20 is substantially the same as the display device 10, except that the display device 20 further includes a display panel 21. The display panel 21 is configured with a plurality of liquid crystal pixels PX arranged in an array, and each light emitting region 15 overlaps with a portion of these liquid crystal pixels PX to supply display light to the overlapping liquid crystal pixels PX. In the present embodiment, the display panel 21 and the light emitting region 15 may share the displacement control circuit 11.

Fig. 7 is a flowchart illustrating a driving method of a light emitting region of a display device according to an embodiment of the invention. Referring to fig. 7, in the present embodiment, the driving method is used for driving a plurality of light emitting regions of the display device, each of the light emitting regions has a light emitting diode, and the driving method includes the following steps. In step S710, a data voltage is received to determine a light emitting current flowing through the light emitting diode from a driving voltage. In step S720, a plurality of digital control signals corresponding to the data voltages are received to adjust the driving voltages, wherein the driving voltages are decreased in response to the decrease of the data voltages. The sequence of steps S710 and S720 is for illustration, and the embodiment of the invention is not limited thereto. The details of steps S710 and S720 can be described with reference to the embodiments of fig. 1A, 1B, 2, 3A, 3B, and 4-6, and are not repeated herein.

In summary, the display device and the driving method of the light emitting region thereof according to the embodiments of the invention receive the plurality of digital control signals corresponding to the data voltage to adjust the driving voltage, and the driving voltage is decreased in response to the decrease of the data voltage. Therefore, when the light-emitting gray-scale value of the light-emitting region is lower, more power can be saved, and the light-emitting brightness of the light-emitting diode can be still maintained.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A display device, comprising:

a plurality of light emitting regions, each of the light emitting regions comprising:

the latch circuit receives a plurality of digital control signals corresponding to a data voltage and a displacement signal and latches the digital control signals according to the displacement signal;

a selection circuit coupled to the latch circuit for receiving the latched digital control signals and providing a plurality of selection signals, wherein the selection circuit enables one of the selection signals according to the latched digital control signals;

a voltage output circuit coupled to the selection circuit for receiving the selection signals and providing a driving voltage, wherein the driving voltage is controlled by the selection signals and decreases in response to a decrease in the data voltage;

a data transistor having a first terminal for receiving the data voltage, a control terminal for receiving the displacement signal, and a second terminal;

a driving transistor having a first terminal for receiving the driving voltage, a control terminal coupled to the second terminal of the data transistor, and a second terminal;

a capacitor coupled between the control terminal of the driving transistor and the second terminal of the driving transistor; and

and the light emitting diode is coupled between the second end of the driving transistor and a system low voltage.

2. The display device of claim 1, wherein the driving voltage is decreased to a minimum voltage level equal to or greater than a minimum voltage level for maintaining a constant light-emitting current flowing through the light-emitting diode in response to a decrease in the data voltage.

3. The display device of claim 2, wherein the driving voltage is also increased by an incremental voltage in response to a decrease in the data voltage as the minimum voltage level is decreased.

4. The display device according to claim 3, wherein the driving voltage is maintained at a maximum driving voltage when the data voltage is between a swing threshold voltage and a maximum gray scale voltage.

5. The display device according to claim 4, wherein the larger the delta voltage is, the lower the varying threshold voltage is.

6. The display device of claim 1, wherein the latch circuit comprises a plurality of latch units respectively receiving the digital control signals to provide one of the digital control signals and a corresponding inverted digital control signal.

7. The display device according to claim 6, wherein the latch units comprise:

a first inverter having an input terminal for receiving one of the digital control signals and an output terminal;

a first AND gate having a first input terminal coupled to the output terminal of the first inverter, a second input terminal receiving the displacement signal, and an output terminal;

a second AND gate having a first input terminal for receiving one of the digital control signals, a second input terminal for receiving the displacement signal, and an output terminal;

a first NOR gate having a first input terminal coupled to the output terminal of the first AND gate, a second input terminal, and an output terminal for providing one of the digital control signals;

a second NOR gate having a first input terminal coupled to the output terminal of the second NOR gate, a second input terminal coupled to the output terminal of the first NOR gate, and an output terminal coupled to the second input terminal of the first NOR gate and providing a corresponding inverted digital control signal.

8. The display device of claim 1, wherein the selection circuit comprises a plurality of transmission gates, each of which receives one of the digital control signals and a corresponding inverted digital control signal to determine whether to turn on or off, wherein a portion of the transmission gates are connected in series between an enable voltage level and a corresponding selection signal, and a portion of the transmission gates are each coupled between an output terminal of one of the transmission gates and a disable voltage level.

9. The display device according to claim 8, wherein the number of transmission gates connected in series between the enable voltage level and the corresponding selection signal corresponds to the number of digital control signals.

10. The display device of claim 8, wherein the transmission gates connected in series between an energy voltage level and the corresponding select signal respectively receive different digital control signals.

11. The display device of claim 1, wherein the voltage output circuit comprises a plurality of switching transistors each having a first terminal receiving one of a plurality of driving levels, a control terminal receiving one of the selection signals, and a second terminal coupled to the driving voltage.

12. The display device of claim 1, wherein the number of the digital control signals corresponds to one bit of a gray scale range of the data voltage.

13. The display device of claim 1, wherein the digital control signals and the data voltage are provided by a data providing circuit.

14. The display device of claim 1, further comprising a liquid crystal display panel having a plurality of liquid crystal pixels, each of the light emitting regions overlapping a portion of the liquid crystal pixels to provide display light to the overlapping liquid crystal pixels.

15. The display device of claim 1, wherein the light emitting regions directly provide light for forming a color image.

16. The display device of claim 1, wherein the light emitting diode is a sub-millimeter light emitting diode.

17. A driving method for driving a plurality of light emitting areas of a display device, each of the light emitting areas having a light emitting diode, the driving method comprising:

receiving a data voltage to determine a light-emitting current flowing through a light-emitting diode by a driving voltage;

receiving a plurality of digital control signals corresponding to a data voltage to adjust the driving voltage, wherein the driving voltage is decreased along with the decrease of the data voltage.

18. The method of claim 17, wherein the driving voltage is decreased to a minimum voltage level that maintains a constant light-emitting current flowing through the LED in response to a decrease in the data voltage.

19. The method of claim 17, wherein the driving voltage is decreased to a minimum voltage level plus an incremental voltage to maintain a constant light-emitting current flowing through the LED in response to a decrease in the data voltage.

20. The driving method according to claim 19, wherein the driving voltage is maintained at a maximum driving voltage when the data voltage is between a varying threshold voltage and a maximum gray scale voltage, wherein the varying threshold voltage is lower as the delta voltage is larger.