TWI678902B - Network system for packet processing/exchange for applications and method thereof - Google Patents

Abstract

The invention relates to a method and a system for processing and exchanging packets, comprising: a plurality of three-state shift registers storing the contents of the exchange or routing table and the mask, for comparing the three-state shift registers; Bit register and bit-serial packet corresponding contents of multiple bit-equal comparators, and multiple bit-registers storing comparison results of bit-equal comparators. Bit-registers compare results Feedback the comparison result to the next bit, and perform the AND logic gate operation on the foregoing comparison result. The table lookup process is repeated in a pipeline manner until the data position of the bit string packet to be compared ends. According to the result of the comparison, a transfer action control signal is generated along with a byte-type packet and transmitted to the switching module for processing.

Description

Network system and method for packet processing / exchange for applications

The present invention relates to a technology for processing and exchanging packets, and particularly to a system and method for processing and exchanging packets by using a three-state shift register.

At present, the switching devices in the Internet are mostly Layer 2 switches (Layer 2) switches or Layer 3 routers (Routers) in OSI (Open System Interconnection). This kind of equipment mainly processes and exchanges packets according to the media access control (MAC, Media Access Control) or Internet Protocol (IP, Internet Protocol) address, and all use the destination address as the basis for processing and exchange; The fourth layer (Layer 4) of the seven layers of OSI is the transport layer, which is mapped to the protocol layer where the IP stacking protocol is TCP and UDP; the headers of the TCP and UDP packet headers contain the port number (Port Number ), The port number can be used to distinguish data packets and their corresponding application layer (Layer 7) protocols (such as: HTTP, FTP, etc.); the fourth-layer switch uses TCP or UDP port numbers to process and exchange packets; The seven-layer switch is based on the actual data content in the IP packet. Line processing and switching; when the switches in the second to seventh layers process and exchange packets, for example, by querying the switching or routing table, the switch knows that the packet will be transmitted to the corresponding port or directly discarded.

In the method of querying the switching or routing table, the existing method is to use the processor to execute the software design, but it will have the disadvantage of slow speed when performing the table lookup function; 't care' or 'X') TCAM (ternary content addressable memory) design, although the speed of table lookup is faster, but there are still problems of high cost and power consumption.

For example, as shown in Figure 1, if you want to query the exchange or routing table, its size is the width of k bytes multiplied by n lengths (meaning that the contents of n lookup tables are compared at the same time). ), At least k * n bits of tri-state memory 11, 8 * k * n bits equal comparator 12 (logic 1 when bit comparison is equal, at this time the bit equality comparator is equivalent to XNOR logic Gates), (8 * k-1) * n two-input AND logic gates 13, and a bit-to-k byte circuit 14, an encoding circuit 15, and a switching circuit 16 The circuit for comparing the contents of the lookup table will be very large and complicated, resulting in higher TCAM cost and power consumption.

It can be seen that there are still many shortcomings in the above-mentioned conventional technology. In view of various shortcomings derived from the above-mentioned conventional technology, it is anxious to improve and innovate. After years of painstaking and meticulous research, it has finally successfully developed and completed the packet processing and exchange for applications Network system and method.

The invention provides a method for processing and exchanging packets. The method Including: storing the contents of the desired lookup table in a shift register with three states; receiving a bit string packet; synchronously inputting the bit string packet in a pipeline manner and the shift register with three states The content of the desired lookup table stored in the register into the bit equality comparator; input the first comparison result of the bit equality comparator into the bit register; enter the next bit of the bit string packet The data and the next set of desired table contents stored in the three-state shift register are transferred to the bit equality comparator to obtain a second comparison result; the second comparison result is temporarily stored with the bit The first comparison result of the controller to the AND logic gate for logical operation, and the result of the logic operation of the AND logic gate is input to the transfer action control signal encoding module through the bit register; repeat the above steps until the The bit-tandem packets are all compared, and then the transfer-action control signal encoding module generates a transfer-action control signal; the bit-serial packet is further converted into a byte-type by a bit-to-byte circuit Packet and save Buffer; and transmitting the packet type and the byte transfer operation control signal to the switching module.

The present invention further provides a system for processing and exchanging packets. The system includes: a plurality of three-state shift registers, each of which stores the contents of a desired look-up table; a plurality of bit-equal comparators, which are respectively connected to The plurality of three-state shift registers; a plurality of AND logic gates, the first inputs of which are respectively connected to the plurality of bit equality comparators; the plurality of bit registers, whose input ends are respectively connected to the plurality of bit registers; Multiple AND logic gates and the output of each bit register are connected to the second input of the corresponding AND logic gate and connected to the transfer action control signal encoding module; a bit string packet is connected to the Multiple bit equality comparators; wherein the bit serial packet and each The contents of the desired lookup table stored in the three-state shift register are synchronously input to the corresponding bit equality comparator in a pipeline manner, and the corresponding bit equality comparator outputs the first comparison result to the corresponding bit. AND logic gate to the corresponding bit register, the next bit data of the bit serial packet, and the next set of desired table contents stored in the corresponding three-state shift register. Input to the corresponding bit equality comparator to obtain a second comparison result; the second comparison result and the first comparison result of the bit register are respectively input to the first input of the corresponding AND logic gate And the second input to input the logical operation result of the AND logic gate to the transfer action control signal encoding module through the corresponding bit register, and the comparison is completed when the bit serial packet is completed At the same time, the transfer action control signal encoding module is caused to generate a transfer action control signal; a bit-to-byte circuit is connected to the bit-sequential packet to convert the bit-serial packet into a byte Packet and store in buffer ; And a switching module connected to the transferring operation control signal encoding module and in the buffer to receive the operation control signals and byte packet type.

In the foregoing method or system, the content of the desired lookup table is the content of the desired lookup mask of the switches or routers in the second to seventh layers of the open system interconnection.

In the foregoing method or system, the contents of the desired lookup table of the switches or routers in the second to seventh layers of the open system interconnection are manually entered and received from other second to seventh layers. Switches or routers, or automatically learned by the switches or routers in the second to seventh layers.

In the foregoing method or system, the second to seventh layer switches Or the length of the mask content of the router's desired lookup table is variable and the part that does not need to be compared is preset as a mask.

In the foregoing method or system, the three-state shift register is a cyclic shift register, wherein the last bit of the serial output terminal of the cyclic shift register is connected to the serial input terminal. First bit.

In the foregoing method or system, the buffer is a non-synchronous first-in-first-out buffer and only stores byte data of a set of longest address packets.

In the foregoing method or system, after the comparison of the bit string packet is completed, at the same time, the switching module reads the byte packet in the buffer and the transfer action of the transfer action control signal encoding module. Control signal.

In the foregoing method or system, the initial value of the bit register is preset to 1.

The purpose of the present invention is to provide a system and method for packet processing and switching for applications, which improves the execution speed and the complexity of the TCAM circuit when the switching equipment in the Internet needs to query the switching or routing table. The table lookup speed of TCAM can be simpler and consume less power than the circuit of TCAM.

11‧‧‧ tri-state memory

12‧‧‧bit equality comparator

13‧‧‧AND logic gate

14‧‧‧bit to k byte circuit

15‧‧‧coding circuit

16‧‧‧Switch circuit

21‧‧‧ Three-state shift register

22‧‧‧bit tandem packets

23‧‧‧bit equality comparator

24‧‧‧AND logic gate

25‧‧‧bit register

26‧‧‧bit transposition circuit

27‧‧‧Buffer

28‧‧‧Transfer motion control signal coding module

29‧‧‧Switch Module

S01 ~ S06‧‧‧step

Please refer to the detailed description of the present invention and the accompanying drawings to further understand the technical content and the purpose and effect of the present invention. The related drawings are as follows: FIG. 1 is a schematic diagram of an existing TCAM circuit architecture.

FIG. 2 is a schematic routing diagram of a system for processing and exchanging packets according to the present invention.

FIG. 3 is a schematic diagram of a packet comparison process according to the present invention.

The present invention provides a method and system for processing and exchanging packets, which are directed to packet comparison applied between a network device and a packet it receives. The method mainly includes: storing the contents of a switching or routing table and a mask. Multiple shift registers 21 having three states (0, 1, and the third state "Don't care" or "X"), for comparing the shift registers 21 having three states with bits A plurality of bit equality comparators 23 corresponding to the contents of the tandem packet 22, and a plurality of bit registers 25 that store the comparison results of the bit equality comparator 23, and the bit register 25 returns the comparison results to The comparison result of the next bit, and the foregoing comparison result is executed by the AND logic gate 24. The packet comparison procedure is repeated in a pipeline manner until the end of the data position of the bit string packet 22 to be compared Then, according to the comparison result, a transfer action control signal is generated together with a byte-type packet, and then transmitted to the switching module 29 for processing.

As shown in FIG. 2, the system for processing and exchanging packets according to the present invention includes: a plurality of shift registers 21 having three states, each of which stores the contents of a table to be looked up; a plurality of bit equality comparators 23, which are respectively connected to the plurality of three-state shift registers 21; a plurality of AND logic gates 24, whose first inputs are respectively connected to the plurality of bit equality comparators 23; Device 25, whose initial value is preset to 1 and whose input terminals are respectively connected to the AND logic gates 24 and the output terminals of the bit registers 25 are feedback-connected to the second input of the corresponding AND logic gate 24 and Connected to the transfer action control signal encoding module 28; bit-sequential packet 22, which is connected to the multiple bit-equal comparators 23; bit-to-byte circuit 26, which is connected to the bit string Type packet 22 for converting the bit-tandem packet 22 into a byte-type packet and storing it in the buffer 27; and a switching module 29 connected to the transfer action control signal encoding module 28 and the buffer The processor 27 receives the motion control signal and the byte-type packet.

The bit tandem packet 22 and the desired look-up table contents stored in the three-state shift register 21 are simultaneously input to the corresponding bit equality comparator 23 in a pipeline manner, and the corresponding bit The bit equality comparator 23 outputs the first comparison result through the corresponding AND logic gate 24 to the corresponding bit register 25, the next bit data of the bit serial packet 22 and the corresponding bit data having three The content of the next set of desired table stored in the state shift register 21 is input to the corresponding bit equalizer 23 to obtain a second comparison result; the second comparison result and the bit register The first comparison result of 25 is input to the first input and the second input of the corresponding AND logic gate 24 to input the result to the transfer action control signal code through the corresponding bit register 25. Module 28. When the bit serial packets are all compared, the transfer action control signal encoding module 28 generates a transfer action control signal.

As shown in FIG. 2, in order to improve the execution speed when the switching equipment in the Internet needs to query the switching or routing table and the complexity of the TCAM circuit, the present invention provides a table lookup speed that can reach TCAM and is more than the circuit of TCAM. Simple and low power consumption, referring to Table 1 below, it is stored in the three-state shift register 21, and the storage method is to look up the table contents in the second to seventh layers (that is, The contents of the lookup table) (e.g. the contents of the lookup tables in the second to seventh layers -n) are stored in each of the three-state shift registers. In the register 21, when the corresponding contents of the lookup mask of the second to seventh layers (for example, the content of the lookup mask of the second to seventh layers -n) are set, the The relative bit position of the register 21 will be set to the third state "X", which means that this bit (for example, bit -m) does not need to be compared, and the corresponding transfer action (for example, transfer action -n) It is stored in the transfer motion control signal coding module 28. When the data position of the bit string packet 22 to be compared is reached (a control circuit not shown in the figure), the bit equality comparator 23 is sequentially synchronized in a pipeline manner, and the comparison result is stored in the bit register 25 The initial value of the bit register 25 is set to logic 1 in advance (that is, logic 1 is assumed when bit comparisons are equal), otherwise the subsequent comparison results will continue to be logic 0; when the next bit data arrives, check The shift register 21 storing the contents of the table is shifted by one bit at the same time. At this time, it also enters the bit equality comparator 23 and compares the result with the previous bit (that is, the feedback signal of the bit register 25) and executes The operation of the AND logic gate 24 is repeated until the data position of the bit tandem packet 22 to be compared ends, and then a transfer operation control signal is generated according to the result of the table lookup operation; at the same time, the bit tandem to be compared The packet 22 is converted into a byte-type packet by the bit-to-byte circuit 26 and then stored in the buffer 27; as the comparison is completed, the byte-type packet and the transfer action control signal encoding module 28 generate Forwarding motion control message It will be transmitted to the switching module 29, for processing or switching to the next port.

Referring to Figure 2, assuming that the size of the exchange or routing table to be queried is m bit widths multiplied by n lengths (that is, it can be compared with the contents of n lookup tables at the same time), only the circuit required There are m * n bits with tri-state shift register 21, n bits equal comparator 23 (assuming that the bit comparison is equal to logic 1, at this time the bit equality comparator is equivalent to XNOR logic gate), If n two-input AND logic gates 24 and n bit registers 25, if m = 8 * k (assuming the same width as the look-up table used by the existing technology), it can be reduced by (8 * k -1) * n bit-equal comparators 23 and (8 * k-2) * n two-input AND logic gates 24, and there is no need to use bit-to-k-bit circuit module, although it still increases The n bit registers 25 are, in fact, the circuit complexity of the present invention is still lower than the traditional TCAM circuit, especially when the value of k is larger.

In the embodiment provided by the present invention, the content of the desired table lookup may be the content of the desired table cover of the switches or routers in the second to seventh layers of the open system interconnection, and the desired table cover The content can be manually entered, received from other switches or routers in the second to seventh layers, or automatically learned by the switches or routers in the second to seventh layers. The length of the mask content to be looked up is The part that is variable and does not need to be compared is a mask; the shift register 21 with three states is a cyclic shift register. The last bit of the serial output must be connected to the serial input. One bit to realize its cyclic function; the transfer action of the transfer action control signal can be manually input, received by other switches or routers of the second to seventh layers, or obtained by the machine itself; in addition, the comparison The bit tandem packet 22 is connected to all bit equality comparators 21 to compare all the contents of the exchange or routing tables and masks at the same time.

The configuration between the AND logic gate 24 and the bit register 25 of the present invention is such that the output of the bit register 25 is connected back to the input of the AND logic gate 24 and temporarily stored with the three-state shift. After the AND terminal performs the AND logic operation, the output terminal of the AND logic gate 24 is then connected to the input terminal of the bit register 25 to complete the serial cumulative comparison work. In addition, the buffer 27 is asynchronously advanced. First-in (First In, First Out) buffer, which can store only the byte data of the longest IP packet. Furthermore, the data of the bit string packet 22 is transferred to the table while completing the table lookup and comparison. The motion control signal encoding module 28 also forwards the motion control signals synchronously to the switching module 29, and the switching module 29 also reads the byte-type packets with the IP packets in the buffer 27 for subsequent processing.

Refer to Figure 3, which is a flowchart illustrating packet comparison. A bit-tandem packet enters the S01 bit equality comparator; the header or payload S02 of the bit-tandem packet is retrieved according to the application method; S03 is sequentially compared with the contents of the look-up table stored in the three-state shift register to judge S03; if it does not match, execute the pre-forward action or discard the packet S04; if it matches, it generates the transfer action control signal S05 , And send the packet to the switching module S06.

Compared with other conventional technologies, the method and system for processing and exchanging packets provided by the present invention have the following advantages:

1. The present invention can achieve the TCAM look-up table speed through a simple and repetitive circuit architecture, and the circuit is more simplified and the power consumption is smaller than that of the TCAM.

2. The present invention can be safely applied to various types of network equipment (for example, switches or routers from the second layer to the seventh layer).

The above content is a detailed description of the feasible specific embodiments of the present invention, but this embodiment is not intended to limit the patent scope of the present invention. Any equivalent implementation or change that does not depart from the technical spirit of the present invention should be included in this case. Within the scope of patents.

To sum up, this case is not only technically innovative, but also enhances the above-mentioned multiple effects over conventional items. You should apply for a legal invention patent element that is fully in line with novelty and progress, and apply in accordance with the law. We ask your office to approve this document. Application for invention patents, to encourage inventions, to the sense of virtue.

Claims (16)

A method for processing and exchanging packets. The method includes: storing the contents of the desired table in a three-state shift register; receiving a bit string packet; and synchronously inputting the bit string in a pipeline manner. Type packet and the content of the desired table stored in the three-state shift register to a bit equality comparator; input the first comparison result of the bit equality comparator to the bit register; enter The next bit data of the bit serial packet and the next set of desired table contents stored in the three-state shift register to the bit equality comparator to obtain a second comparison result; Input the second comparison result and the first comparison result of the bit register to an AND logic gate to perform a logical operation, and the operation result of the logical operation of the AND logic gate is input to the transfer through the bit register. Motion control signal encoding module; repeat the above steps until the bit-tandem packet has completed the comparison, and then cause the transfer motion control signal encoding module to generate a transfer motion control signal; the bit-tandem packet additionally transmits bits turn Tuple circuit is converted into packets and bytes formula stored in a buffer; and transmitting the packet type and the byte transfer operation control signal to the switching module. The method according to item 1 of the scope of patent application, wherein the content of the desired lookup table is the content of the desired lookup mask of the switches or routers in the second to seventh layers of the open system interconnection. The method according to item 2 of the scope of patent application, wherein the contents of the desired table mask of the switches or routers in the second to seventh layers of the open system interconnection are manually entered and received from other second The switches or routers from the layer to the seventh layer, or automatically learned by the switches or routers from the second layer to the seventh layer. The method as described in item 2 of the scope of the patent application, wherein the length of the desired lookup table mask content of the switches or routers of the second to seventh layers is variable and it does not need to be compared. For the mask. The method according to item 1 of the scope of patent application, wherein the three-state shift register is a cyclic shift register, and the last bit of the serial output terminal of the cyclic shift register is Connected to the first bit of the serial input. The method according to item 1 of the scope of patent application, wherein the buffer is a non-synchronous first-in-first-out buffer and stores only a set of byte data of the longest address packet. The method according to item 1 of the scope of patent application, wherein after the comparison of the bit string packet is completed, the switching module simultaneously reads the byte packet and the transfer action control signal code in the buffer. The module forwards the motion control signal. The method according to item 1 of the scope of patent application, wherein the initial value of the bit register is preset to 1. A system for processing and exchanging packets. The system includes: a plurality of three-state shift registers, each of which stores the contents of a desired lookup table; a plurality of bit equality comparators, which are respectively connected to the plurality of Three-state shift register; multiple AND logic gates, the first inputs of which are respectively connected to the multiple bit equality comparators; multiple bit registers, whose input terminals are respectively connected to the multiple ANDs The logic gate and the output end of each bit register are connected to the second input of the corresponding AND logic gate and connected to the transfer motion control signal encoding module; the bit string packet is connected to the multiple bits Element equality comparator; wherein the bit serial packet and the desired table contents stored in each of the three-state shift registers are synchronously input to the corresponding bit equality comparator in a pipeline manner. , The corresponding bit equality comparator outputs the first comparison result to the corresponding bit register via the corresponding AND logic gate, the next bit data of the bit string packet and the corresponding bit data Next set stored in the shift register The content of the table to be checked is input to the corresponding bit equality comparator to obtain a second comparison result, and the second comparison result and the first comparison result of the bit register are respectively input to the corresponding AND logic gates. The first input and the second input are input to the transfer action control signal encoding module through a result of performing a logical operation on the AND logic gate through the corresponding bit register, and when the bit serial packet When the comparison is completed, the transfer action control signal encoding module is caused to generate a transfer action control signal; a bit-to-byte circuit is connected to the bit-sequential packet to convert the bit-serial packet It is a byte-type packet and stored in a buffer; and a switching module connected to the transfer action control signal encoding module and the buffer to receive the action control signal and the byte-type packet. The system according to item 9 of the scope of patent application, wherein the content of the desired lookup table is the content of the desired lookup mask of the switches or routers in the second to seventh layers of the open system interconnection. The system according to item 10 of the scope of patent application, wherein the contents of the desired lookup table of the switches or routers in the second to seventh layers of the open system interconnection are manually entered and received from other second The switches or routers from the layer to the seventh layer, or automatically learned by the switches or routers from the second layer to the seventh layer. The system according to item 10 of the scope of the patent application, wherein the length of the desired lookup table mask content of the switches or routers of the second to seventh layers is variable and it is preset without any comparison For the mask. The system according to item 9 of the scope of patent application, wherein each of the three-state shift registers is a cyclic shift register, wherein the last bit of the serial output terminal of the cyclic shift register Is connected to the first bit of the serial input. The system according to item 9 of the scope of patent application, wherein the buffer is a non-synchronous first-in-first-out buffer and stores only a set of byte data of the longest address packet. The system according to item 9 of the scope of patent application, wherein the switching module synchronously reads the byte-type packet in the buffer and the forwarding action control signal of the forwarding action control signal encoding module. The system according to item 9 of the scope of patent application, wherein the initial value of the bit register is preset to 1.