JP4879728B2 - Search device and data processing device - Google Patents

Description

  The present invention relates to a search device capable of continuing search without interrupting search processing when a search database is updated, and a data processing device including the search device.

  Search processing is used in various fields in a wide range of fields, such as packet routing and detection of malicious code in packets in the communication field, and pattern detection from large amounts of data in the information analysis field. ing. In particular, with the recent increase in the amount of data and the sophistication of processing in the entire information communication field, search processing requires processing with high speed, multi-functionality, and intelligence. There is a need to do it on demand and dynamically.

  For example, Patent Document 1 discloses a semiconductor integrated circuit that realizes a binary search using a semiconductor memory, and starts a binary search in response to a decrease in the number of effective search target data stored in the memory. By providing means for appropriately determining the address on the semiconductor memory, the number of processing cycles required for the search is reduced and high-speed search processing is realized.

  In Non-Patent Document 1, it is pointed out that execution of updating a table at the time of searching becomes difficult depending on the data structure used in the table, taking a binary search using a binary search table as an example. For example, when adding or deleting items in a table, it is necessary to rearrange the entire table. When updating such a table, items are moved or changed. Performing a search becomes difficult. And two methods are proposed as the avoidance method. That is, the first method is a method in which the update process is postponed until a period when the search process is small, and the search is stopped while the table update process is being performed. In the second method, two tables are prepared, one table is used for search, and the other is used for update, and the table is updated in the background. Then, when the table update is completed, the two tables are exchanged.

JP 2000-250737 A By Rich Seifert, translated by Akira Mamiya, "LAN switching thorough commentary", published by Nikkei Business Publications, August 6, 2001, P83-84

  However, according to the prior art described in Patent Document 1, it is necessary to temporarily stop the input of search data when updating the search database entry. Therefore, there has been a problem that non-stop search processing cannot be realized at the time of entry update.

  Further, according to the prior art described in Non-Patent Document 1, it is necessary to stop the search process when performing the table update process (see the first method). Therefore, there was a problem that the search performance suddenly deteriorated. In the second method of preparing two tables, if the data structure used in the table is a tree structure like a binary search tree, if the tables are exchanged during the search process, Data that is being searched based on the tree structure of the table is suddenly applied to the tree structure of the new table, and an incorrect search result is returned. In this way, during the search, there is a problem that the data being searched with the old table information cannot be transferred with the new table information.

  The present invention has been made in view of the above, and an object of the present invention is to provide a search device and a data processing device capable of continuing a search process without stopping the search process even when an entry of a search database is updated. To do.

  In order to solve the above-described problems and achieve the object, a search processing apparatus according to the present invention is a search apparatus that searches a search database stored in a memory using a search key as an input and outputs a search result. The search processing circuit of the preceding stage where the search key is input and the subsequent stage of the search processing circuit of the preceding stage, and sequentially performing the search processing based on the search processing result of the search processing circuit of the preceding stage 1 or A plurality of subsequent search processing circuits, a part of the search database for searching by the previous search processing circuit, and a previous operation memory provided corresponding to the previous search processing circuit; The standby memory provided in a pair with the operation memory of the preceding stage and waiting until the search database is updated and the remainder of the search database are stored as a whole. Each of the subsequent-stage search processing circuits stores data to be searched, and the subsequent-stage operation memory provided corresponding to each of the subsequent-stage search processing circuits, and the respective subsequent-stage operation memories. And a standby memory in a subsequent stage that waits until the search database is updated, and a standby memory in the previous stage and each subsequent stage by writing the updated search database when the search database is updated. A memory update circuit that updates the contents of the memory, and a memory that is searched by the search processing circuit in the previous stage based on an update notification from the memory update circuit, from the previous operation memory to the previous standby memory. Based on the update notification from the selection circuit and the memory update circuit, the memory to be searched by the search processing circuit in each subsequent stage is set as the memory in each subsequent stage. A post-stage selection circuit that switches from the main memory to each of the subsequent standby memories, and the search processing time required for the search process of the pre-stage search processing circuit is searched by each of the post-stage search processing circuits. It is characterized by being longer than the search processing time required for processing.

  According to the present invention, the search processing circuit required for the search processing in the preceding stage is configured to be longer than the search processing time required for the search processing in the subsequent search processing circuit. Based on the above, the memory to be searched by the search processing circuit in the previous stage is switched from the operation memory in the previous stage to the standby memory in the previous stage, and the time during which data being searched from the search processing circuit in the previous stage is not input to the search processing circuit in the subsequent stage By switching the memory searched by the subsequent search processing circuit from the subsequent operation memory to the subsequent standby memory, the search database can be updated without stopping the search operation even during the search operation. can do.

  Embodiments of a search device and a data processing device according to the present invention will be described below in detail with reference to the drawings. The present invention is not limited to the embodiments described below.

Embodiment 1 FIG.
FIG. 1 is a diagram showing a network configuration using a first embodiment of a search device according to the present invention. In this embodiment, a router as a data processing device and a search device mounted on the router are described as examples. However, the application field of the present invention is not limited to the communication field.

  As shown in FIG. 1, the network of this embodiment includes a router 1, a PC (Personal Computer) terminal 2, the Internet 3, a server group 4, an access point 5, a wireless terminal 6, an intranet 7, a control PC 8, and a control link 9. , And a link 10. The router 1 is connected to the Internet 3, the intranet 7, and the server group 4 through links 10, and transfers packets between networks. The access point 5 is connected to the Internet 3 or the intranet 7 via a link 10. The PC terminal 2 performs mutual communication between the terminals via the link 10 and the wireless terminal 6 via the access point 5. The control PC 8 is connected to the router 1 via the control link 9 and transmits data for updating the database to the router 1.

  FIG. 2 is a diagram illustrating a functional configuration example of the router 1 illustrated in FIG. 1. As shown in FIG. 2, the router 1 includes a transmission / reception unit 11, a transfer unit 12, a device 13, an external memory 14, and a controller 15. The transmission / reception unit 11 and the transfer unit 12 are connected by a transfer path 21, and the transfer unit 12 and the device 13 are connected by a search path 22, and the device 13, the external memory 14, and the controller 15 are each connected to an external bus connection line. 24 is connected to the external bus 23.

  Next, the function of each component will be described. The transmission / reception unit 11 is connected to the Internet 3, the server group 4, and the intranet 7 via links 10. FIG. 3 is a diagram showing a format of an Ethernet (registered trademark) frame. The transmission / reception unit 11 receives an IPv4 (Internet Protocol Version 4) packet 27 obtained by removing a MAC (Media Access Control) header 26 and an FCS (FRAMe Check Sequence) 28 from the Ethernet (registered trademark) frame 25 shown in FIG. Is transferred to the transfer unit 12, and the MAC header 26 and FCS 28 are added to the IPv4 packet 27 sent from the transfer unit 12 and transmitted to the link 10.

  The transfer unit 12 extracts data (hereinafter referred to as a search key) necessary for search processing for obtaining routing information necessary for transfer of the frame from the received frame, and searches the device 13 via the search path 22. Send the key. Also, a search result (routing information) is received from the device 13 via the search path 22, and the received frame is transferred to the transmission / reception unit 11 via the transfer path 21 based on the search result.

  In the present embodiment, the header information extracted by the transfer unit 12 and from which the search key is extracted includes the destination / source address, protocol, total length, identifier, flag, and fragment offset included in the network layer header. And a destination / source port number and a sequence number (only in the case of TCP) included in the header of the transport layer. Hereinafter, the search key will be described with reference to FIGS.

  In the following example, the protocol used in the network layer is assumed to be IPv4, and the protocol used in the transport layer is assumed to be TCP (Transmission Control Protocol) or UDP (User Datagram Protocol), but is not limited thereto. For example, the protocol used in the network layer may be IPv6 (Internet Protocol Version 6), and the protocol used in the transport layer may be RDP (Remote Desktop Protocol).

  As shown in FIG. 3, the IPv4 header 29, the TCP header 30, and the UDP header 31 are encapsulated in an Ethernet (registered trademark) frame 25.

  FIG. 4 is a diagram showing a format of an IPv4 header which is a header of the network layer. The TOS (Type of Service) field 32 in the third byte from the beginning of the IPv4 header, the total length 33 in the fourth byte, the identifier 34 in the fifth byte, and the upper three bits in the seventh byte are flags (Flag) 35, the lower 5 bits of the 7th byte and the 8th byte are a fragment offset (Fragment Offset) 36, the protocol (Protocol) 37 in the 10th byte, the source IP address (Source Address) 38 in the 13th byte, A destination IP address (Destination Address) 39 is located at the 17th byte.

  FIG. 5 is a diagram illustrating a format of a TCP header that is a header of the transport layer. Source port number 40 at the first byte from the beginning of the TCP header, destination port number 41 at the third byte, sequence number 42 at the fifth byte, and confirmation response at the ninth byte A number (Acknowledgement Number) 43 is located.

  FIG. 6 is a diagram illustrating a format of a UDP header that is a header of the transport layer. A source port number (Source Port) 44 is located in the first byte of the UDP header, and a destination port number (Destination Port) 45 is located in the third byte.

  In this embodiment, the case where an Ethernet (registered trademark) frame is used as a packet trailer has been described. However, the present invention is not limited to this. For example, the present invention can be similarly implemented when ATM (Asynchronous Transfer Mode) or FDDI (Fiber-Distributed Data Interface) is used.

  Moreover, the item of said search key is an example, and if it is the information which can search routing information, it will not restrict to this. Depending on the search method and protocol, some of the search key information items may not be used, and items other than the above (for example, a VLAN (Virtual Local Area Network) ID that is a field for identifying a flow). May be included.

  The device 13 acquires the database stored in the external memory 14 via the external bus 23 and the external bus connection line 24, and performs a search process on the database based on the search key sent from the search path 22. Then, routing information is obtained as a search result. Then, the device 13 notifies the transfer unit 12 of the search result via the search path 22.

  The external memory 14 stores a database sent from the control PC 8 via the control link 9. The database is used to search routing information using a search key, and includes a correspondence between the search key and routing information.

  The controller 15 converts data from the outside of the router 1 sent from the control PC 8 via the control link 9 into a data format used by the external bus 23 in the router 1.

  FIG. 7 is a diagram showing an internal configuration of the device 13 in FIG. 2, and the device 13 is a search device according to the present embodiment. As illustrated in FIG. 7, the device 13 according to the present embodiment includes a search processing circuit 51 that is a search processing circuit in the preceding stage having a search function, a search processing circuit 52 that is a search processing circuit in the subsequent stage having a search function, and a search. The processing circuit 53 is connected to the internal RAM 57, the internal RAM 58, the internal RAM 59, and the internal RAM 60 on the operation side, the internal RAM 61, the internal RAM 62, the internal RAM 63, and the internal RAM 64 on the standby side, and these internal RAM groups. A RAM update circuit 65 that updates the contents of the internal RAM group on the standby surface in response to a search database update request, and a RAM selection circuit 54 that is connected to the internal RAM 58 and the internal RAM 62 and selects the internal RAM to be connected. A RAM that is connected to the built-in RAM 59 and the built-in RAM 63 and selects a built-in RAM as a connection destination A selection circuit 55, a RAM selection circuit 56 that is connected to the built-in RAM 60 and the built-in RAM 64 and selects a built-in RAM as a connection destination, an update notification from the RAM update circuit 65, a search processing circuit 51, a RAM selection circuit 54, a RAM selection circuit 55 and a notification line 66 for notifying the RAM selection circuit 56. The search processing circuit 51 is connected to the internal RAM 57 and the internal RAM 61, the search processing circuit 52 is connected to the RAM selection circuit 54, and the search processing circuit 53 is connected to the RAM selection circuit 55 and the RAM selection circuit 56, respectively. Next, details of each component will be described.

  A search database is divided and stored in the internal RAM 57, the internal RAM 58, the internal RAM 59, and the internal RAM 60 on the operation side, and search processing is performed by accessing these internal RAM groups. The contents of the internal RAM 57, the internal RAM 58, the internal RAM 59, and the internal RAM 60 on the standby surface are updated when the search database is updated, and the updated search database is stored.

  FIG. 8 is a diagram showing an internal configuration of the search processing circuit 51. As shown in FIG. 8, the search processing circuit 51 is a selection circuit 77 that selects an output destination of a search key input from the search path 22 from two read address generation units, and one output destination of the selection circuit 77. A read address generation unit 71 that generates a read destination address in the internal RAM 57 based on the search key output from the selection circuit 77 or the output from the latch 71, and sends the read destination address to the internal RAM 57; The read data receiving unit 72 that receives the data of the read destination address in the internal RAM 57 and compares the search key with the data of the read destination address, and the read data receiving unit 72 when accessing the internal RAM 57 again. The reception data obtained in this way is temporarily waited, and this reception data is read to the address generation unit 71. It includes a latch 73, the that.

  Further, as shown in FIG. 8, the search processing circuit 51 includes a read address generation unit 74 that is the other output destination of the selection circuit 77, a read data reception unit 75 and a latch 76 connected to the read address generation unit 74. And a multiplexing circuit 78 that receives search processing results from the read data receiving unit 72 and the read data receiving unit 75 and outputs the result to the search processing circuit 52 in the subsequent stage.

  Next, the read address generating unit 74, the read data receiving unit 75, and the latch 76 will be described. As shown in FIG. 7, the built-in RAM 57 is now in operation and the built-in RAM 61 is in standby. Here, the operation side refers to a built-in RAM that receives the address of the reading destination from the search processing circuit and outputs the data of the corresponding address, and the standby side is input with the address of the reading destination from the search processing circuit. This indicates that the internal RAM is not. Therefore, when the built-in RAM 61 changes from the standby side to the operational side, the selection circuit 77 selects the read address generation unit 74 as the output destination of the search key, and the read address generation unit 74, the read data reception unit 75, and the latch 76 perform the respective processes. The search database stored in the internal RAM 61 is searched. This search process is the same as the search process based on the read address generation unit 71, the read data reception unit 72, and the latch 73 described above. The selection processing circuit 77 is connected to the notification line 66, and selects a read address generation unit in accordance with an update notification from the RAM update circuit obtained via the notification line. As described above, in the present embodiment, the search processing circuit 51 includes the read address generation unit 71, the read data reception unit 72, and the latch 73, the read address generation unit 74, the read data reception unit 75, And a search processing circuit having a latch 76 and two search processing circuits.

  FIG. 9 is a diagram showing a circuit configuration inside the search processing circuit 52. As shown in FIG. 9, the search processing circuit 52 receives the search processing result of the search processing circuit 51, generates a read destination address in the built-in RAM based on the input data, and stores the read destination address in the RAM. The read address transmission unit 81 to be transmitted to the selection circuit 54 and the data of the read destination address sent from the RAM selection circuit 54 are received, the search key is compared with the data of the read destination address, and the search processing result And a read data receiving unit 82 that outputs the data to the search processing circuit 53. Since the RAM selection circuit 54 selects an internal RAM in terms of operation, in the example shown in FIG. 7, the internal RAM 58 is accessed to acquire data at a read destination address.

  FIG. 10 is a diagram showing a circuit configuration inside the search processing circuit 53. As shown in FIG. 10, the search processing circuit 53 receives the search processing result of the search processing circuit 52, and based on this input data, generates a read destination address in the built-in RAM, A selection circuit 85 for sending the read destination address sent from the read address transmission unit 83 to the RAM selection circuit 55 or the RAM selection circuit 56 and the data sent from the RAM selection circuit 55 or the RAM selection circuit 56 are multiplexed. And a multiplexing circuit 86 for outputting and a reading data receiving unit 84 for receiving the data of the reading destination address outputted from the multiplexing circuit 86 and outputting the retrieval processing result to the retrieval path 22. Yes. Since the RAM selection circuit 55 and the RAM selection circuit 56 select the built-in RAM on the operation side, respectively, in the example shown in FIG. 7, the internal RAM 59 and the internal RAM 60 are accessed to acquire the data of the read destination address.

  The RAM update circuit 65 is a circuit that writes entry data sent via the external bus 23 to the internal RAM group serving as a standby surface when the search database is updated. In FIG. 7, the standby surfaces are the internal RAM 61, the internal RAM 62, the internal RAM 63, and the internal RAM 64. Further, the RAM update circuit 65 notifies the search processing circuit 51, the RAM selection circuit 54, the RAM selection circuit 55, and the RAM selection circuit 56 of the entry change via the notification line 66.

  In this embodiment, as shown in FIG. 7, the built-in RAM having two-port input / output is used. However, the present invention is not limited to this, and the built-in RAM having other input / output modes is used. Can also be used.

  Next, the data structure of the search database and how the search database is stored in the built-in RAM 57, built-in RAM 58, built-in RAM 59, and built-in RAM 60, which are operational aspects, will be described. The data structure of the search database in the present embodiment is, for example, a tree structure of a binary search tree. FIG. 11 is a diagram showing an example of the data structure of the search database used in the present embodiment and how the tree constituted by the entry data is constructed in the built-in RAM. As shown in FIG. 11, the entry data at the depth 0 to the entry data at the depth 4 which are the starting points of the binary search are shown. The entry data is indicated by black circles, and the relationship between the entry data is indicated by a straight line connecting them. In the built-in RAM 57, tree information from depth 0 to depth 2 is registered. In the built-in RAM 58, tree information at depth 3 is stored. In the built-in RAM 59, the left half of the tree information at depth 4 is stored in the built-in RAM 60. Then, the right half of the tree information of depth 4 is registered.

  Thus, in the present embodiment, the entire data structure of the tree is not stored in one large RAM, but is stored in a plurality of small RAMs divided into tree hierarchies. In particular, the upper RAM stores the upper data of the tree structure including the starting point of the tree structure (that is, data having a shallow depth), and the lower RAM stores the lower data (that is, the depth) of the tree structure. Data) are sequentially stored, and the number of data stages stored in the subsequent RAM is reduced to one, thereby reducing the number of data stages stored in the previous RAM from three. With such a structure, for example, when only the entry data at the deepest part of the tree is changed, it is only necessary to rewrite the internal RAM (the internal RAM 59 and the internal RAM 60) that holds the change data. It can be reflected at high speed.

  As shown in FIG. 9, the internal configuration of the search processing circuit 52 corresponds to the structure of data (depth 3 tree information) stored in the internal RAM 58 that the search processing circuit 52 accesses for search. Thus, the internal RAM 58 is accessed once and the search processing result is output. The internal configuration of the search processing circuit 53 is the same, and the search processing circuit 53 has an internal configuration in which the internal RAM 59 or the internal RAM 56 is accessed once and the search processing result is output. On the other hand, the search processing circuit 51 is provided with latches 73 and 74 so that data from depth 0 to depth 2 can be repeatedly accessed and searched for each depth. The timing for the next access of data to the memory is adjusted, and loop processing is performed.

  In the present embodiment, the binary search tree is used as the data structure of the search database. However, the present invention is not limited to this, and embodiments using other data structures can be configured.

  Next, the operation of the present embodiment will be described. Here, it is assumed that a search database with arbitrary entries is constructed in the internal RAM 57, the internal RAM 58, the internal RAM 59, and the internal RAM 60.

  First, operations of the search processing circuit 51, the search processing circuit 52, and the search processing circuit 53 at times other than when the search database is updated will be described with reference to FIGS. First, a search key is input to the device 13 via the search path 22, and this search key is input to the search processing circuit 51.

  The search key input to the search processing circuit 51 is sent by the selection circuit 77 to the read address generation unit 71 that can access the built-in RAM 57 on the operation side. Here, the selection information between the operation side and the standby side is notified from the RAM update circuit 65 to the selection circuit 77 via the notification line 66. The read address generation unit 71 receives the input of the search key, generates a read destination address in the internal RAM 57, and sends this read destination address to the internal RAM 57. Then, the read data receiving unit 72 acquires the data of the read destination address sent from the built-in RAM 57. The read data receiving unit 72 compares the search key with the acquired data at the read destination address, and if no search result corresponding to the search key is obtained, the internal RAM 57 is further accessed to continue the search process. To do. That is, the latch 73 waits for the data obtained from the read data receiving unit 72, and then the read address generation unit 71 determines the next read destination based on the data of the read destination address output from the latch 73. And the read destination address generated again is sent to the built-in RAM 57. Then, the read data receiving unit 72 acquires the data of the read destination address sent from the built-in RAM 57. Such an operation is repeated a plurality of times according to the structure of the search key and the database to be searched (the number of data stages stored in the RAM, etc.), and the data at the read destination address is sent to the search processing circuit 52 as the search processing result. Output. As shown in FIG. 11, since the internal RAM 57 stores entry data having a tree structure up to a depth of 2, the search processing circuit 51 generally uses the data acquired by the read data receiving unit 72. An operation of generating a reading destination address and reading data at the corresponding address is performed twice.

  12A is a timing chart illustrating processing timings in the selection circuit 77, the read address generation unit 71, the read data reception unit 72, and the multiplexing circuit 78 in FIG. FIG. 12A shows a case where the processing delay of each unit and the read time from the built-in RAM are set to one clock. In order to search up to a tree depth of 2 and prevent collision between looped data and input data, a search key is input every 8 clocks. That is, the search processing circuit 51 takes 8 clocks from the input of the search key until the multiplexing circuit 78 obtains the search processing result. In FIG. 12A, the generation of the address at the depth 0 and the acquisition process of the data of the address are not included, and the entry data and the search key at the depth 0, which are the starting points of the search of the binary search tree, It is assumed that the comparison is performed without generating an address. The generation of the address at the depth 0 and the acquisition process of the data of the address may be included, but the search processing time is increased accordingly.

  Next, the search processing result output from the search processing circuit 51 is input to the search processing circuit 52. If a search result corresponding to the search key has already been obtained, the search processing result is sent to the search processing circuit 53 as it is, but if the search process is in the middle, the search processing by the search processing circuit 52 is performed. Done. As shown in FIG. 9, the read address transmission unit 81 receives the output from the search processing circuit 51, generates a read destination address in the built-in RAM, and sends this read destination address to the RAM selection circuit 54. The RAM selection circuit 54 selects the built-in RAM 58 on the operation side, and sends the read destination address generated by the search processing circuit 52 to the built-in RAM 58. Then, the read data receiving unit 82 acquires the data of the read destination address sent from the built-in RAM 58. This acquired data is the entry data of depth 3 in FIG. The data of the read destination address acquired by the read data receiving unit 82 is compared with the search key. Then, the search processing result is sent to the search processing circuit 53.

  FIG. 12-2 is a timing chart illustrating processing timings in the read address transmitting unit 81 and the read data receiving unit 82 in FIG. In FIG. 12-2, similarly to FIG. 12-1, the processing delay of each unit and the read time from the built-in RAM are one clock. As shown in FIG. 12B, the search processing time in the search processing circuit 52 is the time at which the read data transmission unit 82 receives the search processing result at the depth 2 and the read data transmission unit 82 at the depth 3. It takes 3 clocks until the search processing result is received. Like the search processing circuit 51, the search is finished in one read process without looping the search result.

  Next, the search processing result output from the search processing circuit 52 is input to the search processing circuit 53. If a search result corresponding to the search key has already been obtained, this search processing result is output via the search path 22. When the search process is in progress, the search process by the search processing circuit 53 is performed. As shown in FIG. 10, the read address transmission unit 83 receives an output from the search processing circuit 52, generates a read destination address in the built-in RAM, and sends this read destination address to the selection circuit 85. The selection circuit 85 selects the RAM selection circuit 55 or the RAM selection circuit 56 according to the read destination address and sends the read destination address. Subsequently, the multiplexing circuit 86 performs a process of sending the data at the read destination address sent from the RAM selection circuit 55 or the RAM selection circuit 56 to the read data receiving unit 84. The data acquired by the read data receiving unit 84 is output via the search path 22 as a search processing result. Here, when the selection circuit 85 selects the RAM selection circuit 55, the RAM selection circuit 55 accesses the built-in RAM 59 on the operation side and searches the left half of the tree of depth 4 shown in FIG. When the selection circuit 85 selects the RAM selection circuit 56, the RAM selection circuit 56 accesses the built-in RAM 60 on the operation side and searches the right half of the tree of depth 4 shown in FIG.

  12-3 illustrates the read address transmission unit 83, the selection circuit 85, the RAM selection circuit 55 or the RAM selection circuit 56 in the path from the search circuit to the RAM, and the RAM selection circuit 55 in the path from the RAM to the search circuit in FIG. 7 is a timing chart showing processing timings in a RAM selection circuit 56, a multiplexing circuit 86, and a read data reception 84. 12C, as in FIG. 12A, the processing delay of each unit and the read time from the built-in RAM are set to one clock. As shown in FIG. 12-3, the search processing time in the search processing circuit 53 is the time at which the read data generation unit 83 receives the search processing result at the depth 3 and the read data transmission unit 84 at the depth 4. It takes 7 clocks until the search processing result is received, and the search is completed in one read process without looping the result in the middle of the search as in the search processing circuit 51. In addition, the retrieval processing result at depth 3 is input to the read address generation unit 83 every 8 clocks. This is because the search processing result from the previous stage is input to the search processing circuit 53 in a pipeline manner every 8 clocks.

  Next, a method for updating the search database during the search operation will be described. When the search database is updated, data of the new database whose entry has been changed is sent from the control PC 8 to the router 1 via the control link 9. The controller 15 converts the data in the new database sent from the control PC 8 from the data format on the control link 9 to the data format on the external bus 23. Subsequently, the new database whose data format has been converted is sent to the external memory 14 via the external bus connection line 24 and held therein.

  Next, when a search database update instruction is sent from the control PC 8 to the device 13 in the router 1, an update instruction is sent to the RAM update circuit 65 via the external bus connection line 24. In response to the update instruction, the RAM update circuit 65 writes the new database held in the external memory 14 to the built-in RAM 61, built-in RAM 62, built-in RAM 63, and built-in RAM 64 serving as a standby surface. When the writing is completed, the search processing circuit 51, the RAM selection circuit 54, the RAM selection circuit 55, and the RAM selection circuit 56 are instructed to change the operation side via the notification line 66.

  When the operational change occurs, first, the internal RAM 57 used for the search by the search processing circuit 51 is changed to the internal RAM 61, so that the search circuit 22 inputs the search key 22 at a time when the search key is not input. The search key output destination is changed from the read address generation unit 71 to the read address generation unit 74. As described above, the search processing circuit 51 uses the two search processing circuits selected by the selection circuit 77 to switch the built-in RAM used for the search.

  When the search key has a bit width of one clock or more, the timing of changing the internal RAM by the selection circuit 77 is sent to the read address generation unit 71 or the read address generation unit 74 because the search key is cut off halfway. As a result, the input of the search key is interrupted from one search key to the next search key.

  Next, in the search processing circuit 52, as shown in FIG. 12-2, the search processing result at depth 2 is input every 8 clocks, so the internal RAM for performing the search processing in the search processing circuit 51 is switched. Thereafter, until the search processing result by the new database is input to the search processing circuit 52 (for 7 clocks), the RAM selection circuit 54 changes the output destination of the read destination address from the internal RAM 58 to the internal RAM 62. Search using the new database. At this time, the update of the database by switching the built-in RAM is performed using the speed difference between the processing capabilities of the search processing circuit 51 and the search processing circuit 52, in other words, the difference in the number of search processes per unit time. In other words, the search processing circuit 51 performs a search by looping a result in the middle of a search and reading it to the same built-in RAM, whereas the search processing circuit 52 does not loop the result in the middle of a search process once. Since the search is finished in the read process, the speed of the search processing capability of the search processing circuit 52 exceeds the speed of the search processing capability of the search processing circuit 51. If there is such a speed difference in the search processing capability, the search processing circuit 52 in the subsequent stage performs the search process during the 8 clocks until the next data is input from the search processing circuit 51 in the previous stage, and is built in. Switching between the RAM operation side and standby side can be performed. As shown in FIG. 12B, switching of the internal RAM in the search processing circuit 52 is possible except for the time during which the search processing circuit 52 accesses the internal RAM 58 and performs a search. In FIG. 12-2, the memory switchable time during which the memory can be switched is indicated by hatching.

  Similarly, in the search processing circuit 53, after the built-in RAM is sequentially switched to the search processing circuit 51 and the search processing circuit 52, the search result by the new database is input to the search processing circuit 53 (for 7 clocks). In addition, the RAM selection circuit 55 and the RAM selection circuit 56 change the output destination of the read destination address from the built-in RAM 59 and the built-in RAM 60 to the built-in RAM 63 and the built-in RAM 64, and search processing by the new database is performed until the next update instruction is issued. Continue to do. Similarly, at this time, the update of the database by switching the built-in RAM is performed using the speed difference between the processing capabilities of the search processing circuit 51 and the search processing circuit 53. That is, the search processing circuit 51 performs a search by looping a result in the middle of a search and reading it to the same built-in RAM, whereas the search processing circuit 53 does not loop the result in the middle of a search process once. Since the search is completed in the read process, the speed of the search processing capability of the search processing circuit 53 exceeds the speed of the search processing capability of the search processing circuit 51. As shown in FIG. 12C, switching of the internal RAM in the search processing circuit 53 is possible except for the time during which the search processing circuit 53 accesses the internal RAM 59 or the internal RAM 60 and performs a search. In FIG. 12C, the memory switchable time during which the memory can be switched is indicated by hatching.

  According to the present embodiment, by utilizing the speed difference between the processing capabilities of the search processing circuit of the preceding stage and the subsequent process, the search process circuit of the subsequent stage having a processing speed higher than that of the search process circuit of the previous stage allows the data being searched to be By switching to a memory having new entry information using a time not input from the search processing circuit to the subsequent search processing circuit, the search database entry is updated without stopping the search operation even during the search operation. be able to.

  In this embodiment, the tree structure of the search database is divided into depths and stored in a plurality of built-in RAMs. For example, when only the entry data at the deepest part of the tree is changed. Only the internal RAM that holds the deepest data needs to be updated, and the entry update can be reflected in the search process at high speed. FIG. 13 is a diagram illustrating a case where entry update is performed only in the deepest part of the tree of the search database, and illustrates a case where entry data at depth 4 is updated. As described above, in this case, it is only necessary to update the contents of the internal RAM 59 and the internal RAM 60 that hold the entry data at the depth 4, so that the updated entries are written to the internal RAM 63 and the internal RAM 64 on the standby surface. The RAM selection circuit 55 and the RAM selection circuit 56 may change the built-in RAM on the standby side to the operation side. Note that the determination to update only a part of the built-in RAM based on the data structure of the search database is made via the external control PC 8.

  In the present embodiment, an example in which the number of subsequent search processing circuits is two has been described. This is because the data structure shown in FIG. 11 has been described as an example, and the structure of the search database. Depending on the amount, the number of subsequent search processing circuits can be set as appropriate, and the built-in RAM and RAM selection circuit can also be set accordingly.

  In the present embodiment, the search processing circuit 52 and the search processing circuit 53, which are the subsequent search processing circuits, each access the internal RAM on the operation side and perform a search, but the number of times of the search is one. The number of times is not limited, and the number of times may be arbitrary as long as the number of times the search processing circuit 51 as the search processing circuit in the previous stage accesses the built-in RAM on the operation side and performs the search. That is, if this condition is satisfied, the effect of the present embodiment can be obtained. In this case, the internal structure of the subsequent search processing circuit, the data structure stored in the internal RAM accessed by the subsequent search processing circuit for searching, and the like are appropriately set depending on the number of accesses. The

Embodiment 2.
A second embodiment of the search device and data processing device according to the present invention will be described. A network configuration example using this embodiment is the same as the network configuration in the first embodiment shown in FIG.

  FIG. 14 is a diagram illustrating an internal configuration of the router 1 as the data processing apparatus according to the present embodiment. The difference between the internal configuration of the router 1 shown in FIG. 14 and the internal configuration of the router 1 in the first embodiment shown in FIG. 2 is that the device 13 in FIG. 2 is replaced with a device 73 in FIG. . Other configurations in FIG. 14 are the same as those in FIG. Therefore, in FIG. 14, the same components as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted. Next, the internal configuration of the device 73 as a search device, which is different from FIG. 2, will be described.

  FIG. 15 is a diagram showing an internal configuration of the device 73 in FIG. As shown in FIG. 15, the device 73 includes a RAM update circuit 112, a search key separation circuit 101, a search processing circuit 102 and a search processing circuit 103, which are search processing circuits in the previous stage, and a search processing circuit 102 and a search processing circuit. The search key multiplexing circuit 104 in which the output from 103 is multiplexed, the search processing circuit 105 that is the subsequent search processing circuit, and the search processing circuit that is also the subsequent stage, and the search processing result from the search processing circuit 105 is Input search processing circuit 106, RAM selection circuit 107, RAM selection circuit 108, RAM selection circuit 109, internal RAM 57 and internal RAM 121, internal RAM 58 and internal RAM 122, internal RAM 59 and internal RAM 123, and Built-in RAM 60 and built-in RAM 124, on standby Built-in RAM 61 and built-in RAM 131, built-in RAM 62 and built-in RAM 132, built-in RAM 63 and built-in RAM 133, built-in RAM 64 and built-in RAM 134, and notification line 112 connected from RAM update circuit 112 to search processing circuit 102 and search processing circuit 103 Consists of including. Next, the internal configuration and operation of each component will be described.

  In the present embodiment, as described below, an example in which two different search keys are handled at the same time will be described. However, the number of search keys is not limited to two, and at least three different search keys can be simultaneously used. An embodiment that handles a search key can be realized.

  A search key is input from the search path 22 to the search key separation circuit 101. The search key separation circuit 101 is a circuit that separates a search key described later into two, and sends one of the separated search keys to the search processing circuit 102 and the other to the search processing circuit 103. For this reason, the search processing circuit 102 and the search processing circuit 103 are provided in parallel to the subsequent stage of the search key separation circuit 101.

  FIG. 16 is a diagram illustrating an example of a format of a search key input from the search path 22 to the search key separation circuit 101. The search key 600 includes a search key 601 and a search key 602. The search key separation circuit 101 separates the search key 610 into a search key 601 and a search key 602.

  In the present embodiment, the description is continued on the assumption that the search key 601 is sent to the search processing circuit 102 and the search key 602 is sent to the search processing circuit 103. However, this assumption does not limit the present invention. Key destinations may be interchanged.

  FIG. 17 is a diagram showing a circuit configuration inside the search processing circuit 102. As shown in FIG. 17, the search key 601 input from the search key separation circuit 101 is sent to the read address generation unit 71 by the selection circuit 130. At this time, the read address generation unit 71 is connected to the internal RAM 57 on the operation side, while the read address generation unit 74 is connected to the internal RAM 61 on the standby side. The read address generation unit 71 generates a read destination address in the internal RAM 57 based on the input search key 601, sends the read destination address to the internal RAM 57, and reads the read destination address sent from the internal RAM 57. The address data is read and acquired by the data receiving unit 72.

  The read data receiving unit 72 compares the data of the acquired read destination address with the search key 601, and if a search result corresponding to the search key 601 cannot be obtained, the internal RAM 57 is further accessed to perform the search process. Continue. That is, the latch 73 waits for data from the read data receiving unit 72, and then, based on the data of the read destination address output from the latch 73, the read address generating unit 71 uses the next read destination address. Is sent to the built-in RAM 57 again. Then, the read data receiving unit 72 acquires the data of the read destination address sent from the built-in RAM 57. After repeating this operation an arbitrary number of times, the data at the address to be read is passed to the multiplexing circuit 131, multiplexed, and designated information (indicated by the internal RAM to be searched that is sent via the notification line 111) ( In this case, designation information for designating the internal RAM 57 is added and output to the search key multiplexing circuit 104 in the subsequent stage.

  The search key multiplexing circuit 104 performs processing for sending the search processing results sent from the search processing circuit 102 and the search processing circuit 103 to the search processing circuit 105. Here, the search processing by the search processing circuit 103 is also performed in the same manner as the search processing circuit 102, but the internal RAM on the operational side targeted by the search processing circuit 103 is the internal RAM 121.

  FIG. 18 is a diagram showing a circuit configuration inside the search processing circuit 105. As shown in FIG. 18, the search processing result output from the search key multiplexing circuit 104 is input to the search processing circuit 105, and when the search is in progress, the read address transmission unit 141 sets the read destination address. The generated read destination address is sent to the RAM selection circuit 107 together with the designation information for designating the internal RAM to be searched that is generated and added by the search processing circuit 102 and the search processing circuit 103. Then, the data at the reading destination sent from the RAM selection circuit 107 is acquired by the reading data receiving unit 142, and the obtained search processing result is output to the search processing circuit 106.

  The RAM selection circuit 107 has built-in data that is being searched for by the search key 601 (read destination address) based on the designation information designating the built-in RAM to be searched sent from the search processing circuit 105. The RAM 58 selects the built-in RAM 122 for the data (reading destination address) being searched by the search key 602, and sends the data being searched to the selected built-in RAM. Data is read and the result is output to the search processing circuit 105.

  FIG. 19 is a diagram showing a circuit configuration inside the search processing circuit 106. As shown in FIG. 19, the search processing result output from the search processing circuit 105 is input to the search processing circuit 106, and when the search processing result is in the middle of the search, the read address transmission unit 151 reads the read destination. An address is generated, and this reading destination address is sent to the selection circuit 153 together with designation information for designating the internal RAM to be searched. The selection circuit 153 selects the RAM selection circuit 108 or the RAM selection circuit 109 according to the read destination address. For example, when the RAM selection circuit 108 is selected, the RAM selection circuit 108 selects an internal RAM that is an operational surface, and further reads a read destination based on designation information that designates the internal RAM to be searched. Are sent to the internal RAM 59 or the internal RAM 123. The built-in RAM 59 is selected for the data being searched by the search key 601 (reading address), and the built-in RAM 123 is selected for the data being searched by the search key 602 (reading address). Similarly, when the RAM selection circuit 109 is selected, the RAM selection circuit 109 selects an internal RAM that is in operation, and further reads based on designation information that designates the internal RAM to be searched. The previous address is sent to the internal RAM 60 or the internal RAM 124. The built-in RAM 60 is selected for the data being searched by the search key 601 (reading address), and the built-in RAM 124 is selected for the data being searched by the search key 602 (reading address). Subsequently, the data at the read destination address is sent to the multiplexing circuit 154 via the RAM selection circuit 108 or the RAM selection circuit 109, and further sent from the multiplexing circuit 154 to the read data receiving unit 152. The data acquired by the read data receiving unit 152 is output from the device 73 via the search path 22 as a search processing result.

  The RAM update circuit 112 is a circuit that writes entry data sent via the external bus 23 to the internal RAM group serving as a standby surface when the search database is updated. In FIG. 15, the standby surfaces are an internal RAM 61, an internal RAM 62, an internal RAM 63, an internal RAM 64, an internal RAM 132, an internal RAM 132, an internal RAM 133, and an internal RAM 134. Further, the RAM update circuit 112 notifies the search processing circuit 102 and the search processing circuit 103 of an entry data update instruction using the notification line 111.

  FIG. 20 is a diagram showing how a tree configured by entry data is configured in each internal RAM. As shown in FIG. 20, in this embodiment, two tables including a table 201 and a table 202 are used. In the table 201, tree information from depth 0 to depth 2 is registered in the built-in RAM 57, the tree information of depth 3 is stored in the built-in RAM 58, and the left half of the tree information of depth 4 is stored in the built-in RAM 59. The right half of the tree information of depth 4 is registered in the RAM 60. In the table 202, tree information from depth 0 to depth 2 is registered in the internal RAM 121, the tree information of depth 3 is stored in the internal RAM 122, and the left half of the tree information of depth 4 is stored in the internal RAM 123. The right half of the tree information having a depth of 4 is registered in the RAM 124.

  The search database update method during the search operation in the present embodiment is the same as that in the first embodiment. That is, also in the present embodiment, the search processing circuit in the previous stage loops the result in the middle of the search, and therefore the search result for each clock is not output. On the other hand, in the search processing circuit at the subsequent stage, the search is completed by one read process to the built-in RAM. Then, using the speed difference between the processing capabilities of the search processing circuit of the preceding stage and the subsequent stage, and utilizing the fact that the data being searched to be input to the search processing circuit of the subsequent stage is not every clock, the search processing circuit of the subsequent stage is inserted in the gap. The built-in RAM to be accessed is switched, and the database is updated.

  According to the present embodiment, the search database entry can be updated without stopping the search process even during the search operation. In addition, since the tree structure of the search database is stored in the built-in RAM divided by depth, for example, when only the entry data at the deepest part of the tree is changed, the built-in data that holds the deepest part of the data is stored. Only the RAM needs to be updated, and the entry update can be reflected in the search process at high speed. Further, in this embodiment, since the input search key includes two separable search keys, the two internal memories holding the same data are stored in the internal RAM targeted for the search processing circuit in the previous stage. By using the RAM and the built-in RAM to be searched by the subsequent-stage search processing circuit are two built-in RAMs that hold the same data, the search processing for the two separated search keys can be performed in the first and second stages. It is distributed over one built-in RAM. In this way, by adding another table search processing function to the two different search keys in addition to the table search processing function used in the first embodiment, the search processing speed can be increased. It is possible to realize a high-speed entry update function.

  Further, when there is an unused internal RAM arranged in the subsequent stage, it is allocated to another search table, so that the search processing can be speeded up by effectively using resources.

  As described above, the search device according to the present invention is useful in data processing that performs data search, and is particularly suitable for an information communication system that updates a search database without interrupting search processing.

It is a figure which shows the network structure using Embodiment 1 of this invention. 3 is a diagram illustrating a functional configuration example of a router according to the first embodiment; FIG. It is a figure which shows an Ethernet (trademark) frame format. It is a figure which shows the format of an IPv4 header. It is a figure which shows the format of a TCP header. It is a figure which shows the format of a UDP header. It is a figure which shows the internal structure of the device in FIG. It is a figure which shows the internal structure of a search processing circuit. It is a figure which shows the circuit structure inside a search processing circuit. It is a figure which shows the circuit structure inside a search processing circuit. It is a figure which shows an example of the data structure of the database for a search used in Embodiment 1, and how the tree comprised by entry data is comprised in internal RAM. It is a timing chart which shows the timing of the process in each unit in FIG. It is a timing chart which shows the timing of the process in each unit in FIG. It is a timing chart which shows the timing of the process in each unit in FIG. It is a figure which shows the case where there is entry update only in the deepest part of the tree of the database for search. 6 is a diagram illustrating a functional configuration example of a router according to a second embodiment. FIG. It is a figure which shows the internal structure of the device in FIG. It is a figure which shows an example of the format of the search key input into a search key separation circuit from a search path | route. FIG. 10 is a diagram illustrating a circuit configuration inside a search processing circuit according to a second embodiment. FIG. 10 is a diagram illustrating a circuit configuration inside a search processing circuit according to a second embodiment. FIG. 10 is a diagram illustrating a circuit configuration inside a search processing circuit according to a second embodiment. It is a figure which shows an example of the data structure of the database for search used in Embodiment 2, and how the tree comprised by entry data is comprised in internal RAM.

Explanation of symbols

1 router 2 PC terminal 3 internet 4 server group 5 access point 6 wireless terminal 7 intranet 8 control PC
DESCRIPTION OF SYMBOLS 9 Control link 10 Link 11 Transmission / reception unit 12 Transfer unit 13 Device 14 External memory 15 Controller 22 Search path 23 External bus 24 External bus connection line 25 Ethernet (trademark) frame 26 MAC header 27 IPv4 packet 28 FCS
29 IPv4 header 30 TCP header 31 UDP header 32 TOS field 33 Total length 34 Identifier 35 Flag 36 Fragment offset 37 Protocol 38 Source IP address 39 Destination IP address 40 Source port number 41 Destination port number 42 Sequence number 43 Confirmation response number 44 Source port number 45 Destination port number 51, 52, 53 Search processing circuit 57, 58, 59, 60, 61, 62, 63, 64 Built-in RAM
54, 55, 56 RAM selection circuit 65 RAM update circuit 66 Notification line 67 Standby surface 68 Operation surface 71, 74 Read address generation unit 72, 75, 82, 84 Read data reception unit 73, 76 Latch 77, 85 Selection circuit 78, 86 Multiplexing circuit 81, 83 Read address transmitter

Claims (10)

A search device for inputting a search key and searching a search database stored in a memory and outputting a search result,
A search processing circuit in a previous stage where the search key is input;
One or a plurality of subsequent search processing circuits which are provided in the subsequent stage of the search processing circuit of the preceding stage and sequentially perform the search process based on the search processing result of the search processing circuit of the previous stage;
A part of the search database for the search processing circuit of the previous stage to store is stored, and an operation memory of the previous stage provided corresponding to the search processing circuit of the previous stage,
The standby memory provided in a pair with the previous operation memory, the standby memory of the previous stage for waiting until the update of the search database,
Data for the search processing circuit in each subsequent stage to search is stored so that the remainder of the search database is stored as a whole, and the subsequent stage provided corresponding to the search processing circuit in the subsequent stage, respectively. Operating memory,
A standby memory provided in a pair with each of the subsequent operation memories, which waits until the search database is updated;
A memory update circuit that updates the contents of the standby memory in the previous stage and the subsequent stage by writing the updated search database when the search database is updated;
Based on the update notification from the memory update circuit, the selection circuit in the previous stage that switches the memory to be searched by the search processing circuit in the previous stage from the operation memory in the previous stage to the standby memory in the previous stage;
A subsequent-stage selection circuit that switches a memory to be searched by each subsequent-stage search processing circuit from each subsequent-stage operation memory to each subsequent-stage standby memory based on an update notification from the memory update circuit; ,
With
A search apparatus characterized in that a search processing time required for the search processing by the search processing circuit in the preceding stage is longer than a search processing time required for the search processing circuit in each subsequent stage.   The search processing circuit at the preceding stage performs a search process by accessing the operation memory at the preceding stage a plurality of times, and the search processing circuit at each subsequent stage performs the above-described search operation circuit with respect to the corresponding operation memory at the subsequent stage. The search apparatus according to claim 1, wherein the search processing is performed by accessing the number of times less than the number of accesses of the search processing circuit.   The memory switching from the subsequent operation memory to the subsequent standby memory by the subsequent selection circuit is performed by inputting the search processing result from the previous search processing circuit to the subsequent search processing circuit. 3. The search device according to claim 2, wherein the search processing circuit is performed by using a time excluding a time during which each subsequent-stage search processing circuit is accessing the subsequent-stage operation memory.   A search key is input to the search processing circuit in the previous stage at least at a predetermined time interval, and the predetermined time interval is the next to the data being searched for the search key already input to the search processing circuit in the previous stage. The search device according to claim 2 or 3, wherein an input search key is spaced from the search key so as not to collide with the search processing circuit in the preceding stage.   The latter-stage operation memory is composed of a plurality of memories to which the stored data is divided and allocated, and the latter-stage standby memory is composed of the same number of memories as the latter-stage operation memory, and constitutes the latter-stage operation memory. 5. The search device according to claim 1, wherein each memory and each memory constituting the standby memory in the subsequent stage form a pair.   The search device according to claim 1, wherein the selection circuit at the preceding stage is provided inside the search processing device at the preceding stage.   The search processing circuit in the previous stage includes a first internal search processing circuit that can access the operation memory in the previous stage, and a second internal search processing circuit that can access the standby memory in the previous stage, and By switching the search key destination from the first internal search processing circuit to the second search processing circuit based on the database update notification, the memory to be searched by the search processing circuit in the previous stage is changed to the previous stage. The search device according to claim 1, wherein the operation memory is switched to the standby memory in the preceding stage.   The data structure of the search database is a tree structure, the previous operation memory stores the upper data of the tree structure including the starting point of the tree structure, and each subsequent operation memory stores the previous operation memory. Stores the lower data of the tree structure other than the data stored in the memory, and the number of the upper data stored in the previous operation memory is greater than the number of the lower data stored in the subsequent operation memory. The search device according to any one of claims 1 to 7, wherein there are a large number of the search devices.   A search key separating circuit that separates the input search key into a plurality of search keys that are constituent elements of the input search key configured to include a plurality of different search keys; The upstream operation memory and the standby memory of the previous stage are configured by the same number of memories as the number of the separated search keys storing the same search data, respectively. Each of the standby memories is composed of the same number of memories as the number of the search keys to be separated in which the same search data is stored, and the search processing circuit in the previous stage includes a plurality of the search keys separated by the search key separation circuit. The search for the search key is performed in a distributed manner in a plurality of memories constituting the previous stage operation memory, and the search processing result for each of the separated search keys is detected. Identification information for identifying a target memory is added, and each subsequent search processing circuit is based on the identification information added to the search processing result with respect to the search processing result from the previous search processing circuit. The search device according to claim 1, wherein the search is performed by selecting a memory to be searched from a memory constituting each of the subsequent operation memories.   A data processing device comprising the search device according to claim 1.

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