TWI677091B - Method for manufacturing dual trench device and semiconductor device - Google Patents

Abstract

A power MOSFET or a power rectifier can be manufactured in accordance with the present invention to include a gate trench and a field plate trench. Two trenches can be formed using one of the two-step etching procedures as described in detail in this specification. The devices embodying the present invention can be manufactured with higher packaging density and better and more closely distributed device parameters (such as V _F , R _DSS and BV).

Description

Procedure for manufacturing double trench device and semiconductor device

Traditionally, integrated circuits (ICs) are built on or near the top surface of a semiconductor wafer. The current flowing in the IC in and between circuit elements parallel to and near the surface of the wafer and in certain locations in the surface area is susceptible to stresses from strong electric fields and high currents during the operation of the IC.

Recently, some circuit components have been placed away from the wafer surface toward the wafer block as a way to spread current to reduce resistance to current flow and also redirect the electric field away from the wafer surface to increase device operating voltage. Therefore, the trench structure is widely used in power MOSFETs, rectifiers, and transient voltage suppression devices. Devices in this category are often referred to as vertical devices or vertical ICs.

In some vertical ICs, all trenches have the same depth (such as D5VOLIB2DLP3, by one of the Diodes 6V, 6A, 15pF Zener TVS). In their devices, the trenches are defined by a single light mask and etched simultaneously. In other vertical integrated circuits, the trenches have different depths (such as the MOSFET described in patent US Pat. No. 8,748,976 (the '976 patent)). In the MOSFET disclosed in the '976 patent, there are vertical RESURF trenches and gate trenches (which have different depths) and they are individually separated using a dedicated RESURF trench mask and a dedicated gate trench mask To define.

The inventors studied various known vertical devices including vertical power MOSFETs with trenches of different depths and found that these devices tend to change in performance, even in devices from the same production lot or even from the same wafer . The inventors recognize that this excessive change is not only undesirable but unavoidable. This is because when more than one light mask is used to form the grooves, there will be an unavoidable misalignment between the masks and therefore the relative position between the grooves becomes difficult to control. This misalignment is the root cause of the change between devices and it will become more significant as the design rules continue to shrink and the space between the trenches and the relative position of the trenches becomes increasingly critical.

The effect of misalignment is that many device parameters (such as V _F , _RDSON and BV _{DSS of the} MOSFET) tend to deviate from the designed values. Therefore, when using these devices in a system, the uncertainty of the MOSFET parameters necessitates wider system design tolerances.

To solve this annoying problem, the inventors have worked hard to invent a method using which can virtually eliminate misalignment between trenches with different depths and different widths, and achieved using manufacturing equipment currently available to those skilled in the art Of it.

In this document, a double trench structure will be described as an example to assist those skilled in the art to understand and use the present invention. The exemplary dual trench structure can be incorporated into a MOSFET, a rectifier, or other IC circuits. The concept of the invention is briefly summarized as follows.

In an integrated circuit, trenches can be used for different purposes. For example, in a MOSFET structure similar to the MOSFET structure in the '976 patent, the trench functions as both a RESURF structure and a gate structure. The RESURF trenches need to extend to the full length of the drain region to effectively reduce the electric field in the device. On the other hand, the gate trenches need only reach the drain region and should be kept as short as possible to reduce the gate-to-drain capacitance. The different requirements specify that the gate trench is only part of the RESURF trench in length. And the different voltages strengthened on the two trenches during the operation of the device necessitate different trench widths other than different trench depths.

The inventors have identified that by utilizing the difference in size of the grooves, the two grooves can be borrowed Defined by the use of a light mask but etched using a one or two step etching process, both can reach their respective designed depths. And because the two grooves are printed by a single masking step, there may be no misalignment between the two grooves. The following paragraphs briefly describe the process steps that the wafer goes through after the two trenches are defined using the same light mask.

First, after an initial trench etch step, the wafer has a thin film deposited thereon. Thin films are commonly used in IC manufacturing processes. For example, doped polycrystalline silicon can be used when a conductive film is required; and a silicon dioxide film is often used to insulate between conductive materials such as silicon and metals. In this exemplary dual trench device, polycrystalline silicon is deposited in two trenches lined with silicon dioxide. The deposited polycrystalline silicon film is thicker than a half width of the gate trench that is narrower than the field plate trench. The polycrystalline silicon film covers the bottom and shoulder of the wider trench but completely fills the narrow trench to its full depth.

When the deposited polycrystalline silicon film is etched back using an isotropic etching process, the polycrystalline silicon film in the wider trench will be completely removed and the polycrystalline silicon in the gate trench remains but is recessed from the mouth Some predetermined depth. In a following procedure, the recess is filled with a dielectric film, such as a silicon dioxide film. Next, the film is etched back from the wafer surface, only a part of which remains in the recess to serve as a hard mask to shield the remaining in the gate trench during the second of the two-step trench etching process Polycrystalline silicon.

The second etching step removes silicon from the wider trench to a new trench depth, while the narrower gate trench and the platform area between the trenches are shielded from the hard mask by the hard mask. Etching. This will be explained more fully in a subsequent chapter. For this method, both the wider and narrower trenches are defined using the same light mask and the depths of the two trenches can be independently controlled and virtually no misalignment between the two trenches . Many electronic devices can be manufactured following this novel trench formation process. Several examples are described below. The integrated circuit devices embodying the present invention do not have the problem of parameter dispersion due to misalignment between the trenches and therefore the performance of these devices is more predictable and more reliable.

[definition]

The terms used in the present invention generally have their ordinary meanings in the art within the context of the present invention. Certain terms are discussed below to provide additional guidance to the operator in describing the invention. It will be appreciated that the same thing can be stated in more than one way. Therefore, alternative languages and synonyms can be used.

A semiconductor wafer is a plate of semiconductor materials such as silicon, germanium, silicon carbide, diamond, gallium arsenide, and gallium nitride. A semiconductor wafer usually has two parallel major surfaces, which are the major crystalline planes. Integrated circuits are built in and on top portions of semiconductor wafers; recently, in some integrated circuits, components have been built into blocks of semiconductor wafers perpendicular to the top surface. In the present invention, the term wafer top surface or wafer surface is used to mean the top parallel surface of a semiconductor wafer in which a semiconductor material is in contact with other materials, such as a dielectric or conductive film.

A trench is a structured component of some integrated circuit wafers. Trenches are typically formed by first printing an image on the surface of a semiconductor wafer with a photoresist, and then removing material from the wafer in which the material is not protected by the photoresist. Removal of this material is usually accomplished using a reactive ion etching process. When viewed from the surface of the wafer, the grooves generally have a long stripe shape. A trench wall is a vertical surface of the semiconductor material extending from the surface of the wafer to the bottom of the trench. In the present invention, the width of a trench is the distance between two trench walls, and the length of the trench is a long dimension orthogonal to the width and depth of the trench. The depth of a trench is measured in a direction perpendicular to the top surface of the wafer and is measured from the top surface of the wafer to the end of the etching step (ie, the bottom of the trench).

A MOSFET is a four-terminal electronic circuit element. Current can flow in a channel between the source terminal and the drain terminal, and the amount of current can be controlled by the voltage at the gate terminal and the body terminal. In a MOSFET, current can flow in the channel in both directions. In many trench MOSFETs, the gate is built in the trench, and the body region is internally shorted to the source region.

A rectifier is a two-terminal circuit element. Current may flow between the anode and the cathode depending on the polarity of the voltage across the terminals. In one of the SBR rectifiers made by Diodes, it also has a gate structure. The SBR rectifier can also be built perpendicular to the trench structure.

The present invention refers to a raised edge or flange edge features demonstrated in this document as described in the two step etching process such that the trench wall. The raised edge is parallel to the top surface of the wafer and delimits two sections of the trench wall. The top section of the trench is wider than the bottom section. The raised edge tends to have a smooth surface that slopes downward toward the bottom of the trench, which is characteristic of the reactive ion etching process.

When the depth of the trenches in conjunction with the present invention, as the means is equal to a result of the etching step, these two trenches depth equal to each other. Due to the micro-loading effect known in the art as the reactive ion etch process, the etch rate is a function of the width of the trench-a wider trench tends to etch faster than a narrower trench This is due to the easier transportation of reactive etching materials and products with etching reactions. Since at least one wider trench and one narrower trench exist in the exemplary device disclosed in this paper, the depths of the narrow trenches and wide trenches can be mathematically equal when they are etched within the same length However, for the purposes of describing and claiming the present invention, such trench depths are considered "equal."

When referring to the distance between grooves in the present invention, equidistant means that in a cross-sectional view, the distance between the central lines of one groove pair is equal to the central lines of another groove pair the distance between.

The epi-layer in the present invention refers to a single-crystal semiconductor layer formed by epitaxial growth on, for example, a substrate of another single-crystal semiconductor layer. During or after formation of an epitaxial layer, dopants may be incorporated into the epitaxial layer. Integrated circuit components are usually built in an epitaxial layer.

A source and a drain in a MOSFET refer to the source terminal and the drain terminal or the two semiconductor regions connected to the respective terminals. A MOSFET is a bidirectional device in the sense that current can be manipulated to flow from the source to the drain or from the source to the drain. In a vertical MOSFET, the drain can be on the top of the wafer surface in a configuration known as under-source, or on the bottom of the wafer in a configuration known as under-drain. Office.

The forward voltage (V _F ) of a MOSFET or a rectifier is a measurement of the voltage at the device when the rated current flows through the device. It is a figure of merit in an electrical device because it represents the loss of power (IV _F ) due to ohmic heating when the device is driven forward.

The on-resistance (R _DSON ) of a MOSFET or a rectifier is a measure of the current when the device is driven forward. It is a figure of merit in electrical installations because it represents the power loss (I ² R _DSON ) due to ohmic heating.

The blocking voltage (BV) of a MOSFET or a rectifier is a measure of the maximum voltage across a reverse-biased junction of a device before it enters "crash" mode. It is a figure of merit for an electric device because it represents the maximum operating voltage of the device.

A power MOSFET or a field plate in a rectifier is a conductive element disposed near a pn junction. The conductive element can effectively change the electric field distribution near the pn junction to increase its breakdown voltage when properly biased. The field plate may be a polycrystalline silicon structure at the surface of the device or in a field plate trench. The field plate trench in a vertical MOSFET is designed to increase the breakdown voltage between the body region and the substrate.

Light masks are a tool used in traditional semiconductor manufacturing. It is usually made of a flat and transparent material. A pattern of an opaque material is placed on the mask, which is intended to be transferred to a wafer. In the present invention, the light mask includes more advanced equivalent light lithography tools (such as electron beam writing that engraved a pattern on a wafer without using these conventional light masks).

100‧‧‧MOSFET device

101‧‧‧MOSFET cell

102‧‧‧MOSFET cell

120‧‧‧ substrate / n-type silicon area / layer

130‧‧‧n-type epitaxial layer

131‧‧‧ Drain region

132‧‧‧ surface of the wafer

140‧‧‧field plate trench

141‧‧‧Dielectric film / dielectric material

142‧‧‧Conductive material

143‧‧‧ raised edge

144‧‧‧Width

149‧‧‧ depth

150‧‧‧Gate Trench

151‧‧‧Dielectric material / dielectric layer / silicon dioxide / gate dielectric / gate oxide / component

152‧‧‧polycrystalline silicon / gate / conductive material / component / component

153‧‧‧ Dielectric Components / Assemblies

154‧‧‧Width

160‧‧‧Floor / Main Area

170‧‧‧Source area

180‧‧‧p + area

190‧‧‧metal element / metal layer / anode

200‧‧‧Gate structure

210‧‧‧hard mask layer / oxide / hard mask

211‧‧‧Gap

252‧‧‧polycrystalline silicon film

310‧‧‧hard mask / silicon dioxide / silicon dioxide layer

410‧‧‧oxide film

500‧‧‧field board structure

510‧‧‧ Silicon dioxide film / oxide film / etching mask

540‧‧‧field board trench

543‧‧‧concave / concave shoulder

544‧‧‧distance

643‧‧‧ bottom surface

644‧‧‧wall

645‧‧‧ wall

710‧‧‧Etching mask / hard mask / hard mask part

711‧‧‧hard mask

740‧‧‧field board trench

741‧‧‧Edge Wall

744‧‧‧distance

940‧‧‧field board trench

944‧‧‧Width

950‧‧‧Gate Trench

954‧‧‧Width

FIG. 1 depicts a cross-sectional view of a dual groove device embodying an aspect of the present invention.

FIG. 2 depicts a cross-sectional view of an exemplary gate trench at one point in the manufacturing process.

FIG. 3 depicts a cross-sectional view of the gate trench in FIG. 2 at another point in the manufacturing process.

FIG. 4 depicts a cross-sectional view of the gate trench in FIG. 3 at another point in the manufacturing process.

FIG. 5 depicts a cross-sectional view of an exemplary field plate trench at one point in the manufacturing process.

FIG. 6 depicts a cross-sectional view of the field plate trench in FIG. 5 at another point in the manufacturing process.

FIG. 7 depicts a cross-sectional view of an alternative field plate trench for a MOSFET at one point in the manufacturing process.

FIG. 8 depicts a cross-sectional view of the alternative field plate trench of FIG. 7 at another point in the manufacturing process.

FIG. 9 depicts a schematic diagram of a light mask embodying some aspects of the present invention.

Example 1 a power MOSFET

FIG. 1 depicts a cross-sectional view of a semiconductor wafer having a MOSFET device 100 embodying some aspects of the present invention. The MOSFET 100 includes repeating cells 101 and 102. In the middle of FIG. 1 is a gate trench 150. A field plate trench 140 is tied on either side of the gate trench. The bottom portion of the semiconductor wafer is a substrate 120, and the substrate 120 is servod to the drain of the MOSFET. In this example, the substrate is heavily doped with single crystal silicon. Those skilled in the art should understand that semiconductor materials other than silicon can also be used to implement the present invention. Examples are germanium, diamond, silicon carbide, gallium arsenide, gallium nitride, and mercury-cadmium tellurium.

Layer 130 is a single crystal epitaxial layer that incorporates other chemical elements to modify the characteristics of the MOSFET. These elements include germanium, boron, phosphorus, arsenic, and aluminum. In this example, the MOSFET is an n-type MOSFET, which means that the main dopant in the substrate and in the epitaxial layer is n-type. Those skilled in the art should be able to follow this description using dopant polarity One of them is changed to make a p-type MOSFET.

The layer 160 is the body region, which is a p-type layer incorporated into the epitaxial layer 130 by a procedure such as ion implantation. The layer 160 may also be a separate p-type epitaxial layer grown on the n-type epitaxial layer 130. Region 180 is one of the body regions more heavily doped with p + regions. This heavy doping promotes the formation of an ohmic contact between silicon and the metal layer 190. The MOSFET 100 also has a source region 170 which is a heavily doped n region and is abutted against the wall of the trench 150.

The trench 150 is the gate trench. In this example, the trench is formed by a reactive ion etching process, and the width 154-the distance between the opposing walls of the trench-is about 0.45 micrometers and the depth is about 1 micrometer. The walls of the trench are lined with a dielectric material 151, such as silicon dioxide with a thickness of about 0.1 micron. This thickness is selected for device applications where the gate can experience a voltage of about 20 volts relative to the drain. The inner portion of the gate trench is about 0.25 microns and is filled with a conductive material, such as doped polycrystalline silicon 152. The polycrystalline silicon is part of the gate electrode and is connected to the gate terminal of the MOSFET. The gate terminal receives the gate signal for turning on or off the MOSFET.

In this cross-sectional view, two trenches 140 stand on both sides of the gate trench 150. In this exemplary MOSFET, the conductive material 142 in the trench 140 is electrically connected to the source and the body region through a metal element 190, and the conductive material 142 functions as a field plate to soften the electric field. The walls of the trenches 140 are lined with a dielectric material 141, such as silicon dioxide, which is about 0.6 microns to 0.8 microns thick. This thickness is chosen for devices that can experience a voltage of 100 volts or more between the source and the drain. The inner portion of the field plate trench is also filled with a conductive material 142, such as doped polycrystalline silicon.

The field plate trench 140 is formed using a two-step etching process, which will be described in more detail in a subsequent section. Because of the novel etching process, during the manufacturing process, both the gate trench and the field plate trench can be printed simultaneously using a light mask. Evidence of the field plate trench 140 fabricated using a single mask two-step etching process is via raised edges 143 positioned on the walls of the field plate trench.

Layer 190 is one of the metal layers in this MOSFET. The metal layer 190 is directly connected to the conductive material (polycrystalline silicon) 142 portion of the field plate trench, the p + region 180, and the source region 170. The substrate 120 is the drain of the MOSFET. The polycrystalline silicon 152 in the gate trench is electrically isolated from the metal layer 190 by a dielectric element 153 (which is also silicon dioxide in this example).

When the gate 152 is positively biased higher than the threshold voltage relative to the body region 160, the n-type MOSFET forms a vertical conductive channel in the body region beside the gate trench walls to make the source extreme A current between the terminal and the drain terminal is conducted through the drain region 131. Those skilled in MOSFETs are familiar with the theory of MOSFET operation.

The structure depicted in FIG. 1 includes two MOSFET cells 101 and 102, which share a gate trench 150. Two field plate trenches are equidistant from the gate trench. Because the gate trench and the two field plate trenches are printed using the same light mask, the two MOSFET cells are mirror images of each other.

Example 2 a power rectifier

Alternatively, FIG. 1 depicts a schematic diagram of another exemplary power device-a rectifier that embodies aspects of the present invention. A rectifier is a device with two terminals-an anode and a cathode. The trench structure of the rectifier is similar to the trench structure of the MOSFET described in Example 1. However, the doping schedule of the rectifier is different from the doping schedule of the MOSFET.

In the exemplary n-type rectifier, the drain region 131 in the epitaxial layer is an n-type; and the body region 160 and the region 180 are dominated by a p-type dopant. In contrast to the region of the MOSFET, the region 170 is also dominated by a p-type dopant.

The element 153 in FIG. 1 (which is an electrically insulating element in the MOSFET) lacks the rectifier structure, so the metal layer 190 makes direct electrical contact with the polycrystalline silicon 152 in the gate trench 150. The metal layer 190 is the anode of the rectifier and the substrate is the cathode. Those familiar with the rectifier are familiar with the operating theory of the rectifier and they can also change the polarities of the dopants to make a p-type rectifier in accordance with the present invention.

Example 3-Schottky Diode

Alternatively, FIG. 1 depicts a schematic diagram of another exemplary power device, a Schottky diode, which may be connected to a MOSFET as described in Example 1 or a rectifier as described in Example 2 or to two Coexist. A Schottky two-pole system with a two-terminal unidirectional device is similar to the rectifier in Example 2. Common Schottky diode systems are made of silicon. In FIG. 1, the anode 190 of the Schottky diode is a metal element that makes ohmic contact with a metal silicide material (such as platinum silicide). The cathode is a metal element that makes ohmic contact to the n-type silicon region 120. The metal silicide and the interface of the n-type silicon form a Schottky barrier that allows current to pass between the anode and the cathode only in one direction.

To represent a Schottky diode, regions 131, 160, 170, and 180 in FIG. 1 are all semiconductor regions dominated by n-type dopants. Layer 120 is an n-type substrate, and 130 is an n-type epitaxial layer. Regions 160, 170, and 180 may be formed simultaneously using one or more ion implantation steps, so there may be no detectable boundaries between these regions. In this exemplary Schottky diode device, the gate structure 150 and its related components 153, 151, and 152 may be lacking.

Example 4 Formation of a gate trench structure

FIG. 2, FIG. 3 and FIG. 4 depict schematic diagrams of an exemplary procedure for forming a gate structure 200.

FIG. 2 depicts a partially completed gate structure after a polycrystalline silicon film 252 is deposited in the gate trench 150 and on the wafer surface 132. At this point in the process flow, there is a hard mask layer 210 covering the shoulders of the gate trenches 150, and a dielectric layer 151 is used to line the trench walls. The dielectric layer 151 is also formed on On the hard mask 210. In this exemplary gate structure, the depth of the gate trench is about 1 micron. The hard mask 210 defines the gate and protects silicon in the area around the gate during the etching process. In this example, the gap 211 (which is the width of the gate trench) between the hard masks 210 on both sides of the gate trench is about 0.45 micrometers. In this example, the dielectric material 151 is CVD silicon dioxide. Against In this power device (the gate of which is designed to resist about 20 volts), the thickness of the silicon dioxide 151 is selected to be about 0.1 microns. In terms of the formation of the gate dielectric 151, the opening of the trench is reduced to about 0.25 microns. Thermal oxide can also be used to line the gate trench walls.

In a subsequent step, the trench is filled with a conductive material 152, which will be part of the gate electrode when the process is completed. In this example, the conductive material is doped polycrystalline silicon and the thickness of the polycrystalline silicon film as deposited is about 0.3 microns. The polycrystalline silicon film should completely fill the gate trench 150. If the deposited polycrystalline silicon leaves a suture or hole at the center of the trench, it will not affect the operation of the completed device.

Figure 3 depicts the device of Figure 2 at a later point in the program flow. At this point, the deposited polycrystalline silicon has been removed from the top of the oxide 210 and from the opening of the trench 150. The element 152 is the remainder of the polycrystalline silicon in the trench after the removing step, and the top of the polycrystalline silicon 152 may be recessed from the surface 132. This removal step is highly preferred and does not substantially reduce the silicon dioxide film on the wafer surface 132.

This step is followed by the deposition of one of another silicon dioxide 310 layer, which increases the thickness of the dioxide film above the wafer surface 132 and fills the void in the trench 150 above the polycrystalline silicon 152, which is formed substantially above the wafer A flat surface. The thickness of the silicon dioxide deposited on the top of the wafer is about 0.3 micrometers, so it fills the trench completely again, such as processing the polycrystalline silicon in a previous process step. If the deposited oxide leaves a gap or hole, it will not affect the operation of the completed device.

FIG. 4 depicts the gate trench structure after the oxide film and the gate trench on the wafer surface 132 have been partially removed. The oxide film 410 remaining on the wafer surface 132 and the oxide film 310 remaining on the gate trench 150 are sufficiently thick. In the following silicon etching steps, a hard mask 310 is used to shield the gate trench 150 The polycrystalline silicon 152 is protected from etching.

In the procedure of Example 4, the silicon dioxide film was used exclusively, thermally grown or deposited by chemical vapor deposition (CVD), or both. However, other dielectric materials (such as silicon nitride or silicon oxynitride) can also be used.

Example 5 Formation of a field plate trench structure

5 and 6 depict schematic diagrams of a procedure for forming an exemplary field plate structure 500.

FIG. 5 depicts a field plate structure at one point of the process flow after the first etching step of a two-step etching process. At this point in the procedure, the polycrystalline silicon film deposited in the field plate trench 140 and the polycrystalline silicon film 252 as depicted in FIG. 2 are removed completely from the gate trench 150 at the same time. The silicon dioxide lining the walls of the field trench below the polycrystalline silicon film 252 is also removed simultaneously with the removal of the oxide film from the top of the silicon wafer as depicted in FIG.

In the structure depicted in FIG. 5, there is one lateral recess 543 of the silicon dioxide film 510 from the edge of the field plate trench 540. This is the result of an isotropic oxide etch step using which oxide is removed from the top and from the edges of the field plate trench 540 at approximately equal rates. The recessed portion 543 exposes a portion of the shoulder surface which is not covered by the oxide film 510.

The second and last etching steps of the two-step etching process are similar to the first and initial etching steps because the etching action is highly directional. Because the oxide film 510 exposes a portion of the shoulder 543 of the field plate trench, the exposed silicon will be etched and removed at about the same rate as the silicon at the bottom of the field plate trench 540. Therefore, the downward etching action generates the raised edge 143 feature and the raised edge 143 and the bottom of the field plate trench advance at the same rate until the etching process is completed and the depth of the field plate trench reaches the predetermined depth.

It should be noted that because the reactive ion etching is highly directional, the distance 544 between the raised edge and the bottom of the field plate trench is maintained at the end of the etching. In other words, the distance 544 is approximately the same at the beginning of the second etching step as depicted in FIG. 5 and at the completion of the step as depicted in FIG. 6. And this distance is substantially the same as the depth of the gate trench 150.

Figure 6 depicts the field plate structure at a later point in the program flow. At this point, the field plate trench is etched a second and last time, and the field plate trench has reached the designed depth of 149. A dielectric film 141 is used to line the walls 644 and 645 and the bottom surface 643 of the field trench. In this example, the film is silicon dioxide. And a conductive material 142 fills the field plate trench.

Because the width of the field plate trench 144 (see FIG. 1) is wider than the width of the gate trench 154, the field plate trench will be attributable to the micro loading effect at the first and initial etching steps. Etching is faster than the gate trench. In the context of this document, we identify but ignore this effect and, by approaching, make the depth of the gate trench after the first etching step equal to the etch depth of the field plate trench.

Example 6 An Alternative Method to Form a Field Plate Trench

7 and 8 are schematic diagrams illustrating an alternative method of forming a field plate trench. In the method described in FIG. 5, an etch mask 510 is created by partially removing the oxide film (which results in the recessed shoulder 543) on the covered area using an isotropic etching process; in the example In step 6, an anisotropic etching process is used to produce an etch mask 710 that maintains the oxide on the walls of the field plate trench.

FIG. 7 depicts the formation of hard masks 710 and 711. In this example, hard masks 710 and 711 are silicon dioxide. The thickness of the hard mask portion 710 covering the shoulder of the field plate is after the first etching step (which also removes all silicon dioxide from the bottom of the field plate trench 740), the original hard mask, the The gate oxide and the accumulated remainder of the deposited oxide.

The hard mask 711 covering the edge wall 741 of the field plate trench is the accumulation of the gate oxide 151 and the deposited silicon dioxide layer 310. In this example, the thickness of the hard mask 711 is about 0.4 micrometers thick, which is approximately the same as the thickness of the hard mask 710.

The distance 744 between the wafer surface 132 and the bottom of the field plate trench 740 at the beginning of the second etching step is substantially the same as the depth of the gate trench 150. Because the width of the field plate trench 144 (see FIG. 1) is wider than the width of the gate trench 154, the field plate trench will be attributable to the micro loading effect at the first and initial etching steps. Etching is faster than the gate trench. In the context of this document, we identify but ignore this effect and by approximating the depth of the gate trench after the first etching step is equal to that of the field plate trench. Etching depth.

During the second and last steps of the two-step etching process, only the portion of the field plate trench that is not covered by the hard mask (oxide element) 711 is etched. In this example, the raised edge 143 is the bottom portion of the field plate trench covered by the hard mask 711. And the distance between the raised edge 143 and the top of the trench is maintained during the second and last etch and is equal to the depth of the gate trench.

FIG. 8 depicts a field plate trench at one of the subsequent points in the process after completing the second and last etch of the field plate trench. After the second etching step, the field plate trench is lined with a layer of dielectric material 141. In this example, the liner is silicon dioxide. Since this exemplary structure is designed to withstand up to 100 volts, the thickness of the silicon dioxide is selected to be between 0.6 microns and 0.8 microns.

Finally, the field plate trench is filled with a conductive material 142, which is one of the other nodes used to electrically connect the device. In this example, the conductive material is doped polycrystalline silicon. Other conductive materials (such as metals) can also be used instead of or in combination.

Example 9 a light mask

FIG. 9 depicts a portion of a trench mask embodying aspects of the present invention. FIG. 9 depicts a repeating pattern of staggered gate trenches 950 having a width 954 and field plate trenches 940 having a width 944. The difference between the widths 944 and 954 is only representative.

Traditional light masks used in semiconductor manufacturing are made of a chrome metal quartz substrate with opaque patterns forming, for example, gate trenches 950 and field plate trenches 940. As the feature size shrinks, chromium and quartz light masks are replaced by other techniques to produce patterns on semiconductor wafers. This technique is electron beam writing, in which the pattern is "written" directly onto a photoresist dispersed on a wafer using an electron beam guided by a host computer.

Even though FIG. 9 depicts a portion of a conventional light mask that produces one of two sets of grooves at the same time, the present invention is applicable to updating techniques such as electron beam writing, as long as the two sets of grooves are patterned on a light lithography In this step, there is no need to align one pattern to the other and therefore the two groups Misalignment between the trenches is virtually eliminated.

Claims (21)

A procedure for forming two adjacent trenches in a wafer having a top semiconductor surface and a bottom semiconductor surface, the procedure includes: etching to remove semiconductor material to form a first trench and an adjacent modification. A wide second trench having a bottom and multiple shoulders; depositing a first material to fill the first trench to its full depth and covering the bottom of the second trench and the multiple Shoulders; removing the first material from the second trench and only partially from the first trench; and etching to remove semiconductor material so that the second trench extends deeper toward the bottom semiconductor surface, A final second trench is created and a raised edge is formed on a sidewall of the last second trench. The procedure of claim 1, wherein the position of the raised edge measured from the bottom of one of the last second grooves is equal to the depth of the first grooves. The procedure of claim 1, wherein the first trench and the last second trench are part of a MOSFET or a rectifier. A process for manufacturing a double groove device, comprising: providing a light mask having a repeating pattern for generating a first groove and a wider second groove; and using the light provided The mask forms an image on a surface of a wafer; etching to remove semiconductor material to form a first trench and a top portion of a wider second trench in the wafer; and depositing a first A first film covering a bottom portion and a shoulder portion of a top portion of the second trench but completely filling the first trench to its full depth; and performing a second etch to remove the semiconductor material and generate an extension A second trench deeper than the top portion thereof and a raised edge formed at a first distance from the second trench and at a second distance from the wafer surface. The process as claimed in claim 4, further comprising a removing step by which the first film is completely removed from the second trench, but is recessed only to a specific depth in the first trench. The process as claimed in claim 5, further comprising, after the removing step, forming a hard mask layer in the recess above the first film. The process of claim 4, wherein the first trench is shielded from the second trench by a hard mask layer. The process of claim 6, wherein the hard mask layer is formed by an isotropic oxide etching step. The process as claimed in claim 4, wherein the second etching step is anisotropic. The process of claim 6, wherein the hard mask layer exposes a portion of the shoulder of the second groove. The process as claimed in claim 4, wherein the first distance is equal to the depth of the first groove. The process of claim 4, wherein the second distance is equal to the depth of the first trench. A semiconductor device includes: a wafer formed of a semiconductor material having a top surface; a gate trench located in the wafer, extending from the top surface and having a first depth and a first width; A field plate trench located in the wafer, extending from the top surface and having a second depth deeper than the first depth, the gate trench has a field plate trench on each side; the field plate trench Including two sections with different widths-a first section and a second section, one of the first sections having a length equal to the first depth; and the gate trench and the field plate trench, which Dielectric material is lined with and filled with conductive material. The semiconductor device as claimed in claim 13, which is a MOSFET or a rectifier. The semiconductor device as claimed in claim 13, wherein the width of the first section and the second section is wider than the first width. The semiconductor device of claim 15, wherein the first section is closer to the top surface than the second section. The semiconductor device of claim 16, further comprising: a substrate having a dopant polarity; and an epitaxial material layer on the substrate having a dopant having the same polarity as the dopant of the substrate A dopant polarity; a body region located in the epitaxial material layer and having a dopant polarity opposite to the dopant polarity of the epitaxial material layer; and a source region located in the body region and Close to the top surface between the gate trench and the field trench, the source region has a dopant polarity that is the same as the dopant polarity of the substrate. The semiconductor device of claim 17, wherein the thickness of the dielectric material lining the gate trench is thinner than the thickness of the dielectric material lining the field plate trench. The semiconductor device of claim 15, wherein the second section is closer to the top surface than the first section. The semiconductor device according to claim 19, further comprising: a substrate having a dopant polarity; and an epitaxial material layer located on the substrate and having a dopant having the same polarity as the dopant of the substrate A dopant polarity; a body region located in the epitaxial material layer and having a dopant polarity opposite to the dopant polarity of the epitaxial material layer; and a source region located in the body region and Close to the top surface between the gate trench and the field trench, the source region has a dopant polarity that is the same as the dopant polarity of the substrate. The semiconductor device of claim 19, wherein the thickness of the dielectric material lining the gate trench is thinner than the thickness of the dielectric material lining the field plate trench.