TWI676987B - Data processing system and data processing method - Google Patents

Abstract

A data processing system includes a memory device, a processor, a memory controller, and a detection circuit. The memory device includes a first area and a second area, wherein the first area is configured to store plural codes, and the second area is configured to store system data. The processor is configured to execute at least one instruction according to the code, wherein the processor sends an access control signal to obtain at least a portion of the code. The memory controller is coupled between the processor and the memory device and is configured to access the memory device in response to the access control signal. The detection circuit is coupled to the memory controller and is configured to detect whether the processor has entered an idle state. When the detection circuit detects that the processor has entered an idle state, the detection circuit sends a processor idle signal. In response to the processor idle signal, the memory controller issues an erase command. In response to the erase command, at least a part of the data stored in the second area is erased.

Description

Data processing system and method

The invention relates to a data processing system and a data processing method, in particular to a data processing system and a data processing method which can effectively reduce the interference of the memory erasing operation on the system operation.

Non-volatile memory (non-volatile memory) is a type of memory that can retain data even after restarting after a power failure. When applied to a computer device or a processor device, non-volatile memory can usually be segmented into a code execution region for storing application code, or an application code region. , And a data log region for storing data or parameters that need to be changed or recorded during system operation.

Generally speaking, the write operation of non-volatile memory takes several to several tens of microseconds (uS), and the erase operation takes several to several tens of milliseconds (mS). Therefore, When data or parameters need to be changed or recorded during system operation, the processor will only perform write operations. That is, even if the data or parameters need to be changed or recorded again, in order to avoid the delay of the system process, the data or parameters are written directly into the new memory data page or memory block, instead of the original memory data page. Or erase and overwrite on the memory block.

When the usage rate of the data recording area reaches a certain level, it is still necessary to perform an erasing operation to erase the invalid data in the data recording area to free up memory space.

In order that the system operation (for example, access to the application code area) will not be affected by the data erasure process, and the system processing program will not be forced to be delayed or interrupted by the data erasure process, the present invention proposes A data processing system and a data processing method suitable for the system are used to control the erasing operation of the data recording area.

The invention discloses a data processing system including a memory device, a processor, a memory controller, and a detection circuit. The memory device includes a first area and a second area, wherein the first area is configured to store plural codes, and the second area is configured to store system data. The processor is configured to execute at least one instruction according to the code, wherein the processor sends an access control signal to obtain at least a portion of the code. The memory controller is coupled between the processor and the memory device and is configured to access the memory device in response to the access control signal. The detection circuit is coupled to the memory controller and is configured to detect whether the processor has entered an idle state. When the detection circuit detects that the processor has entered an idle state, the detection circuit sends a processor idle signal. In response to the processor idle signal, the memory controller issues an erase command. In response to the erase command, at least a part of the data stored in the second area is erased.

The invention discloses a data processing method suitable for a data processing system. The data processing system includes a memory device, a processor, and a memory controller. The memory device includes a first area and a second area. The first area is configured to The plurality of codes are stored. The second area is configured to store system data. The processor sends an access control signal to obtain at least a part of the code, and executes at least one instruction according to the obtained code. The memory controller responds to the access. The control signal accesses the memory device. The data processing method includes: receiving an erasure control signal; detecting whether the processor has entered an idle state; and sending a processor idle signal when it is detected that the processor has entered an idle state; In response to the processor idle signal, an erase command is issued; and in response to the erase command, at least a part of the data stored in the second area is erased.

In order to make the objects, features, and advantages of the present invention more comprehensible, specific embodiments of the present invention are specifically listed below, and described in detail with the accompanying drawings. The purpose is to explain the spirit of the present invention and not to limit the protection scope of the present invention. It should be understood that the following embodiments can be implemented by software, hardware, firmware, or any combination thereof.

As mentioned above, non-volatile memory can usually be divided into a code execution region, or application code region, for storing application code, and a storage system that needs The data log region of the data or parameters that were changed or recorded. When data or parameters need to be changed or recorded during system operation, the processor will only perform write operations. Even if the data or parameters need to be changed or recorded again, in order to avoid the delay of the system process, the data or parameters are written directly into the new memory data page or memory block, instead of the original memory data page or memory. Erase and overwrite blocks.

However, when the utilization rate of the data recording area reaches a certain level, it is still necessary to perform an erasing operation to erase invalid data in the data recording area to free up memory space.

Because the design of general flash memory will allocate the application code area and the data record area in the same flash memory, when the data record area needs to be erased, the system cannot access the application code area . That is, the program must stop running until the erase operation of the data recording area is completed.

In order not to affect the execution of the system program, a current solution is to first move the application code stored in the application code area to another memory device (for example, a static random access memory (Static Random Random Access Memory) -Access Memory (SRAM)), and then the system's processor is directed to the SRAM for execution, while the flash memory is erased. After the flash memory erasing operation is completed, the processor is directed back to the original flash memory for execution. However, this method will increase the complexity and difficulty of programming. At the same time, the system must also reserve an additional SRAM that can accommodate the code size, resulting in an increase in system cost.

Another current solution is to allocate the application code area and the data recording area in two completely independent flash banks, or in the same flash memory, but each has its own independent Erase / Program Control Circuit (Erase / Program Control Circuit), so that when the system erases the data recording area, the application code area can still be accessed by the system's processor. However, this method increases the cost of the hardware circuit and needs to be applied to specially customized flash memory.

In order that the system operation (for example, access to the application code area) will not be affected by the data erasure process, and the system processing program will not be forced to be delayed or interrupted due to the data erasure process, the present invention proposes a A data processing system and a data processing method suitable for the system are used to control the erasing operation of the data recording area. With the system and method provided by the present invention, the results of not interrupting the normal operation of the system program can be achieved without greatly increasing the hardware cost and the complexity of system program development. Compared with the prior art, the erasing operation can effectively Interference with system operation is minimized. The data processing system and data processing method proposed by the present invention will be described in more detail below.

FIG. 1 is a block diagram of a data processing system according to an embodiment of the present invention. According to an embodiment of the present invention, the data processing system 100 may be a Micro-Controller Unit (MCU). The data processing system 100 may include a memory device 110, a memory controller 120 and a processor 130. It is worth noting that FIG. 1 is a simplified block diagram in which only elements related to the present invention are shown. Anyone skilled in the art will understand that a data processing system may also include other components not shown in Figure 1.

According to an embodiment of the present invention, the memory device 110 includes a first region and a second region. The first region may be the above-mentioned code execution region, or an application code region. ) Is configured to store plural codes, and the second region may be the data log region described above, and is configured to store data or parameters that need to be changed or recorded during system operation (hereinafter referred to as system data) ). According to an embodiment of the present invention, the memory device 110 may be a flash memory.

The memory controller 120 is coupled between the processor 130 and the memory device 110 and is configured to control access of the memory device 110.

The processor 130 may send an access control signal to the memory controller 120, and the memory controller 120 accesses the memory device 110 according to the access control signal. That is, the processor 130 accesses the application code area and the data recording area of the memory device 110 through the memory controller 120 to obtain the code to be executed and the required system data, where the code can be The processor 130 may include one or more instructions, and the processor 130 may execute corresponding instructions according to the content of the code.

More specifically, the processor 130 may be coupled to the memory controller 120 through a bidirectional bus 21 to transmit a plurality of control signals, such as an access control signal, an erasure control signal, and the like to the memory. The controller 120 receives code and system data obtained from the memory device 110 through the memory controller 120.

The memory controller 120 can also be coupled to the memory device 110 through a plurality of buses. Among them, the control bus 22 is used to transmit a plurality of control commands (Command), and the address bus 23 is used to transmit the data to be accessed. Address, the data bus 24 is a two-way bus for transmitting data to be written into the memory device 110 and receiving data obtained from the memory device 110.

FIG. 2 is a block diagram of a data processing system according to another embodiment of the present invention. According to an embodiment of the present invention, the data processing system 200 may be a microcontroller (MCU). Most of the components included in the data processing system 200 are the same as those of the data processing system 100. Therefore, for related descriptions, reference may be made to the description in FIG. 1 above, and details are not described herein.

According to an embodiment of the present invention, the data processing system 200 may further include a direct memory access (DMA) controller 240. The DMA controller 240 is coupled to the memory controller 220 through a bidirectional bus 25 and is configured to access the memory device 210 through the memory controller 220. The bus 25 is used for transmitting a direct memory access request to the memory controller 220 and receiving data obtained from the memory device 210.

According to an embodiment of the present invention, the memory devices 110/210 may further include a plurality of registers. In one embodiment of the present invention, each memory block may be configured with a register that can be independently set and controlled. In another embodiment of the present invention, each memory data page may be configured with a register that can be independently set and controlled. Each register is used to store an erasing bit, which is used to indicate whether the data stored in a memory data page or a memory block corresponding to the register needs to be erased.

FIG. 3 is a schematic diagram showing erasing bits stored in a plurality of registers according to an embodiment of the present invention. Each erasure bit may correspond to a memory data page or a memory block. When the erase bit is set to 1, it means that the corresponding data stored in a memory data page or a memory block needs to be erased. Therefore, in this embodiment, when the memory controller 120/220 sends an erase command to the memory devices 110/210 to perform the erase operation, only the memory block number or the memory data page number is 2 and 3. The data stored in the memory block or memory data page will be erased, and the data stored in other memory blocks or memory data pages will not be affected. According to an embodiment of the present invention, the memory devices 120/220 may include an erasure control circuit 111/211. In response to the erase command issued by the memory controller 120/220, the erasure control circuit 111/211 can erase the second area (data recording area) according to the information carried by the erase bit as shown in FIG. 3 At least a part of the stored data, for example, the data stored in the second and third memory blocks or the memory data page.

FIG. 4 is a flowchart of an exemplary data processing method according to an embodiment of the present invention. First, the memory controller 120/220 may receive an erasure control signal from the processor 130/230 (step S402). According to an embodiment of the present invention, when the system needs to erase certain memory blocks or memory data pages in the second area (data recording area), it will send an erase to the memory controller 120/220. control signal. Here, the system refers to a whole of software and firmware programs designed for this data processing system 100/200 and processors 130/230 that execute the software and firmware programs. Therefore, the erasure control signal may be issued when the processor 130/230 executes the corresponding code, and through some corresponding judgments, it is considered that the erasure operation needs to be performed.

According to an embodiment of the present invention, the erasing control signal clips the addresses stored in the second area (data recording area) (or, the number of the memory block or the memory data page) to be erased. Information. Then, the memory controller 120/220 may set the erasure bit stored in the corresponding register according to the information carried by the erasure control signal (step S404). For example, the erase bit corresponding to the memory block or memory data page to be erased is set to a specific value. After the setting of the erasing bit is completed, the processor 130/230 will send a command (also a control signal) to the memory controller 120/220 to erase the memory block / memory data page. It is worth noting that in other embodiments of the present invention, the erase command of the memory block / memory data page may be issued together with the erase control signal, or may be integrated into the same control signal.

According to an embodiment of the present invention, the memory controller 120/220 may include an Erase Elapse Timer 121/221. After receiving the erase command, the memory controller 120/220 does not immediately execute the task of erasing the memory block / memory data page on the memory device 110/210, but first sets the erase time. Time, this timer stores the time required to erase the memory block / memory data page. It is worth noting that, in the embodiment of the present invention, when a plurality of memory blocks / memory data pages need to be erased, the erase operation of these memory blocks / memory data pages is performed simultaneously. . Therefore, the time stored by the erasure progress timer 121/221 does not need to change as the number of memory blocks / memory data pages to be erased changes. In the embodiment of the present invention, step S404 may also include setting the erasure timer 121/221.

According to an embodiment of the present invention, after the bit to be erased and the erasing timer 121/221 are set, the memory controller 120/220 will not immediately erase the memory area on the memory device 110/210. Block / memory data page work, but wait until the data processing system 100/200 or processor 130/230 is idle before the task of erasing the memory block / memory data page is performed.

According to an embodiment of the present invention, the memory controller 120/220 may further include a detection circuit 122/222 configured to detect whether the processor 130/230 has entered an idle state (step S406). According to an embodiment of the present invention, when the detection circuit 122/222 detects that the processor 130/230 has entered the idle state, it will send a processor idle signal Processor_Idle to the memory controller 120/220 (step S408), Make judgments for subsequent work. According to an embodiment of the present invention, the detection circuit 122/222 may set the processor idle signal Processor_Idle bit value to '1' to indicate that the processor 130/230 has entered an idle state.

According to the embodiment of the present invention as shown in FIG. 1, in response to the receipt of the processor idle signal Processor_Idle, the memory controller 120 sends an erase command to the memory device 110 to perform an erase operation (step S412) (implemented here) In the example, step S410 is skipped), and the erasing timer 121/221 is started to start counting at the same time. According to the embodiment shown in FIG. 2 of the present invention, in response to the reception of the processor idle signal Processor_Idle, the memory controller 220 further determines whether the DMA controller 240 has not issued a direct memory access request (step S410). When it is determined that the DMA controller 240 has not issued a direct memory access request, the memory controller 220 issues an erase command to the memory device 210 to perform the erase operation (step S412), and simultaneously starts the erase execution timer 121. / 221 starts timing.

Finally, in response to the erase command issued by the memory controller 120/220, the erasure control circuit 111/211 can erase at least a part of the data stored in the second area (data recording area) according to the information carried by the erase bit. (Step S414).

It is worth noting that in various implementable architectures of the present invention, the detection circuit and the erasure timer are not limited to being set in the memory controller. FIG. 5 is a block diagram of a data processing system according to yet another embodiment of the present invention. The data processing system 500 may be a microcontroller (MCU). Most of the components included in the data processing system 500 are the same as those of the data processing systems 100/200. Therefore, for related descriptions, please refer to the descriptions in FIGS. 1 and 2 above, and will not be repeated here.

In this embodiment, the erasure progress timer 521 and the detection circuit 522 are configured outside the memory controller 520 and can communicate with the memory controller 520 through corresponding buses and / or signal lines.

It is worth noting that the control methods, processes and operations performed by the components described above can be applied to the memory device 510, the erasure control circuit 511, the memory controller 520, the erasure as shown in FIG. 5 The timer 521, the detection circuit 522, the processor 530, and the DMA controller 540 are performed. Therefore, related descriptions can refer to the above description, and will not be repeated here.

According to an embodiment of the present invention, the detection circuit 122/222/522 can determine whether the processor 130/230/530 has entered an idle state by decoding the instruction executed by the processor 130/230/530. For example, the detection circuit 122/222/522 can interpret (interprete) the code that the processor 130/230/530 wants to obtain, so as to decode the instructions currently executed or to be executed by the processor 130/230/530. . According to an embodiment of the present invention, when the processor 130/230/530 executes the wait, while loop, jump to the same stroke code or hold and other related instructions, the detection circuit 122/222/522 can judge whether the processor 130/230/530 has entered the idle state according to the relevant instruction content.

More specifically, for example, when the processor 130/230/530 executes a WFI (Wait For Interrupt) instruction to wait for an interrupt signal from an external peripheral device, the detection circuit 122/222/522 can determine the processor 130/230/530 has entered an idle state. For another example, when the processor 130/230/530 executes a WFE (Wait For Event) instruction to wait for a specific event, the detection circuit 122/222/522 can determine that the processor 130/230/530 has entered Idle state. For another example, when the processor 130/230/530 executes a similar instruction such as a while (1) loop or JMP $, it will continue to stay or repeatedly jump to the execution of the same stroke code. The circuits 122/222/522 can determine that the processor 130/230/530 has entered an idle state.

According to another embodiment of the present invention, the detection circuit 122/222/522 can also detect whether the address corresponding to the program code obtained by the processor 130/230/530 has changed, thereby determining the processor 130/230. / 530 has entered the idle state. For example, when the address given by the processor 130/230/530 to the memory controller 110/210/520 (the address of the code to be accessed) is the same as one or more previous access requests The detection circuit 122/222/522 can determine that the processor 130/230/530 has entered an idle state.

According to yet another embodiment of the present invention, the detection circuit 122/222/522 can also determine whether the processor 130/230/530 has executed a specific instruction or has not sent the memory controller 120 / 220/520 sends an access control signal to fetch the code to be executed from the application code area to determine whether the processor 130/230/530 has entered an idle state. For example, if the processor 130/230/530 does not send an access control signal to the memory controller 120/220/520 for a certain period of time after executing a specific instruction, or obtain it from the application code area ( fetch), the detection circuit 122/222/522 can determine that the processor 130/230/530 has entered an idle state.

In the embodiment of the present invention, as long as one of the instruction decoding result, the judgment result of whether the code address is changed, and whether the access control signal is not issued to obtain the judgment result of the desired code is established, the detection is performed. The circuit 122/222/522 can judge that the processor 130/230/530 has entered the idle state.

According to an embodiment of the present invention, when the erasure control circuit 111/211/511 erases the data stored in the second area (data recording area) according to the information carried by the erasure bit, the memory controller 120/220 The / 520 can further judge whether the erasing operation is completed according to the timing result of the erasing progress timer 121/221/521. When the erase progress timer 121/221/521 overflows (for example, the timer counts out), it will send an overflow signal Time_out to notify the memory controller 120/220/520, and the memory controller 120 / 220/520 can infer that the erase operation should have been completed.

After receiving the overflow signal Time_out, the memory controller 120/220/520 can read the data in the memory block / memory data page to be erased to confirm whether the erase operation is successful. For example, if the data in the memory block / memory data page to be erased is a specific value, for example, if the content recorded by each element is 1, the memory controller 120/220/520 may It is judged that the erasing operation has been successfully completed, and a status register (for example, an erasing completion flag) inside the memory controller 120/220/520 can be set to notify the system that the erasing operation has been successfully completed. If the memory controller 120/220/520 determines that the erase operation was unsuccessful, the memory controller 120/220/520 can reset the erasure timer 121/221/521 and reset the memory device 110 again. / 210/510 issues an erase command to perform the erasing operation, and simultaneously starts the erasing timer 121/221/521 to count. This process can be repeated until the memory controller 120/220/520 confirms that the erase operation has been successfully completed.

It is worth noting that if the memory controller 120/220/520 detects the status of the processor idle signal Processor_Idle during the erase operation, for example, the original processor 130/230/530 has entered the idle state. State bit '1' changes to bit '0' representing the processor 130/230/530 entering a non-idle state, or, in another embodiment, during the erase operation, the memory controller 120 / 220/520 When the DMA controller 140/240/540 receives a direct memory access request, the memory controller 120/220/520 will immediately issue an interrupt command to the memory device 110/210/510 to interrupt the erase Division operation. At the same time, the memory controller 120/220/520 will also suspend erasing for timer 121/221/521. According to an embodiment of the present invention, until the memory controller 120/220/520 detects the processor idle signal Processor_Idle again to indicate that the processor 130/230/530 has entered the idle state (for example, changes to bit '1') Time), the memory controller 120/220/520 again sends an erase command to the memory device 110/210/510 to perform the erasing operation, and simultaneously starts the erasure timer 121/221/521 to count again. Or, in another embodiment, until the memory controller 120/220/520 detects the processor idle signal Processor_Idle again to indicate that the processor 130/230/530 has entered the idle state and judges the DMA controller 140/240 / When the 540 does not issue a direct memory access request, the memory controller 120/220/520 issues an erase command to the memory device 110/210/510 again to perform the erasing operation, and simultaneously starts the erasure timer 121 again. / 221/521.

FIG. 6 is a flowchart illustrating an example of a data processing method according to an embodiment of the present invention, and is used to explain the flow of the data processing method after the erasing operation is started. The process described in this embodiment is a control process performed by the memory controller 120/220/520. Before the system does not send the erasure control signal to the memory controller 120/220/520, the memory controller 120/220/520 performs its normal work. After the system sends an erase control signal and / or an erase command to the memory controller 120/220/520, the memory controller 120/220/520 can set the corresponding register location according to the information carried by the erase control signal. The erased bits are stored, and the erasing timer and the erasing completion flag are set (step S602). Next, the memory controller 120/220/520 determines whether the processor 130/230/530 has entered an idle state (step S604).

If not, the flow returns to step S604. If yes, the memory controller 220/520 further determines whether a direct memory access request is received from the DMA controller (step S606) (in some embodiments, step S606 may be omitted). If yes, the flow returns to step S604.

If the processor 130/230/530 has entered the idle state and has not received a direct memory access request, the memory controller 120/220/520 starts the erasure timer 121/221/521 to count (step S608), and an erase command is issued to the memory devices 110/210/510 to cause it to perform an erase operation (step S610). As described above, the erasure control circuit 111/211/5111 can erase at least a part of the data stored in the data recording area according to the set value of the erasure bit.

During the execution of the erase operation, the memory controller 120/220/520 continuously detects whether the state of the processor idle signal Processor_Idle has changed to determine whether the processor is still idle (step S612), and continues to determine whether A direct memory access request is received from the DMA controller (step S614) (in some embodiments, step S614 may be omitted). If the processor is still idle and no direct memory access request has been received from the DMA controller, the memory controller 120/220/520 further judges based on the timing results of the erasure timer 121/221/521 Whether the erasing operation is completed (step S616). If the erase operation has not been completed, the flow returns to step S612. If the erase operation has been completed, the memory controller 120/220/520 further confirms whether the erase operation is successful (step S618). If yes, the memory controller 120/220/520 sets the erasing completion flag (step S620) to notify the system that the erasing operation has been successfully completed. If not, the flow returns to step S602.

On the other hand, during the execution of the erase operation, if the memory controller 120/220/520 detects that the processor has entered a non-idle state, or receives a direct memory access request from the DMA controller, the memory The body controller 120/220/520 stops erasing the timer 121/221/521 (step S622), and issues an interrupt command to the memory device 110/210/510 (step S624) to interrupt the erasing operation. Then, the flow returns to step S604, the memory controller 120/220/520 returns to perform its normal work, and continuously waits for the state of the processor idle signal Processor_Idle to change again (for example, the bit value changes to '1' again), and / Or the judgment of the direct memory access request is no (that is, no direct memory access request has been received from the DMA controller, or no new one has been received after the previously received direct memory access request is completed Direct memory access request), then instruct the memory device 110/210/510 to continue to perform the previously uncompleted erase operation until the erasure timer 121/221/521 overflows (Time_out) and confirms the erasure Until the operation is successful.

As mentioned above, it is different from the prior art in that the data processing system and data processing method applicable to the system provided by the present invention can achieve the system program without interruption without greatly increasing hardware cost and system program development complexity. As a result of normal operation, compared with the prior art, the data processing system and method provided by the present invention can effectively minimize the interference degree of the erase operation on the system operation.

The use of ordinal numbers such as "first" and "second" in the scope of the patent application does not imply any priority, order of priority, order between elements, or the order of steps performed by the method. It is only used as an identifier to distinguish different elements with the same name (with different ordinal numbers).

Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

21, 22, 23, 24, 25‧‧‧ Bus

100, 200, 500‧‧‧ data processing system

110, 210, 510‧‧‧Memory devices

111, 211, 511‧‧‧ Erase control circuit

120, 220, 520‧‧‧Memory controller

121, 221, 521‧‧‧‧ Erase progress timer

122, 222, 522‧‧‧ detection circuits

130, 230, 530‧‧‧ processors

240, 540‧‧‧DMA controller

FIG. 1 is a block diagram of a data processing system according to an embodiment of the present invention. FIG. 2 is a block diagram of a data processing system according to another embodiment of the present invention. FIG. 3 is a schematic diagram showing erasing bits stored in a plurality of registers according to an embodiment of the present invention. FIG. 4 is a flowchart of an exemplary data processing method according to an embodiment of the present invention. FIG. 5 is a block diagram of a data processing system according to yet another embodiment of the present invention. FIG. 6 is a flowchart of an exemplary data processing method according to an embodiment of the present invention.

Claims (8)

A data processing system includes: a memory device including a first area and a second area, wherein the first area is configured to store plural codes, and the second area is configured to store system data; a A processor configured to execute at least one instruction according to the code, wherein the processor sends an access control signal to obtain at least a portion of the code; a memory controller coupled to the processor And the memory device are configured to access the memory device in response to an access control signal; a direct memory access controller is coupled to the memory controller and is configured to pass through the memory The memory controller accesses the memory device; and a detection circuit coupled to the memory controller and configured to detect whether the processor has entered an idle state; wherein the memory controller is further from the memory controller; The processor receives an erasure control signal and is used to set one or more erasure bits of the memory device according to the erasure control signal; wherein when the detection circuit detects that the processor has When entering the idle state, the detection circuit sends a processor idle signal; wherein after the one or more erase bits are set, the memory controller waits until the processor idle signal is received, and further judges The direct memory access controller does not issue a direct memory access request before issuing an erase command, and at least a portion of the data stored in the second area is erased in response to the erase command. The data processing system according to item 1 of the scope of patent application, wherein the detection circuit is disposed inside the memory controller. The data processing system according to item 1 of the scope of patent application, wherein the detection circuit determines whether the processor has entered the idle state by decoding the instruction executed by the processor. The data processing system according to item 1 of the scope of patent application, wherein the detection circuit determines whether the processor has entered the address by judging whether the address corresponding to the code that the processor wants to obtain has not changed. Idle state. The data processing system according to item 1 of the scope of patent application, wherein the memory device further includes a plurality of registers, each of which is used to store an erasure bit, and each erasure bit is used to indicate the register Whether the corresponding data stored in a memory data page or a memory block needs to be erased. A data processing method is applicable to a data processing system. The data processing system includes a memory device, a processor, a memory controller, and a direct memory access controller. The memory device includes a first area. And a second area, the first area is configured to store plural codes, the second area is configured to store system data, and the processor sends an access control signal to obtain at least a part of the codes And execute at least one instruction according to the obtained codes, the memory controller accesses the memory device according to the access control signal, and the direct memory access controller is configured to pass through the memory controller To access the memory device, the method includes: receiving an erasure control signal; setting one or more erasure bits of the memory device according to the erasure control signal; detecting whether the processor has entered an idle state ; When detecting that the processor has entered the idle state, a processor idle signal is issued; after the one or more erase bits are set, wait until After receiving the processor idle signal, it is further determined that the direct memory access controller does not issue a direct memory access request before issuing an erase command; and in response to the erase command, erase the second area At least part of the data stored. The data processing method according to item 6 of the scope of patent application, wherein the step of detecting whether the processor has entered an idle state further comprises: decoding the instruction executed by the processor to determine whether the processor has entered the idle state Idle state. The data processing method described in item 7 of the scope of patent application, wherein the step of detecting whether the processor has entered an idle state further includes: judging whether the addresses corresponding to the codes that the processor wants to obtain are not Change to determine if the processor has entered the idle state.