TW202008371A - Data processing system and data processing method - Google Patents

Abstract

A data processing system includes a memory device, a processor, a memory controller and a detection circuit. The memory device includes a first region and a second region. The first region is configured to store program codes and the second region is configured to store system data. The processor is configured to execute at least one instruction according to the program codes. The processor issues an access control signal to fetch at least a portion of the program codes stored in the first region. The memory controller is coupled between the processor and the memory device and is configured to access the memory device in response to the access control signal. The detection circuit is coupled to the memory controller and is configured to detect whether the processer has entered an idle state. When the detection circuit detects that the processer has entered the idle state, the detection circuit issues a processor idle signal. In response to the processor idle signal, the memory controller issues an erase command. In response to the erase command, the memory device erases at least a portion of data stored in the second region.

Description

Data processing system and data processing method

The invention relates to a data processing system and a data processing method, in particular to a data processing system and a data processing method which can effectively reduce the interference of the erase operation of the memory to the system operation.

Non-volatile memory (Non-volatile memory) is a kind of memory that can retain data even after power-off and restart. When applied to a computer device or a processor device, the non-volatile memory can usually be divided into a code execution region (application code region) for storing application code And a data log region used to store data or parameters that need to be changed or recorded during system operation.

Generally speaking, the write operation of non-volatile memory takes several to tens of microseconds (uS), and the erase operation takes several to tens of milliseconds (mS). Therefore, When the system needs to change or record data or parameters during operation, the processor will only perform write operations. That is, even if the data or parameters need to be changed or recorded again, in order to avoid delays in system processing procedures, the data or parameters are written directly to the new memory data page or memory block, rather than the original memory data page Or erase and overwrite on the memory block.

When the usage rate of the data recording area reaches a certain level, it is still necessary to perform an erasing operation to erase invalid data in the data recording area to free up memory space.

In order that the system operation (for example, access to the application code area) will not be affected by the data erasure, and the system processing procedure will not be forced to be delayed or interrupted by the data erasure, the present invention proposes a A data processing system and a data processing method suitable for this system are used to control the erasing operation of the data recording area.

The invention discloses a data processing system including a memory device, a processor, a memory controller and a detection circuit. The memory device includes a first area and a second area, wherein the first area is configured to store a plurality of program codes, and the second area is configured to store system data. The processor is configured to execute at least one instruction according to the code, wherein the processor issues an access control signal to obtain at least a part of the code. The memory controller is coupled between the processor and the memory device, and is configured to access the memory device in response to the access control signal. The detection circuit is coupled to the memory controller and is configured to detect whether the processor has entered an idle state. When the detection circuit detects that the processor has entered an idle state, the detection circuit sends a processor idle signal. In response to the processor idle signal, the memory controller issues an erase command. In response to the erase command, the memory device erases at least a part of the data stored in the second area.

The invention discloses a data processing method suitable for a data processing system. The data processing system includes a memory device, a processor and a memory controller. The memory device includes a first area and a second area. The first area is configured to Store a plurality of code, the second area is configured to store system data, the processor sends an access control signal to obtain at least a part of the code, and executes at least one command according to the obtained code, the memory controller responds to the access The control signal accesses the memory device. The data processing method includes: receiving an erase control signal; detecting whether the processor has entered an idle state; and sending a processor idle signal when it is detected that the processor has entered the idle state; An erase command is issued in response to the processor idle signal; and at least a portion of the data stored in the second area is erased in response to the erase command.

In order to make the purpose, features and advantages of the present invention more obvious and understandable, specific embodiments of the present invention are specifically listed below, and in conjunction with the accompanying drawings, detailed descriptions are as follows. The purpose is to illustrate the spirit of the present invention rather than to limit the protection scope of the present invention. It should be understood that the following embodiments can be implemented by software, hardware, firmware, or any combination of the above.

As mentioned above, non-volatile memory can generally be divided into a code execution region, or application code region, for storing application code, as well as storage system operation needs. The data log region of the changed or recorded data or parameters. When the system needs to change or record data or parameters during operation, the processor will only perform write operations. Even if the data or parameters need to be changed or recorded again, in order to avoid delays in system processing procedures, the data or parameters are written directly to the new memory data page or memory block, rather than the original memory data page or memory Erase and overwrite on the block.

However, when the usage rate of the data recording area reaches a certain level, it is still necessary to perform an erasing operation to erase invalid data in the data recording area to free up memory space.

Since the design of the general flash memory will arrange the application code area and the data recording area in the same flash memory, when the data recording area needs to be erased, the system cannot access the application code area . That is, the program must stop running until the erase operation of the data recording area is completed.

In order not to affect the execution of system programs, a current solution is to first move the application code stored in the application code area to another memory device (for example, a static random access memory (Static Random -Access Memory, SRAM)), then direct the system's processor to SRAM for execution, and at the same time erase the flash memory. After the flash memory erase operation is completed, the processor is directed back to the original flash memory for execution. However, this method will increase the complexity and difficulty of programming. At the same time, the system must reserve an additional SRAM that can accommodate the size of the code, resulting in an increase in system cost.

Another current solution is to configure the application code area and data record area in two completely independent flash memory banks (banks), or in the same flash memory, but each has its own independent The Erase/Program Control Circuit makes the application code area still accessible by the system processor when the system is erasing the data recording area. However, this method will increase the cost of the hardware circuit, and needs to be applied to a specially customized flash memory.

In order that the system operation (for example, access to the application code area) will not be affected by the data erasure, and the system processing procedure will not be forced to be delayed or interrupted by the data erasure, the present invention proposes a A data processing system and a data processing method suitable for this system are used to control the erasing operation of the data recording area. With the system and method proposed by the present invention, without significantly increasing the cost of hardware and the complexity of system program development, the result of uninterrupted normal operation of the system program can be achieved, and compared with the prior art, the erasing operation can be effectively The degree of interference of system operation is minimized. The data processing system and data processing method proposed in the present invention will be described in more detail below.

Figure 1 shows a block diagram of a data processing system according to an embodiment of the invention. According to an embodiment of the present invention, the data processing system 100 may be a microcontroller (Micro-Controller Unit, MCU). The data processing system 100 may include a memory device 110, a memory controller 120, and a processor 130. It is worth noting that Figure 1 is a simplified block diagram showing only the components related to the present invention. Anyone familiar with this art should understand that a data processing system may also include other components not shown in FIG.

According to an embodiment of the invention, the memory device 110 includes a first region and a second region. The first region may be the aforementioned code execution region, or application code region ), configured to store plural code, the second area can be the above data log region (data log region), configured to store data or parameters that need to be changed or recorded during system operation (hereinafter referred to as system data) ). According to an embodiment of the invention, the memory device 110 may be a flash memory.

The memory controller 120 is coupled between the processor 130 and the memory device 110 and is configured to control the access of the memory device 110.

The processor 130 may send an access control signal to the memory controller 120, and the memory controller 120 accesses the memory device 110 in response to the access control signal. That is, the processor 130 accesses the application code area and the data recording area of the memory device 110 through the memory controller 120 to fetch the program code to be executed and the required system data, where the code can be Including one or more instructions, the processor 130 can execute the corresponding instructions according to the content of the program code.

More specifically, the processor 130 may be coupled to the memory controller 120 through a bidirectional bus 21 to transmit a plurality of control signals, such as access control signals, erase control signals, etc. to the memory The controller 120, and receives the program code and system data obtained from the memory device 110 through the memory controller 120.

The memory controller 120 can also be coupled to the memory device 110 through a plurality of busses, wherein the control bus 22 is used to send a plurality of control commands (Command), and the address bus 23 is used to send data to be accessed Address, the data bus 24 is a bidirectional bus used to transmit data to be written to the memory device 110 and receive data obtained from the memory device 110.

Figure 2 is a block diagram of a data processing system according to another embodiment of the invention. According to an embodiment of the invention, the data processing system 200 may be a microcontroller (MCU). Most of the components included in the data processing system 200 are the same as those of the data processing system 100. Therefore, for related descriptions, reference may be made to the introduction in FIG. 1 above, and details are not repeated here.

According to an embodiment of the present invention, the data processing system 200 may further include a direct memory access (DMA) controller 240. The DMA controller 240 is coupled to the memory controller 220 through a bidirectional bus 25, and is configured to access the memory device 210 through the memory controller 220. The bus 25 is used to send a direct memory access request to the memory controller 220 and receive data obtained from the memory device 210.

According to an embodiment of the invention, the memory device 110/210 may further include a plurality of registers. In one embodiment of the present invention, each memory block can be configured with a register that can be independently set and controlled. In another embodiment of the present invention, each memory data page may be configured with a register that can be independently set and controlled. Each register is used to store an erase bit to indicate whether the data stored in a memory data page or a memory block corresponding to the register needs to be erased.

FIG. 3 is a schematic diagram showing erase bits stored in a complex register according to an embodiment of the invention. Each erase bit may correspond to a memory data page or a memory block. When the erase bit is set to 1, it means that the data stored in a corresponding memory data page or a memory block needs to be erased. Therefore, in this embodiment, when the memory controller 120/220 issues an erase command to the memory device 110/210 to perform an erase operation, only the memory block number or memory data page number is 2 and 3. The data stored in the memory block or the memory data page will be erased, and the data stored in other memory blocks or the memory data page will not be affected. According to an embodiment of the invention, the memory device 120/220 may include an erase control circuit 111/211. In response to the erase command issued by the memory controller 120/220, the erase control circuit 111/211 can erase the second area (data recording area) based on the information carried by the erase bit as shown in FIG. 3 At least a part of the stored data, for example, the data stored in the second or third memory block or the memory data page.

FIG. 4 is a flowchart showing an example of a data processing method according to an embodiment of the invention. First, the memory controller 120/220 may receive an erase control signal from the processor 130/230 (step S402). According to an embodiment of the present invention, when the system needs to erase certain memory blocks or memory data pages in the second area (data recording area), it will send an erase to the memory controller 120/220 control signal. Here, the system refers to the entirety of the software and firmware programs designed for the data processing system 100/200 and the processors 130/230 that execute the software and firmware programs. Therefore, the erasure control signal can be issued when the processor 130/230 executes the corresponding program code, and after some corresponding judgment that the erasure operation needs to be performed.

According to an embodiment of the present invention, the data stored in the addresses (or the number of the memory block or memory data page) in the second area (data recording area) with the erasure control signal needs to be erased News. Then, the memory controller 120/220 can set the erase bit stored in the corresponding register according to the information carried by the erase control signal (step S404). For example, the erase bit corresponding to the memory block or memory data page to be erased is set to a specific value. After the erasing bit setting is completed, the processor 130/230 will issue a command (also a kind of control signal) to the memory controller 120/220 to erase the memory block/memory data page. It is worth noting that in other embodiments of the present invention, the erase command of the memory block/memory data page may also be issued together with the erase control signal, or may be integrated into the same control signal.

According to an embodiment of the invention, the memory controller 120/220 may include an Erase Elapse Timer 121/221. After receiving the erase command, the memory controller 120/220 does not immediately erase the memory block/memory data page to the memory device 110/210, but first sets the erase for timing The time of the device. This timer stores the time required to erase the memory block/memory data page. It is worth noting that, in the embodiment of the present invention, when a plurality of memory blocks/memory data pages need to be erased, the erasing operations of these memory blocks/memory data pages are simultaneously performed . Therefore, the time stored in the erase progress timer 121/221 does not need to change as the number of memory blocks/memory data pages to be erased changes. In the embodiment of the present invention, step S404 may also include setting the erasure timer 121/221.

According to an embodiment of the present invention, after the erasing bit and erasing progress timer 121/221 are set, the memory controller 120/220 still does not immediately erase the memory area of the memory device 110/210 The task of block/memory data page is to wait until the data processing system 100/200 or the processor 130/230 is idle before the task of erasing the memory block/memory data page is performed.

According to an embodiment of the invention, the memory controller 120/220 may further include a detection circuit 122/222 configured to detect whether the processor 130/230 has entered an idle state (step S406). According to an embodiment of the present invention, when the detection circuit 122/222 detects that the processor 130/230 has entered an idle state, it will issue a processor idle signal Processor_Idle to the memory controller 120/220 (step S408), Do the basis for subsequent work judgment. According to an embodiment of the present invention, the detection circuit 122/222 may set the value of the processor idle signal Processor_Idle bit to '1', which represents that the processor 130/230 has entered the idle state.

According to the embodiment shown in FIG. 1 of the present invention, in response to the reception of the processor idle signal Processor_Idle, the memory controller 120 issues an erase command to the memory device 110 to perform an erase operation (step S412) (implemented here In the example, step S410 is skipped), and at the same time, the erasure progress timer 121/221 is started to start timing. According to the embodiment shown in FIG. 2 of the present invention, in response to the reception of the processor idle signal Processor_Idle, the memory controller 220 further determines whether the DMA controller 240 has not issued a direct memory access request (step S410). When it is determined that the DMA controller 240 has not issued a direct memory access request, the memory controller 220 issues an erase command to the memory device 210 to perform an erase operation (step S412), and simultaneously starts the erase progress timer 121 /221 starts timing.

Finally, in response to the erase command issued by the memory controller 120/220, the erase control circuit 111/211 can erase at least a part of the data stored in the second area (data recording area) according to the information carried by the erase bit (Step S414).

It is worth noting that, in various implementable architectures of the present invention, the detection circuit and the erase progress timer are not limited to being installed in the memory controller. Figure 5 is a block diagram of a data processing system according to yet another embodiment of the present invention. The data processing system 500 may be a microcontroller (MCU). Most of the components included in the data processing system 500 are the same as those of the data processing system 100/200. Therefore, for related descriptions, reference may be made to the introductions in FIGS. 1 and 2 above, and they are not repeated here.

In this embodiment, the erasure progress timer 521 and the detection circuit 522 are arranged outside the memory controller 520, and can communicate with the memory controller 520 through corresponding bus bars and/or signal traces.

It is worth noting that the control methods, processes and operations performed by the components described above can be applied to the memory device 510, the erase control circuit 511, the memory controller 520, and the erase as shown in FIG. A timer 521, a detection circuit 522, a processor 530, a DMA controller 540, etc. are performed. Therefore, the relevant description can refer to the above introduction, and will not be repeated here.

According to an embodiment of the present invention, the detection circuit 122/222/522 can determine whether the processor 130/230/530 has entered an idle state by decoding the instruction executed by the processor 130/230/530. For example, the detection circuit 122/222/522 can interpret the code to be obtained by the processor 130/230/530 to decode the instruction currently executed or to be executed by the processor 130/230/530 . According to an embodiment of the invention, when the processor 130/230/530 executes wait, while loop, jump to the same line of code or hold and other related instructions, the detection circuit 122/222/522 can determine whether the processor 130/230/530 has entered the idle state according to the relevant instruction content.

More specifically, for example, when the processor 130/230/530 executes a WFI (Wait For Interrupt) command to wait for an external peripheral device to issue an interrupt signal, the detection circuit 122/222/522 can determine the processor 130/230/530 has entered the idle state. As another example, when the processor 130/230/530 executes a WFE (Wait For Event) command to wait for a specific event, the detection circuit 122/222/522 can determine that the processor 130/230/530 has entered Idle state. For another example, when the processor 130/230/530 executes a similar instruction such as while(1) loop or JMP $, it will continue to stay or jump to the same line of code repeatedly. The circuit 122/222/522 can determine that the processor 130/230/530 has entered an idle state.

According to another embodiment of the present invention, the detection circuit 122/222/522 can also detect whether the address corresponding to the program code to be obtained by the processor 130/230/530 has changed, according to which the processor 130/230 is determined /530 has entered the idle state. For example, when the address (the address of the code to be accessed) sent by the processor 130/230/530 to the memory controller 110/210/520 is the same as the previous one or more access requests The detection circuit 122/222/522 can determine that the processor 130/230/530 has entered the idle state.

According to yet another embodiment of the present invention, the detection circuit 122/222/522 may also be based on whether the processor 130/230/530 executes a certain instruction or does not report to the memory controller 120/ The 220/520 sends an access control signal to fetch the code to be executed from the application code area to determine whether the processor 130/230/530 has entered an idle state. For example, if the processor 130/230/530 does not send an access control signal to the memory controller 120/220/520 after executing a certain instruction or for a period of time to obtain from the application code area ( fetch) the code to be executed, the detection circuit 122/222/522 can determine that the processor 130/230/530 has entered an idle state.

In the embodiment of the present invention, as long as one of the instruction decoding result, the judgment result of whether the program code address is changed, and whether the access control signal is not issued to obtain the code to be executed is established, the detection The circuit 122/222/522 can then determine that the processor 130/230/530 has entered an idle state.

According to an embodiment of the present invention, when the erasing control circuit 111/211/511 erases the data stored in the second area (data recording area) according to the information carried by the erasing bit, the memory controller 120/220 /520 may further determine whether the erasing operation is completed according to the timing result of the erasing progress timer 121/221/521. When the erasure progress timer 121/221/521 overflows (for example, when the timer counts up to expire), an overflow signal Time_out is sent to notify the memory controller 120/220/520 and the memory controller 120/ 220/520 can infer that the erase operation should have been completed.

After receiving the overflow signal Time_out, the memory controller 120/220/520 can read the data in the memory block/memory data page to be erased to confirm whether the erase operation is successful. For example, if the data in the memory block/memory data page to be erased is a specific value, for example, the content recorded by each bit is 1, the memory controller 120/220/520 may It is determined that the erasing operation has been successfully completed, and a state register (for example, an erasing completed flag) in the memory controller 120/220/520 can be set to notify the system that the erasing operation has been successfully completed. If the memory controller 120/220/520 determines that the erase operation is unsuccessful, the memory controller 120/220/520 may reset the time of the erasure progress timer 121/221/521, and the memory device 110 again /210/510 issues an erase command to perform an erase operation, and at the same time restarts the erase progress timer 121/221/521 to count. This process can be repeated until the memory controller 120/220/520 confirms that the erase operation has been successfully completed.

It is worth noting that if the memory controller 120/220/520 detects a state change of the processor idle signal Processor_Idle during the erase operation, for example, the original representative processor 130/230/530 has entered idle The bit '1' of the state changes to a bit '0' representing that the processor 130/230/530 enters the non-idle state, or, in another embodiment, during the erase operation, the memory controller 120 /220/520 When receiving a direct memory access request from the DMA controller 140/240/540, the memory controller 120/220/520 will immediately issue an interrupt command to the memory device 110/210/510 to interrupt the erase Except operation. At the same time, the memory controller 120/220/520 will also pause erasing and count the timers 121/221/521. According to an embodiment of the present invention, until the memory controller 120/220/520 detects the processor idle signal Processor_Idle again to indicate that the processor 130/230/530 has entered the idle state (for example, it transitions to bit '1' Time), the memory controller 120/220/520 issues an erase command to the memory device 110/210/510 again to perform the erase operation, and at the same time restarts the eraser timer 121/221/521 to count. Or, in another embodiment, until the memory controller 120/220/520 detects the processor idle signal Processor_Idle again indicating that the processor 130/230/530 has entered the idle state and judges the DMA controller 140/240/ When the 540 does not issue a direct memory access request, the memory controller 120/220/520 issues an erase command to the memory device 110/210/510 again to perform the erase operation, and at the same time starts the erasure timer 121 /221/521 for timing.

FIG. 6 is an exemplary flowchart of a data processing method according to an embodiment of the present invention, for illustrating the flow of the data processing method after the start of the erasing operation. The process described in this embodiment is a control process executed by the memory controller 120/220/520. When the system does not send an erase control signal to the memory controller 120/220/520, the memory controller 120/220/520 performs its normal work. After the system sends an erase control signal and/or an erase command to the memory controller 120/220/520, the memory controller 120/220/520 can set the corresponding register location according to the information carried by the erase control signal The stored erasure bit is set, and the time for the erasure timer is set, and the erasure complete flag is cleared (step S602). Next, the memory controller 120/220/520 determines whether the processor 130/230/530 has entered the idle state (step S604).

If not, the flow returns to step S604. If yes, the memory controller 220/520 further determines whether a direct memory access request is received from the DMA controller (step S606) (in some embodiments, step S606 may be omitted). If yes, the flow returns to step S604.

If the processor 130/230/530 has entered an idle state and has not received a direct memory access request, the memory controller 120/220/520 starts the erasure timer 121/221/521 to count (step S608), and issue an erase command to the memory device 110/210/510 to perform an erase operation (step S610). As described above, the erasing control circuit 111/211/5111 can erase at least a part of the data stored in the data recording area according to the setting value of the erasing bit.

During the execution of the erase operation, the memory controller 120/220/520 continuously detects whether the state of the processor idle signal Processor_Idle changes to determine whether the processor is still in the idle state (step S612), and continuously determines whether A direct memory access request is received from the DMA controller (step S614) (in some embodiments, step S614 may be omitted). If the processor is still idle and no direct memory access request is received from the DMA controller, the memory controller 120/220/520 further determines the timing results of the timers 121/221/521 based on the erase Whether the erase operation is completed (step S616). If the erase operation has not been completed, the flow returns to step S612. If the erase operation is completed, the memory controller 120/220/520 further confirms whether the erase operation is successful (step S618). If yes, the memory controller 120/220/520 sets the erasure complete flag (step S620) to notify the system that the erasure operation has been successfully completed. If not, the flow returns to step S602.

On the other hand, during the execution of the erase operation, if the memory controller 120/220/520 detects that the processor has entered a non-idle state, or receives a direct memory access request from the DMA controller, the memory The body controller 120/220/520 stops the erase progress timer 121/221/521 (step S622), and issues an interrupt command to the memory device 110/210/510 (step S624) to interrupt the erase operation. Then, the flow returns to step S604, the memory controller 120/220/520 resumes performing its normal work, and continues to wait for the state of the processor idle signal Processor_Idle to change again (for example, the bit value changes to '1' again), and /Or the judgment of the direct memory access request is negative (ie, no direct memory access request is received from the DMA controller, or no new memory is received after the completion of the previously received direct memory access request Direct memory access request), and then instruct the memory device 110/210/510 to continue to perform the previously unfinished erase operation until the erase progress timer 121/221/521 overflow (Time_out) and confirm the erase Until the operation is successful.

As described above, the difference from the prior art is that the data processing system and the data processing method applicable to the system proposed by the present invention can achieve uninterrupted system programs without significantly increasing the hardware cost and the complexity of system program development The result of normal operation, and compared with the prior art, the data processing system and method proposed by the present invention can effectively minimize the degree of interference of the erase operation with the system operation.

The use of ordinal numbers such as "first" and "second" in the scope of the patent application to modify an element itself does not imply any priority, priority order, order between elements, or order of steps performed by the method, It is only used as a logo to distinguish different components with the same name (with different ordinal numbers).

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone who is familiar with this skill can do some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be as defined in the scope of the attached patent application.

21, 22, 23, 24, 25‧‧‧‧ bus; 100, 200, 500‧‧‧‧ data processing system; 110, 210, 510‧‧‧ memory device; 111, 211, 511‧‧‧ erasing control Circuit; 120, 220, 520‧‧‧ memory controller; 121, 221, 521‧‧‧ erasing timer; 122, 222, 522‧‧‧ detection circuit; 130, 230, 530‧‧‧ processing Controller; 240, 540 ‧‧‧ DMA controller

Figure 1 shows a block diagram of a data processing system according to an embodiment of the invention. Figure 2 is a block diagram of a data processing system according to another embodiment of the invention. FIG. 3 is a schematic diagram showing erase bits stored in a complex register according to an embodiment of the invention. FIG. 4 is a flowchart showing an example of a data processing method according to an embodiment of the invention. Figure 5 is a block diagram of a data processing system according to yet another embodiment of the present invention. FIG. 6 is an exemplary flowchart of a data processing method according to an embodiment of the invention.

21, 22, 23, 24, 25 ‧‧‧ bus

200‧‧‧Data processing system

210‧‧‧Memory device

211‧‧‧Erase control circuit

220‧‧‧Memory controller

221‧‧‧Erase progress timer

222‧‧‧ detection circuit

230‧‧‧ processor

240‧‧‧DMA controller

Claims (10)

A data processing system includes: a memory device including a first area and a second area, wherein the first area is configured to store a plurality of program codes, and the second area is configured to store system data; A processor configured to execute at least one instruction according to the program codes, wherein the processor issues an access control signal to obtain at least a portion of the program codes; a memory controller coupled to the processor And the memory device, configured to access the memory device in response to an access control signal; and a detection circuit, coupled to the memory controller, configured to detect whether the processor Has entered an idle state; wherein when the detection circuit detects that the processor has entered the idle state, the detection circuit sends a processor idle signal, and in response to the processor idle signal, the memory controller An erase command is issued, and in response to the erase command, the memory device erases at least a portion of the data stored in the second area. The data processing system as described in item 1 of the patent application scope, wherein the detection circuit is provided inside the memory controller. The data processing system as described in item 1 of the patent application scope, wherein the detection circuit determines whether the processor has entered the idle state by decoding the instruction executed by the processor. A data processing system as described in item 1 of the patent application scope, wherein the detection circuit determines whether the processor has entered the program by determining whether the addresses corresponding to the program codes that the processor wants to obtain have not changed Idle state. The data processing system as described in item 1 of the patent application scope, wherein the memory device further includes a plurality of registers, each register is used to store an erase bit, and each erase bit is used to indicate the register Whether the data stored in a corresponding memory data page or a memory block needs to be erased. The data processing system as described in item 1 of the patent application range, wherein the memory controller further receives an erase control signal from the processor for setting one or more of the memory devices according to the erase control signal Erase bits, and after the one or more erase bits are set, the memory controller waits until the processor idle signal is received before issuing the erase command. The data processing system described in item 6 of the patent application scope further includes: a direct memory access controller, coupled to the memory controller, configured to access the memory through the memory controller Device; wherein after the one or more erase bits are set, the memory controller waits until the processor idle signal is received, and further determines that the direct memory access controller has not issued a direct memory After the access request, the erase command is issued. A data processing method suitable for a data processing system including a memory device, a processor and a memory controller, the memory device includes a first area and a second area, the first The area is configured to store plural codes, the second area is configured to store system data, the processor sends an access control signal to obtain at least a part of the codes, and according to the obtained codes Execute at least one instruction, the memory controller accesses the memory device in response to the access control signal, the method includes: receiving an erase control signal; detecting whether the processor has entered an idle state; when detected When the processor has entered the idle state, a processor idle signal is issued; an erase command is issued in response to the processor idle signal; and at least a portion of the data stored in the second area is erased in response to the erase command. The data processing method as described in item 8 of the patent application scope, wherein the step of detecting whether the processor has entered an idle state further includes: decoding the instruction executed by the processor to determine whether the processor has entered the Idle state. The data processing method as described in item 9 of the patent application scope, wherein the step of detecting whether the processor has entered an idle state further includes: determining whether the address corresponding to the program codes that the processor wants to obtain is not Change to determine whether the processor has entered the idle state.

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