TWI675126B - Method for extending holes on textured surface of the silicon wafer - Google Patents

Abstract

A method for reaming a plurality of holes on a textured surface of a silicon wafer. The reaming method according to the present invention firstly immerses a silicon wafer in an etching solution to maintain an etching time to perform a reaming process. The components of the etching solution include HNO ₃ , HF, and H ₃ PO ₄ . Then, according to the method for expanding holes in the present invention, the silicon wafer is subjected to a first cleaning process. Next, according to the method for expanding a hole of the present invention, a silicon wafer is immersed in an alkaline solution to perform a modification process. Next, according to the method of expanding the hole of the present invention, the silicon wafer is subjected to a second cleaning process. Next, according to the method for expanding a hole of the present invention, the silicon wafer is subjected to pickling treatment. Then, according to the method for expanding a hole of the present invention, the silicon wafer is subjected to a third cleaning process. Finally, the reaming method according to the present invention is to dry a silicon wafer.

Description

Hole reaming method for holes on textured surface of silicon wafer

The present invention relates to a method for reaming a plurality of holes on a textured surface of a silicon wafer, and in particular, to a method for reaming a silicon wafer having a low reflectance.

At present, in the field of silicon solar cells, the silicon wafers they use are more common: polycrystalline silicon wafers, single crystal silicon wafers, and similar single crystal silicon wafers. Silicon wafers extracted from silicon ingots are more commonly cut by mortar cutting and diamond wire cutting. The silicon wafer obtained by slicing from a silicon ingot must be subjected to a texturing process to produce a texturized surface with a low reflectance.

In the past, polycrystalline silicon wafers cut by mortar were generally made by acid texturing, and single wafers cut by diamond wire were generally made by alkaline texturing. Due to the high market share of polycrystalline silicon, in order to further reduce the cost of polycrystalline silicon wafer solar cells, the existing polycrystalline silicon ingot slicing has been widely changed to diamond wire cutting technology. Compared with traditional mortar cutting technology, the use of diamond wire-cut polycrystalline silicon ingots has been widely used by slicing manufacturers due to its advantages in environmental protection, greater cost reduction space, and greater efficiency space for polycrystalline silicon solar cells. s concern.

However, compared with mortar-cut polycrystalline silicon wafers, if diamond wire-cut polycrystalline silicon wafers are made of textured surfaces using the acid texturing technology widely used by solar cell manufacturers, the surface of the silicon wafers obtained by diamond wire cutting The damage layer is relatively thin, about 1 to 3 microns, and the reactivity is not enough. After texturing, the reflectivity of polycrystalline silicon wafers cut with diamond wire will be higher than that with mortar. The reflectivity of polycrystalline silicon wafers is 4 ~ 6% higher. The increase in reflectivity will cause the short-circuit current of solar cells to decrease, which will affect the photoelectric conversion efficiency of diamond wire-cut polycrystalline silicon solar cells.

For diamond wire-cut polycrystalline silicon wafers, recently, some manufacturers have also tried to use reactive-ion etching (RIE) technology, metal catalyzed texturing (MCT) technology, silver-induced nanotechnology, and other technologies. Wool, trying to reduce the reflectivity of diamond wire-cut polycrystalline silicon wafers. Although these previous technologies can increase the light trapping effect and reduce the reflectivity of diamond wire-cut polycrystalline silicon wafers after texturing, at the same time, too many composite centers are formed on the surface of the silicon wafers, so that the final solar cell is obtained. The short-circuit current increases, but the open-circuit voltage decreases, which is not conducive to reducing the packaging loss after the final battery slice is made into a component. In addition, these texturing technologies still have a lot of room to increase the reflectivity of diamond wire-cut polycrystalline silicon wafers. The inventor of this case has developed the acid wafer and self-catalyst vapor for texturing silicon wafers, which is especially suitable for diamond wire-cut polycrystalline silicon wafers.

Please refer to FIG. 1, a schematic partial cross-sectional view of a typical silicon wafer 1 is shown in FIG. 1. As shown in FIG. 1, the textured surface 10 of the silicon wafer 1 has a plurality of nano-holes 12. The texturing of diamond wire-cut polycrystalline silicon wafer 1 with acid vapor and self-catalyst vapor will form a plurality of nano-sized holes 13 on the surface 10 of polycrystalline silicon wafer 1, as shown in FIG. The existence of a 10 nm structure on the surface of the silicon wafer 1 reduces the reflectance, but the photocurrent cannot be improved, and the battery efficiency is not good. Therefore, after the texturing process, the typical silicon wafer 1 must be expanded to reduce the nanostructure, and the original hole 12 (or nanohole 13) is also enlarged, as shown by the dotted line in FIG. 1 14. The depth-to-width ratio of the hole 14 subjected to the reaming treatment is also smaller than that of the original hole 12. Therefore, the reflectivity of the surface 10 of the silicon wafer 1 after the reaming process is relatively improved. However, there is still room for improvement in the current reaming method used to further reduce the reflectivity of the surface of the silicon wafer.

Therefore, one technical problem to be solved by the present invention is to provide a method for expanding a plurality of holes on a textured surface of a silicon wafer. According to the reaming method of the present invention, a silicon wafer having low reflectivity can be manufactured.

A method for reaming a plurality of holes on a textured surface of a silicon wafer according to a preferred embodiment of the present invention is to first immerse a silicon wafer in an etching solution to maintain an etching time for reaming. The components of the etching solution include 30 ~ 40wt.% HNO ₃ , 20 ~ 30wt.% HF and 35 ~ 50wt.% H ₃ PO ₄ . The weight ratio of the components of the etching solution is HNO ₃ : HF: H ₃ PO ₄ = 16 ~ 74: 3 ~ 23: 13, 28 ~ 81. Next, the method for expanding holes in the present invention is to perform a first cleaning process on the silicon wafer. Next, the method of reaming the present invention is to immerse a silicon wafer in an alkaline solution to perform a modification process. Next, the method of reaming in the present invention is to perform a second cleaning process on the silicon wafer. Next, the reaming method of the present invention involves pickling a silicon wafer. Next, the reaming method of the present invention involves performing a third cleaning process on the silicon wafer. Finally, the reaming method of the present invention is to dry the silicon wafer.

In a specific embodiment, the etching time ranges from 1 min. To 20 min.

In a specific embodiment, the temperature of the etching solution ranges from 10 ° C to 30 ° C.

In a specific embodiment, the composition of the alkaline solution contains 0.025 wt.% ~ 0.05 wt.% KOH.

In a specific embodiment, the time range for performing the modification process is 20 seconds to 40 seconds.

In a specific embodiment, the pickling process involves immersing the silicon wafer in an acidic solution. The components in the acidic solution include 25 ~ 35wt.% HF and 5 ~ 15wt% HCl. The weight ratio of the components of the acidic solution is HF: HCl: H ₂ O = 30 ~ 50: 10 ~ 20: 40 ~ 60.

In a specific embodiment, the time range during which the pickling process is performed is 3 minutes to 7 minutes.

In a specific embodiment, a plurality of holes have a pore size ranging from 400 nm to 2 μm after being processed by the pore expanding method of the present invention.

In a specific embodiment, a plurality of holes have a hole aspect ratio ranging from 0.2 to 0.5 after being processed by the hole expanding method.

Unlike the prior art, the reaming method of the present invention can manufacture silicon wafers with low reflectivity.

The advantages and spirit of the present invention can be further understood through the following detailed description of the invention and the accompanying drawings.

1‧‧‧ silicon wafer

10‧‧‧ surface

12‧‧‧ Hole

13‧‧‧ Nano hole

14‧‧‧ Hole

2‧‧‧ Reaming Method

S20 ~ S32‧‧‧‧Process steps

Figure 1 is a schematic partial cross-sectional view of a typical silicon wafer.

FIG. 2 is a flow chart of each program step of a method for expanding a hole in a preferred embodiment of the present invention.

3 to 12 are scanning electron microscope (SEM) photographs of the surface profile or cross section of a polycrystalline silicon wafer processed by the reaming method of the present invention.

Please refer to FIG. 2, which is a flowchart of a method 2 for expanding a hole according to a preferred embodiment of the present invention. The reaming method 2 according to a preferred embodiment of the present invention is to ream a plurality of holes on a textured surface of a silicon wafer.

In practical applications, silicon wafers can be slices taken from various commercial silicon ingots, such as polycrystalline silicon ingots, single crystal silicon ingots, or similar single crystal silicon ingots. The texturing methods performed on the silicon wafer in advance are the various texturing methods described above.

As shown in FIG. 2, in the method 2 of the present invention, step S20 is first performed, and a silicon wafer is immersed in an etching solution for an etching time to perform a hole expansion process. The components of the etching solution include 30 ~ 40wt.% HNO ₃ , 20 ~ 30wt.% HF and 35 ~ 50wt.% H ₃ PO ₄ . The weight ratio of the components of the etching solution is HNO ₃ : HF: H ₃ PO ₄ = 16 ~ 74: 3 ~ 23: 13, 28 ~ 81.

In a specific embodiment, the etching time ranges from 1 min. To 20 min.

In a specific embodiment, the temperature of the etching solution ranges from 10 ° C to 30 ° C.

Next, the hole expanding method 2 of the present invention executes step S22 to perform a first cleaning process on the silicon wafer.

In a specific embodiment, the first cleaning process may be performed by immersing the silicon wafer in deionized water for several seconds.

Next, the hole expanding method 2 of the present invention executes step S24 to immerse the silicon wafer in an alkaline solution to perform a modification process.

In a specific embodiment, the composition of the alkaline solution contains 0.025 wt.% ~ 0.05 wt.% KOH.

In a specific embodiment, the time range for performing the modification process is 20 seconds to 40 seconds.

Next, the hole expanding method 2 of the present invention executes step S26 to perform a second cleaning process on the silicon wafer.

In a specific embodiment, the second cleaning process can be performed by immersing the silicon wafer in deionized water for several seconds.

Next, the hole expanding method 2 of the present invention executes step S28 to perform a pickling process on the silicon wafer.

In a specific embodiment, the pickling process involves immersing the silicon wafer in an acidic solution. The components in the acidic solution contain 25 ~ 35wt.% HF and 5 ~ 15wt% HCl. The weight ratio of the components of the acidic solution is HF: HCl: H ₂ O = 30 ~ 50: 10 ~ 20: 40 ~ 60.

Next, the hole expanding method 2 of the present invention executes step S30 to perform a third cleaning process on the silicon wafer.

In a specific embodiment, the third cleaning process may be performed by immersing the silicon wafer in deionized water for several seconds.

Finally, the method 2 of the present invention performs step S32 to dry the silicon wafer.

In a specific embodiment, the pickling process is performed for a period of time ranging from 3 minutes to 7 minutes.

In a specific embodiment, a plurality of holes have a pore size ranging from 400 nm to 2 μm after being processed by the hole expanding method.

In a specific embodiment, a plurality of holes have a hole aspect ratio ranging from 0.2 to 0.5 after being processed by the hole expanding method.

Please refer to FIGS. 3 to 12. FIG. 3 is a scanning electron microscope (SEM) photograph of the surface profile of a diamond wire-cut polycrystalline silicon wafer after texturing using acid vapor and self-catalyst vapor. Figure 3 shows the nanostructures on the surface of the polycrystalline silicon wafer after texturing.

Figure 4 shows the weight ratio of the components of the polycrystalline silicon wafer using the etching solution after texturing is HNO ₃ (35wt.%): HF (24.5wt.%): H ₃ PO ₄ (42.5wt.%) = 49: 9: SEM image of the surface profile of 42 after etching for about three minutes, and a hole expanding method using 0.025 wt.% KOH for about 30 seconds. FIG. 5 is a SEM photograph of a cross section of the polycrystalline silicon wafer shown in FIG. 4. FIG. 4 shows that the nano-structure has been reduced on the surface of the polycrystalline silicon wafer after adopting the hole expanding method of the present invention, and the average pore diameter of the holes on the surface is about 1 μm. FIG. 5 shows that the depth-to-width ratio of the holes on the surface of the polycrystalline silicon wafer is about 0.35 after the method of expanding the hole according to the present invention is used.

FIG. 6 shows the weight ratio of components using etching solution after texturing of polycrystalline silicon wafers: HNO ₃ (35wt.%): HF (24.5wt.%): H ₃ PO ₄ (42.5wt.%) = 49: 9: SEM image of the surface profile after 42 minutes of etching for about three minutes, and a hole-reaming method using 0.05wt.% KOH for about 30 seconds. FIG. 7 is a SEM photograph of a cross section of the polycrystalline silicon wafer shown in FIG. 6. FIG. 6 shows that after using the method of expanding the hole of the present invention, there is no flat area on the surface of the polycrystalline silicon wafer, and the average pore diameter of the holes on the surface is about 1 μm. FIG. 7 shows that the depth-to-width ratio of the holes on the surface of the polycrystalline silicon wafer is about 0.35 after the method for expanding holes according to the present invention is used.

FIG. 8 shows that the weight ratio of components using an etching solution after texturing of a polycrystalline silicon wafer is HNO ₃ (35wt.%): HF (24.5wt.%): H ₃ PO ₄ (42.5wt.%) = 49:23: 28. SEM photo of the surface profile after etching for about three minutes and using a 0.025wt.% KOH modification treatment for about 30 seconds. FIG. 8 shows that the nanostructure has been reduced on the surface of the polycrystalline silicon wafer after the method of expanding the hole according to the present invention, and the average pore diameter of the holes on the surface is about 500 nm to 1.2 μm.

FIG. 9 shows that the weight ratio of components using an etching solution after texturing of a polycrystalline silicon wafer is HNO ₃ (35wt.%): HF (24.5wt.%): H ₃ PO ₄ (42.5wt.%) = 49:23: 28. SEM photograph of the surface profile after etching for about three minutes, and a reaming method using 0.05 wt.% KOH for about 30 seconds. FIG. 9 shows that the nano-structure has been reduced on the surface of the polycrystalline silicon wafer after the method of expanding holes according to the present invention, and the average pore diameter of the holes on the surface is about 500 nm to 1 μm.

FIG. 10 shows that the weight ratio of components using an etching solution after texturing of a polycrystalline silicon wafer is HNO ₃ (35wt.%): HF (24.5wt.%): H ₃ PO ₄ (42.5wt.%) = 74:13: 13 SEM photo of the surface profile of the hole-reaming method after etching for about three minutes. FIG. 10 shows that the nano-structure has been reduced on the surface of the polycrystalline silicon wafer after adopting the hole expanding method of the present invention, and the average pore diameter of the holes on the surface is about 1.5 μm.

FIG. 11 shows that the weight ratio of components using an etching solution after texturing of a polycrystalline silicon wafer is HNO ₃ (35wt.%): HF (24.5wt.%): H ₃ PO ₄ (42.5wt.%) = 49: 9: 42 An SEM photograph of the surface profile of the hole-reaming method after etching for about three minutes. FIG. 11 shows that the nanostructure has been reduced on the surface of the polycrystalline silicon wafer after the method of expanding the hole according to the present invention, and the average pore diameter of the holes on the surface is about 1 μm.

FIG. 12 shows that the weight ratio of components using an etching solution after texturing of a polycrystalline silicon wafer is HNO ₃ (35wt.%): HF (24.5wt.%): H ₃ PO ₄ (42.5wt.%) = 16: 3: 81 SEM image of the surface profile of the hole-reaming method after etching for about three minutes. FIG. 12 shows that the nano-structure has been reduced on the surface of the polycrystalline silicon wafer after adopting the hole expanding method of the present invention, and the average pore diameter of the holes on the surface is about 600 nm.

Figures 3 to 12 show that the reflectance of a polycrystalline silicon wafer using the reaming method of the present invention measured from 17.5% to 18.4%, which confirms that the reaming method of the present invention can reduce the silicon wafer after texturing. Reflectivity. The polycrystalline silicon wafer using the reaming method of the present invention is further fabricated into a solar cell, and the photoelectric conversion efficiency measured is about 19.69%.

In summary, Xianxin can clearly understand that the reaming method of the present invention can effectively further reduce the reflectivity of the silicon wafer.

With the above detailed description of the preferred embodiments, it is hoped that the features and spirit of the present invention may be more clearly described, rather than limiting the aspects of the present invention with the preferred embodiments disclosed above. On the contrary, the intention is to cover various changes and equivalent arrangements within the scope of the patent scope of the present invention. Therefore, the aspect of the patent scope of the present invention should be explained in the broadest sense according to the above description, so that it covers all possible changes and equal arrangements.

Claims (9)

A method for reaming a plurality of holes on a textured surface of a silicon wafer includes the following steps: immersing the silicon wafer in an etching solution for an etching time to perform a hole reaming process, wherein the etching The composition of the solution contains 30 ~ 40wt.% HNO ₃ , 20 ~ 30wt.% HF and 35 ~ 50wt.% H ₃ PO _4. The weight ratio of the composition of the etching solution is HNO ₃ : HF: H ₃ PO ₄ = 16 ~ 74: 3 ~ 23: 13, 28 ~ 81; the silicon wafer is subjected to a first cleaning process; the silicon wafer is immersed in an alkaline solution to perform a modification process; the silicon wafer is subjected to a A second cleaning process; performing an acid cleaning process on the silicon wafer; performing a third cleaning process on the silicon wafer; and drying the silicon wafer. The reaming method according to claim 1, wherein the etching time ranges from 1 min. To 20 min. The reaming method according to claim 2, wherein a temperature of one of the etching solutions ranges from 10 ° C to 30 ° C. The pore expanding method according to claim 2, wherein the component of the alkaline solution contains 0.025 wt.% ~ 0.05 wt.% KOH. The reaming method according to claim 4, wherein the time range for performing the modification treatment is 20 seconds to 40 seconds. The reaming method according to claim 4, wherein the pickling treatment is immersing the silicon wafer in an acidic solution, and the components in the acidic solution include 25 to 35 wt.% HF and 5 to 15 wt% HCl. The weight ratio of the components of the solution is HF: HCl: H ₂ O = 30 ~ 50: 10 ~ 20: 40 ~ 60. The reaming method according to claim 1, wherein the pickling process is performed for a period of time ranging from 3 minutes to 7 minutes. The reaming method according to claim 1, wherein the plurality of holes have a pore size ranging from 400 nm to 2 μm after being processed by the reaming method. The hole expanding method according to claim 8, wherein the plurality of holes have a hole aspect ratio ranging from 0.2 to 0.5 after being processed by the hole expanding method.