TWI673697B - Optoelectronic devices and electronic machines - Google Patents

Abstract

The object of the present invention is to realize an optoelectronic device that can display a high-resolution image with high resolution and multiple gray levels with low power consumption, and can operate at a higher speed and obtain a brighter display. The optoelectronic device 10 of the present invention is characterized by including a scanning line 42, a signal line 43, a pixel circuit 41 provided corresponding to the intersection of the scanning line 42 and the signal line 43, a first high potential line 47 supplied with a first potential, The low-potential line 46 to which the second potential is supplied and the second high-potential line 49 to which the third potential is supplied. The pixel circuit 41 includes a light-emitting element 20 and a portion disposed between the first high-potential line 47 and the low-potential line 46. The memory circuit 60, the first transistor 31 electrically connected to the memory circuit 60, and the second transistor 32 electrically connected to the scan line 42, and the second transistor 32 is disposed to the memory circuit 60 and the signal line. Between 43, the potential difference between the first potential and the second potential is smaller than the potential difference between the third potential and the second potential.

Description

Photoelectric device and electronic equipment

The invention relates to a photoelectric device and an electronic device.

In recent years, as an electronic device capable of forming and observing a virtual image, a head-mounted display (HMD: Head Mount Display) of a type that guides image light from a photoelectric device to an observer's pupil has been proposed. In such an electronic device, for example, an organic EL device having an organic EL (Electro Luminescence) element that is a light-emitting element is used as a photovoltaic device. Among organic EL devices used in head-mounted displays, high resolution (micronization of pixels), multiple gray levels of display, and low power consumption have been sought.

In the previous organic EL device, if the transistor was selected to be in the ON state by the scanning signal supplied to the scanning line, the potential based on the image signal supplied from the signal line was maintained at the gate connected to the driving transistor. Capacitive element. If the driving transistor is turned on according to the potential held in the capacitive element, that is, the gate potential of the driving transistor, a current corresponding to the gate potential of the driving transistor flows through the organic EL element, and the organic EL element Light is emitted at a brightness corresponding to the amount of current.

In this way, in the previous organic EL device, since the gray scale display is performed by analog driving that controls the current flowing in the organic EL element according to the gate potential of the driving transistor, there is a voltage-current characteristic or threshold voltage of the driving transistor. The difference between the pixels causes a difference in brightness or grayscale shift between pixels, which causes the display quality to decrease. On the other hand, an organic EL device including a compensation circuit that compensates for differences in voltage and current characteristics of a driving transistor or a threshold voltage is proposed (for example, refer to Patent Document 1). [Prior Art Literature] [Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open No. 2004-062199

[Problems to be solved by the invention]

However, if a compensation circuit is provided as described in Patent Document 1, a current also flows through the compensation circuit, which causes an increase in power consumption. Moreover, in the previous analog driving, in order to make the display more grayscale, it is necessary to increase the capacitance of the capacitive element of the memory image signal, so it is difficult to coexist with high resolution (micronization of the pixel), and accompanied by the capacitive element. Charge and discharge power consumption also increases. In other words, in the prior art, it has been difficult to realize an optoelectronic device capable of displaying a high-resolution image with high resolution and multiple gray levels with low power consumption. [Technical means to solve the problem]

The present invention has been made to solve at least a part of the problems described above, and can be implemented as the following forms or application examples.

(Application Example 1) The optoelectronic device of this application example is characterized by including a scanning line, a signal line, a pixel circuit provided corresponding to the intersection of the scanning line and the signal line, a first potential line supplied with a first potential, The second potential line to which the second potential is supplied and the third potential line to which the third potential is supplied; the pixel circuit includes a light emitting element, a memory circuit disposed between the first potential line and the second potential line, The first transistor is electrically connected to the memory circuit and the second transistor is electrically connected to the scan line. The second transistor is disposed between the memory circuit and the signal line, and the light is emitted. The element and the first transistor are arranged in series between the second potential line and the third potential line, and an absolute value of a potential difference between the first potential with respect to the second potential is smaller than the third potential with respect to the second potential. The absolute value of the potential difference.

According to the configuration of this application example, the pixel circuit includes a memory circuit disposed between the first potential line and the second potential line, and a second transistor whose gate is electrically connected to the scanning line is disposed between the memory circuit and the signal line. The first transistor electrically connected to the memory circuit and the light emitting element are arranged in series between the second potential line and the third potential line. Therefore, the digital signal represented by the binary value of ON / OFF can be written into the memory circuit via the second transistor, and the gray scale display can be performed by controlling the ratio of the light-emitting and non-light-emitting of the light-emitting element through the first transistor. Therefore, since it is not easily affected by the voltage-current characteristics of each transistor or the difference in threshold voltage, even if there is no compensation circuit, the brightness difference or grayscale shift between pixels can be reduced. In addition, in the digital driving, the number of gray levels can be easily increased even if there is no capacitive element by increasing the number of sub-fields that are used to control the light emission and non-light emission of the light emitting element in the field displaying an image. In addition, since it is not necessary to maintain a capacitor element having a large capacitance, miniaturization of pixels can be achieved. This makes it possible to miniaturize the pixels and increase the resolution, and to reduce the power consumption associated with the charging and discharging of the capacitive element.

The absolute value of the potential difference between the first potential supplied to the memory circuit and the second potential is smaller than the absolute value of the potential difference between the third potential supplied to the light-emitting element and the first transistor and the second potential. That is, the memory circuit is operated by the low-voltage system power supply of the first potential and the second potential, and the light-emitting element is caused to emit light by the high-voltage system power supply of the third potential and the second potential. Therefore, the memory circuit can be miniaturized to make it operate at high speed, and the light-emitting brightness of the light-emitting element can be improved. Thereby, the writing or overwriting of the image signal can be speeded up, and the display can be made brighter. As a result, a photovoltaic device capable of brightly displaying high-resolution and multi-grayscale high-quality images with low power consumption can be realized.

(Application Example 2) The optoelectronic device of this application example is preferably such that the memory circuit includes a third transistor, and a gate length of the third transistor is shorter than a gate length of the first transistor.

According to the configuration of this application example, since the gate length of the third transistor included in the memory circuit is shorter than the gate length of the first transistor arranged in series with the light-emitting element, the third transistor can be made smaller than the first transistor. , And miniaturize the memory circuit. Therefore, the memory circuit can be operated at high speed, and the light-emitting element can emit light at a high voltage.

(Application Example 3) The optoelectronic device of this application example is preferably such that the area of the channel formation region of the third transistor is smaller than the area of the channel formation region of the first transistor.

According to the configuration of this application example, since the transistor capacitance of the third transistor included in the memory circuit is smaller than the transistor capacitance of the first transistor, it is possible to speed up writing or overwriting of the image signal to the memory circuit.

(Application Example 4) The optoelectronic device of this application example is preferably that the source of the first transistor is electrically connected to the second potential line, and is between the drain of the first transistor and the third potential line. The light-emitting element is arranged.

According to the configuration of this application example, since the source potential of the first transistor is fixed to the second potential, when the first transistor is turned on, even if the absolute value of the source drain voltage of the first transistor is smaller than If it is small, the conductivity of the first transistor can also be increased. That is, when the first transistor is turned on and the light-emitting element emits light, the first transistor can be operated substantially linearly (hereinafter referred to as linear operation). As a result, a large portion of the potential difference between the second potential and the third potential, which is a high-voltage power source, is applied to the light-emitting element. Therefore, when the light-emitting element emits light, it is not easily affected by the threshold voltage difference of the first transistor. As a result, the uniformity of brightness between pixels can be improved.

(Application Example 5) The optoelectronic device of this application example is preferably such that the on-resistance of the first transistor is sufficiently lower than the on-resistance of the light-emitting element.

According to the configuration of this application example, when the first transistor is turned on and the light-emitting element emits light, the first transistor can be operated linearly. As a result, since most of the potential drop generated between the light-emitting element and the first transistor is applied to the light-emitting element, it is difficult to be affected by the difference in threshold voltage of the first transistor when the light-emitting element emits light. Thereby, the difference in brightness or grayscale shift between pixels can be reduced.

(Application Example 6) In the photovoltaic device of this application example, it is preferable that the first transistor and the second transistor have the same polarity.

According to the configuration of this application example, for example, when the first transistor is of the N type and the signal is turned on by the signal of High, the second transistor is also of the N type and is turned on by the signal of High. Since the potential of the selection signal supplied from the scanning line to the gate of the second transistor can be set to the highest third potential among the first potential, the second potential, and the third potential, the non-selected signal can be set to the first potential, The lowest second potential among the second potential and the third potential can be set higher than the potential of the image signal (the first potential or the second potential). Therefore, when the second transistor is turned on and the image signal is written to the memory circuit, the gate-source voltage of the second transistor can be increased only by the amount higher than the selection signal. The electrode potential rises due to the writing of the image signal (even if the first potential supplied to the high potential side as the image signal), the on-resistance of the second transistor can be kept low.

Similarly, when the first transistor is a P-type and is turned on by a signal of Low, the second transistor is also a P-type and turned on by a signal of Low. Since the potential of the selection signal supplied from the scanning line to the gate of the second transistor can be set to the lowest third potential among the first potential, the second potential, and the third potential, the non-selected signal can be set to the first potential, The highest second potential among the second potential and the third potential can be set to a potential lower than the image signal potential (the first potential or the second potential). Therefore, when the second transistor is turned on and the image signal is written to the memory circuit, the absolute value of the gate-source voltage of the second transistor can be increased only by the amount by which the selection signal is reduced. Even if the source potential is reduced by the writing of the image signal (even if the first potential on the low potential side is supplied as the image signal), the on-resistance of the second transistor can be kept low. Thereby, writing or overwriting of the image signal to the memory circuit can be performed at high speed and reliably.

(Application Example 7) The optoelectronic device of this application example preferably includes a control line, and the pixel circuit includes a fourth transistor whose gate is electrically connected to the control line, the light-emitting element, the first transistor, and the first transistor. The four transistors are arranged in series between the second potential line and the third potential line.

According to the configuration of this application example, the fourth transistor, which is arranged in series with the light-emitting element and the first transistor, can be independently controlled by the control line and the second transistor. That is, the period during which the second transistor is turned on and the image signal is written to the memory circuit, and the period when the fourth transistor is turned on and the light-emitting element is turned on can be controlled independently. Period. Therefore, in each pixel, the light-emitting element can be set to a non-light-emitting state while the image signal is written into the memory circuit. After the image signal is written into the memory circuit, the light-emitting element can emit light for a specific period of time as a display period. The device is set to be in a light-emitting state, so that accurate grayscale display can be achieved by time-sharing driving.

(Application Example 8) In the photovoltaic device of this application example, it is preferable that the drain of the fourth transistor is electrically connected to the light-emitting element.

According to the configuration of this application example, the drain of the fourth transistor is electrically connected to the light-emitting element disposed between the first transistor and the third potential line whose source is electrically connected to the second potential line. Therefore, if the fourth transistor is N-type, the fourth transistor is disposed at a lower potential side than the light-emitting element, and if the fourth transistor is P-type, the fourth transistor is disposed at a higher potential than the light-emitting element. On the other hand, when the fourth transistor is turned on, even if the source-drain voltage of the fourth transistor is small, the conductivity of the fourth transistor can be increased. That is, when the fourth transistor is turned on and the light-emitting element emits light, the fourth transistor can be operated in a linear manner. Accordingly, since a large portion of the potential difference between the second potential and the third potential, which is a high-voltage power source, is applied to the light-emitting element, the light-emitting element is hardly affected by the threshold voltage difference of the fourth transistor when emitting light. As a result, the uniformity of brightness between pixels can be improved.

(Application Example 9) In the photovoltaic device of this application example, the on-resistance of the fourth transistor is preferably lower than the on-resistance of the light-emitting element.

According to the configuration of this application example, when the first transistor and the fourth transistor are turned on and the light-emitting element emits light, the fourth transistor can be operated linearly. As a result, most of the potential drop generated in the light-emitting element, the first transistor, and the fourth transistor is applied to the light-emitting element, so that the light-emitting element is hardly affected by the difference in threshold voltage of the fourth transistor when emitting light. Thereby, the difference in brightness or grayscale shift between pixels can be reduced.

(Application Example 10) In the photovoltaic device of this application example, it is preferable that the first transistor and the fourth transistor have opposite polarities.

According to the configuration of this application example, the source of the first transistor and the source of the fourth transistor are electrically connected to potential lines of different potentials, respectively. Therefore, since the source potential of the first transistor and the source potential of the fourth transistor are fixed to various potentials, when the two transistors are turned on, the electrical conductivity of the two transistors can be enlarged and made to be in line. action.

(Application Example 11) The optoelectronic device of this application example is preferably when the second transistor is in an on state and the fourth transistor is in an off state.

According to the configuration of this application example, when the second transistor is turned on and the image signal is written into the memory circuit from the signal line, the fourth transistor is turned off and the light-emitting element is turned off. Therefore, signals can be written (or overwritten) to the memory circuit reliably and at high speed with low power consumption. Thereby, it is possible to suppress erroneous display or reduce the quality of image display caused by the image signal not being written into the memory circuit correctly.

(Application Example 12) The optoelectronic device of this application example is preferably configured to supply the control line to the control line during a first period in which a selection signal for setting the second transistor to the ON state is supplied to any one of the scanning lines. The fourth transistor is set to a non-enabled signal in an off state.

According to the configuration of this application example, since the fourth transistor is turned off during the first period when the second transistor is turned on according to the selection signal, light can be emitted during the first period when the image signal is written into the memory circuit. The element is set to non-light emitting.

(Application Example 13) In the optoelectronic device of this application example, it is preferable that during the second period during which the enable signal for turning on the fourth transistor to be turned on is supplied to the control line, the second voltage is supplied to the scan line. The crystal is set to an unselected signal in the off state.

According to the configuration of this application example, since the second transistor is turned off in the second period in which the fourth transistor is turned on according to the enable signal, it is possible to stop writing to the memory circuit during the second period in which the light emitting element can emit light. Like signal. In addition, since the first period and the second period can be controlled independently, the length of the second period in which the light-emitting element can emit light can be different regardless of the length of the first period. Thereby, a higher grayscale display can be realized by digital time-sharing driving. In addition, since a plurality of pixels can share a signal (enable signal, non-enable signal) supplied to the control line, even if the second period is shorter than the sub-field in the vertical period when one of all the plurality of scanning lines is selected, it is easy. Ground drive photovoltaic device.

(Application Example 14) In the photovoltaic device of this application example, it is preferable that the first transistor is an N-type and the fourth transistor is a P-type. The first potential is set to V1, and the second potential is set to V2. When the third potential is V3, the potential of the enable signal supplied to the control line is V3- (V1-V2) or less.

According to the configuration of this application example, the source of the N-type first transistor is electrically connected to the second potential line, and the source of the P-type fourth transistor is electrically connected to the third potential line. The 3 potential is higher than the second potential. The fourth transistor is turned on when the Low enable signal is supplied to the gate. However, the potential of the enable signal is set to V3- (V1-V2) or less, that is, it is lower than the source potential of the fourth transistor. The third potential decreases the amount of low-voltage system power supply voltage, so that the fourth transistor can be reliably turned on in accordance with the enable signal. In addition, the lower the potential of the enable signal, the larger the gate-source voltage of the fourth transistor in the negative direction, and the lower the on-resistance of the fourth transistor in the on state, so that when the light-emitting element is caused to emit light Not easily affected by the threshold voltage difference of the fourth transistor.

(Application Example 15) In the optoelectronic device of this application example, the potential of the enable signal is preferably the second potential described above.

According to the configuration of this application example, the potential of the enable signal is set to the second potential that is the lowest among the first potential, the second potential, and the third potential, without introducing a new potential. In addition, since the absolute value of the gate-source voltage of the fourth transistor can be sufficiently increased, the on-resistance of the fourth transistor in the on state can be sufficiently reduced, and the threshold voltage of the fourth transistor can be substantially eliminated. The effect of the difference on the light-emitting brightness of the light-emitting element.

(Application Example 16) The optoelectronic device of this application example is preferably such that the first transistor and the second transistor are both N-type, and the potential of the selection signal supplied to the scanning line is equal to or higher than the first potential.

According to the configuration of this application example, the N-type first transistor whose source is electrically connected to the second potential line is supplied with a High signal to a memory circuit disposed between the first potential line and the second potential line. When the gate is turned on, the first potential is higher than the second potential. The source potential of the N-type second transistor becomes a potential between the first potential and the second potential, but since the potential of the selection signal supplied from the scanning line to the gate of the second transistor is equal to or higher than the first potential, The second transistor can be reliably turned on. In addition, since the potential of the selection signal is higher than the first potential, the on-resistance of the second transistor in the on-state is lower, so that writing or writing of image signals to the memory circuit can be performed at high speed and without malfunction. Overwrite.

(Application Example 17) In the photovoltaic device of this application example, the potential of the selection signal is preferably the third potential described above.

According to the configuration of this application example, the potential of the selection signal is set to the highest third potential among the first potential, the second potential, and the third potential, without introducing a new potential. In addition, since the gate-source voltage of the second transistor can be sufficiently increased, the on-resistance of the second transistor in the on-state can be sufficiently reduced, and the map to the memory circuit can be reliably performed at high speed and without malfunction. Like writing or overwriting of signals.

(Application Example 18) In the photovoltaic device of this application example, the first transistor is preferably a P-type, and the fourth transistor is an N-type. The first potential is set to V1, and the second potential is set to V2. When the third potential is set to V3, the potential of the enable signal supplied to the control line is V3 + (V2-V1) or more.

According to the configuration of this application example, the source of the P-type first transistor is electrically connected to the second potential line, and the source of the N-type fourth transistor is electrically connected to the third potential line. The 3 potential is lower than the second potential. The fourth transistor is turned on when the High enable signal is supplied to the gate, but the potential of the enable signal is set to V3 + (V2-V1) or more, that is, the potential of the fourth transistor is the first The 3 potential increases the amount of low-voltage system power supply voltage, so the fourth transistor can be reliably turned on according to the enable signal. In addition, the higher the potential of the enable signal, the larger the gate-source voltage of the fourth transistor, and the lower the on-resistance of the fourth transistor in the on state, which makes it less susceptible to the fourth when the light-emitting element emits light. Influence of threshold voltage difference of transistor.

(Application Example 19) In the photovoltaic device of this application example, it is preferable that the potential of the enable signal is the second potential described above.

According to the configuration of this application example, by setting the potential of the enable signal to the second potential that is the highest among the first potential, the second potential, and the third potential, it is not necessary to introduce a new potential. In addition, since the gate-source voltage of the fourth transistor can be sufficiently increased, the on-resistance of the fourth transistor in the on state can be sufficiently reduced, and the threshold voltage difference of the fourth transistor can substantially eliminate light emission. The effect of the luminous brightness of the device.

(Application Example 20) The optoelectronic device of this application example is preferably that the first transistor and the second transistor are both P-type, and the potential of the selection signal supplied to the scanning line is equal to or lower than the first potential.

According to the configuration of this application example, the P-type first transistor whose source is electrically connected to the second potential line is supplied with a signal of Low to a memory circuit disposed between the first potential line and the second potential line. When the gate is turned on, the first potential is lower than the second potential. The source potential of the second transistor of the P type is a potential between the first potential and the second potential, but the potential of the selection signal supplied from the scanning line to the gate of the second transistor is equal to or lower than the first potential, so The second transistor can be reliably turned on. In addition, the lower the potential of the selection signal is, the lower the on-resistance of the second transistor in the on-state is. Therefore, it is possible to write or write image signals to the memory circuit at high speed and without malfunction. Overwrite.

(Application Example 21) In the photovoltaic device of this application example, the potential of the selection signal is preferably the third potential described above.

According to the configuration of this application example, the potential of the selection signal is set to the third potential that is the lowest among the first potential, the second potential, and the third potential, without introducing a new potential. In addition, since the gate-source voltage of the second transistor can be sufficiently increased, the on-resistance of the second transistor in the on-state can be sufficiently reduced, and the map to the memory circuit can be reliably performed at high speed and without malfunction. Like writing or overwriting of signals.

(Application Example 22) The electronic device of this application example is provided with the photoelectric device described in the above application example.

According to the configuration of this application example, it is possible to improve the quality of an image displayed on an electronic device such as a head-mounted display.

Hereinafter, embodiments of the present invention will be described using drawings. In addition, in the following drawings, in order to set each layer or each member to a size recognizable on the drawing, the scale of each of the layers or each member may be different.

[Outline of Electronic Device] First, an outline of the electronic device will be described with reference to FIG. 1. FIG. 1 is a diagram illustrating the outline of an electronic device according to this embodiment.

The head-mounted display 100 is an example of an electronic device in this embodiment, and includes a photoelectric device 10 (see FIG. 3). As shown in FIG. 1, the head mounted display 100 has an appearance like glasses. The user who wears the head-mounted display 100 visually recognizes the image light GL (see FIG. 3) as an image, and allows the user to visually recognize external light. In short, the head-mounted display 100 has a see-through function for overlapping display of external light and image light GL, wide viewing angle, high performance, and small size and light weight.

The head-mounted display 100 includes a see-through member 101 covering the eyes of the user, a frame 102 supporting the see-through member 101, and a first built-in device portion 105a and a second built-in device portion 105b, which are attached to the lens frame 102. The parts from the left and right ends to the rear hanging parts (glasses legs).

The see-through member 101 is a thick and curved optical member (transmitting an eye mask) that covers a user's eyes, and is divided into a first optical portion 103a and a second optical portion 103b. In FIG. 1, the first display device 151 that combines the first optical portion 103 a on the left side and the first built-in device portion 105 a is a portion that displays a virtual image for the right eye through perspective, and functions as an electronic device with a display function even if it is independent. In FIG. 1, the second display device 152 combining the right second optical portion 103b and the second built-in device portion 105b is a portion for forming a virtual image for the left eye through see-through, and it functions as an electronic device with a display function even if it is independent. Features. The photovoltaic device 10 is incorporated in the first display device 151 and the second display device 152 (see FIG. 3).

[Internal Structure of Electronic Device] FIG. 2 is a diagram illustrating the internal structure of the electronic device according to this embodiment. FIG. 3 is a diagram illustrating an optical system of an electronic device according to this embodiment. Next, the internal structure and optical system of the electronic device will be described with reference to FIGS. 2 and 3. In addition, in FIG. 2 and FIG. 3, an example in which the first display device 151 is an electronic device will be described. However, the second display device 152 also has almost the same structure symmetrically. Therefore, the first display device 151 will be described, and the detailed description of the second display device 152 will be omitted.

As shown in FIG. 2, the first display device 151 includes a projection see-through device 170 and a photoelectric device 10 (see FIG. 3). The projection see-through device 170 includes: a light guide member 110, a light transmitting member 150, and an imaging projection lens 130 (see FIG. 3). The 稜鏡 110 and the light transmitting member 150 are integrated by joining, and are firmly fixed to the lower side of the frame 161, for example, so that the upper surface 110e of the 稜鏡 110 and the lower surface 161e of the frame 161 are in contact with each other. .

The projection lens 130 is fixed to the end of the cymbal 110 via a lens barrel 162 that houses the projection lens 130. The 稜鏡 110 and the light transmitting member 150 in the projection see-through device 170 correspond to the first optical portion 103 a in FIG. 1, and the projection lens 130 and the photoelectric device 10 in the projection see-through device 170 correspond to the first built-in device portion in FIG. 1. 105a.

The 稜鏡 110 in the projection perspective device 170 is an arc-shaped member curved along the face when viewed from above, and can be divided into a first 稜鏡 111 near the center side of the nose and a second 稜鏡 near the peripheral side of the nose. Part 112 to study. The first frame portion 111 is disposed on the light exit side and has a first surface S11 (see FIG. 3), a second surface S12, and a third surface S13 as side surfaces having optical functions.

The second frame portion 112 is disposed on the light incident side, and has a fourth surface S14 (see FIG. 3) and a fifth surface S15 as a side surface having an optical function. Among them, the first surface S11 is adjacent to the fourth surface S14, the third surface S13 is adjacent to the fifth surface S15, and a second surface S12 is disposed between the first surface S11 and the third surface S13. In addition, 稜鏡 110 has a top surface 110e adjacent to the fourth surface S14 from the first surface S11.

Rhenium 110 is formed of a resin material exhibiting high light transmittance in a visible region, and is formed by, for example, injecting and curing a thermoplastic resin into a mold. The main body portion 110s (see FIG. 3) of the cymbal 110 is an integrally formed product, but it can also be divided into the first cymbal portion 111 and the second cymbal portion 112 for research. The first part 111 can realize the guided wave and exit of the image light GL, and can see outside light. The second part 112 can realize the incident and guided wave of the image light GL.

The light transmitting member 150 is fixed integrally with the cymbal 110. The light transmitting member 150 is a member (auxiliary member) that assists the perspective function of the member 110. The light transmitting member 150 is formed of a resin material that exhibits high light transmittance in the visible region and has a refractive index substantially the same as that of the body portion 110s of the osmium 110. The light transmitting member 150 is formed by, for example, molding of a thermoplastic resin.

As shown in FIG. 3, the projection lens 130 includes, for example, three lenses 131, 132, and 133 along the incident-side optical axis. Each of the lenses 131, 132, and 133 is a lens that is rotationally symmetric with respect to a central axis of a light incident surface of the lens, and at least one of them is an aspheric lens.

The projection lens 130 allows the image light GL emitted from the photoelectric device 10 to be incident on the ridge 110 and re-images on the eye EY. In short, the projection lens 130 is a relay optical system for re-imaging the image light GL emitted from each pixel of the optoelectronic device 10 on the eye EY through 稜鏡 110. The projection lens 130 is held in the lens barrel 162, and the photoelectric device 10 is fixed to one end of the lens barrel 162. The second part 112 of the 110 is connected to the lens barrel 162 holding the projection lens 130, and indirectly supports the projection lens 130 and the photoelectric device 10.

In electronic devices of the type that are worn on the head of a user and cover the eyes like the head-mounted display 100, a small size and light weight are sought. Moreover, in the optoelectronic device 10 used in electronic devices such as the head mounted display 100, high resolution (pixel miniaturization), multiple grayscale display, and low power consumption have been sought.

[Configuration of Photoelectric Device] Next, the configuration of the photovoltaic device will be described with reference to FIG. 4. FIG. 4 is a schematic plan view showing the structure of the photovoltaic device of this embodiment. In this embodiment, a case where the photovoltaic device 10 is an organic EL device including an organic EL element as a light-emitting element will be described as an example. As shown in FIG. 4, the photovoltaic device 10 according to this embodiment includes an element substrate 11 and a protective substrate 12. A color filter (not shown) is provided on the element substrate 11. The element substrate 11 and the protective substrate 12 are opposed to each other through a filler (not shown), and are then bonded.

The element substrate 11 is composed of, for example, a single crystal semiconductor substrate (for example, a single crystal silicon substrate). The element substrate 11 includes a display area E and a non-display area D surrounding the display area E. In the display area E, for example, sub pixels 58B that emit blue (B) light, sub pixels 58G that emit green (G) light, and sub pixels 58R that emit red (R) light are arranged in a matrix. A light emitting element 20 is provided in each of the sub pixel 58B, the sub pixel 58G, and the sub pixel 58R (see FIG. 6). In the optoelectronic device 10, a pixel 59 including a sub-pixel 58B, a sub-pixel 58G, and a sub-pixel 58R is a display unit, and provides display of all colors.

In this specification, the sub-pixel 58B, the sub-pixel 58G, and the sub-pixel 58R may be collectively referred to as the sub-pixel 58 without distinguishing them. The display area E is an area that facilitates display by transmitting light emitted from the sub-pixels 58. The non-display area D is an area that does not pass through the light emitted from the sub-pixel 58 and is not conducive to display.

The element substrate 11 is larger than the protective substrate 12, and a plurality of external connection terminals 13 are arranged along the first side of the element substrate 11 beyond the protective substrate 12. A signal line driving circuit 53 is provided between the plurality of external connection terminals 13 and the display area E. A scanning line driving circuit 52 is provided between the other second side orthogonal to the first side and the display area E. A control line driving circuit 54 is provided between the third side orthogonal to the first side and opposed to the second side and the display area E.

The protective substrate 12 is smaller than the element substrate 11 and is arranged so that the external connection terminal 13 is exposed. The protective substrate 12 is a light-transmissive substrate, and, for example, a quartz substrate, a glass substrate, or the like can be used. The protective substrate 12 has a function of protecting the light emitting element 20 arranged in the sub-pixel 58 from being damaged in the display area E, and is arranged to face at least the display area E.

In addition, the color filter may be disposed on the light emitting element 20 in the element substrate 11, and may be disposed on the protective substrate 12. When the light emitting device 20 emits light corresponding to each color, a color filter is not necessary. In addition, the protective substrate 12 is not necessarily required, and a configuration in which a protective layer for protecting the light emitting element 20 is provided on the element substrate 11 instead of the protective substrate 12 may be used.

In this specification, the direction along the first side on which the external connection terminals 13 are arranged is referred to as the X direction (column direction), and the other two sides that are orthogonal to the first side and face each other ( The direction (row direction) of the second side and the third side is the Y direction. In this embodiment, for example, a so-called stripe method is used in which sub-pixels 58 that emit light of the same color are arranged in the row direction (Y direction), and sub-pixels 58 that emit light of different colors are arranged in the column direction (X direction). Configuration.

In addition, the arrangement of the sub-pixels 58 in the column direction (X direction) is not limited to the order of B, G, and R shown in FIG. 4, and may be, for example, the order of R, G, or B. The arrangement of the sub-pixels 58 is not limited to the stripe method, and may be a triangle method, a Bayer method, an S-type stripe method, or the like. In addition, the shapes or sizes of the sub-pixels 58B, 58G, and 58R are not limited to the same.

(First Embodiment) [Circuit Configuration of Photoelectric Device] Next, a circuit configuration of a photoelectric device will be described with reference to FIG. 5. FIG. 5 is a circuit block diagram of the photovoltaic device of this embodiment. As shown in FIG. 5, a plurality of scanning lines 42 and a plurality of signal lines 43 crossing each other are formed in the display area E of the photoelectric device 10, and the scanning lines 42 and the signal lines 43 are arranged in a matrix in correspondence with each other. Sub-pixel 58. A pixel circuit 41 including a light emitting element 20 (see FIG. 8) and the like is provided in each sub-pixel 58.

A control line 44 is formed in the display area E of the photoelectric device 10 corresponding to each scanning line 42. The scanning lines 42 and the control lines 44 extend in a column direction (X direction). In the display area E, a complementary signal line 45 is formed corresponding to each signal line 43. The signal line 43 and the complementary signal line 45 extend in a row direction (Y direction).

In the optoelectronic device 10, sub-pixels 58 of M columns × N rows are arranged in a matrix in the display area E. Specifically, in the display area E, M scanning lines 42, M control lines 44, N signal lines 43, and N complementary signal lines 45 are formed. In addition, M and N are integers of 2 or more. As an example in this embodiment, M = 720 and N = 1280 × p. p is an integer of 1 or more, and represents the number of basic colors displayed. In this embodiment, a case where p = 3, that is, the basic colors displayed are three colors of R, G, and B will be described as an example.

The optoelectronic device 10 includes a driving section 50 outside the display area E. The self-driving section 50 supplies various signals to the pixel circuits 41 arranged in the display area E, and displays an image on the display area E with the pixels 59 (three-color sub-pixels 58) as a display unit. The driving section 50 includes a driving circuit 51 and a control device 55. The control device 55 supplies a display signal to the drive circuit 51. The driving circuit 51 supplies a driving signal to each pixel circuit 41 via a plurality of scanning lines 42, a plurality of signal lines 43, and a plurality of control lines 44 based on a display signal.

Further, in the non-display area D and the display area E, a first high-potential line 47 as a first potential line to which a first potential is supplied, and a low-potential line 46 as a second potential line to which a second potential is supplied. And a second high potential line 49 which is a third potential line to which a third potential is supplied. For each pixel circuit 41, a first high potential line 47 is supplied with a first potential, a low potential line 46 is supplied with a second potential, and a second high potential line 49 is supplied with a third potential.

In this embodiment, the first potential (V1) is the first high potential VDD1 (for example, V1 = VDD1 = 3.0 V), the second potential (V2) is the low potential VSS (for example, V2 = VSS = 0 V), and the third The potential (V3) is the second high potential VDD2 (for example, V3 = VDD2 = 7.0 V). Therefore, the first potential is higher than the second potential, and the third potential is higher than the first potential.

In this embodiment, a low-voltage system power source is constituted by a first potential (first high potential VDD1) and a second potential (low potential VSS), and a third potential (second high potential VDD2) and a second potential (low potential) VSS) constitutes a high-voltage system power supply. The second potential is a potential that becomes a reference among the low-voltage power source and the high-voltage power source.

In this embodiment, as an example, the second potential line (low potential line 46), the first potential line (first high potential line 47), and the third potential line (second high potential line 49) are displayed on the display. The area E extends in the column direction, but it can also extend in the row direction, and one of these portions can extend in the column direction, and the other portion can extend in the row direction. It can also be arranged in a grid pattern in the column and row direction.

The driving circuit 51 includes a scanning line driving circuit 52, a signal line driving circuit 53, and a control line driving circuit 54. The driving circuit 51 is provided in the non-display area D (see FIG. 4). In this embodiment, the driving circuit 51 and the pixel circuit 41 are formed on the element substrate 11 (a single-crystal silicon substrate in this embodiment) shown in FIG. 4. Specifically, the driving circuit 51 or the pixel circuit 41 is composed of an element such as a transistor formed on a single crystal silicon substrate.

A scanning line 42 is electrically connected to the scanning line driving circuit 52. The scanning line driving circuit 52 outputs a scanning signal (Scan) with or without selecting the pixel circuit 41 in the column direction to each scanning line 42, and the scanning line 42 transmits the scanning signal to the pixel circuit 41. In other words, the scanning signal has a selected state and a non-selected state, and the scanning line 42 can receive and appropriately select the scanning signal from the scanning line driving circuit 52. The scanning signal takes a potential between a second potential (low potential VSS) and a third potential (second high potential VDD2).

As described later, in this embodiment, since the second transistor 32 and the complementary second transistor 38 are both N-type (see FIG. 8), the scanning signal (selection signal) in the selected state is High (high potential). ), The scan signal (non-selection signal) in the non-selected state is Low (low potential). The selection signal is set to a high potential above the first potential (V1), and is preferably a third potential (V3). The non-selection signal is set to a low potential that is equal to or lower than the second potential (V2), and is preferably the second potential (V2).

In addition, when a scan signal is specifically supplied to the scan line 42 in the i-th column among the M scan lines 42, the scan signal Scan i is described in the i-th column. The scanning line driving circuit 52 includes a shift register circuit (not shown), and outputs a signal that shifts the shift register circuit step by step as a shift output signal. The shift output signal is used to form the scan signal Scan 1 in the first column to the scan signal Scan M in the M column.

A signal line 43 and a complementary signal line 45 are electrically connected to the signal line driving circuit 53. The signal line driving circuit 53 includes a shift register circuit, a decoder circuit, or a demultiplexer circuit, which are not shown. The signal line driving circuit 53 is synchronized with the selection of the scanning lines 42 and supplies an image signal (Data) to each of the N signal lines 43 and a complementary image signal (XData) to each of the N complementary signal lines 45 . The image signal and the complementary image signal are digital signals that take any one of a first potential (VDD1 in this embodiment) and a second potential (VSS in this embodiment).

In addition, when the image signal supplied to the signal line 43 in the j-th row among the N signal lines 43 is specified, it is described as the image signal Data j in the j-th row. Similarly, when the complementary image signal supplied to the complementary signal line 45 in the j-th row of the N complementary signal lines 45 is specified, it is described as the complementary image signal XData j in the j-th row.

A control line 44 is electrically connected to the control line driving circuit 54. The control line driving circuit 54 outputs a control signal specific to a column to each control line 44 divided for each column. The control line 44 supplies this control signal to the corresponding pixel circuits 41. The control signal has an enabled state and a non-enabled state, and the control line 44 can receive the control signal from the control line driving circuit 54 and set it to the enabled state appropriately. The control signal takes a potential between the second potential (low potential VSS) and the third potential (second high potential VDD2).

As described later, in this embodiment, since the fourth transistor 34 is a P-type (see FIG. 8), the control signal (enable signal) in the enabled state is Low (low potential), and the control in the non-enabled state The signal (non-enable signal) is High. The first potential is described as V1, the second potential is described as V2, the third potential is described as V3, and the enable signal is set to V3- (V1-V2) or less, and preferably the second potential (V2). The non-enable signal is set to a third potential (V3) or more, and is preferably a third potential (V3).

In addition, when the control signal supplied to the control line 44 in the i-th column among the M control lines 44 is specified, it is described as the control signal Enb i in the i-th column. The control line driving circuit 54 may supply the enable signals (or non-enable signals) as control signals one by one in a row, or may simultaneously provide enable signals (or non-enable signals) in a plurality of columns. In this embodiment, the control line driving circuit 54 simultaneously supplies the enable signals (or non-enable signals) to all the pixel circuits 41 located in the display area E via the control lines 44.

The control device 55 includes a display signal supply circuit 56 and a VRAM (Video Random Access Memory) circuit 57. The VRAM circuit 57 temporarily stores a frame image and the like. The display signal supply circuit 56 generates a display signal (image signal, clock signal, etc.) from the frame image temporarily stored in the VRAM circuit 57, and supplies the signal to the drive circuit 51.

In this embodiment, the driving circuit 51 or the pixel circuit 41 is formed on the element substrate 11 (a single-crystal silicon substrate in this embodiment). Specifically, the driving circuit 51 or the pixel circuit 41 is composed of a transistor element formed on a single crystal silicon substrate.

The control device 55 is composed of a semiconductor integrated circuit formed on a substrate (not shown) including a single crystal semiconductor substrate different from the element substrate 11. The substrate on which the control device 55 is formed is connected to an external connection terminal 13 provided on the element substrate 11 through a flexible printed circuit (FPC). A display signal is supplied to the drive circuit 51 via the flexible printed board self-control device 55.

[Configuration of Pixel] Next, a configuration of a pixel according to this embodiment will be described with reference to FIG. 6. FIG. 6 is a diagram illustrating the structure of a pixel in this embodiment.

As described above, in the optoelectronic device 10, an image is displayed using the pixels 59 including the sub-pixels 58 (sub-pixels 58B, 58G, 58R) as a display unit. In this embodiment, the length a in the column direction (X direction) of the sub-pixels 58 is 4 micrometers (μm), and the length b in the row direction (Y direction) of the sub-pixels 58 is 12 micrometers (μm). In other words, the arrangement pitch in the column direction (X direction) of the sub-pixels 58 is 4 micrometers (μm), and the arrangement pitch in the row direction (Y direction) of the sub-pixels 58 is 12 micrometers (μm).

A pixel circuit 41 including a light emitting device (Light Emitting Device: LED) 20 is provided in each sub-pixel 58. The light emitting element 20 emits white light. The photovoltaic device 10 includes a color filter (not shown) that transmits light emitted from the light emitting element 20. The color filter includes a color filter corresponding to a color of the displayed basic color p. In this embodiment, the basic color p = 3, and color filters of colors B, G, and R are arranged corresponding to each of the sub-pixel 58B, the sub-pixel 58G, and the sub-pixel 58R.

In this embodiment, as an example of the light emitting element 20, an organic EL (Electro Luminescence) element is used. The organic EL element may have a light resonance structure that amplifies the intensity of light of a specific wavelength. That is, it can be configured as follows: components of blue light are extracted from white light emitted from the light emitting element 20 in the sub-pixel 58B, components of green light are extracted from white light emitted from the light emitting element 20 in the sub-pixel 58G, and sub-pixel 58R A component of red light is extracted from the white light emitted from the light emitting element 20.

In addition to the above examples, it is also possible to set the basic color p = 4, and prepare colors other than B, G, and R for the color filter, such as a color filter for white light (substantially no color filter). Sub-pixel 58), and color filters for other colors such as yellow or cyan can be prepared. As the light emitting element 20, a light emitting diode element such as gallium nitride (GaN), a semiconductor laser element, or the like can be used.

[Digital Drive of Optoelectronic Device] Next, an image display method of digital drive in the optoelectronic device 10 of this embodiment will be described with reference to FIG. 7. FIG. 7 is a diagram illustrating digital driving of the photovoltaic device according to this embodiment.

The optoelectronic device 10 displays a specific image on the display area E (see FIG. 4) according to the digital driving. That is, the light-emitting element 20 (refer to FIG. 6) disposed in each sub-pixel 58 adopts one of two states of light emission (light display) or non-light emission (dark display), and the gray scale of the displayed image is determined by each light-emitting element. The proportion of 20 luminous periods is determined. This is called time-sharing drive.

As shown in FIG. 7, in the time-division driving, one field (F) displaying one image is divided into a plurality of sub-fields (SF), and the light-emitting element 20 is controlled by controlling each sub-field (SF). Luminous and non-luminous and grayscale display. Here, as an example, a case where 2 ⁶ = 64 gray levels are displayed by using a 6-bit time-sharing gray level method is described as an example. In the 6-bit time-sharing grayscale method, one field F is divided into six subfields SF1 to SF6.

In FIG. 7, in one field F, the i-th subfield is represented by SFi, and six subfields of the first subfield SF1 to the sixth subfield SF6 are displayed. Each subfield SF includes a display period P2 (P2-1 to P2-6) as the second period, and a non-display period (signal writing period) P1 (P1-1 to P1-6) as the first period as necessary. ).

In addition, in this specification, the sub-fields SF1 to SF6 are not distinguished and may be collectively referred to as the sub-field SF. The non-display period P1-1 to P1-6 may be collectively referred to as the non-display period P1 and the display period P2-1 may not be distinguished. ～ P2-6 are collectively referred to as display period P2.

The light-emitting element 20 is light-emitting or non-light-emitting during the display period P2, and is non-light-emitting during the non-display period (signal writing period) P1. The non-display period P1 is used to write an image signal to the memory circuit 60 (refer to FIG. 8) or to adjust the display time. When the shortest secondary field (for example, SF1) is relatively long, etc., the non-display period may be omitted. P1 (P1-1).

In the 6-bit time-sharing grayscale mode, the display period P2 (P2-1 to P2-6) of each subfield SF is set to (SF2-1 to P2-1): (SF2 to P2-2): (SF3 (P2-3 of SF4): (P2-4 of SF4): (P2-5 of SF5): (P2-6 of SF6) = 1: 2: 4: 8: 16: 32. For example, when displaying an image in a progressive manner with a frame frequency of 30 Hz, 1 frame = 1 field (F) = 33.3 milliseconds (msec).

In the case of the above example, if the non-display period P1 (P1-1 to P1-6) in each subfield SF is set to 1 millisecond, then it is set to (SF2-1 of P2-1) = 0.434 milliseconds, (SF2 (P2-2) = 0.868 ms, (SF2-3 P2-3) = 1.735 ms, (SF4 P2-4) = 3.471 ms, (SF5 P2-5) = 6.942 ms, (SF6 P2-6) = 13.884 ms.

Here, if the time of the non-display period P1 is represented by x (sec) and the shortest display period P2 is represented by y (sec) (in the case of the above example, it is the display period P2-1 in the first subfield SF1) For the time, the number of bits of the gray scale (= the number of sub-field SF) is represented by g, and the field frequency is represented by f (Hz), then the relationship is displayed according to the following formula 1.

[Number 1]

In the digital driving of the photoelectric device 10, gray-scale display is realized based on the ratio of the light-emitting period to the total display period P2 in one field F. For example, in a black display with a gray level of "0", the light-emitting element 20 is set to non-light-emitting during all display periods P2-1 to P2-6 of the six sub-fields SF1 to SF6. On the other hand, in the white display of the gray level "63", the light emitting element 20 is set to emit light in all the display periods P2-1 to P2-6 of the six subfields SF1 to SF6.

In addition, if it is desired to obtain a display of intermediate brightness such as gray level "7" in 64 gray levels, the display period P2-1 of the first subfield SF1 and the display period P2- of the second subfield SF2 2, and the third sub-field SF3 display period P2-3 causes the light-emitting element 20 to emit light, and during the other sub-fields SF4 to SF6 display periods P2-4 to P2-6, the light-emitting element 20 is set to non-emission. For each of the sub-fields SF constituting one field F in this manner, the light-emitting element 20 can be light-emitting or non-light-emitting during the display period P2 to appropriately perform intermediate gray-scale display.

However, in the previous analog-driven optoelectronic device (organic EL device), the gray-scale display is performed by performing analog control on the current flowing through the organic EL element according to the gate potential of the driving transistor. Differences in voltage and current characteristics or threshold voltages cause brightness differences or grayscale shifts between pixels, resulting in reduced display quality. On the other hand, if a compensation circuit for compensating the difference between the voltage and current characteristics or the threshold voltage of the driving transistor is provided as described in Patent Document 1, the power consumption is increased because the compensation circuit also flows current.

In addition, in the conventional organic EL device, in order to make the display more grayscale, it is necessary to expand the capacitance of the capacitive element of the memory analog signal, that is, the image signal. Therefore, it is difficult to take into account the high resolution (micronization of pixels), Charge and discharge of larger capacitive elements also increase power consumption. In other words, the conventional organic EL device has a problem that it is difficult to realize a photovoltaic device capable of displaying a high-resolution and multi-grayscale high-quality image with low power consumption.

In the optoelectronic device 10 of the present embodiment, since it is digitally driven with a binary operation of ON / OFF, the light-emitting element 20 can adopt either a binary state of light emission or non-light emission. Therefore, compared with the case of analog driving, it is less susceptible to the difference in the voltage and current characteristics of the transistor or the threshold voltage. Therefore, it is possible to obtain high quality with fewer brightness differences or grayscale shifts in the pixel 59 (sub-pixel 58). Display image. Furthermore, in the digital drive, since it is not necessary to maintain a capacitive element with a larger capacitance required in analog driving, the miniaturization of the pixel 59 (sub-pixel 58) can be achieved, and it is easy to promote high resolution and reduce the accompanying Power consumption for charging and discharging larger capacitors.

Further, in the digital driving of the photovoltaic device 10, the number of gray levels can be easily increased by increasing the number g of the sub-fields SF constituting one field F. In this case, if there is the non-display period P1 as described above, the number of gray levels can be increased by shortening only the shortest display period P2. For example, in a case where the frame frequency is f = 30 Hz in a progressive manner and g = 8 is set to display 256 gray levels, if the time of the non-display period P1 is set to x = 1 millisecond, according to formula 1, As long as the time of the shortest display period (P2-1 of SF1) is set to y = 0.100 milliseconds.

As described in detail later, in the digital driving of the photoelectric device 10, the non-display period P1, which is the first period, may be set as a signal writing period (or an image signal overwriting) for writing an image signal to the memory circuit 60. Signal overwrite period). Therefore, without changing the signal writing period (that is, without changing the clock frequency of the driving circuit 51), it is possible to simply change from a 6-bit grayscale display to an 8-bit grayscale display.

Furthermore, in the digital driving of the optoelectronic device 10, the image signal of the memory circuit 60 (see FIG. 8) of the sub-pixel 58 which changes the display between the sub-field SF or the field F is overwritten. On the other hand, since the image signal of the memory circuit 60 of the sub-pixel 58 that has not been displayed is not overwritten (held), low power consumption is achieved. That is, according to the present configuration, it is possible to realize the photoelectric device 10 which reduces power consumption, has a small luminance difference or grayscale shift between the pixels 59 (sub-pixels 58), and displays high-resolution images in multiple grayscales.

(Embodiment 1) "Structure of Pixel Circuit" Next, the structure of a pixel circuit according to the first embodiment will be described with examples and modifications. First, the structure of a pixel circuit according to the first embodiment of the first embodiment will be described with reference to FIG. 8. FIG. 8 is a diagram illustrating the structure of a pixel circuit of the first embodiment.

As shown in FIG. 8, a pixel circuit 41 is provided for each of the sub-pixels 58 arranged corresponding to the intersection of the scanning line 42 and the signal line 43. A control line 44 is arranged along the scanning line 42, and a complementary signal line 45 is arranged along the signal line 43. For each pixel circuit 41, the scanning line 42, the signal line 43, the control line 44, and the complementary signal line 45 correspond.

In the first embodiment (the first and the following variations), each pixel circuit 41 is supplied with a first potential (VDD1) from a first high potential line 47 and a second potential (from a low potential line 46) VSS), and a third potential (VDD2) is supplied from the second high potential line 49.

The pixel circuit 41 of the first embodiment includes an N-type first transistor 31, a light-emitting element 20, a P-type fourth transistor 34, a memory circuit 60, an N-type second transistor 32, and an N-type complementary transistor. 2 电 晶 38。 2 transistor 38. Since the pixel circuit 41 includes the memory circuit 60, the optoelectronic device 10 can realize digital driving. Compared with the case of analog driving, since the difference in light emission brightness of the light-emitting element 20 between the sub-pixels 58 is suppressed, the display difference between the pixels 59 can be reduced. .

The first transistor 31, the light-emitting element 20, and the fourth transistor 34 are arranged in series between a third potential line (second high potential line 49) and a second potential line (low potential line 46). The memory circuit 60 is disposed between the first potential line (first high potential line 47) and the second potential line (low potential line 46). The second transistor 32 is disposed between the memory circuit 60 and the signal line 43. The complementary second transistor 38 is disposed between the memory circuit 60 and the complementary signal line 45.

The memory circuit 60 includes a first inverter 61 and a second inverter 62. The memory circuit 60 is configured such that these two inverters 61 and 62 are connected in a loop to form a so-called static memory and store an image signal, which is a digital signal. The output terminal 25 of the first inverter 61 is electrically connected to the input terminal 28 of the second inverter 62, and the output terminal 27 of the second inverter 62 is electrically connected to the input terminal 26 of the first inverter 61.

In addition, in this specification, the state where the terminal (output or input) A and the terminal (output or input) B are electrically connected refers to a state where the logic of the terminal A can be the same as the logic of the terminal B. For example, even when the terminal A and the A transistor, a resistance element, a diode, etc. are arranged between the terminals B, and it can also be said that they are electrically connected. In addition, the "arrangement" when described as "the transistor or element is arranged between A and B" is not a layout arrangement but a layout on a circuit diagram.

The digital signal memorized by the memory circuit 60 is a high value or a low value. In this embodiment, when the potential of the output terminal 25 of the first inverter 61 is Low (the potential of the output terminal 27 of the second inverter 62 is High), the light emitting element 20 is capable of emitting light. In a state where the potential of the output terminal 25 of the first inverter 61 is High (the potential of the output terminal 27 of the second inverter 62 is Low), the light emitting element 20 is non-light emitting.

In this embodiment, the two inverters 61 and 62 constituting the memory circuit 60 are arranged between the first potential line (the first high potential line 47) and the second potential line (the low potential line 46). The inverters 61 and 62 supply VDD1 as a first potential and VSS as a second potential. Therefore, High corresponds to the first potential (VDD1), and Low corresponds to the second potential (VSS).

For example, if a digital signal is stored in the memory circuit 60 and the potential of the output terminal 25 of the first inverter 61 is Low, Low is input to the input terminal 28 of the second inverter 62 and the second inverter 62 The potential of the output terminal 27 is High. Next, High is input to the input terminal 26 of the first inverter 61 and the potential of the output terminal 25 of the first inverter 61 is Low. In this way, the digital signal stored in the memory circuit 60 is maintained in a stable state until the next overwriting.

The first inverter 61 includes a third transistor 33 of an N type and a fifth transistor 35 of a P type, and has a CMOS structure. The third transistor 33 and the fifth transistor 35 are arranged in series between the first potential line (first high potential line 47) and the second potential line (low potential line 46). The source of the third transistor 33 is electrically connected to the second potential line (low potential line 46). The source of the fifth transistor 35 is electrically connected to the first potential line (first high potential line 47).

The second inverter 62 includes a P-type sixth transistor 36 and an N-type seventh transistor 37, and has a CMOS structure. The sixth transistor 36 and the seventh transistor 37 are arranged in series between the first potential line (first high potential line 47) and the second potential line (low potential line 46). The source of the sixth transistor 36 is electrically connected to a first potential line (first high potential line 47). The source of the seventh transistor 37 is electrically connected to the second potential line (low potential line 46).

The output terminal 25 of the first inverter 61 is the drain of the third transistor 33 and the fifth transistor 35. The output terminal 27 of the second inverter 62 is the drain of the sixth transistor 36 and the seventh transistor 37. The input terminal 26 of the first inverter 61 is the gate of the third transistor 33 and the fifth transistor 35, and is electrically connected to the output terminal 27 of the second inverter 62. Similarly, the input terminal 28 of the second inverter 62 is the gate of the sixth transistor 36 and the seventh transistor 37, and is electrically connected to the output terminal 25 of the first inverter 61.

In addition, in this embodiment, the first inverter 61 and the second inverter 62 are both configured by CMOS, but the inverters 61 and 62 may be configured by a transistor and a resistance element. For example, one of the third transistor 33 and the fifth transistor 35 may be replaced by a resistance element in the first inverter 61, and the sixth transistor 36 and the seventh transistor may be replaced by a resistance element in the second inverter 62. One of crystals 37.

The light-emitting element 20 is an organic EL element in this embodiment, and includes an anode (pixel electrode) 21, a light-emitting portion (light-emitting functional layer) 22, and a cathode (counter electrode) 23. The light-emitting portion 22 is configured such that excitons are formed by a hole injected from the anode 21 side and electrons injected from the cathode 23 side, and when the exciton disappears (when the hole and the electron are recoupled), a part of the energy becomes fluorescent light or Phosphorescence is emitted, thereby emitting light.

In the pixel circuit 41 of the first embodiment, the light emitting element 20 is disposed between the first transistor 31 and the fourth transistor 34. The anode 21 of the light-emitting element 20 is electrically connected to the drain of the fourth transistor 34, and the cathode 23 of the light-emitting element 20 is electrically connected to the drain of the first transistor 31.

The first transistor 31 is a driving transistor for the light emitting element 20. That is, when the first transistor 31 is turned on, the light emitting element 20 can emit light. The gate of the first transistor 31 is electrically connected to the output terminal 27 of the second inverter 62 of the memory circuit 60. The source of the first transistor 31 is electrically connected to the second potential line (low potential line 46). The drain of the first transistor 31 is electrically connected to the light emitting element 20 (cathode 23). That is, the N-type first transistor 31 is disposed on the low potential side with respect to the light emitting element 20.

The fourth transistor 34 is a control transistor that controls the light emission of the light-emitting element 20. When the fourth transistor 34 is turned on, the light emitting element 20 can emit light. Although described later, in this embodiment, if the enable signal is supplied to the control line 44 as a control signal, the fourth transistor 34 is turned on, and the output terminal 27 of the second inverter 62 is equivalent to emitting light. When the potential of the first transistor 31 is turned on, the light-emitting element 20 emits light.

The gate of the fourth transistor 34 is electrically connected to the control line 44. The source of the fourth transistor 34 is electrically connected to a third potential line (second high potential line 49). The drain of the fourth transistor 34 is electrically connected to the light emitting element 20 (anode 21). That is, the P-type fourth transistor 34 is disposed on the high potential side with respect to the light emitting element 20.

Here, in the N-type transistor, the source potential and the drain potential are compared, and the lower potential is the source. In the P-type transistor, the source potential and the drain potential are compared, and the source having the higher potential is the source. The N-type transistor is disposed on a lower potential side than the light emitting element 20. On the other hand, the P-type transistor is disposed on a higher potential side than the light emitting element 20. By disposing the N-type transistor and the P-type transistor with respect to the light-emitting element 20 in this manner, each transistor can be operated substantially linearly (hereinafter referred to as a linear operation).

The first transistor 31 and the fourth transistor 34 are preferably of opposite polarities. In Embodiment 1, the first transistor 31 is an N-type, the fourth transistor 34 is a P-type, the first transistor 31 of the N-type is disposed on a lower potential side than the light-emitting element 20, and the fourth transistor of the P-type is The crystal 34 is disposed on a higher potential side than the light emitting element 20. Therefore, the first transistor 31 and the fourth transistor 34 can be operated linearly, and the difference in the threshold voltage of the first transistor 31 or the fourth transistor 34 can be prevented from affecting the display characteristics (luminous brightness of the light emitting element 20).

Furthermore, the source of the first transistor 31 is electrically connected to the second potential line (low potential line 46), and the source of the fourth transistor 34 is electrically connected to the third potential line (second high potential line). 49), the source potential of the first transistor 31 is fixed to the second potential, and the source potential of the fourth transistor 34 is fixed to the third potential. Thereby, even if the source-drain voltage of the first transistor 31 or the fourth transistor 34 is small, the conductivity of the first transistor 31 or the fourth transistor 34 in the on state can be increased. As a result, since most of the potential difference between the third potential (VDD2) and the second potential (VSS) is applied to the light-emitting element 20, it is not easily affected by the threshold voltage difference of the first transistor 31 or the fourth transistor 34. The uniformity of the light emission brightness of the light-emitting element 20 between the pixels 59 (the sub-pixels 58) is improved.

The second transistor 32 is disposed between the memory circuit 60 (the input terminal 28 of the second inverter 62 = the output terminal 25 of the first inverter 61) and the signal line 43. One of the source-drain electrodes of the N-type second transistor 32 is electrically connected to the signal line 43 and the other is electrically connected to the memory circuit 60 (the input terminal 28 of the second inverter 62), that is, the sixth The gates of the transistor 36 and the seventh transistor 37 (the drains of the third transistor 33 and the fifth transistor 35). The gate of the second transistor 32 is electrically connected to the scanning line 42.

The complementary second transistor 38 is disposed between the memory circuit 60 (the input terminal 26 of the first inverter 61 = the output terminal 27 of the second inverter 62) and the complementary signal line 45. One of the source-drain electrodes of the N-type complementary second transistor 38 is electrically connected to the complementary signal line 45, and the other is electrically connected to the memory circuit 60 (input terminal 26 of the first inverter 61), that is, Gates of the third transistor 33 and the fifth transistor 35 (the drains of the sixth transistor 36 and the seventh transistor 37). The gate of the complementary second transistor 38 is electrically connected to the scanning line 42.

The photovoltaic device 10 according to the present embodiment includes a plurality of complementary signal lines 45 in a display area E (see FIG. 5). For one pixel circuit 41, one signal line 43 corresponds to one complementary signal line 45. The signal lines 43 of one pixel circuit 41 and complementary signal lines 45 paired with them are supplied with signals complementary to each other. That is, a signal (hereinafter, referred to as an inverted signal) in which the polarity of the signal supplied to the signal line 43 is inverted is supplied to the complementary signal line 45. For example, when High is supplied to the signal line 43, Low is supplied to the complementary signal line 45 paired with it. When Low is supplied to the signal line 43, High is supplied to the complementary signal line 45 paired with it.

The second transistor 32 and the complementary second transistor 38 are selected transistors for the pixel circuit 41. The gate of the second transistor 32 and the gate of the complementary second transistor 38 are electrically connected to the scanning line 42. The second transistor 32 and the complementary second transistor 38 switch between the on state and the off state at the same time based on the scanning signal (selection signal or non-selection signal) supplied to the scan line 42.

When a selection signal is supplied to the scanning line 42 as a scanning signal, the second transistor 32 and the complementary second transistor 38 are selected and both are turned on. In this way, the signal line 43 and the input terminal 28 of the second inverter 62 of the memory circuit 60 are in a conducting state, and at the same time, the complementary signal line 45 and the input terminal 26 of the first inverter 61 of the memory circuit 60 are in a conducting state.

Thereby, a digital image signal is written to the input terminal 28 of the second inverter 62 from the signal line 43 via the second transistor 32. Furthermore, an inverted signal (digital complementary image signal) of a digital image signal is written to the input terminal 26 of the first inverter 61 from the complementary signal line 45 via the complementary second transistor 38. As a result, the digital image signal and the digital complementary image signal are stored in the memory circuit 60.

The digital image signal and the digital complementary image signal stored in the memory circuit 60 are maintained in a stable state until the next time the second transistor 32 and the complementary second transistor 38 are selected and both are on. Since the signal line 43 and The complementary signal line 45 continues until the digital image signal and the digital complementary image signal are rewritten.

In addition, it is preferable to determine the polarity or size of each transistor (gate length) in such a manner that the on-resistance of the second transistor 32 is lower than that of the third transistor 33 or the on-resistance of the fifth transistor 35. Or gate width), driving conditions (potential when the scanning signal is a selection signal), and so on. Similarly, it is preferable to determine the polarity, size, and drive of each transistor in a manner that the on-resistance of the complementary second transistor 38 is lower than the on-resistance of the sixth transistor 36 or the seventh transistor 37. Conditions, etc. By doing so, the signals stored in the memory circuit 60 can be quickly and surely overwritten.

The optoelectronic device 10 of this embodiment includes a plurality of control lines 44 in a display area E. A gate of the fourth transistor 34 is electrically connected to the control line 44. The fourth transistor 34, which is a control transistor for the light-emitting element 20, switches the on state and the off state in accordance with a control signal (enable signal or non-enable signal) supplied to the control line 44.

When an enable signal is supplied to the control line 44 as a control signal, the fourth transistor 34 is turned on. When the fourth transistor 34 is turned on, the light emitting element 20 can emit light. On the other hand, when a non-enable signal is supplied to the control line 44 as a control signal, the fourth transistor 34 is turned off, and the light emitting element 20 does not emit light. When the fourth transistor 34 is in the off state, the memory circuit 60 can overwrite the stored image signals without malfunction. This point will be described below.

In this embodiment, since the control line 44 and the scanning line 42 are made independent of each other for each pixel circuit 41, the second transistor 32 and the fourth transistor 34 operate in an independent state. As a result, when the second transistor 32 is turned on, the fourth transistor 34 can be turned off.

That is, when the image signal is written into the memory circuit 60, the fourth transistor 34 is set to the off state, and the second transistor 32 and the complementary second transistor 38 are set to the on state. The inverted signal of the image signal and the image signal is supplied to the memory circuit 60. When the second transistor 32 is in the on state and the fourth transistor 34 is in the off state, the light emitting element 20 does not emit light while the image signal is written into the memory circuit 60. With this, the gray scale of time division can be accurately represented.

Thereafter, when the light-emitting element 20 is caused to emit light, the second transistor 32 and the complementary second transistor 38 are turned off, and then the fourth transistor 34 is turned on. At this time, when the first transistor 31 is on, the third potential line (second high potential line 49) reaches the second potential line from the third transistor 34, the light-emitting element 20, and the first transistor 31. The path of (low potential line 46) is in an on state, and a current flows through the light emitting element 20.

When the fourth transistor 34 is in the on state, the second transistor 32 and the complementary second transistor 38 are in the off state. Therefore, during the period when the light-emitting element 20 is caused to emit light, the image signal and the image signal are not switched. The inverted signal is supplied to the memory circuit 60. Therefore, since the image signals stored in the memory circuit 60 are not overwritten by mistake, high-quality image display without error display can be realized.

[Relationship Between Each Potential and Threshold Voltage of Transistor] As described above, in this embodiment, a low-voltage power source is constituted by the first potential (VDD1) and the second potential (VSS), and the third potential (VDD2) and The second potential (VSS) constitutes a high-voltage system power source. With such a configuration, the photovoltaic device 10 that realizes high-speed operation and obtains a bright display. This point will be described below.

In the following description, the first potential is described as V1, the second potential is described as V2, and the third potential is described as V3. In this embodiment, the potential difference (V1-V2 = 3.0 V) of the first potential (as an example, V1 = 3.0 V) to the second potential (as an example, V2 = 0 V) of the low-voltage system power source is less than The voltage of the high-voltage power source is the potential difference (V3-V2 = 7.0 V) of the third potential (V3 = 7.0 V) with respect to the second potential (V2 = 0 V) (V1-V2 <V3-V2).

When the potentials are set as described above, since the driving circuit 51 or the memory circuit 60 is operated by the low-voltage power supply supplied with the first potential and the second potential, the transistors constituting the driving circuit 51 or the memory circuit 60 can be made fine. And high speed operation. On the other hand, since the light-emitting element 20 is caused to emit light by a high-voltage power source supplied with a third potential and a second potential, the light-emitting brightness of the light-emitting element 20 can be increased. That is, with the configuration of this embodiment, the optoelectronic device 10 that enables each circuit to operate at high speed and causes the light-emitting element 20 to emit light at a high brightness to obtain a bright display can be realized.

Generally, in a light-emitting element such as an organic EL element, a relatively high voltage (for example, 5 V or more) is required for the light-emitting element to emit light. However, in a semiconductor device, if the power supply voltage is increased, the size of the transistor (gate length L or gate width W) must be increased in order to prevent malfunction, so the operation of the circuit is slow. On the other hand, if the power supply voltage is reduced in order to operate the circuit at a high speed, the light-emitting brightness of the light-emitting element is reduced. In short, in the configuration in which the power supply voltage of the light-emitting element emits light and the power supply voltage of the circuit operation as before, it is difficult to coexist the high-brightness light emission and high-speed operation of the circuit.

In contrast, in this embodiment, the power source of the photovoltaic device 10 includes a low-voltage-based power source and a high-voltage-based power source, and the power source for operating the drive circuit 51 or the memory circuit 60 is a low-voltage power source. Accordingly, the size of each transistor constituting the driving circuit 51 or the memory circuit 60 is set to about L = 0.5 micrometer (μm), which is smaller than L = 0.75 micrometer (μm) of the first transistor 31 or the fourth transistor 34. Since these circuits are driven with a low voltage of V1-V2 = 3.0 V, the driving circuit 51 or the memory circuit 60 can be operated at high speed.

In addition, since the light-emitting element 20 emits light with a high voltage of V3-V2 = 7.0 V by a high-voltage power source, the light-emitting element 20 can emit light with high brightness. Furthermore, as described later, by operating the first transistor 31 or the fourth transistor 34 arranged in series with the light emitting element 20 in a linear manner, most of the high voltage of V3-V2 = 7.0 V can be applied to the light emitting element 20. Therefore, the brightness when the light-emitting element 20 emits light can be further improved.

In this embodiment, the threshold voltage (V _th1 ) of the first transistor 31 which is the driving transistor is positive (0 <V _th1 ). When the image signal stored in the memory circuit 60 is equivalent to non-light emission, the potential of the output terminal 27 of the memory circuit 60 is Low, that is, the second potential (V2). Since the source of the first transistor 31 is connected to the second potential line (low potential line 46), the source potential and the gate potential of the first transistor 31 are both the second potential (V2), so the first transistor The gate-source voltage V _{gs1 of 31} is 0 V.

Therefore, when the threshold voltage V _th1 (as an example, V _th1 = 0.36 V) of the first transistor 31 is positive (0 <V _th1 ), the gate-source voltage V _{gs1 of the} N-type first transistor 31 is less than Since the threshold voltage V _th1 , the first transistor 31 is turned off. Thereby, when the image signal is non-emission, the first transistor 31 can be surely turned off.

Further, in this embodiment, the potential difference of the first potential (V1) with the second potential (V2) as a reference is larger than the threshold voltage Vt _h1 (V _th1 <V1-V2) of the first transistor 31. When the image signal stored in the memory circuit 60 corresponds to light emission, the potential of the output terminal 27 of the memory circuit 60 is High. Since High is the first potential (V1), the gate-source voltage V _gs1 of the first transistor 31 becomes the potential difference _between the first potential (V1) and the second potential (V2) (V _gs1 = V1-V2 = 3.0 V-0 V = 3.0 V).

If the potential difference (V1-V2 = 3.0 V) of the first potential (V1) with respect to the second potential (V2) is greater than the threshold voltage V _th1 (V _th1 = 0.36 V) of the first transistor 31 (V _th1 <V1-V2 ), When the potential of the output terminal 27 of the memory circuit 60 is High, the gate-source voltage V _{gs1 of the} N-type first transistor 31 is greater than the threshold voltage V _th1 , so the first transistor 31 is in an on state. Therefore, when the image signal emits light, the first transistor 31 can be reliably turned on.

The fourth transistor 34, which is a control transistor, is turned off when a non-enable signal is supplied to the control line 44 electrically connected to the gate as a control signal, and is turned on when an enable signal is supplied. In this embodiment (Example 1), since the fourth transistor 34 is a P-type, as described above, the non-enable signal is set to a high potential higher than the third potential (V3), and preferably the third potential (V3) V3). The enable signal is set to a low potential of V3- (V1-V2) or less, and preferably the second potential (V2).

When a non-enable signal of the third potential (V3) is supplied to the gate self-control line 44 of the fourth transistor 34, both the source potential and the gate potential of the fourth transistor 34 become the third potential (V3). The gate-source voltage V _gs4 of the fourth transistor 34 is 0 V. If the threshold voltage V _{th4 of the} P-type fourth transistor 34 (as an example, V _th4 = -0.36 V), the gate-source voltage V _{gs4 of} the fourth transistor 34 is greater than the threshold voltage V _th4 . The 4 transistor 34 is in an off state. Therefore, when the control signal is a non-enable signal, the fourth transistor 34 can be surely turned off.

When the enable signal is supplied from the control line 44 to a voltage of _V3- (V1-V2) or lower, that is, 7.0 V- (3.0 V-0 V) = 4.0 V or lower, the gate-source voltage V _{gs4 of} the fourth transistor 34 It is 4.0 V-7.0 V = -3.0 V or less. Therefore, the gate-source voltage V _{gs4 of} the fourth transistor 34 is sufficiently smaller than the threshold voltage V _th4 . Therefore, when the control signal is an enable signal, the fourth transistor 34 can be reliably turned on.

The lower the potential of the enable signal, the larger the gate-source voltage V _{gs4 of} the fourth transistor 34. If the potential of the enable signal is set to the second potential (V2), the gate-source voltage V _gs4 of the fourth transistor 34 is 0 V-7.0 V = -7.0 V, because the fourth transistor in the on state Since the on-resistance of 34 is reduced, the light-emitting element 20 is not easily affected by the difference in the threshold voltage of the fourth transistor 34 when the light-emitting element 20 emits light.

By setting the highest third potential (V3) among the existing three potentials (the first potential, the second potential, and the third potential) to the potential of the non-enabled signal, the lowest second potential (V2) is set In order to enable the potential of the signal, the potential of the non-enabled signal and the enable signal can be set without setting a new potential (potential line). In addition, since the absolute value of the gate-source voltage of the fourth transistor 34 can be sufficiently increased by the enable signal, the on-resistance of the fourth transistor 34 in the on state can be sufficiently reduced, and the fourth transistor can be basically eliminated. The effect of the difference in threshold voltage of the transistor 34 on the light-emitting brightness of the light-emitting element.

That is, with the configuration of this embodiment, even when two types of electrical systems, namely, a low-voltage power supply and a high-voltage power supply are used, the first transistor 31 and the first transistor 31 can be set when the light-emitting element 20 is to be non-light-emitting. The 4 transistor 34 is set to the off state and is definitely set to be non-light-emitting. When the light-emitting element 20 is to be set to light, the first transistor 31 and the fourth transistor 34 are set to be on-state and definitely set to emit light. .

The second transistor 32, which is a selection transistor, is turned off when a non-selection signal is supplied as a scanning signal to the scanning line 42 which is electrically connected to the gate, and is turned on when a selection signal is supplied. In this embodiment, since the second transistor 32 is an N-type, as described above, the non-selection signal is set to a low potential that is equal to or lower than the second potential (V2), and is preferably the second potential (V2). The selection signal is set to a high potential higher than the first potential (V1), and is preferably a third potential (V3).

The first transistor 31 and the second transistor 32 preferably have the same polarity. In the first embodiment, both the first transistor 31 and the second transistor 32 are N-type. Therefore, the first transistor 31 is turned on when the potential of the image signal supplied to the gate is High, and the second transistor 32 is turned on when the scanning signal supplied to the gate is the selection signal (High). . Although High of the image signal is the first potential (V1), the selection signal (High) is set to the first potential (V1) or more, and preferably the third potential (V3).

The case where the potential of the selection signal is set to the third potential (V3) and the image signal of the memory circuit 60 is overwritten from Low to High will be described. The input terminal 28 of the second inverter 62 (= the output terminal 25 of the first inverter 61) which is electrically connected to one of the source and drain terminals of the second transistor 32 is Low until the image signal is overwritten. The second potential (V2). When a selection signal of a third potential (V3) is supplied to the gate self-scanning line 42 of the second transistor 32, the gate source voltage V _gs2 of the second transistor 32 is V3-V2 = 7.0 V-0 V = 7.0 V is higher than the threshold voltage V _{th2 of} the second transistor 32 (for example, V _th2 = 0.36 V), so the second transistor 32 is turned on.

By writing the high (V1) image signal to the memory circuit 60 from the signal line 43, the potential of the output terminal 25 of the first inverter 61 gradually rises from Low (V2) to High (V1), but it is accompanied by Therefore, the gate-source voltage V _{gs2 of} the second transistor 32 gradually decreases to V3-V1 = 7.0 V-3.0 V = 4.0 V. Even if the gate-source voltage V _gs2 of the second transistor 32 becomes the lowest 4.0 V, the gate-source voltage V _{gs2 is} sufficiently higher than the threshold voltage V _{th2 of} the second transistor 32. Therefore, before the image signal is written into the memory circuit 60, the on-resistance of the second transistor 32 is kept low, so the image signal is surely written into the memory circuit 60.

Here, a case is assumed in which the second transistor 32 is a P-type having a characteristic opposite to that of the first transistor 31 (it is assumed to be the second transistor 32A). In this case, the second transistor 32A is turned on when the selection signal is Low. When the potential of the selection signal is set to the second potential (V2) and the image signal of the memory circuit 60 is overwritten from High to Low, when the selection signal of the second potential (V2) is supplied from the scanning line 42, the first The gate-source voltage V _gs2 of the transistor 32A is V2-V1 = 0 V-3.0 V = -3.0 V, because it is lower than the threshold voltage V _{th2 of} the second transistor 32A (as an example, V _th2 = -0.36 V) Therefore, the second transistor 32A is turned on.

By writing the image signal of Low (V2) to the memory circuit 60 through the signal line 43, the potential of the input terminal 28 of the second inverter 62 gradually decreases from High (V1), and along with this, the second transistor The gate-source voltage V _{gs2 of} 32A gradually rises from -3.0 V, and reaches the threshold voltage V _th2 of the second transistor 32A of the P type before the potential of the input terminal 28 becomes the second potential (V2), resulting in the second voltage The crystal 32A is turned off.

In addition, before the second transistor 32A is turned off, the on-resistance of the second transistor 32A increases as the gate-source voltage V _gs2 rises and approaches the threshold voltage V _th2 . Therefore, the memory circuit 60 is overwritten. Like the signal takes time, or the overwrite fails. To avoid this, it is only necessary to set the potential of the selection signal to a lower potential, but in this case, a potential line different from the existing potential is further required.

As in the first embodiment, if both the first transistor 31 and the second transistor 32 have the same polarity of N type, the potential of the selection signal can be set to the third potential which is the highest between the third potential and the first potential. There is no need to set a new ground potential setting. Furthermore, when the second transistor 32 is turned on and an image signal is written to the memory circuit 60, the gate-source voltage V _{gs2 of} the second transistor 32 can be increased. The writing of the image signal rises, and the on-resistance of the second transistor 32 can also be kept low. This makes it possible to write or overwrite the image signal to the memory circuit 60 at high speed and reliably.

Based on the above results, if the relationship between the potentials (V1, V2, V3) and the threshold voltage ( _Vth1 ) of the first transistor 31 in this embodiment is summarized, the relationship between them is expressed by Equation 2 and Equation 3. .

[Number 2]

[Number 3]

[Characteristics of Transistor] Next, the characteristics of the transistor provided in the photovoltaic device 10 of this embodiment will be described. In the optoelectronic device 10 of this embodiment, the light-emitting element 20 is arranged in series between the third potential line (second high potential line 49) and the second potential line (low potential line 46) constituting the high-voltage power supply. There are a first transistor 31 and a fourth transistor 34. The on-resistance of the first transistor 31 is preferably sufficiently lower than the on-resistance of the light-emitting element 20. The on-resistance of the fourth transistor 34 is preferably sufficiently lower than the on-resistance of the light-emitting element 20.

Sufficiently low is the driving condition for linear operation of the first transistor 31 or the fourth transistor 34, specifically, the on-resistance of the first transistor 31 or the fourth transistor 34 is 1 / the on-resistance of the light-emitting element 20. 100 or less, preferably 1/1000 or less. By doing so, the first transistor 31 or the fourth transistor 34 can be operated linearly when the light emitting element 20 emits light.

As a result, most of the potentials generated in the first transistor 31, the fourth transistor 34, and the light-emitting element 20 arranged in series decrease (in short, the voltage difference between the third potential and the second potential of the high-voltage power source voltage) ) Is applied to the light-emitting element 20, and therefore it is not easily affected by the difference in threshold voltage of the two transistors 31 and 34 when the light-emitting element 20 emits light. That is, if such a configuration is used, the influence of the difference in threshold voltage of the first transistor 31 or the fourth transistor 34 can be reduced, so that the brightness difference or gray scale between the pixels 59 (sub-pixels 58) can be suppressed. Shift and realize image display with excellent uniformity.

The reason is that by setting the on-resistance of the first transistor 31 or the fourth transistor 34 to 1/100 or less of the on-resistance of the light-emitting element 20, the light-emitting element 20 receives more than 99% of the power supply voltage, and The potential in the two transistors 31 and 34 drops below 1%. Since the potential of the two transistors 31 and 34 drops below 1%, the difference in the threshold voltage of the two transistors 31 and 34 has a small effect on the light-emitting characteristics of the light-emitting element 20.

In this embodiment (Example 1), the series resistance of the first transistor 31 and the fourth transistor 34 is about 1/1000 of the on-resistance of the light-emitting element 20. In this case, the light-emitting element 20 receives about 99.9% of the power supply voltage, and the potential of the two transistors 31 and 34 drops to about 0.1%. Therefore, the difference between the threshold voltages of the two transistors 31 and 34 can be ignored. The effect caused by the light-emitting characteristics of 20.

The on-resistance of a transistor depends on the transistor's polarity or gate length, gate width, threshold voltage, and gate insulation film thickness. In this embodiment, it is preferable to determine the polarity or the gate of the two transistors 31 and 34 such that the on-resistance of the first transistor 31 and the fourth transistor 34 is sufficiently lower than that of the light-emitting element 20. Pole length, gate width, threshold voltage, gate insulation film thickness, etc. This point will be described below.

In this embodiment, an organic EL element is used for the light emitting element 20, and transistors such as the first transistor 31 and the fourth transistor 34 are formed on the element substrate 11 including a single crystal silicon substrate. The voltage-current characteristics of the light-emitting element 20 are roughly expressed by the following Equation 4.

[Number 4]

In Formula 4, I _EL is the current passing through the light-emitting element 20, V _EL is the voltage applied to the light-emitting element 20, L _EL is the length of the light-emitting element 20 in plan view, and W _EL is the width of the light-emitting element 20 in plan view. J ₀ is the current density coefficient of the light-emitting element 20, V _tm is a coefficient voltage (fixed voltage at a fixed temperature) depending on the temperature of the light-emitting element 20, and V ₀ is a threshold voltage with respect to the light-emitting element 20's light emission.

When V _P represents the voltage of the high-voltage system power source, and V _ds represents the potential drop in the first transistor 31 and the fourth transistor 34, V _EL + V _ds = V _P. In this embodiment, L _EL = 11 micrometers (μm), W _EL = 3 micrometers (μm), J ₀ = 1.449 milliamperes per square centimeter (mA / cm ² ), and V ₀ = 3.0 volts (V). , V _tm = 0.541 Volts (V).

On the other hand, when the first transistor 31, the fourth transistor 34, and the like are represented as an i-th transistor (i is 1 or 4), the drain current I _{dsi thereof} is expressed by the following formula 5.

[Number 5]

5 in the formula, W is _i for the i-th gate electrode of transistor width, L _i is the i-th gate electrode of the transistor length, ε ₀ = dielectric constant of a vacuum, ε _ox is the dielectric constant of the gate insulating film of the gate, t _oxi is the thickness of the gate insulating film, μ _i is the mobility of the i-th transistor, V _gsi is the gate voltage, V _dsi is the drain voltage due to the potential drop of the i-th transistor, and V _thi is the i-th transistor The threshold voltage of the crystal.

In Example 1, W ₁ = 1.0 micrometer (μm), W ₄ = 1.25 micrometer (μm), L ₁ = L ₄ = 0.75 micrometer (μm), _tox = 20 nanometers (nm), μ ₁ = 240 Square centimeter per volt per second (cm ² / V • s), μ ₄ = 150 square centimeter per volt per second (cm ² / V • s), V _th1 = 0.36 V, V _th4 = -0.36 V, V _gs1 = V1-V2 = 3.0 V, V _gs4 = V2-V3 = -7 V.

When the first transistor 31 and the fourth transistor 34 are linearly operated, the potential of the two transistors 31 and 34 is reduced by V _ds , and the voltage and current of the light-emitting element 20 are reduced near V _ds = 0 V. The characteristics are approximated by Equation 6 below.

[Number 6]

In Embodiment 1, the coefficient k defined by Formula 6 is k = 1.39 × 10 ^-6 (Ω ^-1 ). I ₀ is the amount of current when all the voltages V _{P of the} high-voltage power sources are applied to the light-emitting element 20, and I ₀ = 7.82 × 10 ^-7 (A).

Under such conditions, the voltage at which the light-emitting element 20 emits light is based on the voltages of I _EL = I _ds based on Equation 4 and Equation 6. In this embodiment, V _P = V3-V2 = 7 V, V _ds1 = 0.0053 V, V _ds4 = 0.0027 V, V _EL = 6.9920 V, I _EL = I _ds1 = I _ds4 = 7.672 × 10 ^-7 A. At this time, the on-resistance of the first transistor 31 is 6.859 × 10 ³ Ω, the on-resistance of the fourth transistor 34 is 3.491 × 10 ³ Ω, and the on-resistance of the light-emitting element 20 is 9.113 × 10 ⁶ Ω .

Therefore, the on-resistance of the first transistor 31 is lower than the on-resistance of the light-emitting element 20 by 1/1000, which is about 1/1300, and the on-resistance of the fourth transistor 34 is lower than the on-resistance of the light-emitting element 20. Since / 1000 is about 1/2600, most of the voltage of the high-voltage power source can be applied to the light-emitting element 20.

Under this condition, even if the threshold voltage of the transistor fluctuates, for example, by more than 30% (in Example 1, even if V _th1 or V _{th4 varies} between 0.29 V and 0.53 V), V _EL = 6.99 V and I _EL = I _ds1 = I _ds4 = 7.67 × 10 ^-7 A does not change. Generally, the threshold voltage of a transistor does not differ so much. Therefore, by setting the on-resistance of the fourth transistor 34 to about 1/1000 or less of the on-resistance of the light-emitting element 20, the difference in threshold voltage between the first transistor 31 and the fourth transistor 34 is not substantially equal. The light-emitting brightness of the light-emitting element 20 affects.

Approximately, the effect of the difference in threshold voltage of the i-th transistor with respect to the current I _EL = I _dsi can be expressed by Equation 5 and Equation 6 as I _EL = I _dsi simultaneously.

[Number 7]

Since I ₀ is the amount of current when all the high-voltage power supply voltages V _{P are} applied to the light-emitting element 20, as determined by Equation 7, in order to make the light-emitting element 20 emit light near the power-supply voltage V _P , just increase the gate The pole voltage V _gsi or Z _{i is sufficient} . In other words, the larger Z _i is, the less the light-emitting brightness of the light-emitting element 20 is affected by the threshold voltage difference of the transistor.

In Example 1, since k / Z ₁ = 2.52 × 10 ^-2 V and k / Z ₄ = 3.22 × 10 ^-2 V, which are smaller values, the second term on the left side of Formula 7 is relative to the first transistor. 31 is k / (Z ₁ (V _gs1 -V _th1 )) = 0.01, which is k / (Z ₄ (V _gs4 -V _th4 )) = 0.005 with respect to the fourth transistor 34, which is less than 0.01 (1%). degree. As a result, the current (light emission brightness) when the light emitting element 20 emits light is hardly affected by the threshold voltage of the two transistors 31 and 34. That is, by satisfying the value of k / (Z _i (V _gsi -V _thi )) to about 0.01 (1%), the two transistors 31 and 34 with respect to the light emission luminance of the light emitting element 20 can be substantially excluded. Difference in threshold voltages (V _th1 , V _{th 4} ).

In Equation 7, k and Zi are defined according to Equation 5 and Equation 6. In addition, since the mobility μ _i is smaller than the N-type transistor in the P-type transistor, the W (W ₃ in this embodiment) of the P-type transistor is made larger than the W (W in this embodiment) of the N-type transistor. _1), the first P-type transistor 4 of the Z 34 _4, and the first N-type transistor 31 of the Z ₁ to substantially the same extent.

In order for the light emitting element 20 to emit light in the vicinity of the power supply voltage V _P , the gate voltage V _{gsi is preferably} as large as possible. In this embodiment (Example 1), the third potential (V3) of the potential of the control signal (enable signal) in the enabled state with respect to the source potential of the fourth transistor 34 is set as the second potential. (V2), and the gate-source voltage V _{gs4 of} the fourth transistor 34 is increased.

In the optoelectronic device 10 of this embodiment, a memory circuit is arranged between the first potential line (first high potential line 47) and the second potential line (low potential line 46) constituting the low-voltage power supply. The first transistor 33 and the fifth transistor 35 of the first inverter 61 included in 60, and the sixth transistor 36 and the seventh transistor 37 constituting the second inverter 62.

Since these transistors 33, 35, 36, and 37 have a smaller amount of current flow than the first transistor 31 or the fourth transistor 34 that operates with a high-voltage power source, the area of the channel formation region can be reduced. That is, the memory circuit 60 can be miniaturized. In addition, when the area of the channel formation area of the transistors 33, 35, 36, and 37 is small, the capacitance of the transistor is reduced, so that charging and discharging can be performed at high speed. That is, writing or overwriting of the image signal to the memory circuit 60 can be speeded up.

In this embodiment, the gate length of the third transistor 33, the fifth transistor 35, the sixth transistor 36, and the seventh transistor 37 included in the memory circuit 60 when viewed in plan is shorter than that of the light-emitting element. 20 The gate lengths of the first transistor 31 and the fourth transistor 34 arranged in series in plan view.

The gate length of the third transistor 33, the fifth transistor 35, the sixth transistor 36, and the seventh transistor 37 in a plan view is L ₃ = L ₅ = L ₆ = L ₇ = 0.5 micrometer (μm). As described above, since the gate lengths of the first transistor 31 and the fourth transistor 34 in plan view are L ₁ = L ₄ = 0.75 micrometer (μm), the third transistor 33, the fifth transistor 35, and the first transistor The gate length of the sixth transistor 36 and the seventh transistor 37 is short.

In this embodiment, the area of the channel formation region of the third transistor 33, the fifth transistor 35, the sixth transistor 36, and the seventh transistor 37 in plan view is smaller than that of the first transistor 31 and the fourth transistor. The area of the channel formation region of the transistor 34 in a plan view. The area of the channel formation region of the transistor is approximately equal to the area of the gate electrode disposed oppositely, that is, the product of the gate length and the gate width in a plan view.

The gate width of the N-type third transistor 33 and the seventh transistor 37 is W ₃ = W ₇ = 0.5 micrometer (μm), and the gate width of the P-type fifth transistor 35 and the sixth transistor 36 is W ₅ = W ₆ = 0.75 micrometers (μm). Therefore, the area of the channel formation area of the third transistor 33 and the seventh transistor 37 is 0.5 × 0.5 = 0.25 square micrometers (μm ² ), and the area of the channel formation area of the fifth transistor 35 and the sixth transistor 36 is 0.5 × 0.75 = 0.375 square micrometers (μm ² ).

As described above, since the gate width of the first transistor 31 is W ₁ = 1.0 micrometer (μm), the area of the channel formation region of the first transistor 31 is 0.75 × 1.0 = 0.75 square micrometer (μm ² ). Since the gate width of the fourth transistor 34 is W ₄ = 1.25 micrometers (μm), the area of the channel formation region of the fourth transistor 34 is 0.75 × 1.25 = 0.9375 square micrometers (μm ² ). Therefore, the area of the channel formation region of the third transistor 33, the fifth transistor 35, the sixth transistor 36, and the seventh transistor 37 is small.

Thus, in this embodiment, the area of the channel formation region of the transistors 33, 35, 36, and 37 included in the memory circuit 60 can be made smaller than the channel formation region of the transistors 31 and 34 arranged in series with the light emitting element 20. In this way, the memory circuit 60 is miniaturized and operated at high speed, and the light-emitting element 20 emits light with high brightness.

[Driving Method of Pixel Circuit] Next, a driving method of a pixel circuit in the photovoltaic device 10 of this embodiment will be described with reference to FIG. 9. FIG. 9 is a diagram illustrating a driving method of a pixel circuit in this embodiment. In FIG. 9, the horizontal axis is a time axis and includes a first period (non-display period) and a second period (display period). The first period corresponds to P1 (P1-1 to P1-6) shown in FIG. 7. The second period corresponds to P2 (P2-1 to P2-6) shown in FIG. 7.

In the vertical axis of FIG. 9, Scan 1 to Scan M represent the scanning signals supplied to each of the scanning lines 42 in the first to M columns of the M scanning lines 42 (see FIG. 5). The scanning signals include: a scanning signal in a selected state (selection signal), and a scanning signal in a non-selection state (non-selection signal). Enb indicates a control signal supplied to the control line 44 (see FIG. 5). The control signals include: an enable signal (enable signal) and a non-enable signal (non-enable signal).

As described with reference to FIG. 7, one field (F) displaying one image is divided into a plurality of sub-fields (SF), and each sub-field (SF) includes a first period (non-display period) and a first period. The second period (display period) that starts after the period ends. The first period (non-display period) is a signal writing period in which an image signal is written into the memory circuit 60 (see FIG. 8) in each pixel circuit 41 (see FIG. 5) located in the display area E. The second period (display period) is a period during which the light-emitting element 20 (see FIG. 8) in each pixel circuit 41 located in the display area E can emit light.

As shown in FIG. 9, in the optoelectronic device 10 of this embodiment, a non-enable signal is supplied as a control signal to all the control lines 44 in the first period (non-display period). When the non-enable signal is supplied to the control line 44, the fourth transistor 34 (see FIG. 8) is in an off state, so that the light-emitting elements 20 in all the pixel circuits 41 located in the display area E do not emit light.

In the first period, a selection signal is supplied to each of the scanning lines 42 as a scanning signal in each subfield (SF). When a selection signal is supplied to the scanning line 42, the second transistor 32 and the complementary second transistor 38 (see FIG. 8) in the selected pixel circuit 41 are turned on. Thereby, in the selected pixel circuit 41, an image signal is written into the memory circuit 60 from the signal line 43 and the complementary signal line 45 (see FIG. 8). In this way, the image signal is written and stored in the memory circuit 60 of each pixel circuit 41 in the first period.

In the second period (display period), the enable signal is supplied as a control signal to all the control lines 44. When the enable signal is supplied to the control line 44, the fourth transistor 34 is in the on state, so that the light-emitting elements 20 in all the pixel circuits 41 located in the display area E can emit light. In the second period, a non-selection signal in which the second transistor 32 is turned off is supplied to all the scanning lines 42 as a scanning signal. Thereby, in the memory circuit 60 of each pixel circuit 41, the written image signal is held in the sub-field (SF).

As described above, in this embodiment, the first period (non-display period) and the second period (display period) can be controlled independently, so gray-scale display using digital time-sharing driving can be performed. As a result, since the second period can be made shorter than the first period, higher grayscale display can be realized.

In addition, since the control signals supplied to the control line 44 can be shared by the plurality of pixel circuits 41, it is easy to drive the photoelectric device 10. Specifically, when there is no digital driving in the first period, a relatively complicated driving is required to make the light emission period shorter than one vertical period after all the scanning lines 42 are selected. On the other hand, in this embodiment, the control signal supplied to the control line 44 is shared by the plurality of pixel circuits 41, even if the light emission time is shorter than the side field (SF in the vertical period in which all the scanning lines 42 are selected). ), It is also possible to simply drive the photovoltaic device 10 simply by shortening the second period.

As described above, according to the configuration of the pixel circuit 41 of this embodiment, it is possible to display a high-resolution image with high resolution and multiple gray levels with low power consumption, and can operate at a higher speed and obtain a brighter display. Photoelectric device 10.

Hereinafter, a modification of the pixel image configuration of the first embodiment will be described. In the description of the following modified examples, differences from the first embodiment or the above-mentioned modified examples will be described. For the same constituent elements as those of the first embodiment or the modified examples, the same symbols are assigned to the drawings, and descriptions thereof are omitted. In addition, the driving method of the pixel circuit described above is the same as that of the first embodiment, and the same effects as those of the first embodiment can also be obtained in the configuration of the following modification.

(Modification 1) "Configuration of Pixel Circuit" First, a pixel circuit according to Modification 1 of the first embodiment will be described. FIG. 10 is a diagram illustrating a configuration of a pixel circuit according to a first modification. As shown in FIG. 10, the pixel circuit 41A of the first modification differs from the pixel circuit 41 of the first embodiment in that the fourth transistor 34A is an N-type transistor and is disposed between the light-emitting element 20 and the first transistor 31. However, the other components are the same.

The pixel circuit 41A of the first modification includes a light-emitting element 20, an N-type fourth transistor 34A, an N-type first transistor 31, a memory circuit 60, an N-type second transistor 32, and an N-type complementary element. 2 电 晶 38。 2 transistor 38. The anode 21 of the light-emitting element 20 is electrically connected to the third potential line (second high-potential line 49), and the cathode 23 of the light-emitting element 20 is electrically connected to the drain of the fourth transistor 34A.

The source of the fourth transistor 34A is electrically connected to the drain of the first transistor 31. The source of the first transistor 31 is electrically connected to the second potential line (low potential line 46). Therefore, in the pixel circuit 41A of the modification 1, the N-type fourth transistor 34A is disposed on the lower potential side than the light-emitting element 20, and the N-type first transistor 31 is disposed more than the fourth transistor 34A It is closer to the low potential side.

In the modification 1, since the fourth transistor 34A is an N-type, the non-enabled signal is set to a low potential with respect to the source potential of the fourth transistor 34A, and is preferably the second potential (V2). The enable signal is set to a high potential with respect to the source potential of the fourth transistor 34A, and is preferably a third potential (V3).

The first transistor 31 is disposed between the fourth transistor 34A and the second potential line (low potential line 46). Therefore, when the first transistor 31 is turned on and the fourth transistor 34A is also turned on, the source potential of the fourth transistor 34A is slightly higher than the second potential (V2). However, since the source potential of the first transistor 31 can be fixed to the second potential (V2) and the first transistor 31 can be operated linearly, the source potential of the fourth transistor 34A can be set to the second potential. (V2) is approximately equal.

When the non-enabled signal of the second potential (V2) is supplied from the control line 44 to the fourth transistor 34A, the gate-source voltage V _gs4 of the fourth transistor 34A is approximately 0 V. When the threshold voltage V _{th4 of the} N-type fourth transistor 34A is _set (for example, V _th4 = 0.36 V), the gate-source voltage V _{gs4 of} the fourth transistor 34 is smaller than the threshold voltage V _th4 , so the fourth The transistor 34A is in an off state. Therefore, when the control signal is a non-enable signal, the fourth transistor 34A can be reliably turned off.

When the enable signal of the third potential (V3) is supplied from the control line 44, the potential difference ( _V3-) between the gate source voltage _{Vgs4 of} the fourth transistor 34A and the third potential (V3) with respect to the second potential (V2) V2 = 7.0 V-0 V = 7.0 V). Therefore, since the gate-source voltage V _{gs4 of} the fourth transistor 34A is sufficiently larger than the threshold voltage V _th4 , when the control signal is an enable signal, the fourth transistor 34A can be reliably turned on to make it Linear action.

When the first transistor 31 and the fourth transistor 34A are turned on, the third potential line (the second high potential line 49) passes from the light emitting element 20, the fourth transistor 34A, and the first transistor 31 to the first potential line. The path of the two-potential line (low-potential line 46) is turned on, and a current flows through the light-emitting element 20. In addition, the first transistor 31 and the fourth transistor 34A can be operated linearly when the light emitting element 20 is caused to emit light, and therefore it is not easily affected by the difference in threshold voltage between the two transistors 31 and 34A. In addition, in the pixel circuit 41A of the first modification, a high voltage of V3-V2 = 7.0 V can be applied to the light-emitting element 20, so that the brightness of the light-emitting element 20 can be increased.

(Modification 2) Next, a pixel circuit according to Modification 2 of the first embodiment will be described. FIG. 11 is a diagram illustrating a configuration of a pixel circuit according to a second modification. As shown in FIG. 11, the pixel circuit 41B of the second modification differs from the pixel circuit 41A of the first modification in that the first transistor 31 is disposed between the light-emitting element 20 and the fourth transistor 34A, and the other structures are the same. .

The pixel circuit 41B of the second modification includes a light-emitting element 20, an N-type first transistor 31, an N-type fourth transistor 34A, a memory circuit 60, an N-type second transistor 32, and an N-type complementary transistor. 2 电 晶 38。 2 transistor 38. The anode 21 of the light-emitting element 20 is electrically connected to the third potential line (second high-potential line 49), and the cathode 23 of the light-emitting element 20 is electrically connected to the drain of the first transistor 31.

The source of the first transistor 31 is electrically connected to the drain of the fourth transistor 34A. The source of the fourth transistor 34A is electrically connected to the second potential line (low potential line 46). Therefore, in the pixel circuit 41B of the modification 2, the N-type first transistor 31 is disposed on a lower potential side than the light-emitting element 20, and the N-type fourth transistor 34A is disposed more than the first transistor 31. It is closer to the low potential side.

In the modification 2, the source of the fourth transistor 34A is electrically connected to the second potential line (low potential line 46). Therefore, when the light emitting element 20 emits light, that is, when the third potential (V3) When the enable signal is supplied to the control line 44, the gate-source voltage V _gs4 of the fourth transistor 34A is the potential difference based on the third potential (V3) and the second potential (V2) (V _gs4 = V3-V2 = 7.0 V). Therefore, the fourth transistor 34A can be reliably turned on and linearly operated.

In the second modification, the fourth transistor 34A is disposed between the first transistor 31 and the second potential line (low potential line 46). Therefore, the fourth transistor 34A is turned on and the first transistor is turned on. When 31 is also on, the source potential of the first transistor 31 is slightly higher than the second potential (V2). However, since the source potential of the fourth transistor 34A can be fixed to the second potential (V2) and the fourth transistor 34A can be operated in a line shape, the source potential of the first transistor 31 can be set to the second potential. (V2) is approximately equal.

Therefore, when the potential of the output terminal 27 of the memory circuit 60 becomes High (the first potential), the gate-source voltage V _gs1 and the first potential (V1) of the first transistor 31 are relative to the second potential (V2). The potential difference (V1-V2 = 3.0 V) is approximately equal and is greater than the threshold voltage of the first transistor 31 (V _th1 = 0.36 V). Therefore, the first transistor 31 can be reliably turned on and made linear. action.

In the pixel circuit 41B of the second modification, the first transistor 31 and the fourth transistor 34A can be operated linearly when the light-emitting element 20 is caused to emit light, and therefore it is not easily affected by the difference in threshold voltage between the two transistors 31 and 34A. In addition, as a result, most of the high voltage of V3-V2 = 7.0 V can be applied to the light-emitting element 20, so that the brightness when the light-emitting element 20 emits light can be improved.

(Modification 3) Next, a pixel circuit according to Modification 3 of the first embodiment will be described. FIG. 12 is a diagram illustrating a configuration of a pixel circuit according to a third modification. As shown in FIG. 12, the pixel circuit 41C of the third modification differs from the first embodiment and the modification in that the fourth transistor 34 (or the fourth transistor 34A) is not provided, and the other components are the same.

The pixel circuit 41C of the third modification includes a light-emitting element 20, an N-type first transistor 31, a memory circuit 60, an N-type second transistor 32, and an N-type complementary second transistor 38. The anode 21 of the light-emitting element 20 is electrically connected to the third potential line (second high-potential line 49), and the cathode 23 of the light-emitting element 20 is electrically connected to the drain of the first transistor 31. The source of the first transistor 31 is electrically connected to the second potential line (low potential line 46).

In the pixel circuit 41C of the modified example 3, a light emitting element 20 and a first transistor 31 are arranged in series between a third potential line (second high potential line 49) and a second potential line (low potential line 46). . When the potential of the output terminal 27 of the memory circuit 60 is High (first potential) and the first transistor 31 is in the on state, the light emitting element 20 emits light. When the light-emitting element 20 emits light, the source potential of the first transistor 31 can be fixed to the second potential (V2), and the first transistor 31 can be operated linearly, so it is not easily affected by the threshold voltage difference of the first transistor 31 . Thereby, most of the high voltage of V3-V2 = 7.0 V can be applied to the light-emitting element 20, so that the brightness when the light-emitting element 20 emits light can be improved.

In addition, since the control line 44 is not required in the pixel circuit 41C of the third modification, the number of wirings can be reduced, and the number of wiring layers can also be reduced. In general, if the number of wiring layers is large, each wiring layer is formed with an interlayer insulating layer interposed therebetween, so that there may be an increase in manufacturing man-hours of a photovoltaic device (element substrate) or a reduction in manufacturing yield. According to the configuration of Modification 3, even if the number of wiring layers is small, image display can be performed by digital driving. Therefore, compared with the said Example 1 and the modification, a manufacturing man-hour can be reduced or a manufacturing yield can be improved. In addition, since the light-shielding area can be reduced by reducing the number of wirings having light-shielding properties, high resolution (micronization of pixels) can be achieved.

(Second Embodiment) Next, the structure of a photovoltaic device according to a second embodiment will be described. The photovoltaic device of the second embodiment is different from the photovoltaic device 10 of the first embodiment in that the first transistor and the second transistor are P-type, and the second potential (V2) is higher than the first potential (V1) and the first 3 potential (V3). With this, the structure of the pixel circuit of the second embodiment is also different from that of the pixel circuit of the first embodiment. Fig. 13 is a circuit block diagram of a photovoltaic device according to a second embodiment of the present invention. FIG. 14 is a diagram illustrating a pixel structure according to a second embodiment of the present invention. As shown in FIGS. 13 and 14, in the optoelectronic device 10 of this embodiment, a first low potential VSS1, a second low potential VSS2, and a high potential VDD are supplied to the driving unit 50, and the first low potential VSS1, the second The low potential VSS2 and the high potential VDD are supplied to the pixel circuit 71.

The structure of the pixel circuit according to the second embodiment will be described below with examples and a plurality of modifications. In the following description of the examples and modifications, differences from the first embodiment or the first embodiment will be described. The same constituent elements as those of the first embodiment or the first embodiment will be described below. The drawings are marked with the same symbols and their descriptions are omitted.

(Embodiment 2) "Configuration of Pixel Circuit" First, a configuration of a pixel circuit according to a second embodiment of the second embodiment will be described with reference to FIG. 15. FIG. 15 is a diagram illustrating the structure of a pixel circuit of the second embodiment. As shown in FIG. 15, the pixel circuit 71 of the second embodiment includes a P-type first transistor 31A, a light-emitting element 20, an N-type fourth transistor 34A, a memory circuit 60, and a P-type second transistor 32A. And P-type complementary second transistor 38A.

In addition, in the second embodiment (a modification of the second embodiment and the following), the high potential and the low potential are changed to the first embodiment. Specifically, the first potential (V1) is the first low potential VSS1 (for example, V1 = VSS1 = 4.0 V), the second potential (V2) is the high potential VDD (for example, V2 = VDD = 7.0 V), and the third potential (V2) V3) is the second low potential VSS2 (for example, V3 = VSS2 = 0 V). Therefore, the first potential is lower than the second potential, and the third potential is lower than the first potential.

In this embodiment, a low-voltage system power source is constituted by a first potential (first low potential VSS1) and a second potential (high potential VDD), and a third potential (second low potential VSS2) and a second potential (high potential) VDD) constitutes a high-voltage system power supply. The second potential is a potential that becomes a reference among the low-voltage power source and the high-voltage power source.

Further, in the second embodiment (a variation of Example 2 and below), each pixel circuit 71 is supplied with a first potential (VSS1) from a first low-potential line 46 that is a first potential line, and as a second potential The high potential line 47 of the line is supplied with the second potential (VDD), and the third potential (VSS2) is supplied from the second low potential line 48 which is the third potential line.

In Example 2, the first transistor 31A, the light-emitting element 20, and the fourth transistor 34A were arranged in series between the second potential line (high potential line 47) and the third potential line (second low potential line 48). between. As in the first embodiment, the memory circuit 60 is arranged between the first potential line (first low potential line 46) and the second potential line (high potential line 47). The second transistor 32A is disposed between the memory circuit 60 and the signal line 43. The complementary second transistor 38A is disposed between the memory circuit 60 and the complementary signal line 45.

The gate of the first transistor 31A is electrically connected to the output terminal 27 of the second inverter 62 of the memory circuit 60. The source of the first transistor 31A is electrically connected to a second potential line (high potential line 47). The drain of the first transistor 31A is electrically connected to the anode 21 of the light-emitting element 20. The gate of the fourth transistor 34A is electrically connected to the control line 44. The source of the fourth transistor 34A is electrically connected to a third potential line (second low potential line 48). The drain of the fourth transistor 34A is electrically connected to the cathode 23 of the light emitting element 20.

In the pixel circuit 71 of the second embodiment, the first transistor 31A and the fourth transistor 34A have opposite characteristics. The first transistor 31A of the P type is disposed on the high potential side with respect to the light emitting element 20, and the fourth transistor 34A of the N type is disposed on the low potential side with respect to the light emitting element 20. The light emitting element 20 can emit light when the fourth transistor 34A and the first transistor 31A are in an on state. When the first transistor 31A and the fourth transistor 34A are turned on, the third potential is reached from the second potential line (high potential line 47) via the first transistor 31A, the light-emitting element 20, and the fourth transistor 34A. The path of the line (second low-potential line 48) is turned on, and a current flows through the light-emitting element 20.

In the second embodiment (the variation of Embodiment 2 and below), the potential of the output terminal 25 of the first inverter 61 in the memory circuit 60 is High (the output terminal 27 of the second inverter 62 When the potential is Low), the light-emitting element 20 is capable of emitting light, and when the potential of the output terminal 25 of the first inverter 61 is Low (when the potential of the output terminal 27 of the second inverter 62 is High) ), The light emitting element 20 does not emit light.

[Relationship Between Each Potential and Threshold Voltage of Transistor] In the second embodiment (a variation of Example 2 and below), a low-voltage power source is also composed of the first potential (V1) and the second potential (V2). The third potential (V3) and the second potential (V2) constitute a high-voltage system power source. The potential difference (V2-V1 = 7.0 V-4.0 V = 3.0 V) of the second potential (V2) with respect to the first potential (V1) of the low-voltage power source is smaller than the second potential (2 of the high-voltage power source) ) Potential difference from the third potential (V3) (V2-V3 = 7.0 V-0 V = 7.0 V) (V2-V1 <V2-V3).

In the second embodiment, the driving circuit 51 or the memory circuit 60 is driven at a low voltage of V2-V1 = 3.0 V by the low voltage system power supply, so that the driving circuit 51 or the memory circuit 60 can be operated at high speed. In addition, since the light-emitting element 20 emits light with a high voltage of V2-V3 = 7.0 V by a high-voltage power source, the light-emitting element 20 can emit light with high brightness. Furthermore, the first transistor 31A or the fourth transistor 34A arranged in series with the light-emitting element 20 can be linearly operated to apply most of the high voltage of V2-V3 = 7.0 V to the light-emitting element 20, which can further increase the voltage. Brightness when the light emitting element 20 emits light.

In the second embodiment, the two inverters 61 and 62 constituting the memory circuit 60 are arranged between the first potential line (the first low potential line 46) and the second potential line (the high potential line 47). The two inverters 61 and 62 supply VSS1 as a first potential and VDD as a second potential. Therefore, Low corresponds to the first potential (VSS1), and High corresponds to the second potential (VDD).

In this embodiment, the threshold voltage (V _th1 ) of the first transistor 31A which is the driving transistor is negative (V _th1 <0). When the image signal stored in the memory circuit 60 corresponds to non-light emission, the potential of the output terminal 27 of the memory circuit 60 is High (second potential). The source of the first transistor 31A is connected to the second potential line (high potential line 47), so the source potential is the second potential (VDD), and the gate-source voltage V _gs1 of the first transistor 31A is 0. V.

Therefore, if with respect to the threshold voltage V _th1 of the first transistor 31A of the (as an example V _th1 = -0.36 V), the gate-source voltage V _GS1 0 V, the since the gate-source voltage V _GS1 is greater than the threshold voltage V _th1 , the first transistor 31A is in an off state. Thereby, when the image signal is non-emission, the first transistor 31A can be surely turned off.

When the image signal stored in the memory circuit 60 corresponds to light emission, the potential of the output terminal 27 of the memory circuit 60 is Low (first potential). Since the source potential of the first transistor 31A is the second potential, the gate-source voltage V _gs1 of the first transistor 31A is the potential difference between the first potential (V1) and the second potential (V2) (V _gs1 = V1-V2 = 4.0 V-7.0 V = -3.0 V). Therefore, since the gate-source voltage V _{gs1 of the} first transistor 31A is smaller than the threshold voltage V _th1 , the first transistor 31A is turned on. Thereby, when the image signal emits light, the first transistor 31A can be reliably turned on.

In the second embodiment, also in the first period (non-display period), a non-enable signal is supplied as a control signal to all control lines 44 and the fourth transistor 34A is in an off state, so the light-emitting element 20 is non-light-emitting. status. When the selection signal is supplied to any one of the scanning lines 42 as a scanning signal in the first period, the selected second transistor 32A and the complementary second transistor 38A are turned on, and the image signal is confident. The number line 43 and the complementary signal line 45 are written into the memory circuit 60.

In the second period (display period), the enable signal is supplied as a control signal to all the control lines 44 and the fourth transistor 34A is in an on state, so the light emitting element 20 is in a state capable of emitting light. In the second period, a non-selection signal in which the second transistor 32A is turned off is supplied to all the scanning lines 42 as a scanning signal. In this way, in the second embodiment, the first period (non-display period) and the second period (display period) can also be controlled independently, so gray-scale display of digital time division driving can be performed.

In the second embodiment (Example 2), since the fourth transistor 34A is an N-type, the control signal (enable signal) in the enabled state is high, and the control signal (non-enabled signal) in the non-enabled state is low. . Specifically, the non-enable signal is set to a low potential that is equal to or lower than the third potential (V3), and is preferably the third potential (V3). The enable signal is set to a high potential of V3 + (V2-V1) or higher, and preferably the second potential (V2).

When the non-enabled signal of the third potential (V3) is supplied from the control line 44 to the gate of the fourth transistor 34A, the source potential and the gate potential of the fourth transistor 34A are both the third potential (V3) Therefore, the gate-source voltage V _gs4 of the fourth transistor 34A is 0 V. If the threshold voltage V _{th4 of the} N-type fourth transistor 34A is _set (as an example, V _th4 = 0.36 V), since the gate-source voltage V _{gs4 of} the fourth transistor 34A is smaller than the threshold voltage V _th4 , the fourth The transistor 34A is turned off. Therefore, when the control signal is a non-enable signal, the fourth transistor 34A can be reliably turned off.

When the enable signal from the control line 44 is supplied above V3 + (V2-V1), that is, a potential of 0 V + (7.0 V-4.0 V) = 3.0 V or more, the gate-source voltage V _gs4 of the fourth transistor 34A is 3.0 -0 V = 3.0 V or more. Therefore, since the gate-source voltage V _{gs4 of} the fourth transistor 34A is sufficiently larger than the threshold voltage V _th4 , the fourth transistor 34A can be reliably turned on when the control signal is an enable signal.

In addition, the higher the potential of the enable signal, the larger the gate-source voltage V _{gs4 of} the fourth transistor 34A. If the potential of the enable signal is set to the second potential (V2), the gate-source voltage V _gs4 of the fourth transistor 34A is V2-V3 = 7.0 V-0 V = 7.0 V. Since the on-resistance of the fourth transistor 34A is reduced, the light-emitting element 20 is less likely to be affected by the threshold voltage difference of the fourth transistor 34A when it emits light.

In addition, the second transistor 32A, which is the selection transistor, is turned off when the scanning line 42 electrically connected to the gate is supplied as a scanning signal to the non-selection signal, and is turned on when the selection signal is supplied. In the second embodiment, since the second transistor 32A is a P-type, as described above, the non-selection signal is set to a high potential higher than the second potential (V2), and preferably the second potential (V2). The selection signal is set to a low potential below the first potential (V1), and is preferably a third potential (V3).

In the second embodiment, it is also preferable that the first transistor 31A and the second transistor 32A have the same polarity. In the second embodiment, the first transistor 31A and the second transistor 32A are both P-type. Therefore, the first transistor 31A is turned on when the potential of the image signal supplied to the gate is Low, and the second transistor 32A is turned on when the scanning signal supplied to the gate is the selection signal (Low). . The Low of the image signal is the first potential (V1), but the selection signal (Low) is set to the first potential (V1) or less, and preferably the third potential (V3).

The case where the potential of the selection signal is set to the third potential (V3) and the image signal of the memory circuit 60 is overwritten from High to Low will be described. The input terminal 28 of the second inverter 62 (= the output terminal 25 of the first inverter 61) electrically connected to one of the source and drain terminals of the second transistor 32A is High before the image signal is overwritten. The second potential (V2). When the self-scanning line 42 supplies the selection signal of the third potential (V3) to the gate of the second transistor 32A, the gate-source voltage V _gs2 of the second transistor 32A is V3-V2 = 0 V-7.0 V = -7.0 V. Since the threshold voltage V _{th2 of} the second transistor 32A is lower than V _th2 (for example, V _th2 = -0.36 V), the second transistor 32A is turned on.

By writing the image signal of Low (V1) to the memory circuit 60 from the signal line 43, the potential of the input terminal 28 of the second inverter 62 gradually decreases from High (V2) to Low (V1), but is accompanied by Therefore, the absolute value of the gate-source voltage V _gs2 of the second transistor 32A gradually decreases until V3-V2 = 0 V-4.0 V = -4.0 V. Even if the gate-source voltage V _{gs2 of} the second transistor 32A is the highest (near zero) of -4.0 V, the gate-source voltage V _{gs2 is} sufficiently lower than the threshold voltage V _{th2 of} the second transistor 32A. Therefore, since the on-resistance of the second transistor 32A is kept low before the image signal is written into the memory circuit 60, the image signal is surely written into the memory circuit 60.

Here, a case is assumed in which the second transistor 32A is an N-type having the characteristics opposite to those of the first transistor 31A (it is assumed to be the second transistor 32). In this case, the second transistor 32 is turned on when the selection signal is High. When the potential of the selection signal is set to the second potential (V2) and the image signal of the memory circuit 60 is overwritten from Low to High, when the selection signal of the second potential (V2) is supplied from the scanning line 42, The gate-source voltage V _gs2 of the second transistor 32 is V2-V1 = 7.0 V-4.0 V = 3.0 V, which is higher than the threshold voltage V _{th2 of} the second transistor 32 (as an example, V _th2 = 0.36 V), Therefore, the second transistor 32 is turned on.

The image signal of High (V2) is written into the memory circuit 60 through the signal line 43. The potential of the input terminal 28 of the second inverter 62 gradually rises from Low (V1). With this, the second transistor The gate-source voltage V _{gs2 of} 32 gradually decreases from 3.0 V, and reaches the threshold voltage V _th2 (for example, 0.36 V) of the N-type second transistor 32 before the potential of the input terminal 28 reaches the second potential (V2). , Causing the second transistor 32 to be turned off.

In addition, before the second transistor 32 is turned off, the gate-source voltage V _gs2 decreases and approaches the threshold voltage V _th2 . With this, the on-resistance of the second transistor 32 increases, so that it is applied to the memory circuit 60. Writing image signals takes time, or overwriting fails. In order to avoid this, the potential of the selection signal may be set to a lower potential, but in this case, a potential line different from the existing potential is further required.

As in this embodiment, if the first transistor 31A and the second transistor 32A are of the same polarity of the P type, the potential of the selection signal can be set to the third potential that is the lowest between the third potential and the second potential. There is no need to set a new ground potential setting. In addition, when the second transistor 32A is turned on and the image signal is written to the memory circuit 60, the gate-source voltage V _{gs2 of} the second transistor 32A can be increased. The writing of the image signal rises, and the on-resistance of the second transistor 32A can also be kept low. This makes it possible to write or overwrite the image signal to the memory circuit 60 at high speed and reliably.

Therefore, according to the configuration of the pixel circuit 71 of Example 2 of the second embodiment, it is possible to display a high-resolution image with high resolution and multiple gray levels with low power consumption, and operate at a higher speed and obtain a brighter display.的 电 装置 10。 The photovoltaic device 10.

Hereinafter, a modification of the configuration of the pixel circuit according to the second embodiment will be described. In the description of the following modified examples, differences from the second embodiment or the above-mentioned modified examples are described. For the same constituent elements as those of the second embodiment or the modified examples, the same symbols are attached to the drawings, and descriptions thereof are omitted.

(Modification 4) Next, a pixel circuit according to a modification (Modification 4) of the second embodiment will be described. FIG. 16 is a diagram illustrating a configuration of a pixel circuit according to a fourth modification. As shown in FIG. 16, the pixel circuit 71A of the modification 4 is different from the pixel circuit 71 of the embodiment 2 in that the fourth transistor 34 is a P-type and is disposed between the first transistor 31A and the light-emitting element 20. The other components are the same.

The pixel circuit 71A of the fourth modification includes a P-type first transistor 31A, a P-type fourth transistor 34, a light-emitting element 20, a memory circuit 60, a P-type second transistor 32A, and a P-type complementary transistor. 2 transistor 38A. The drain of the first transistor 31A is electrically connected to the source of the fourth transistor 34. The drain of the fourth transistor 34 is electrically connected to the anode 21 of the light emitting element 20. That is, in the pixel circuit 71A of the modification 4, the P-type fourth transistor 34 is disposed on the high-potential side with respect to the light-emitting element 20, and the P-type first transistor 31A is disposed with respect to the fourth transistor 34. High potential side.

In the modification 4, since the fourth transistor 34 is a P-type, the potential of the non-enabled signal is set to the second potential (V2) of the high potential, and the potential of the enabled signal is set to the third potential (V3) of the low potential. ). When the enable signal is supplied to the control line 44 so that the gate potential of the fourth transistor 34 becomes the same potential as the third potential, the fourth transistor 34 is turned on. When the first transistor 31A and the fourth transistor 34 are turned on, the third potential is reached from the second potential line (high potential line 47) via the first transistor 31A, the fourth transistor 34, and the light-emitting element 20. The path of the line (second low-potential line 48) is turned on, and a current flows through the light-emitting element 20.

In the modification 4, a first transistor 31A is arranged between the fourth transistor 34 and the second potential line (high potential line 47). Therefore, when the fourth transistor 34 is turned on, the source potential of the fourth transistor 34 is slightly lower than the second potential (V2). However, by operating the first transistor 31A in a linear manner, the source potential of the fourth transistor 34 can be made substantially equal to the second potential.

Therefore, the gate-source voltage _{Vgs4 of} the fourth transistor 34 and the potential difference (V3-V2 = -7.0 V) of the third potential (V3) with respect to the second potential (V2) are approximately equal, since it is smaller than that of the P-type Since the threshold voltage V _{th4 of the} fourth transistor 34 (V _th4 = −0.36 V), the fourth transistor 34 is surely turned on. In addition, since the gate-source voltage V _gs4 of the fourth transistor 34 in the on state is sufficiently smaller than the threshold voltage V _th4 , the fourth transistor 34 can be _operated linearly.

(Modification 5) Next, a pixel circuit according to a modification (Modification 5) of the second embodiment will be described. FIG. 17 is a diagram illustrating a configuration of a pixel circuit according to a fifth modification. As shown in FIG. 17, the pixel circuit 71B of the fifth modification differs from the pixel circuit 71A of the fourth modification in that the first transistor 31A is disposed between the fourth transistor 34 and the light-emitting element 20, and the other structures are the same. .

The pixel circuit 71B of the fifth modification includes a P-type fourth transistor 34, a P-type first transistor 31A, a light-emitting element 20, a memory circuit 60, a P-type second transistor 32A, and a P-type complementary transistor. 2 transistor 38A. The source of the fourth transistor 34 is electrically connected to the second potential line (high potential line 47). The source of the first transistor 31A is electrically connected to the drain of the fourth transistor 34, and the drain of the first transistor 31A is electrically connected to the anode 21 of the light-emitting element 20. That is, in the pixel circuit 71B of the modification 5, the P-type first transistor 31A is disposed on a higher potential side than the light-emitting element 20, and the P-type fourth transistor 34 is disposed more than the first transistor 31A. It is closer to the high potential side.

In Modification 5, a fourth transistor 34 is arranged between the first transistor 31A and the second potential line (high potential line 47). Therefore, when the first transistor 31A is turned on, the source potential of the first transistor 31A is slightly lower than the second potential (V2). However, by operating the fourth transistor 34 linearly, the source potential of the first transistor 31A can be made substantially equal to the second potential. Therefore, the gate-source voltage V _gs1 of the first transistor 31A and the potential difference (V1-V2 = -3 V) of the first potential (V1) with respect to the second potential (V2) are approximately equal, so that the first The single transistor 31A is turned on and is operated in a linear shape.

(Modification 6) Next, a pixel circuit according to a modification (Modification 6) of the second embodiment will be described. FIG. 18 is a diagram illustrating a configuration of a pixel circuit according to a modification 6. FIG. As shown in FIG. 18, the pixel circuit 71C of the modification 6 is different from the above-mentioned embodiment 2 and the modification in that the fourth transistor 34 (or the fourth transistor 34A) is not provided, and the other components are the same.

The pixel circuit 71C of the modification 6 includes a light-emitting element 20, a P-type first transistor 31A, a memory circuit 60, a P-type second transistor 32A, and a P-type complementary second transistor 38A. The source of the first transistor 31A is electrically connected to the second potential line (high potential line 47), and the drain of the first transistor 31A is electrically connected to the anode 21 of the light emitting element 20. The cathode 23 of the light emitting element 20 is electrically connected to a third potential line (second low potential line 48).

In the pixel circuit 71C of the modification 6, a first transistor 31A and a light-emitting element 20 are arranged in series between a second potential line (high potential line 47) and a third potential line (second low potential line 48). . Therefore, when the potential of the output terminal 27 of the memory circuit 60 is Low (first potential) and the first transistor 31A is on, the light-emitting element 20 emits light. In the modification 6, as in the second embodiment and the modification, the brightness of the light-emitting element 20 when it emits light can be increased, and the threshold voltage V _th1 of the first transistor 31A with respect to the light-emitting brightness of the light-emitting element 20 can be substantially excluded. Difference.

In addition, since the control line 44 is not required in the pixel circuit 71C of the modification 6, the number of wirings can be reduced and the number of wiring layers can also be reduced. Therefore, compared with the said Example and the modification, a manufacturing man-hour can be reduced or a manufacturing yield can be improved. In addition, since the light-shielding area can be reduced by reducing the number of wirings having light-shielding properties, high resolution (micronization of pixels) can be achieved.

(Third Embodiment) Next, the structure of a photovoltaic device according to a third embodiment will be described. FIG. 19 is a circuit block diagram of a photovoltaic device according to a third embodiment of the present invention, and FIG. 20 is a diagram illustrating a pixel structure of the third embodiment of the present invention. FIG. 21 is a diagram illustrating the structure of a pixel circuit according to a third embodiment of the present invention.

As shown in FIG. 19, in this embodiment, the signal line driving circuit 53 is synchronized with the selection of the scanning lines 42 and supplies an image signal (Data) to each of the N signal lines 43. However, in this embodiment, unlike the first embodiment and the second embodiment, the signal line driving circuit 53 does not output a complementary image signal. Therefore, as shown in FIG. 20, although the image signal (Data) is supplied to the pixel circuit 81, a complementary image signal is not supplied. Therefore, as illustrated in FIG. 21, in the pixel circuit 81, for example, an image signal (Data) is supplied to the gate of the P-type first transistor 31A through the second transistor 32A and the memory circuit 60, and the The control signal Enb is supplied to the P-type fourth transistor 34 of the gate, and controls the energization of the light-emitting element 20.

In the present embodiment, it is configured based on the second embodiment in which the first low potential VSS1, the second low potential VSS2, and the high potential VDD are supplied to the driving portion 50, but the first high potential may be supplied to the driving portion 50. VDD1, the second high potential VDD2, and the low potential VSS are configured based on the first embodiment.

The above-mentioned embodiments (examples and modifications) are always those who disclose one aspect of the present invention, and can be arbitrarily changed and applied within the scope of the present invention. As a modification other than the above, for example, the following may be considered.

(Modification 7) In the pixel circuit of the above-mentioned embodiment (examples and modifications), the gate of the first transistor 31 (or the first transistor 31A) is electrically connected to the second of the memory circuit 60. The output terminal 27 of the inverter 62 is not limited to this embodiment. The gate of the first transistor 31 (or the first transistor 31A) may be configured to be electrically connected to the output terminal 25 of the first inverter 61 of the memory circuit 60.

(Modification 8) In the pixel circuit of the above-mentioned embodiment (embodiment and modification), the second transistor 32 is arranged at the input terminal 28 (= the first inverter of the second inverter 62 of the memory circuit 60) Between the output terminal 25 of the phase inverter 61) and the signal line 43, a complementary second transistor 38 is arranged at the input terminal 26 of the first inverter 61 of the memory circuit 60 (= output terminal 27 of the second inverter 62) And the complementary signal line 45, the present invention is not limited to this form. The second transistor 32 may be arranged between the input terminal 26 of the first inverter 61 (= the output terminal 27 of the second inverter 62) and the signal line 43, and the complementary second transistor 38 may be arranged at the first The input terminal 28 (= the output terminal 25 of the first inverter 61) of the two inverter 62 and the complementary signal line 45.

(Modification 9) In the pixel circuit of the above-mentioned embodiments (examples and modifications), the memory circuit 60 includes two inverters 61 and 62, but the present invention is not limited to this embodiment. The memory circuit 60 may be configured to include two or more even-numbered inverters.

(Modification 10) In the above-mentioned embodiments (examples and modifications), as the optoelectronic device, the element substrate 11 including a single crystal semiconductor substrate (single crystal silicon substrate) is arranged in 720 rows × 3840 (1280 × 3 The organic EL device including the light-emitting element 20 of the organic EL element has been described as an example, but the photovoltaic device of the present invention is not limited to this form. For example, a photovoltaic device may have a structure in which a thin film transistor (TFT) is formed on the element substrate 11 including a glass substrate as each transistor, and may be formed on a flexible substrate including polyimide or the like. Structure of thin film transistor. In addition, the optoelectronic device may be a micro LED display in which fine LED elements are arranged at a high density as a light emitting element, or a quantum dot display using a nano-scale semiconductor crystal material for the light emitting element. In addition, as the color filter, a quantum dot that converts incident light into light of another wavelength may be used.

(Modification 11) In the embodiment described above, as the electronic device, the see-through type head-mounted display 100 incorporating the photoelectric device 10 was described as an example, but the photoelectric device 10 of the present invention can also be applied to Enclosed head-mounted displays are other electronic devices represented. Examples of other electronic devices include a projector, a rear projection television, a direct-view television, a mobile phone, a mobile audio device, a personal computer, a video camera monitor, a car navigation device, a head-up display, a pager, and an electronic notebook. , Calculators, watches and other wearable machines, handheld displays, word processors, workstations, video phones, POS terminals, digital still cameras, electronic sign displays, etc.

10 Photoelectric device 11 Element substrate 12 Protective substrate 13 External connection terminal 20 Light-emitting element 21 Anode 22 Light-emitting portion 23 Cathode 25 Output terminal 26 Input terminal 27 Output terminal 28 Input terminal 31 First transistor 31A First transistor 32 Second transistor Crystal 32A 2nd transistor 33 3rd transistor 34 4th transistor 34A 4th transistor 35 5th transistor 36 6th transistor 37 7th transistor 38 complementary 2nd transistor 38A complementary 2nd transistor 41 pixel circuit 41A pixel circuit 41B pixel circuit 41C pixel circuit 42 scanning line 43 signal line 44 control line 45 complementary signal line 46 low potential line (second potential line ) 47 First high potential line (first potential line) 48 Second low potential line (third potential line) 49 Second high potential line (third potential line) 50 Drive section 51 Drive circuit 52 Scan line drive circuit 53 Signal Line drive circuit 54 Control line driving circuit 55 Control device 56 Display signal supply circuit 57 VRAM circuit 58 Sub-pixel 58B Sub-pixel 58G Sub-pixel 58R Sub-pixel 59 Pixel 60 Memory circuit 61 First inverter 62 Second inverter 71 Pixel circuit 71A Pixel Circuit 71B Pixel circuit 71C Pixel circuit 81 Pixel circuit 100 Head-mounted display (electronic device) 101 Perspective member 102 Frame 103a First optical section 103b 2nd optical part 105a 1st built-in device part 105b 2nd built-in device part 110 部 110e upper surface 110s body part 111 1st part 112 2nd part 130 projection lens 131 lens 132 lens 133 lens 150 light for imaging Transmissive member 151 First display device 152 Second display device 161 Frame 161e Lower surface 162 Lens tube 170 Projection perspective device a Sub-pixel row direction (X direction) Length b Sub-pixel row direction ( Y direction) Length D Non-display area Data Image signal Data1 ～ Data N Image signal Data j ～ Data j + 3 Image signal E Display area Enb Control signal Enb i Control signal Enb 1 ～ Enb M Control signal EY Eye F field GL image light P1-1 ～ P1-6 non-display period P2-1 ～ P2-6 display period S11 first surface S12 second surface S13 third surface S14 fourth surface S15 fifth surface Scan Scan signal Scan 1 ～ Scan M Scan signal Scan i Scan i + 1 Scan signal SF1 ～ SF6 Secondary field VDD high potential VDD1 first high potential VDD2 second high potential VSS low potential VSS1 first low potential VSS2 second low potential XData complementary image signals XData 1 to XData N complementary image signals XData j to XData j + 2 complementary Image signal X direction Y direction Z direction

FIG. 1 is a diagram illustrating the outline of an electronic device according to this embodiment. FIG. 2 is a diagram illustrating the internal structure of the electronic device of this embodiment. FIG. 3 is a diagram illustrating an optical system of an electronic device according to this embodiment. FIG. 4 is a schematic plan view showing the structure of the photovoltaic device of this embodiment. FIG. 5 is a circuit block diagram of the photovoltaic device of this embodiment. FIG. 6 is a diagram illustrating the structure of a pixel in this embodiment. FIG. 7 is a diagram illustrating digital driving of the photovoltaic device according to this embodiment. FIG. 8 is a diagram illustrating the structure of a pixel circuit of the first embodiment. FIG. 9 is a diagram illustrating a driving method of a pixel circuit in this embodiment. FIG. 10 is a diagram illustrating a configuration of a pixel circuit according to a first modification. FIG. 11 is a diagram illustrating a configuration of a pixel circuit according to a second modification. FIG. 12 is a diagram illustrating a configuration of a pixel circuit according to a third modification. Fig. 13 is a circuit block diagram of a photovoltaic device according to a second embodiment of the present invention. FIG. 14 is a diagram illustrating a pixel structure according to a second embodiment of the present invention. FIG. 15 is a diagram illustrating the structure of a pixel circuit of the second embodiment. FIG. 16 is a diagram illustrating a configuration of a pixel circuit according to a fourth modification. FIG. 17 is a diagram illustrating a configuration of a pixel circuit according to a fifth modification. FIG. 18 is a diagram illustrating a configuration of a pixel circuit according to a modification 6. FIG. Fig. 19 is a circuit block diagram of a photovoltaic device according to a third embodiment of the present invention. FIG. 20 is a diagram illustrating a pixel structure according to a third embodiment of the present invention. FIG. 21 is a diagram illustrating the structure of a pixel circuit according to a third embodiment of the present invention.

Claims (22)

An optoelectronic device includes a scanning line, a signal line, a pixel circuit provided corresponding to the intersection of the scanning line and the signal line, a first potential line to which a first potential is supplied, and a second potential to which a second potential is supplied. A second potential line and a third potential line supplied with a third potential; the pixel circuit includes a light-emitting element, a memory circuit disposed between the first potential line and the second potential line, and a gate electrically connected to the above The first transistor of the memory circuit and the second transistor whose gate is electrically connected to the scanning line; and the second transistor is disposed between the memory circuit and the signal line; the light-emitting element and the first transistor The crystal is arranged in series between the second potential line and the third potential line. The absolute value of the potential difference between the first potential and the second potential is smaller than the absolute value of the potential difference between the third potential and the second potential. . The optoelectronic device according to claim 1, wherein the memory circuit includes a third transistor; and a gate length of the third transistor is shorter than a gate length of the first transistor. The photovoltaic device according to claim 2, wherein the area of the channel formation region of the third transistor is smaller than the area of the channel formation region of the first transistor. For example, the photovoltaic device of claim 1, wherein the source of the first transistor is electrically connected to the second potential line; and the light-emitting element is arranged between the drain of the first transistor and the third potential line. . The photovoltaic device according to claim 1, wherein the on-resistance of the first transistor is sufficiently lower than the on-resistance of the light-emitting element. The photovoltaic device according to claim 1, wherein the first transistor and the second transistor have the same polarity. For example, the optoelectronic device of claim 1 includes a control line; and the pixel circuit includes a fourth transistor whose gate is electrically connected to the control line; the light-emitting element, the first transistor, and the fourth transistor are connected in series. It is arranged between the second potential line and the third potential line. The photovoltaic device according to claim 7, wherein the drain of the fourth transistor is electrically connected to the light-emitting element. The photovoltaic device according to claim 7, wherein the on-resistance of the fourth transistor is sufficiently lower than the on-resistance of the light-emitting element. The photovoltaic device according to claim 7, wherein the first transistor and the fourth transistor have opposite polarities. The optoelectronic device according to claim 7, wherein when the second transistor is in an on state, the fourth transistor is in an off state. The optoelectronic device according to claim 7, wherein during the first period in which a selection signal for setting the second transistor to the on state is supplied to any one of the scanning lines, the fourth transistor is provided to the control line. It is a non-enabled signal in the OFF state. For example, in the optoelectronic device of claim 12, during the second period during which the enable signal for turning the fourth transistor to the on state is supplied to the control line, the second transistor is turned off when the scan line is supplied. Is not a selection signal. For example, the optoelectronic device of claim 13, wherein the first transistor is an N-type and the fourth transistor is a P-type; set the first potential to V1, the second potential to V2, and the third When the potential is set to V3, the potential of the enable signal supplied to the control line is V3- (V1-V2) or less. The photovoltaic device according to claim 14, wherein the potential of the enable signal is the second potential. The photovoltaic device according to claim 14, wherein the first transistor and the second transistor are both N-type; and the potential of the selection signal supplied to the scanning line is equal to or higher than the first potential. The photovoltaic device according to claim 16, wherein the potential of the selection signal is the third potential. For example, the photovoltaic device of claim 13, wherein the first transistor is a P-type and the fourth transistor is an N-type; the first potential is set to V1, the second potential is set to V2, and the third When the potential is set to V3, the potential of the enable signal supplied to the control line is V3 + (V2-V1) or more. The photovoltaic device according to claim 18, wherein the potential of the enabling signal is the second potential. For example, the photovoltaic device of claim 18, wherein the first transistor and the second transistor are both P-type; and the potential of the selection signal supplied to the scanning line is equal to or lower than the first potential. The photovoltaic device according to claim 20, wherein the potential of the selection signal is the third potential. An electronic device including the photoelectric device according to any one of claims 1 to 21.