TWI668696B - Detecting methods and memory devices - Google Patents

Abstract

A detection method is used for detecting a flash memory array, and the flash memory array includes a complex digital element line and a complex bit line to a source line. The detection method includes: performing a first detection procedure. The first detection procedure includes: applying a first positive voltage to the P-type well of the flash memory array; applying a ground voltage to all of the word lines; floating the bit line and the source line; determining flowing through the P-well Whether the leakage current exceeds the leakage threshold; and when the leakage current exceeds the leakage threshold, determining that at least one of the word lines is shorted to at least one of the bit lines or the source line.

Description

Detection method and memory device

The present invention is directed to a method of detecting an error in a non-gate flash memory.

Non-gate flash memory uses ECC to correct read errors of certain bits. However, defects in some processes, such as short-circuiting of word lines and bit lines or shorting of word lines and source lines, can cause The entire memory array is erased, causing read errors or write errors, and even data cannot be recovered using ECC.

Therefore, we need to detect the defects of the flash memory array. The defects of the flash memory array are short between the word line and the bit line or the word line and the source line. In addition, a special reading method is also required to read the data stored in the damaged word line. Since the corrupted array cannot be erased, a special reading method can be used to move the data stored in the corrupted array to a redundant array or other array for storage.

In view of the above, the present invention provides a detection method for detecting a flash memory array, wherein the flash memory array includes a complex digital element line and a complex bit line to a source line, including: a first detecting procedure, wherein the first detecting process comprises: applying a first positive voltage to one of the P-type wells of the flash memory array; applying a ground voltage to all of the word lines; floating the above a bit line and the source line; determining a leakage through one of the P-type wells Whether the current exceeds a leakage threshold; and when the leakage current exceeds the leakage threshold, determining that at least one of the word lines is short-circuited to at least one of the bit lines or the source line.

According to an embodiment of the present invention, after the step of determining whether at least one of the word lines is short-circuited to at least one of the bit lines or the source line, the detecting method further comprises: performing a second a detecting program, wherein the second detecting process comprises: sequentially selecting one of the word lines as a selected word line; charging the selected word line to a second positive voltage by using a first fixed current Applying the ground voltage to all of the bit lines and the source lines; determining that the selected word line is at a high logic level or a low logic level; when the selected word line is located above Determining that the selected word line is not short-circuited to any one of the bit lines or the source line; and when the selected character line is located at the low logic level, determining the selection The word line is shorted to at least one of the bit lines or the source line.

According to an embodiment of the present invention, after the step of performing the second detecting process, the detecting method further includes: performing a third detecting process, wherein the third detecting process further comprises: utilizing a second Applying a third positive voltage to the selected word line such that the plurality of memory cells on the selected word line are non-conducting; floating all of the bit lines; applying the ground voltage to The source line is determined to be located at the high logic level or the low logic level; when the selected character line is located at the high logic level, determining that the selected word line is not Shorting to the source line; and when the selected word line is at the low logic level At this time, it is judged that the selected character line is short-circuited to the source line.

According to an embodiment of the present invention, after the step of performing the third detecting process, the detecting method further includes: performing a fourth detecting process, wherein the fourth detecting process comprises: placing a fourth positive Applying a voltage to the selected word line such that the plurality of memory cells on the selected word line are non-conducting; sequentially selecting one of the bit lines as a selected bit line, wherein the remaining ones The bit line is a plurality of unselected bit lines; the selected bit line is discharged to the ground voltage by a fourth fixed current; the source line and the unselected bit line are floated; and the selected bit is determined. The meta-line is located at the high logic level or the low logic level; when the selected bit line is at a high logic level, determining that the selected bit line is shorted to the selected word line; and when When the selected bit line is located at the low logic level, it is determined that the selected bit line is not shorted to the selected word line.

The invention further provides a memory device comprising: a flash memory array, a bias circuit, a sensing circuit and a controller. The flash memory array includes a complex digital line, a complex bit line, a source line, and a P-well. The bias circuit generates voltage and current of the flash memory array. The sensing circuit is configured to sense a logic level of the word line, the bit line, and the source line, and a leakage current of the P-type well. The controller selects one of the character lines and one of the bit lines and performs a detection method, wherein the detecting method includes a first detecting process, wherein the first detecting process includes: applying one a first positive voltage to the P-type well of the flash memory array; applying a ground voltage to all of the word lines; floating the bit line and the source line; and determining to flow through the P-type well Leakage current Whether the leakage threshold is exceeded; and when the leakage current exceeds the leakage threshold, determining whether at least one of the word lines is short-circuited to at least one of the bit lines or the source line.

According to an embodiment of the present invention, after the step of determining whether at least one of the word lines is short-circuited to at least one of the bit lines or the source line, the detecting method further includes a second detecting a program, wherein the second detecting process comprises: sequentially selecting one of the word lines as a selected word line; charging the selected word line to a second positive voltage by using a first fixed current; Applying the ground voltage to all of the bit lines and the source lines; determining that the selected word line is at a high logic level or a low logic level; when the selected word line is at the above height When the logic bit is on time, determining that the selected word line is not short-circuited to any one of the bit lines or the source line; and when the selected character line is located at the low logic level, determining the selected word The line is shorted to at least one of the bit lines or the source line.

According to an embodiment of the present invention, after the step of performing the second detecting process, the detecting method further includes a third detecting process, wherein the third detecting process further comprises: utilizing a second fixed current And applying a third positive voltage to the selected word line such that the plurality of memory cells on the selected word line are non-conducting; floating all of the bit lines; applying the ground voltage to the source a line of pixels; determining that the selected character line is located at the high logic level or the low logic level; and when the selected character line is located at the high logic level, determining that the selected word line is not shorted to The source line; and when the selected character line is located at the low logic level The selected word line is shorted to the source line.

According to an embodiment of the present invention, after the step of performing the third detecting process, the detecting method further includes a fourth detecting process, wherein the fourth detecting process comprises: applying a fourth positive voltage Up to the selected word line, such that the plurality of memory cells on the selected character line are non-conducting; one of the bit lines is sequentially selected as a selected bit line, wherein the remaining bits are The line system is a plurality of unselected bit lines; the selected bit line is discharged to the ground voltage by a fourth fixed current; the source line and the unselected bit line are floated; and the selected bit line is determined. Is located at the high logic level or the low logic level; when the selected bit line is at a high logic level, determining that the selected bit line is shorted to the selected word line; and when the above selection When the bit line is at the low logic level, it is determined that the selected bit line is not shorted to the selected word line.

100‧‧‧Flash memory device

200, 110, 810, 1010, 1210‧‧‧ flash memory array

120, 600, 820, 1020, 1220‧‧‧ bias circuit

130, 1230‧‧‧Sensor circuit

140‧‧‧ Controller

BL<0>, BL<1>, ..., BL<k>, ..., BL<n>, BL‧‧‧ bit lines

WL<0>, WL<1>, ..., WL<p>, ..., WL<m>, WL‧‧‧ character lines

SL‧‧‧ source line

201, 300‧‧‧ memory unit

310‧‧‧P type well

320‧‧‧First N-doped region

330‧‧‧Second N-doped region

340‧‧‧Third N-doped region

350‧‧ ‧ gate extreme

400‧‧‧Detection method

500‧‧‧First detection procedure

700‧‧‧Second detection procedure

900‧‧‧ third detection procedure

1100‧‧‧ Fourth detection procedure

610‧‧‧current mirror

620‧‧‧First current source

821‧‧‧second current source

822, 1022‧‧‧Restricted N-type transistors

1021‧‧‧ Third current source

1221‧‧‧ fourth current source

VP1‧‧‧ first positive voltage

VP2‧‧‧second positive voltage

VP3‧‧‧ third positive voltage

VB‧‧‧ bias voltage

VG‧‧‧ gate voltage

N1‧‧‧ first node

P1‧‧‧First P-type transistor

P2‧‧‧Second P-type transistor

S1‧‧‧ first output node

S2‧‧‧second output node

S3‧‧‧ third output node

I1‧‧‧First fixed current

I2‧‧‧Second fixed current

I3‧‧‧ third fixed current

I4‧‧‧fourth fixed current

S41~S44, S501~S506, S701~S708‧‧‧ Step procedure

S901~S908, S1101~S1111‧‧‧ Step procedure

1 is a block diagram of a flash memory device in accordance with an embodiment of the present invention.

2 is a circuit diagram showing a flash memory array according to an embodiment of the present invention.

Figure 3 is a cross-sectional view showing a flash memory cell in accordance with an embodiment of the present invention.

Figure 4 is a flow chart showing a method of detecting according to an embodiment of the present invention.

Figure 5 is a diagram showing a first detection procedure according to an embodiment of the present invention. Flow chart.

Figure 6 is a circuit diagram showing a bias circuit according to an embodiment of the present invention.

Figure 7 is a flow chart showing a second detection procedure according to an embodiment of the present invention.

Figure 8 is a diagram showing the detection of a flash memory array using a second detection procedure in accordance with an embodiment of the present invention.

Figure 9 is a flow chart showing a third detection procedure according to an embodiment of the present invention.

Figure 10 is a diagram showing the detection of a flash memory array using a third detection procedure in accordance with an embodiment of the present invention.

11A-11B are flowcharts showing a fourth detection procedure according to an embodiment of the present invention.

Figure 12 is a diagram showing the detection of a flash memory array by a fourth detection procedure according to an embodiment of the invention.

The following description is an embodiment of the present invention. The intent is to exemplify the general principles of the invention and should not be construed as limiting the scope of the invention, which is defined by the scope of the claims.

It is noted that the following disclosure may provide embodiments or examples for practicing various features of the present invention. The specific elements and arrangements of the elements described below are merely illustrative of the spirit of the invention and are not intended to limit the scope of the invention. In addition, the following description may reuse the same component symbols or characters in various examples. However, the purpose of reuse is only The simplifications and clarity of the description are not intended to limit the relationship between the various embodiments and/or configurations discussed below. In addition, the description of one of the features described in the following description is connected to, coupled to, and/or formed on another feature, etc., and may include a plurality of different embodiments, including direct contact of the features, or other additional Features are formed between the features and the like such that the features are not in direct contact.

1 is a block diagram of a flash memory device in accordance with an embodiment of the present invention. As shown in FIG. 1, the flash memory device 100 includes a flash memory array 110, a bias circuit 120, a sensing circuit 130, and a controller 140. The flash memory array 110 includes complex digital lines, negative bit source lines, source lines, and P-type wells, as will be described in detail in the following paragraphs.

In accordance with an embodiment of the present invention, the flash memory array 110 is a non-gate flash memory array. In accordance with other embodiments of the present invention, flash memory device 100 can have a plurality of flash memory arrays 110. In this FIG. 1, only one flash memory array 110 is explained for illustrative purposes, and is not limited thereto in any way.

The bias circuit 120 is configured to generate a voltage and a current supplied to the flash memory array 110, and the sensing circuit 130 senses the logic level and current of the word line, the bit line, the source line, and the P-well. .

2 is a circuit diagram showing a flash memory array according to an embodiment of the present invention. As shown in FIG. 2, the flash memory array 200 corresponds to the flash memory array 110 of FIG. 1, and includes a plurality of bit lines BL<0>, BL<1>, ..., BL<k>. ,..., BL<n>, complex digital element line WL<0>, WL<1>, ..., WL<p>, ..., WL<m> and source line SL, in which flash Memory array 200 includes an m x n flash memory unit.

According to an embodiment of the present invention, when the controller 140 of FIG. 1 selects the memory unit 201 of FIG. 2, the bias circuit 120 generates a corresponding voltage to the word line WL<1>, and the bit line BL< 2> and the source line SL, so that the sensing circuit 130 can read the data stored in the memory unit 201 and transmit the read data to the controller 140.

Figure 3 is a cross-sectional view showing a flash memory cell in accordance with an embodiment of the present invention. According to an embodiment of the present invention, the cross-sectional view of the flash memory array 110 is exemplified by the flash memory unit 300. As shown in FIG. 3, the flash memory cell 300 includes a P-type well 310, a first N-type doping region 320, a second N-type doping region 330, a third N-type doping region 340, and a gate terminal 350. . The second N-type doping region 330 and the third N-type doping region 340 are coupled to the source line SL, the first N-type doping region 320 is coupled to the bit line BL, and the gate terminal 350 is coupled to the Word line WL.

After performing a series of erase operations on the flash memory array, the bit line or source line may be shorted to the word line. Accordingly, the present invention proposes a method of detecting the defect.

Figure 4 is a flow chart showing a method of detecting according to an embodiment of the present invention. As shown in the detection method 400 of FIG. 4, the first detection process (step S41) is first performed to determine whether the flash memory array 110 has a defect. When it is determined that the flash memory array 110 has at least one defect, the second detection process is performed (step S42) to confirm which of the word lines the defect occurs.

Performing a third detection procedure (step S43) to confirm whether the source is The line is shorted to the damaged word line. Then, the fourth detection process is executed (step S44) to confirm which one of the bit lines is short-circuited to the damaged word line. The first detection procedure, the second detection procedure, the third detection procedure, and the fourth detection procedure are described in detail in the following paragraphs. According to an embodiment of the invention, the detecting method 400 may be terminated after step S41.

Figure 5 is a flow chart showing a first detection procedure according to an embodiment of the present invention. The following description of the first detection procedure 500 of FIG. 5 will be described in detail with reference to FIGS. 1-3. As shown in FIG. 5, the first detection process 500 corresponds to the step S41 of the detecting method 400 of FIG. 4, wherein the bias circuit 120 supplies the first positive voltage to the P-type of the flash memory array 110. Well 310 (as shown in Fig. 3) (step S501). The bias circuit 120 supplies the ground voltage to all of the word lines WL<0>, WL<1>, . . . , WL<p>, . . . , WL<m> of the flash memory array 110 (steps) S502), and floating all the bit lines BL<0>, BL<1>, . . . , BL<k>, . . . , BL<n> and the source line SL (step S503).

Next, the controller 140 determines whether the leakage current flowing through the P-well 310 exceeds the leakage threshold (step S504). When the leakage current exceeds the leakage threshold, the controller 140 determines the word lines WL<0>, WL<1>, . . . , WL<p>, . . . , WL< of the flash memory array 110. At least one of m> is short-circuited to at least one of bit line BL<0>, BL<1>, ..., BL<k>, ..., BL<n> or short-circuited to source line SL (Step S505). Then, after the first detection process 500 is terminated, step S42 is performed to further determine which of the word lines is shorted to at least one of the bit lines or shorted to the source line.

According to an embodiment of the present invention, returning to FIG. 3, the P-well 310 is biased to a first positive voltage, and in FIG. 3, all bit lines are taken as a bit line BL. BL<0>, BL<1>, ..., BL<k>, ..., BL<n> and source line SL are all floating, and in FIG. 3, the word line WL is taken as an example. All word lines WL<0>, WL<1>, ..., WL<p>, ..., WL<m> are biased to the ground voltage. When the controller 140 determines that the leakage current flowing through the P-type well 310 exceeds the leakage threshold, the bit line BL or the source line SL representing the third figure is short-circuited to the word line WL of FIG. 3 to generate a flow. Leakage current of P-type well 310.

When the controller 140 determines that at least one of the word lines is short-circuited to at least one of the bit lines and the source line, the process returns to step S504, and when the controller 140 determines that the leakage current does not exceed the leakage threshold, the controller is fast. The flash memory array 110 functions normally, and the detection method is terminated (step S506). After the first detection process 500, it is determined whether at least one of the word lines of the flash memory array 110 is shorted to at least one of the bit lines or the source line.

Figure 6 is a circuit diagram showing a bias circuit according to an embodiment of the present invention. As shown in FIG. 6, the bias circuit 600 corresponding to the bias circuit 120 of FIG. 1 includes a current mirror 610 and a first current source 620. The current mirror 610 is powered by the first positive voltage VP1 and coupled to the first node N1 and the first output node S1, wherein the current mirror 610 includes a first P-type transistor P1 coupled in the form of a diode and a first Two P-type transistors P2. The first node N1 is coupled to the P-well 310 of FIG.

The first current source 620 generates a first fixed current I1, wherein the first fixed current I1 is the leakage threshold of step S504 of FIG. According to an embodiment of the invention, when the leakage current flowing through the P-type well 310 of FIG. 3 exceeds the first fixed current I1, the first output node S1 is at a high logic level.

According to another embodiment of the present invention, when flowing through the P-type well of Figure 3 When the leakage current of 310 does not exceed the first fixed current I1, the first output node S1 is at a low logic level. Therefore, the controller 140 of FIG. 1 can determine whether the leakage current exceeds the leakage threshold based on the logic level of the first output node S1.

Figure 7 is a flow chart showing a second detection procedure according to an embodiment of the present invention. The following description of the second detection program 700 of FIG. 7 is provided in conjunction with FIGS. 1-3 for detailed description. As shown in FIG. 7, the second detection procedure 700 corresponds to step S42 of the detection method 400 of FIG. The controller 140 selects at least one of the word line WL<0>, WL<1>, . . . , WL<p>, . . . , WL<m> as the selected word line (step S701).

According to an embodiment of the present invention, the controller 140 may sequentially select one of the word line WL<0>, WL<1>, . . . , WL<p>, . . . , WL<m> as a selection. The word line. According to other embodiments of the present invention, the controller 140 may select one of the word lines WL<0>, WL<1>, . . . , WL<p>, . . . , WL<m> in any particular order. As the character line of choice.

When one of the word line WL<0>, WL<1>, . . . , WL<p>, . . . , WL<m> is selected, the bias circuit 120 selects the second fixed current. The word line is charged to the second positive voltage (step S702). The bias circuit 120 also applies a ground voltage to all of the bit lines BL<0>, BL<1>, . . . , BL<k>, . . . , BL<n>, and the source line SL (step S703). The controller 140 determines whether the selected character line is at a high logic level or a low logic level (step S704).

When it is determined that the selected character line is at a high logic level, the controller 140 determines that the selected word line is not shorted to the bit line BL<0>, BL<1>, ..., BL<k>, . .., BL<n> or source line SL (step S705). When it is determined that the selected character line is at a low logic level, the controller 140 Determining that the selected word line is short-circuited to at least one of the bit line BL<0>, BL<1>, . . . , BL<k>, . . . , BL<n> or the source line SL ( Step S706).

After step S705 and step S706, the controller 140 further determines whether the selected character line is a word line WL<0>, WL<1>, . . . , WL<p>, . . . , WL<m>. The last one (step S707). When the selected character line is not the last one of the word line WL<0>, WL<1>, . . . , WL<p>, . . . , WL<m>, the controller 140 selects the character. One of the lines WL<0>, WL<1>, . . . , WL<p>, . . . , WL<m> is selected as the word line (step S708), and the process returns to step S702. When the selected character line is the last one of the word line WL<0>, WL<1>, . . . , WL<p>, . . . , WL<m>, the controller 140 ends the second The program 700 is detected and the step S43 is started.

Figure 8 is a diagram showing the detection of a flash memory array using a second detection procedure in accordance with an embodiment of the present invention. As shown in FIG. 8, the flash memory array 810 is the same as the flash memory array 200 corresponding to the second image of the flash memory array 110 of FIG. 1, and the bias circuit 820 corresponds to the first The bias circuit 120 of the figure. In accordance with an embodiment of the present invention, bias circuit 820 can bias flash memory array 810 through an X decoder, which is not shown in FIG.

Bias circuit 820 includes a second current source 821 and a limiting N-type transistor 822. The second current source 822 generates a second fixed current I2 from the second positive voltage VP2, wherein the second fixed current I2 is used to charge the selected word line to the second positive voltage VP2. As shown in Fig. 8, the selected character line is exemplified by the word line WL<p>. The N-type transistor 822 is limited such that the bias voltage VB of the selected word line is not limited by the gate voltage VG. According to an embodiment of the present invention, when performing Figure 7 In the second detection procedure 700, the gate voltage VG exceeds the second positive voltage VP2 such that the bias voltage VB is not limited by the gate voltage VG.

The bias circuit 820 also applies a ground voltage to the bit lines BL<0>, BL<1>, . . . , BL<k>, . . . , BL<n>, and the source lines SL. According to an embodiment of the present invention, when the selected word line (Fig. 8 is taken as an example of the word line WL<p>), it is short-circuited to the bit line BL<0>, BL<1>, ..., At least one of BL<k>, . . . , BL<n>, and the second output node S2 is at a low logic level.

According to other embodiments of the present invention, when the selected word line (Fig. 8 is taken as an example of the word line WL<p>), it is not short-circuited to the bit line BL<0>, BL<1>, ... At least one of BL<k>, ..., BL<n> or the source line SL, and the second output node S2 is at a high logic level. Therefore, the controller 140 determines whether the selected word line is short-circuited to the bit line BL<0>, BL<1>, ..., BL<k>, .. according to the logic level of the second output node S2. At least one of BL<n> or source line SL.

Figure 9 is a flow chart showing a third detection procedure according to an embodiment of the present invention. The following description of the third detection procedure 900 of FIG. 9 will be combined with the first to third figures for detailed description. As shown in FIG. 9, the third detection procedure 900 corresponds to step S43 of the detection method 400 of FIG. 4, wherein the bias circuit 120 applies the third positive voltage to the selected word using the second fixed current. The element line (step S901), and the memory unit coupled to the selected word line is not turned on.

According to an embodiment of the invention, once the memory cells on the selected word line are turned on, the source line SL is shorted to the bit line shorted to the selected word line, causing an erroneous detection result. According to an embodiment of the present invention, the character line selected in step S901 is determined to be a loss in the second detection program 700. One of the ruined word lines. Therefore, the second detection procedure 700 is used to identify which character line is corrupted, so that the damaged word line can be directly selected in the third detection procedure 900.

Next, the bias circuit 120 floats all the bit lines BL<0>, BL<1>, . . . , BL<k>, . . . , BL<n> (step S902), and grounds the voltage It is coupled to the source line SL (step S903). The controller 140 determines that the selected character line is at a high logic level or a low logic level (step S904).

When the selected character line is at the high logic level, the controller 1440 determines that the selected word line is not shorted to the source line SL (step S905). When the selected character line is at the low logic level, the controller 140 determines that the selected character line is shorted to the source line SL (step S906).

After step S905 and step S906, the controller 140 determines whether the selected character line is the last one of the word lines determined to be corrupted in the second detection program 700 (step S907). The controller 140 ends the third detection procedure 900 when the selected character line is the last of the corrupted character lines. When the selected character line is not the last one of the damaged character lines, the controller 140 selects one of the damaged word lines as the selected character line (step S908), and returns to step S901.

In accordance with an embodiment of the present invention, when the selected character line is shorted to the source line SL, the data stored in the selected word line of the flash memory array 110 will be lost and cannot be recovered using ECC.

Figure 10 is a diagram showing the detection of a flash memory array using a third detection procedure in accordance with an embodiment of the present invention. As shown in FIG. 10, the flash memory array 1010 is connected to the flash memory array 110 of FIG. The flash memory 200 of FIG. 2 is the same, and the bias circuit 1020 corresponds to the bias circuit 120 of FIG. In accordance with an embodiment of the present invention, the bias circuit 1020 can bias the flash memory array 1010 through the X decoder, wherein the X decoder is not shown in FIG.

The bias circuit 1020 includes a third current source 1021 and a limiting N-type transistor 1022. The third current source 1022 generates a third fixed current I3 from the third positive voltage VP3, wherein the third current source 1022 charges the selected word line with the third fixed current I3. As shown in Fig. 10, the selected character line is exemplified by the word line WL<p>. The N-type transistor 1022 is limited to limit the bias voltage VB of the selected word line by the gate voltage VG.

According to an embodiment of the present invention, when the third detection procedure 900 of FIG. 9 is performed, the gate voltage VG is equal to the memory cell on the selected word line (ie, the memory on the word line WL<p>). The unit erases the threshold voltage and limits the sum of the threshold voltages of the N-type transistors 1022 such that the memory cells on the selected word line remain non-conductive.

The bias circuit 1020 applies a ground voltage to the source line SL, and floats all the bit lines BL<0>, BL<1>, . . . , BL<k>, . . . , BL<n> . According to an embodiment of the invention, when the selected word line (Fig. 10 is taken as an example of the word line WL<p>) is short-circuited to the source line SL, the third output node S3 is at a low logic level. .

According to another embodiment of the present invention, when the selected word line is not short-circuited to the ground voltage, the leakage current of the selected word line does not exceed the third fixed current I3, so that the third output node S3 is located at high logic. Level. Therefore, the controller 140 can determine the selected word line according to the logic level of the third output node S3. Is it shorted to the source line SL.

11A-11B are flowcharts showing a fourth detection procedure according to an embodiment of the present invention. The following description of the fourth detection program 1100 of the 11A, 11B drawings will be described in detail with reference to Figures 1-3. As shown in FIGS. 11A and 11B, the fourth detection program 1100 corresponds to step S44 of the detecting method 400 of FIG. 4, wherein the bias circuit 120 applies a fourth positive voltage to the selected word line (step S1101), and the memory cells on the selected character line are not turned on. In accordance with an embodiment of the present invention, the selected character line is one of the word lines that are determined to be corrupted by the second detection program 700.

The controller 140 selects one of the bit lines as the selected bit line (step S1102), wherein the remaining bit lines are unselected bit lines. According to an embodiment of the invention, the controller 140 sequentially selects one of the bit lines as the selected bit line. In accordance with another embodiment of the present invention, controller 140 selects one of the bit lines as the selected bit line in any particular order.

The bias circuit 120 discharges the selected bit line to the ground voltage using the fourth fixed current (step S1103), and floats the source line SL and the unselected bit line (step S1104). The controller 140 determines whether the selected bit line is a high logic level or a low logic level (step S1105).

When the selected bit line is on the high logic, the controller 140 determines that the selected bit line is shorted to the selected word line (step S1106). When the selected bit line is at the low logic level, the controller 140 determines that the selected bit line is not shorted to the selected word line (step S1107).

The controller 140 further determines whether the selected bit line is the last one of the bit line BL<0>, BL<1>, . . . , BL<k>, . . . , BL<n> (step S1108). When the selected bit line is not the last one of the bit line BL<0>, BL<1>, . . . , BL<k>, . . . , BL<n>, the controller 140 selects the bit element. One of the lines BL<0>, BL<1>, ..., BL<k>, ..., BL<n> is selected as the bit line (step S1109).

When the selected bit line is the last one of the bit line BL<0>, BL<1>, ..., BL<k>, ..., BL<n>, the controller 140 determines whether the selected character line is the last one of the word lines determined to be corrupted by the second detecting program 700 (step S1110). When the selected character line is not the last one of the damaged character lines, the controller 140 selects one of the damaged character lines (step S1111), and returns to step S1101. When the selected character line is the last one of the damaged character lines, the fourth detecting process 1100 is ended, and the detecting method 400 is also terminated.

Figure 12 is a diagram showing the detection of a flash memory array by a fourth detection procedure according to an embodiment of the invention. As shown in FIG. 12, the flash memory array 1210 is the same as the flash memory array 110 of FIG. 1 and the flash memory array 200 of FIG. 2, and the bias circuit 1220 corresponds to the first 1 bias circuit 120.

As shown in FIG. 12, the bias circuit 1220 includes a fourth current source 1221. The fourth current source 1221 discharges the selected bit line (in the twelfth figure, taking the bit line BL<k> as an example) to the ground voltage by using the fourth fixed current I4. When the selected word line is biased, any of the memory cells on the selected word line may not be turned on. According to an embodiment of the present invention, the bias circuit 1220 can bias the selected word line shown in FIG. 10, and the details are not repeated herein.

According to an embodiment of the invention, the source line SL may be floating. root According to another embodiment of the present invention, since the memory cells on the selected word line are all non-conductive, the source line SL can be grounded without affecting the selected bit line.

When the selected bit line is discharged to the ground voltage, the sensing circuit 1230 determines whether the selected bit line is at a high logic level or a low logic level. When the selected bit line is at a high logic level, the selected bit line is shorted to the selected word line. When the selected bit line is at a low logic level, the selected bit line is not shorted to the selected word line.

According to an embodiment of the invention, when the selected bit line is shorted to the selected word line, the data stored on the selected bit line of the memory array will be lost, but stored on the selected word line. The information can be recovered using ECC.

According to an embodiment of the present invention, when the selected bit line is short-recorded to select the word line, the data stored in the memory unit corresponding to the selected word line and the selected bit line can be applied by The voltage is selected to the selected word line and the selected bit line is floated. After reading the data stored in the selected character line, all the bit lines must be floated to facilitate discharge to ground voltage.

After performing the detection method proposed by the present invention, the system can know which flash memory array is damaged, so that the system can perform a series of operations to protect the data stored on the flash memory array.

The above is an overview feature of the embodiment. Those having ordinary skill in the art should be able to use the present invention as a basis for design or adaptation to achieve the same objectives and/or achieve the same advantages of the embodiments described herein. Those having ordinary skill in the art should also understand that the same configuration should not depart from the spirit and scope of the present invention, without departing from the spirit and scope of the present creation. We can make various changes, substitutions and alternations. The illustrative methods are merely illustrative of the steps, but are not necessarily performed in the order presented. The steps may be additionally added, substituted, changed, and/or eliminated, as appropriate, and are consistent with the spirit and scope of the disclosed embodiments.

Claims (12)

A method for detecting a flash memory array, wherein the flash memory array includes a complex digital line, a plurality of bit lines, and a source line, including: performing a first detection process, wherein The first detecting process includes: applying a first positive voltage to one of the P-type wells of the flash memory array; applying a ground voltage to all of the word lines; floating the bit lines and the source a line; determining whether a leakage current flowing through one of the P-type wells exceeds a leakage threshold; and when the leakage current exceeds the leakage threshold, determining that at least one of the word lines is short-circuited to the bit line At least one of the source lines or the source line; wherein, after the step of determining whether at least one of the word lines is short-circuited to at least one of the bit lines or the source line, the detecting method further comprises: performing a second detecting process, wherein the second detecting process comprises: sequentially selecting one of the word lines as a selected word line; charging the selected word line to the first using a first fixed current Second positive ; Applying the ground voltage to all of the bit lines and the source lines; determining that the selected word line is at a high logic level or a low logic level; when the selected word line is at the above height When the logic bit is on time, determining that the selected word line is not short-circuited to any one of the bit lines or the source line; and when the selected character line is located at the low logic level, determining the selected word The line is shorted to at least one of the bit lines or the source line. The detecting method of claim 1, wherein after the step of performing the second detecting process, the detecting method further comprises: performing a third detecting process, wherein the third detecting program The method further includes: applying a third positive voltage to the selected word line by using a second fixed current, so that the plurality of memory cells on the selected word line are non-conducting; floating all of the bit lines Applying the ground voltage to the source line; determining that the selected word line is located at the high logic level or the low logic level; and when the selected character line is located at the high logic level, determining the above The selected word line is not shorted to the source line; and when the selected word line is at the low logic level, it is determined that the selected word line is shorted to the source line. The detecting method of claim 2, wherein when the selected character line is short-circuited to the source line, the data stored on the selected character line of the flash memory array will be Lost and unable to recover with ECC. The detecting method of claim 2, wherein after the step of performing the third detecting process, the detecting method further comprises: performing a fourth detecting process, wherein the fourth detecting process The method includes: applying a fourth positive voltage to the selected word line, so that the plurality of memory cells on the selected character line are non-conducting; sequentially selecting one of the bit lines as a selected bit a line, wherein the remaining bit line is a plurality of unselected bit lines; discharging the selected bit line to the ground voltage by using a fourth fixed current; floating the source line and the unselected bit a line; determining that the selected bit line is located at the high logic level or the low logic level; and when the selected bit line is at a high logic level, determining that the selected bit line is shorted to the selected a word line; and when the selected bit line is at the low logic level, determining that the selected bit line is not shorted to the selected word line. The detecting method of claim 4, wherein when the selected bit line is short-circuited to the selected word line, the selected bit line of the flash memory array is stored. The information will be lost, The data stored in the selected character line can be recovered using ECC. The detecting method of claim 4, wherein when the selected bit line is short-circuited to the selected word line, the word line corresponding to the selected word line and the selected bit line are stored. Data of a memory cell can be read by applying a positive voltage to the selected word line and floating the selected bit line, wherein after reading the data stored on the selected word line, All of the above bit lines are floated and discharged to the above ground voltage. A memory device includes: a flash memory array including a complex digital line, a complex bit line, a source line, and a P-type well; and a bias circuit to generate the flash memory array a voltage and a current; a sensing circuit for sensing a logic level of the word line, the bit line and the source line, and a leakage current of the P-type well; and a controller for selecting the word And detecting a method, wherein the detecting method comprises a first detecting process, wherein the first detecting process comprises: applying a first positive voltage to the foregoing a P-type well of the flash memory array; applying a ground voltage to all of the word lines; floating the bit line and the source line; determining whether the leakage current flowing through the P-type well exceeds one Leakage threshold; and When the leakage current exceeds the leakage threshold, determining whether at least one of the word lines is short-circuited to at least one of the bit lines or the source line; wherein at least one of the word lines is determined After the step of short-circuiting to at least one of the bit lines or the source line, the detecting method further includes a second detecting process, wherein the second detecting process comprises: sequentially selecting the word line One as a selected word line; charging the selected word line to a second positive voltage by using a first fixed current; applying the ground voltage to all of the bit lines and the source line; The selected character line is located at a high logic level or a low logic level; when the selected character line is located at the high logic level, it is determined that the selected word line is not shorted to the bit line Any one of the source lines or the source line; and when the selected word line is at the low logic level, determining that the selected word line is shorted to at least one of the bit lines or the source line The memory device of claim 7, wherein after the step of performing the second detecting process, the detecting method further comprises a third detecting process, wherein the third detecting program further comprises : Applying a third positive voltage to the selected word line using a second fixed current such that the plurality of memory cells on the selected word line are non-conducting; floating all of the bit lines; a ground voltage is applied to the source line; determining that the selected word line is located at the high logic level or the low logic level; and when the selected word line is located at the high logic level, determining the selected word The source line is not shorted to the source line; and when the selected word line is at the low logic level, it is determined that the selected word line is shorted to the source line. The memory device of claim 8, wherein when the selected character line is short-circuited to the source line, the data stored on the selected character line of the flash memory array will be Lost and unable to recover with ECC. The memory device of claim 8 , wherein after the step of performing the third detecting process, the detecting method further comprises a fourth detecting program, wherein the fourth detecting program comprises: Applying a fourth positive voltage to the selected word line such that the plurality of memory cells on the selected word line are non-conducting; sequentially selecting one of the bit lines as a selected bit line, The remaining bit line is a plurality of unselected bit lines; the selected bit line is discharged to the ground voltage by a fourth fixed current; Floating the source line and the unselected bit line; determining that the selected bit line is located at the high logic level or the low logic level; and when the selected bit line is at a high logic level, determining The selected bit line is shorted to the selected word line; and when the selected bit line is at the low logic level, it is determined that the selected bit line is not shorted to the selected word line. The memory device of claim 10, wherein when the selected bit line is shorted to the selected word line, the selected bit line of the flash memory array is stored. The data will be lost and the data stored in the selected word line will be recovered using ECC. The memory device of claim 10, wherein when the selected bit line is shorted to the selected word line, the word line corresponding to the selected word line and the selected bit line are stored. Data of a memory cell can be read by applying a positive voltage to the selected word line and floating the selected bit line, wherein after reading the data stored on the selected word line, All of the above bit lines are floated and discharged to the above ground voltage.