JP5236949B2 - Erased sector detection mechanism - Google Patents

Abstract

The present invention presents a non-volatile memory and method for its operation that allows instant and accurate detection of erased sectors when the sectors contain a low number of zero bits, due to malfunctioning cells or other problems, and the sector can still be used as the number of corrupted bits is under the ECC correction limit. This method allows the storage system to become tolerant to erased sectors corruption, as such sectors can be used for further data storage if the system can correct this error later in the written data by ECC correction means.

Description

  The present invention relates generally to non-volatile memories and their operation, and more specifically to techniques for determining whether a portion of a rewritable memory has been erased and its level of destruction.

  A typical application for flash EEPROM devices is as an electronic device mass data storage subsystem. Such a subsystem is typically implemented as a removable memory card that can be inserted into and removed from multiple host systems, or as a non-removable embedded storage device within the host system. In both implementations, the subsystem includes one or more flash devices and often includes a subsystem controller.

  A flash EEPROM device is composed of one or more arrays of transistor cells, each cell being capable of storing one or more data bits in a nonvolatile manner. Thus, flash memory does not require power to hold the programmed data therein. However, once programmed, the cell must be erased before being reprogrammed with new data values. These arrays of cells are partitioned into groups to provide an efficient implementation of read, programming, and erase functions. The typical flash memory structure of mass storage devices arranges large groups of cells into erasable blocks. In this case, one block includes the minimum number of cells (erase units) that can be erased at one time.

  In one commercial form, each block contains enough cells to store one sector of user data and some overhead data. This overhead data is associated with user data and / or the block in which it is stored. The amount of user data contained in one sector is standard 512 bytes in one type of such memory system, but may be other sizes. Isolating individual blocks of cells from each other is necessary so that those blocks can be individually erased, but such isolation takes up space on the integrated circuit chip, so other types of Flash memory significantly increases the blocks and reduces the space required for such isolation. However, since it is also desirable to handle user data in a much smaller sector, each large block often goes to an individually addressable page, which is the basic unit for reading and programming user data. It is further divided. Each page typically stores one sector of user data, but a page may store partial sectors or multiple sectors. In this specification, “sector” means the amount of user data transferred as a unit between hosts.

  Subsystem controllers in large block systems perform many functions. Such functions include conversion between logical addresses received by the memory subsystem from the host and physical addresses in the memory cell array. This conversion often involves the use of logical block numbers (LBN) and intermediate terms for logical pages. The controller further manages low level flash circuit operation through a series of commands. The controller issues the above-described series of commands to the flash memory device via the interface bus. Another function performed by the controller is to maintain the integrity of the data stored in the subsystem using various means such as error correction codes (ECC).

  In flash and some other memory systems, a page of data must be erased before it can be rewritten. Therefore, before selecting a page of data for storing data, it is necessary to find the erased page. It is therefore important for the system to be able to determine as quickly and expediently as possible which part of the memory is erased. The reason is to determine whether the memory portion must still be used or whether the memory portion is a sector that was written before undergoing the erase process. This is not necessarily the direct case where the controller simply tracks the block that introduced the erase operation. For example, if power is interrupted during operation of such a memory circuit, the memory may have been in an erase operation, for example, when the memory card is removed from the host or when power to the device with integrated memory is lost. Incomplete operation will occur. Furthermore, if the sector has been erased but contains a small number of corrupted bits, a simple read of the sector will appear to hold the data.

Many sector erase techniques are known. For example, it is possible to simply read the contents of the sector. However, apart from the problem that there may possibly be a broken bit, this does not distinguish between an actually erased sector and the same data, that is, a sector that happens to be written with the corresponding all-FF. One prior art solution found in US Pat. No. 5,928,370, which is incorporated herein by reference, is an “ideal” elimination using an ECC engine. It is a solution to detect the sector. The sector data can be used to generate a new ECC field, and this new ECC field can be compared to the reference ECC field previously generated for all FFs. If the ECC field is the same, the sector is considered erased (including all FFs). However, this still has the problem that there is a chance of false detection. Furthermore, this method cannot detect an erased sector even if the erased sector has only one zero bit.
US Pat. No. 5,928,370 US Pat. No. 6,522,586 US patent application Ser. No. 10 / 086,495 US Pat. No. 6,282,130 US Pat. No. 5,546,341 US patent application Ser. No. 09 / 956,201 US patent application Ser. No. 10 / 751,096 US patent application Ser. No. 10 / 841,379 US patent entitled "Multi-state non-volatile non-volatile integrated circuit memory system using dielectric storage elements" by Eliyaho Harari, George Samatissa, Jack H. Ewan, and Daniel C. Gutterman, filed Oct. 25, 2002 application US Pat. No. 5,768,192 U.S. Pat. No. 4,630,086 US Pat. No. 5,991,193 US Pat. No. 5,892,706

  According to the first aspect, the present invention is because the sector contains a low number of zero bits due to malfunctioning cells or other problems, and the number of corrupted bits is below the ECC correction limit. Provided is a non-volatile memory and method of operation thereof that allows for immediate and accurate detection of erased sectors when the sectors are still available. This method makes the storage system resistant to the destruction of erased sectors. This is because if the system can later correct this error in the write data by the ECC correction means, such a sector can be used for further data storage.

  The first set of embodiments inverts the contents of the page (including the ECC field), and an erased page (all FFs) with some destruction (0 bits) has some high Except for bits, the page has zero data. The system can then interpret the erased page as valid data and apply the system's standard ECC method to it. A new syndrome is generated and the page is corrected using this new syndrome. If the page was successfully corrected, check if it contains all zeros. If so, an erased sector has been found.

  In a further aspect of the invention, an additional embodiment describes a method for detecting partially erased sectors (main data with overhead and ECC areas). This method not only detects such pages, but also quantifies the destruction level so that it can be determined whether the pages are suitable for further use. When the sector data is transferred to the controller, the firmware or ECC customized circuit can detect zeros in the sector or in all codewords when the sector is divided into multiple adjacent or interleaved codewords. Detect and count bits (for BCH) or symbols with at least one zero bit (for Reed-Solomon). Thus, the value of the counter will contain the number of bits or symbols that were not erased in the sector (or in all codewords of the sector). These values indicate the destruction level of the erased sector.

  In an additional aspect of the present invention, for any of these embodiments, the erased sector detection process includes a preliminary check to see if the page is in a non-destructive erased state, and the page has a limited number of zero It can be preceded by a process that determines whether to include a bit.

  Additional aspects, features, and advantages of the present invention are included in the following description of exemplary embodiments that should be considered in conjunction with the accompanying drawings.

To provide a specific example of an exemplary non-volatile memory system, a specific non-volatile memory system in which various aspects of the present invention are implemented will be described with reference to FIGS. In order to reduce the amount of interference in the erase process, the present invention maintains the control gates of unselected storage elements at the same voltage level as the underlying well structure. In the exemplary embodiment, the storage element is formed over the well structure. During the erase process, both selected and non-selected storage elements above the well are raised to the erase voltage and in parallel establish this voltage level in the well. This voltage is then maintained on the wells and unselected storage elements, thereby reducing any erase opportunity associated with the disturbance. Meanwhile, the selected storage element is allowed to discharge and generates the necessary erase conditions. In addition, this can be achieved without increasing the circuit pitch area or adding new wiring into the memory array, resulting in the addition of minimal additional peripheral areas to the circuit.

To be specific, the present invention will be described with respect to a NAND EEPROM flash memory. However, the generalization will be further described below. In particular, the current discussion uses systems such as those described in US Pat. No. 6,522,580 and other applications related to NAND systems previously incorporated by reference. When a specific voltage is required below, the erase voltage V _erase is taken in the range of 15-20 volts, the low logic level is taken by ground, and the high logic level V _dd is in the range of 1.5-3 volts. Taken at. However, other values may be used depending on the design.

  FIG. 1 is a block diagram of a flash memory system. A memory cell array 1 including a plurality of storage units M arranged as a matrix is controlled by a column control circuit 2, a row control circuit 3, a c source control circuit 4, and a cp well control circuit 5. The column control circuit 2 is connected to the bit line (BL) of the memory cell array 1, reads the data stored in the memory cell (M), determines the state of the memory cell (M) during the programming operation, and Control the potential level of the line (BL) to facilitate programming or inhibit programming. The row control circuit 3 is connected to the word line (WL), selects one of the word lines (WL), applies a read voltage, and is combined with the bit line potential level controlled by the column control circuit 2 A programming voltage is applied and an erase voltage combined with the voltage of the p-type region (labeled “cp well” 11 in FIG. 3) in which the memory cell (M) is formed. The c source control circuit 4 controls a common source line (labeled “c source” in FIG. 2) connected to the memory cell (M). The cp well control circuit 5 controls the voltage of the cp well.

  Data stored in the memory cell (M) is read by the column control circuit 2 and output to the external I / O line via the I / O line and the data input / output buffer 6. Program data to be stored in the memory cell is input to the data input / output buffer 6 via the external I / O line and transferred to the column control circuit 2. The external I / O line is connected to the controller 20. Command data for controlling the flash memory device is input to a command interface connected to an external control line connected to the controller 20. The command data notifies the flash memory of what operation is required. Input commands are transferred to the state machine 8 that controls the column control circuit 2, row control circuit 3, c source control circuit 4, cp well control circuit 5, and data input / output buffer 6. The state machine 8 can output flash memory status data, eg ready / busy (READY / BUSY) or pass / fail (PASS / FAIL).

  The controller 20 is connected to or connectable to a host system, such as a personal computer, digital camera, or personal digital assistant (PDA). The host initiates a command, eg, a command to store data in the memory array 1 or read data from the memory array, and provide or receive such data, respectively. The controller converts such commands into command signals that can be interpreted and executed by the command circuit 7. The controller further typically includes a buffer memory for user data to be written to or read from the memory array. A typical memory system includes one integrated circuit chip 21 that includes a controller 20 and one or more integrated circuit chips 22 that each include a memory array and associated control circuitry, input / output circuitry, and state machine circuitry. . The trend is, of course, to integrate the system's memory array and controller circuitry together on one or more integrated circuit chips. The memory system may be included in a memory card that can be embedded as part of the host system or removably inserted into the mating socket of the host system. Such a card may comprise the entire memory system or a controller and memory array with associated peripheral circuitry may be provided on separate cards.

  An exemplary structure of the memory cell array 1 will be described with reference to FIG. A NAND flash EEPROM will be described as an example. The memory cell (M) is divided into a large number, in a specific example, 1024 blocks. The data stored in each block is erased simultaneously. Thus, a block is the smallest unit of many cells that can be erased simultaneously. Within each block, there are N columns, in this example N = 8,512 columns, as further described in US Pat. No. 6,522,580. These columns are divided into a left column and a right column. The bit line is also divided into a left bit line (BLL) and a right bit line (BLR). Four memory cells connected to the word lines (WL0 to WL3) at each gate electrode are connected in series to form a NAND cell unit. One terminal of the NAND cell unit is connected to a corresponding bit line (BL) via a first select transistor (S) whose gate electrode is coupled to a first (drain) select gate line (SGD). The other terminal is connected to the c source via a second (source) select transistor (S) whose gate electrode is coupled to a second select gate line (SGS). For simplicity of illustration, four floating gate transistors are shown to be included in each cell unit, but other numbers, eg, 8, 16, or even 32 transistors are used. . FIG. 2 further includes a connection cp well that supplies the well voltage.

  Within each block, in this example, 8,512 columns are divided into even and odd columns. The bit line is further divided into an even bit line (BLe) and an odd bit line (BLo). Four memory cells connected to the word lines (WL0 to WL3) at each gate electrode are connected in series to form a NAND cell unit. One terminal of the NAND cell unit is connected to the corresponding bit line (BL) via a first selection transistor (S) whose gate electrode is coupled to the first selection gate line (SGD), and the other The terminal is connected to the c source via a second selection transistor (S) whose gate electrode is coupled to a second selection gate line (SGS). For simplicity of illustration, four floating gate transistors are shown to be included in each cell unit, but higher numbers, for example, 8, 16, or even 32 transistors, are used.

  In an alternative set of embodiments, as described in US patent application Ser. No. 10 / 086,495, filed Feb. 27, 2002, which is incorporated herein by reference, The array can be divided into left and right parts instead of odd and even arrays. The left and right sides may additionally have independent well structures, and each of the right and left sides of the array is formed on such a separate well structure and is controlled by the cp well control circuit 5 of FIG. The voltage level can be set independently. In a further variant, this allows the erasing of sub-blocks that are smaller than the entire block section. Further variations compatible with the present invention are also described in US patent application Ser. No. 10 / 086,495.

  In the exemplary embodiment, the page size is 512 bytes. This is smaller than the number of cells on the same word line. This page size is based on user preferences and practices. Associating the size of the word line with more cells than one page saves the space of the X decoder (row control circuit 3). This is because data for different pages can share the decoder. During user data read and programming operations, N = 4,256 cells (M) are simultaneously selected in this example. The selected cell (M) has the same word line (WL), for example, WL2, and the same type of bit line (BL). Therefore, 532 bytes of data can be read or programmed simultaneously. These 532 bytes of data that are read or programmed at the same time logically form a “page”. Thus, one block can store at least 8 pages. When each memory cell (M) stores two data bits, i.e., a multi-level cell, one block stores 16 pages for a storage device of 2 bits per cell. In this embodiment, the storage element of each memory cell, in this case the floating gate of each memory cell, stores two bits of user data.

  FIG. 3 shows a cross-sectional view in the bit line (BL) direction of a NAND cell unit of the form shown in the schematic diagram of FIG. A p-type region cp well 11 is formed on the surface of the p-type semiconductor substrate 9, and each of the left and right cp wells is surrounded by the n-type region 10, thereby electrically connecting the cp well from the p-type substrate. Insulate. The n-type region 10 is connected to a cp well line made from the first metal M0 via the first contact hole (CB) and the n-type diffusion layer 12. The p-type region cp well 11 is also connected to the cp well line via the first contact hole (CB) and the p-type diffusion layer 13. The cp well line is connected to the cp well control circuit 5 (FIG. 1).

  The exemplary embodiment uses a flash EEPROM storage unit. In this case, each memory cell is made up of a floating gate (FG) that stores an amount of charge corresponding to data stored in the cell, a word line (WL) that forms a gate electrode, and a p-type diffusion layer 12. Having drain and source electrodes. The floating gate (FG) is formed on the surface of the cp well via the tunnel oxide film (14). The word line (WL) is stacked on the floating gate (FG) through the insulating film (15). The source electrode is connected to a common source line (c source) made of the first metal (M0) via the second selection transistor (S) and the first contact hole (CB). The common source line is connected to the c source control circuit (4). The drain electrode is connected to the second metal via the first selection transistor (S), the first contact hole (CB), the intermediate wiring of the first metal (M0), and the second contact hole (V1). The bit line (BL) made from (M1) is connected. The bit line is connected to the column control circuit (2).

  4 and 5 show cross-sectional views of the memory cell (section 4-4 in FIG. 3) and the select transistor (section 5-5 in FIG. 3) in the direction of the word line (WL2), respectively. Each column is separated from adjacent columns by trenches formed in the substrate and filled with an insulating material, known as shallow trench isolation (STI). In the trench, the floating gate (FG) is separated from each other by the STI, the insulating film 15 and the word line (WL). Since the gate electrode (SG) of the selection transistor (S) is formed in the same formation process steps as the floating gate (FG) and the word line (WL), a stacked gate structure is shown. These two select gate lines (SG) are shunted at the end of the line.

US Pat. No. 6,522,580, previously incorporated by reference, describes various voltages for operating the memory cell array 1. In a particular example, the floating gate of each memory cell stores two bits and has one of the states “11”, “10”, “01”, “00”. The case where the bit lines of the word lines “WL2” and “BLe” are selected for erasing, reading or programming will be briefly outlined here. The data of the selected block is erased by raising the cp well to an erase voltage of V _erase = 15 to 20 V and grounding the word line (WL) of the selected block. Since the word line (WL), bit line (BL), selection line (SG), and c source of the non-selected block are all placed in a floating state, these are also approximately V due to capacitive coupling with the cp well. _Raised to _erase . Therefore, a strong electric field is applied only to the tunnel oxide film 14 (FIGS. 4 and 5) of the selected memory cell (M), and the tunnel current flows across the tunnel oxide film 14 in the data of the selected memory cell. So erased. The erased cell is in this example one of four possible programming states, ie “11”.

  High voltage values used for erase and programming values can be generated from lower supply values using a charge pump (not shown in FIG. 1). These high voltage values may be generated on the memory chip 22 itself or supplied from other chips in the memory system. The use and location of the high voltage source is fully described in US Pat. No. 6,282,130, incorporated herein by reference, and additional references cited therein. ing.

FIG. 6 schematically shows such a prior art arrangement. Three representative word lines WL _A , WL _B , and WL _C are connected to lines 107 that supply various voltage levels via transistors 101, 103, and 105, respectively. Transistors 101, 103, and 105 may be part of row control circuit 3 of FIG. The cp well control circuit 5 of FIG. 1 provides a voltage for the well structure cp well 11. Next, the word line continues onto any of the various word lines in different blocks of the memory 1 shown in FIG. In the erase process, using both the word line WL _C corresponding to the selected word line, and the unselected WL _A and WL _B , the voltage in the cp well is raised to the erase voltage, eg, 17 volts. And line 107 is grounded. The gate of transistor 105 is set to a high level of V _dd and word line WL _C is grounded, while both transistors 101 and 103 are turned off by grounding their gates, WL _A and WL _B is left floating. This produces the erasure condition described above. In that case, the unselected erase gate can be changed in electrical quantity by capacitive coupling from the well (eg, as described in previously incorporated US Pat. No. 5,546,341). ), The selected erase gate is forced to ground. Another aspect of the erasure process is described in US patent application Ser. No. 09 / 956,201 filed Sep. 17, 2001, which is incorporated herein by reference. Specifically, US patent application Ser. No. 09 / 956,201 can be incorporated into alternative embodiments of various aspects of the present invention, processes that can float unselected word lines. Explain the process.

In order to store electrons in the floating gate (FG) during the programming operation, the selected word line WL2 is connected to the programming pulse Vpgm and the selected bit line BLe is grounded. On the other hand, to inhibit programming on the memory cell (M) where programming should not occur, the corresponding bit line BLe, like the unselected bit line BLo, is connected to the power supply V _dd , eg 3V. Unselected word lines WL0, WL1, and WL3 are connected to 10V, the first selection gate (SGD) is connected to _Vdd , and the second selection gate (SGS) is grounded. As a result, the channel potential of the programmed memory cell (M) is set to 0V. The channel potential in the programming inhibit is raised to about 6V as a result of the channel potential being raised by capacitive coupling with the word line (WL). As described above, during programming, a strong electric field is applied only to the tunnel oxide film 14 of the memory cell (M), and the tunnel current flows across the tunnel oxide film 14 in the opposite direction compared to erasure, and the logic The state is changed from “11” to one of the other states “10”, “01”, or “00”.

In order to store electrons in the floating gate (FG) during the programming operation, the selected word line WL2 is connected to the programming pulse Vpgm and the selected bit line BLe is grounded. On the other hand, in order to inhibit programming on memory cells (M) where programming should not occur, the corresponding bit line BLe, like the unselected bit line BLo, is connected to the power supply V _dd , eg 3V. Unselected word lines WL0, WL1, and WL3 are connected to 10V, the first selection gate (SGD) is connected to _Vdd , and the second selection gate (SGS) is grounded. As a result, the channel potential of the programmed memory cell (M) is set to 0V. The channel potential in programming inhibit is raised to about 6V. This is because the channel potential is raised by capacitive coupling with the word line (WL). As described above, during programming, a strong electric field is applied only to the tunnel oxide film 14 of the memory cell (M), and the tunnel current flows across the tunnel oxide film 14 in the opposite direction compared to erasure, and the logic The state is changed from “11” to one of the other states “10”, “01”, or “00”.

  In read and verify operations, select gates (SGD and SGS) and unselected word lines (WL0, WL1, and WL3) are raised to a read pass voltage of 4.5V, which is then passed to the pass gate. To do. The selected word line (WL2) is connected to a specified voltage level for each read and verify operation. This is to determine whether the threshold voltage of the relevant memory cell has reached such a level. For example, in the READ10 operation, since the selected word line WL2 is grounded, it is detected whether or not the threshold voltage is higher than 0V. In the case of this reading, it can be said that the reading level is 0V. In the VERIFY01 operation, the selected word line WL2 is connected to 2.4V, and it is verified whether or not the threshold voltage has reached 2.4V. In this verification, the verification level can be said to be 2.4V. Again, for all of the described processes, the cited voltage levels are merely exemplary values.

  The selected bit line (BLe) can be precharged to a high level, eg, 0.7V. If the threshold voltage is higher than the read or verify level, the potential level of the relevant bit line (BLe) remains high for the non-conductive memory cell (M). On the other hand, if the threshold voltage is lower than the read or verify level, the potential level of the relevant bit line (BLe) is reduced to a low level, eg, a level below 0.5 V, due to the conducting memory cell (M). To do. Further details of the read and verify operations are described below.

Example of Erased Sector Detection Mechanism The main aspect of the present invention is that the sector contains a low number (but not necessarily zero) of zero bits because of a malfunctioning cell or other problem and has been destroyed A technique for detecting erased sectors immediately and accurately when the number of bits is below the ECC correction limit and the sector can still be used. Prior art systems to date are not tolerant in such cases and result in the system stopping functioning, assuming that the sector was previously written and destroyed. This method allows the storage system to withstand such destruction of erased sectors, and if the system can later correct this error in the write data by the ECC correction means, such sectors will be further It can be used for data storage. Further, these techniques may be combined with the sort erased sector abort detection mechanism described in US patent application Ser. No. 10 / 751,096, filed Dec. 31, 2003.

  More specifically, the present invention describes a method for detecting partially erased sectors (main user data and overhead and ECC areas). This method not only detects such pages, but also quantifies the destruction level so that it can be determined whether the pages are suitable for further use. When the sector data is transferred to the controller, the firmware or ECC customized circuit can detect zeros in the sector or in all codewords when the sector is divided into multiple adjacent or interleaved codewords. Detect and count bits (for BCH) or symbols with at least one zero bit (for Reed-Solomon). Thus, the value of the counter will contain the number of bits or symbols that were not erased in the sector (or in all codewords of the sector). These values indicate the destruction level of the erased sector. For example, for BCH, the counter counts the number of zero bits. If the number is below the ECC correctable limit, the page is available for programming. If the ECC method allows 4-bit correction, it is quite safe to use an erased sector with one or two failed bits.

  The exemplary embodiment is based on the properties of the Galois field and the ECC algorithm that uses it. For example, the BCH and Reed-Solomon methods generate a zero ECC algorithm for zero data. This is because an all-zero codeword is a valid codeword. Similar strategies can be used for other, more complex error correction methods. The following description will further often refer to units of data sectors. This is because this is a common unit in which ECC codewords are calculated. More generally, however, the described techniques may be easily performed for other data units.

  FIG. 7 illustrates a first exemplary embodiment of the present invention that uses an ECC algorithm to help detect erased pages (all FFs). If the sector does not contain all FFs and the data cannot be corrected by the error correction algorithm, the technique assumes that the sector was an erased (all FF) sector but some bits are faulty (0) Then, another attempt is made to correct the sector data. The sector data is first inverted to make the “erased” sector data a valid codeword. Inverted and erased sectors (including the ECC field) have all zeros that are valid codewords. This is because zero data produces a zero ECC. As a result, if some bits (within ECC limits) are high, they can be corrected by the same error correction routine that the system normally uses.

  The first stage 710 is an initial data error detection and correction operation. This operation includes an initial check whether the sector has been erased. The first stage 710 is followed by a second stage 750 in which the erased sector detection method is performed. The initial stage 710 is optional and may be skipped. This is because an erased page can be detected without it. However, it is preferable to include this initial stage. This is because it provides an initial check whether a page has been erased (without destruction) or contains valid data.

  The process begins at 701 and an initial check is performed at step 711 to see if the page has been erased without destruction (all FF). If so, the process proceeds directly to step 763 and ends. Otherwise, the process continues to step 713 where it is checked whether the page contains data that was correct and not erased. Alternatively, step 711 can be followed by step 711 before moving to step 750.

  Step 713 determines if the page contains valid and unerased data (715). If not, the process continues with a data correction operation (717). If this results in corrected data, the process ends (721). This is because the corrected data was extracted using ECC. If the data cannot be corrected, the error correction phase begins. At that stage, it is assumed that the section is erased and contains mainly FF.

  The process moves to step 750 where it is determined whether the page contains erased but corrupted data. This starts at step 751 and inverts all of the sector data including the ECC field. Inverted and erased pages are valid codewords for a given ECC algorithm. Step 753 generates a new error correction syndrome as if it were generated by an ECC block. In one very special example of 4 codewords per sector with 1 byte syndrome, generating the first byte using data bytes 0-128 and 129 for all 4 subcodewords Data bytes 0-128 and 130 can be used to generate the second byte, and data bytes 0-128 and 131 can be used to generate the third byte. The more general case of codeword number and size follows easily. Using this new syndrome, a correction operation is performed on the inverted data using the new syndrome. If the process is not successful (757-759), the sector is determined to have an uncorrectable amount of errors. If the data has been corrected (757 to 761), it is checked in step 761 whether the data consists of only zeros. If not configured (761-759), there may be an error that cannot be corrected again, and the initial assumption that went to step 750 may have been incorrect. Sector errors are potentially too serious to correct, and the errors were not corrected properly. If the sector contains all zeros in step 761, a sector that was erased but had a destructible amount that could be processed was found (763).

  The various steps of FIG. 7 and the embodiments described with respect to the following figures can be implemented in hardware or firmware / software. Some steps are easier to implement in one form than others. For example, step 711 (inspect data to see if it is all FF) can be inspected fairly easily in hardware by inspecting the received data on the memory bus. The execution of step 761 (check for all zeros in the data buffer) is relatively infrequent and can be accomplished with firmware.

  If the hardware at step 711 can count the number of zero bits in the data, step 761 may be skipped. This is because the system only needs to know the initial number of zero bits and the number of 1 bits changed by error correction. If they are equal, the page has all zeros. This is easily achieved for BCH-based codes that change bits during correction. In Reed Solomon that corrects the symbol, the count is a non-FF symbol. In any case, this is preferably done for each codeword. (As explained below, this is almost the same as what is done in step 771 of FIG. 9.)

  The embodiment of FIG. 7 uses an ECC inspection method that does not quantify the destruction level of erased pages. In this case, the number of zero bits (Z) allowed in the erased page is fixed based on the ECC method being used. For example, if BCH is used, the maximum number of erased bits Z for correcting an erased page to the all-FF state (if the faults are evenly distributed) is Z = (per codeword Maximum number of correctable bits) x (number of codewords per sector (or other data unit)). In Reed-Solomon, the corresponding formula is Z = (number of correctable symbols per codeword) x (bits per symbol) x (codeword per sector (or other data unit)). In practical implementations, the acceptance criterion may not exceed a certain allowed number Z of non-erased bits (BCH) or symbols (Reed-Solomon) in each codeword. Here, Z in this embodiment is equal to the number of correctable bits or symbols. The embodiment shown in FIGS. 8 and 9 allows quantification of the destruction level of erased pages.

  The embodiment shown in FIG. 8 includes ECC checking based on the method described above, but includes quantifying the destruction level of erased pages. The number of allowed zero bits (Z) in the erased page is identified by the ECC algorithm. For example, BCH gives the number of bit errors that it can correct, and Reed-Solomon gives the number of multi-bit symbols that can be corrected. In this case, the destruction level is detected as acceptable based on the number of symbols destroyed. If a sector is composed of more than one codeword, the goodness of the sector may be defined by the worst maximum destruction codeword.

  For the embodiment of FIG. 7, the new elements of FIG. 8 are found in the partial stage 770 of the error detection routine 750. This embodiment places this partial stage 770 immediately after step 753 of generating a new syndrome for the inverted data. The other steps in FIG. 8 (including the option to skip stage 710 and the placement of step 711) may be considered essentially the same as described above with respect to FIG. However, if the erased page pattern corresponds to all 0s, the reversal of step 751 is not necessary prior to subsequent destruction level quantification. (More generally, if an erased page produces a valid codeword only when it is flipped, an inversion step should be included.)

  Step 771 quantifies the destruction level as described above. In this embodiment, step 757 is used to determine if the corrected page has been erased. This is because step 771 quantifies the error amount for the nearest valid codeword. The nearest valid codeword may be all zeros, but may be any other codeword.

  Step 773 determines whether the level is within acceptable limits. If it is not within acceptable limits, the error is considered so high that it cannot be corrected, and the routine proceeds directly to 759 without attempting to correct the data. If the level is determined to be acceptable, the process proceeds to step 755 and can continue as in FIG. 7, but if an erased sector is found, the end result includes a destruction level at step 763. That is different. Note that in this embodiment, the destruction level is not included if 763 is reached directly from step 711.

  As a modification of FIG. 8, step 771 can be part of step 755. In this way, the destruction quantification is complete when the correction is complete, so the combined result is the number of bits or symbols corrected. If steps 771 and 755 are combined, step 773 is placed after combined steps 771/755.

  FIG. 9 is a second exemplary embodiment that includes quantifying the destruction level of erased pages. The routine of FIG. 9 begins again at the optional initial stage 710 described above in other embodiments before proceeding to a different stage 750. FIG. 9 again includes quantification of the destruction level of erased pages, which is similar to that shown in FIG. 8, but can be achieved without a method based on ECC inspection. Instead, the number of allowed zero bits (Z) in the erased page is identified, for example, by counting zero bits (BCH) or non-all-zero symbols (Reed-Solomon).

  The process of FIG. 9 begins again at an optional stage 710, similar to the previously described embodiment. As before, step 711 may be placed at the beginning or end of stage 710. If step 711 is performed by hardware that can count the number of zero bits in the data, the subsequent step 761 may be skipped. This is because the system only needs to know the initial number of zero bits and the number of 1 bits changed by error correction. If these bit numbers are equal, the page has all zeros. This is easily achieved for BCH-based codes that change bits during correction. In Reed-Solomon correcting symbols, the count is the count of non-FF symbols. In any case, this is preferably done for each codeword.

  In the embodiment of FIG. 9, the ECC algorithm itself is not used, but only knowledge about the ECC algorithm characteristics is used. The counting may be done again by hardware (in the controller or memory) or firmware. As a result, the failure level is quantified in step 771 of FIG. 9 without the need for steps 751 and 753 of FIG. Once the destruction level is quantified at step 771, its acceptability is determined at step 773 as before. If the level exceeds an acceptable limit, the data is considered to have an uncorrectable amount of error (759).

  Step 771 has already determined the number of incorrect bits or symbols for the erased sector pattern, so if this error amount is determined to be acceptable in step 773, it is corrected directly to all zeros. be able to. As a result, steps 755 and 757 of FIG. 8 are redundant and removed from the flowchart, while step 761 is now a step of setting the data to the corrected value. Unlike FIG. 8, step 757 of determining whether the corrected page has been erased is not required.

  The description so far is based on the detection of erased sectors. In that case, erasing corresponds to an all-FF pattern, and ECC is based on a Reed-Solomon or BCH algorithm. As mentioned above, these methods can be extended to other ECC algorithms as will be apparent to those skilled in the art. It is also clear that these techniques can be applied to detect other data patterns that may occur in other types of memory, for example erased pages consisting of all zeros.

  With respect to other memory types, as described above, the present invention is not only applicable to the NAND flash memory of the exemplary embodiments, but is also incorporated by reference herein in other structures and memory technologies, such as this application. It can be applied to what is described in US Patent Application No. 10 / 841,379 (Patent Document 8) filed on May 7, 2004. For example, it is useful for other EEPROM or charge storage cells such as NOR flash memory with well erase. Similarly, if the storage element is not a floating gate transistor, for example, Eliyaho Harari, George Samachisa, Jack H. Yuan, filed Oct. 25, 2002, which is incorporated herein by reference, And can be extended to dielectric storage elements of the type described in the US patent application (Patent Document 9) entitled “Multi-state non-volatile integrated circuit memory system using dielectric storage elements” by Daniel C. Gutterman. The discussion so far has focused on embodiments that use charge storage devices such as floating gate EEPROMs or flash cells as memory devices, but other embodiments such as NROM and MNOS cells such as Eitan. US Pat. No. 5,768,192 and US Pat. No. 4,630,086 to Sato et al., Respectively, or magnetic RAM and FRAM cells, such as Gallagher et al. U.S. Pat. No. 5,991,193 (Patent Document 12) and Shimizu et al., U.S. Pat. No. 5,892,706 (Patent Document 13), respectively. All of these patents are incorporated herein by reference.

  Although various aspects of the invention have been described with reference to specific embodiments, it will be understood that the invention is entitled to protection within the full scope of the appended claims.

FIG. 6 is a block diagram of a non-volatile memory system in which implementations of various aspects of the invention are described. Fig. 2 illustrates existing circuitry and organization when the memory array of Fig. 1 is NAND-type. FIG. 3 shows a cross-sectional view along a column of a NAND memory array formed on a semiconductor substrate. FIG. 4 is a cross-sectional view of the memory array taken at section 4-4 of FIG. FIG. 5 is a cross-sectional view of the memory array taken at section 5-5 of FIG. An array for the erase mechanism is shown. 6 is a flowchart of a first embodiment of an erased page detection mechanism that takes into account the destruction level. 12 is a flowchart of a second embodiment of an erased page detection mechanism that takes into account quantification of the destruction level. 12 is a flowchart of a third embodiment of an erased page detection mechanism that takes into account quantification of destruction levels.

Claims (28)

A method for determining whether a data unit of memory has been erased, comprising:
An initial determination step for performing an initial determination of whether the data unit of the memory corresponds to the erased state;
Determining to determine whether the data unit contains valid and unerased data;
In the determining step, a data correction operation step for performing a data correction operation on the content of the data unit ;
Inverting the ECC field associated with the data content of the data unit if the data correction operation does not correct the data;
Generating an error correction code syndrome for the inverted data content;
Performing data correction on the inverted data content using the syndrome; and
Determining whether the data content of the data unit has been erased based on the corrected and inverted data content including the inverted data state ;
Including methods. The method of claim 1, wherein
The method wherein the data unit is a sector of data. The method of claim 1, wherein
A method in which the error correction code uses a Reed-Solomon algorithm. The method of claim 1, wherein
A method in which the error correction code uses a BCH algorithm. The method of claim 1, wherein
The method is performed by firmware. The method of claim 1 , wherein
The method wherein the initial determination is performed in hardware by examining received data on a memory bus. A method for determining whether a data unit of memory has been erased, comprising:
Performing initial data error detection and correction operations;
If the data is not corrected in the step of detecting and correcting the initial data error, the contents of the data unit without performing an operation of generating a new error correction code syndrome that can be reversed based on the data unit. Quantifying the destruction level of
Determining whether a failure level is acceptable based on the error correction code associated in the initial data error detection and correction operation ;
Responsive to determining whether the destruction level is acceptable, correcting data content;
Determining whether the data content of the data unit has been erased based on the corrected data content; and
Including methods. The method of claim 7 , wherein
Before the step of quantifying the destruction level of the content of the data unit, the method further includes generating an error correction code syndrome for the data content, the step of correcting the data content using the syndrome A method based on the corrected data content, wherein the step of determining whether the data content of the data unit has been erased is performed. The method of claim 8 , wherein
Before the step of generating an error correction code syndrome for the data content, the method further includes the step of inverting the data content of the data unit, wherein the error correction code syndrome is generated using the data content in the inverted format, and the data content Is performed on the inverted data content using the syndrome, and determining whether the data content of the data unit has been erased is based on the corrected inverted data content. Method. The method of claim 9 , wherein
The method wherein inverting the data content includes inverting an associated ECC field. The method of claim 8 , wherein
A method further comprising performing an initial determination of whether the data content corresponds to the erased state prior to generating an error correction code syndrome for the data content. The method of claim 11 wherein:
The method wherein the initial determination is performed in hardware by examining received data on a memory bus. The method of claim 8 , wherein
A method further comprising: prior to generating an error correction code syndrome for the data content, determining whether the data unit includes valid and unerased data. 14. The method of claim 13 , wherein
The method of determining whether a data unit includes valid and unerased data further comprises performing a data correction operation on the contents of the data unit. The method of claim 7 , wherein
The method wherein the data unit is a sector of data. The method of claim 7 , wherein
A method in which the error correction code uses a Reed-Solomon algorithm. The method of claim 7 , wherein
A method in which the error correction code uses a BCH algorithm. The method of claim 7 , wherein
The method is performed by firmware. A method of processing a data unit in memory,
Performing initial data error detection and correction operations;
If the data is not corrected in the step of detecting and correcting the initial data error, the data is erased without performing an operation of generating a new error correction code syndrome that can be obtained by inverting the data content based on the data unit. Determining and quantifying the destruction level of the data unit content for
Determining whether a failure level is acceptable based on the error correction code associated in the initial data error detection and correction operation ;
Including methods. The method of claim 19 , wherein
A method further comprising correcting data content in response to determining whether the destruction level is acceptable. The method of claim 19 , wherein
A method further comprising performing an initial determination of whether data content corresponds to an erased state prior to determining and quantifying the destruction level. The method of claim 21 , wherein
The method wherein the initial determination is performed in hardware by examining received data on a memory bus. The method of claim 19 , wherein
A method further comprising the step of determining whether a data unit contains valid and unerased data prior to determining and quantifying the destruction level. 24. The method of claim 23 .
The method of determining whether a data unit includes valid and unerased data further comprises performing a data correction operation on the contents of the data unit. The method of claim 19 , wherein
The method wherein the data unit is a sector of data. The method of claim 19 , wherein
A method in which the error correction code uses a Reed-Solomon algorithm. The method of claim 19 , wherein
A method in which the error correction code uses a BCH algorithm. The method of claim 19 , wherein
The method is performed by firmware.

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