TWI664715B - Flash memory with multiple control gates and flash memory array device made thereof - Google Patents

Abstract

The invention relates to a flash memory with multiple control gates, including: a substrate, a silicon oxide layer, a fin-shaped channel layer, a two-charge storage structure, a two-gate, a two-character conductive pillar, and a two-character. line. A silicon oxide layer is disposed on the substrate. The fin-shaped channel layer is disposed on the silicon oxide layer and includes a first end portion, a second end portion, a top surface, and two side surfaces. The two charge storage structures are disposed on the silicon oxide layer and are respectively combined with two sides of the fin-shaped channel layer. Two gates are disposed on the silicon oxide layer and are respectively disposed on one side of the two charge storage structure. The two-character conductive pillars are respectively connected to the two gates and extend from the two gates in a direction away from the charge storage structure. The two-character lines are respectively connected to the two-character conductive pillars, and the orthographic projection on the substrate intersects the orthographic projection of the fin-shaped channel layer on the substrate.

Description

Flash memory and flash memory array device with multiple control gates

The invention relates to a flash memory having a plurality of control gates, and a flash memory array device.

The existing flash memory can be used for data storage. Traditional flash memory has a two-dimensional array structure. In recent years, many three-dimensional memory products have increased the amount of data stored per unit area. The principle of flash memory is mainly written by high voltage, which can store data in the critical voltage type of the transistor. Flash memory can also be used in neural network-like circuits as computing units.

However, the problem with the use of traditional planar flash memory is that its transistor can only store an analog information through a threshold voltage. Moreover, in the traditional FinFET structure, the gate voltages on both sides are the same, and both ends must be read / write simultaneously. Today's three-dimensional memory arrays can increase the storage density per unit area, but the development cost is very high, and it is not suitable for neural network-like NOR connection methods (source grounding).

Therefore, one of the objectives of the present invention is to provide a flash memory with multiple control gates, which can store charges on both sides (dual gates) of the memory element and double the information density. It also has the ability to control read / write of the memory at both ends, and double the density of the layout of the memory array.

The invention relates to a flash memory with a plurality of control gates, including: a substrate. A silicon oxide layer is disposed on the substrate. A fin-shaped channel layer disposed on the silicon oxide layer and including a first end Portion, a second end portion, a top surface and two side surfaces, the top surface and the two side surfaces are both located between the first end portion and the second end portion, and the top surface faces away from the silicon oxide layer and separates the Two sides. The two charge storage structures are disposed on the silicon oxide layer and are respectively coupled to two sides of the fin-shaped channel layer. Two gates are disposed on the silicon oxide layer and are respectively disposed on one side of the two charge storage structures. The two-character conductive pillars are respectively connected to the two gates and extend from the two gates in a direction away from the charge storage structure. And the two-character line are respectively connected to the two-character conductive pillar, and the orthographic projection of the two-character line on the substrate intersects with the orthographic projection of the fin-shaped channel layer on the substrate.

The invention also relates to a flash memory array device, comprising: a first flash memory, the first flash memory system is a flash memory with a plurality of control gates as described above. And a second flash memory, the second flash memory system is a flash memory with a plurality of control gates as described above. The bit line of the first flash memory and the bit line of the second flash memory together form a first bit line. The substrates of the first and second flash memories are the same substrate, and the first and The silicon oxide layer of the second flash memory is the same silicon oxide layer.

100‧‧‧Flash memory

110‧‧‧ substrate

120‧‧‧Silicon oxide layer

130‧‧‧ fin channel layer

135‧‧‧ substrate conductive pillar

141, 142‧‧‧Gate

143, 144‧‧‧ charge storage structure

150‧‧‧ spacer

161, 162‧‧‧character conductive pillars

171, 172‧‧‧character lines

180‧‧‧bit conductive post

190‧‧‧bit line

200‧‧‧Flash memory

210‧‧‧ substrate

220‧‧‧Silicon oxide layer

230‧‧‧ fin channel layer

235‧‧‧ substrate conductive pillar

241, 242‧‧‧Gate

243, 244‧‧‧ charge storage structure

250‧‧‧ spacer

261, 262‧‧‧character conductive post

271、272‧‧‧Character line

280‧‧‧bit conductive post

290‧‧‧bit line

300‧‧‧Gate structure

310‧‧‧ tunneling oxide

320‧‧‧ charge storage layer

330‧‧‧ barrier insulation

340‧‧‧Gate material

M1‧‧‧First flash memory

M2‧‧‧Second flash memory

M3‧‧‧Third flash memory

M4‧‧‧Fourth flash memory

Please refer to the accompanying drawings to describe additional features and advantages of the present invention. The description will be made with reference to the drawings, which are intended to illustrate preferred embodiments of the present invention. It should be understood that these examples do not represent the full scope of the invention.

1A and 1B are schematic perspective views illustrating a flash memory including a plurality of control gates according to a first embodiment of the present invention.

FIG. 2 is a schematic perspective view illustrating a flash memory including a plurality of control gates according to a second embodiment of the present invention.

3A to 3H are schematic diagrams illustrating a manufacturing process of a flash memory having a plurality of control gates according to the present invention.

FIG. 4 is a schematic perspective view illustrating a flash memory array device composed of a plurality of flash memories having a plurality of control gates.

FIG. 5 is a circuit diagram showing a neural network composed of a flash memory array device.

FIG. 6 and FIG. 7 show the distribution of doping inside the fin channel layer and the change in V _t of the rear gate when the program is written only to the front gate of the fin channel layer using TCAD simulation.

The detailed features and advantages of the present invention are described in detail in the following embodiments. The content is sufficient for any person skilled in the art to understand and implement the technical contents of the present invention. Anyone skilled in the relevant art can easily understand the related objects and advantages of the present invention. The following examples further illustrate the viewpoints of the present invention in detail, but do not limit the scope of the present invention in any way.

Please refer to FIGS. 1A and 1B, which is a first embodiment of a flash memory with multiple control gates according to the present invention. FIG. 1A is viewed from one side of the flash memory, and FIG. 1B is Look at the other side opposite this side. The flash memory 100 includes a substrate 110, a silicon oxide layer 120, a fin-shaped channel layer 130, a substrate conductive pillar 135, two gates 141 and 142, two charge storage structures 143 and 144, a spacer 150, and a two-character conductive pillar 161. , 162, two character line 171, 172, bit conductive pillar 180, bit line 190.

In FIGS. 1A and 1B, the silicon oxide layer 120 is disposed on the substrate 110. The fin-shaped channel layer 130 is disposed on the silicon oxide layer 120 and its composition contains silicon or germanium. The fin-shaped channel layer 130 includes a first end portion, a second end portion, a top surface, and two side surfaces. The top surface and two side surfaces of the fin-shaped channel layer 130 are both located between the first end portion and the second end portion. The top surface faces away from the silicon oxide layer 120 and separates the two side surfaces. The charge storage structures 143 and 144 are disposed on the silicon oxide layer 120 and are respectively coupled to the two sides of the fin-shaped channel layer 130. The gate electrodes 141 and 142 are respectively disposed on one side of the charge storage structures 143 and 144, and are all disposed on the silicon oxide layer 120. The charge storage structures 143 and 144 are sandwiched between the gate electrodes 141 and 142 and the fin channel layer 130. Between the two sides. The character conductive pillars 161 and 162 are respectively connected to the gate electrodes 141 and 142 and extend from the gate electrodes 141 and 142 in a direction away from the silicon oxide layer 120. The character lines 171 and 172 are connected to the character conductive pillars 161 and 162, respectively, and the orthographic projection of the two character lines 171 and 172 on the substrate 110 intersects the orthographic projection of the fin-shaped channel layer 130 on the substrate 110. In this embodiment, the bit conductive pillars 190 are longer than the character conductive pillars 161 and 162, so the word lines 171 and 172 are located between the silicon oxide layer 120 and the bit lines 190. In the above structure, the doping concentration of the fin-shaped channel layer 130 is relatively high, about 5 * 10 ²⁰ cm ^-1 to 2 * 10 ¹⁹ cm ^-1 . At this time, when only the two gate electrodes 141, When one of the 142 is written, the operation of one gate will deplete the doping in the fin channel layer 130, while the other gate is hardly affected. By projecting on the substrate 110 across the two word lines 171, 172 of the fin-shaped channel layer 130, the structure of the flash memory capable of independently operating and separately controlling the dual gates can be simplified.

The gate electrodes 141 and 142 and the two insulating layers are a blocking insulating layer and a tunneling insulating layer (not shown in FIG. 1) and a layer of charge storage structures 143 and 144. The flash memory of the present invention can be Symmetric structure, so there will be the same type of structure included in the component. Since the electrodes in the gate electrodes 141 and 142 are not connected, they can be operated independently. The charge storage layer may use other structures or materials such as silicon nitride, floating-gate composed of highly doped silicon, and quantum dots.

The gates 141 and 142 apply a proper bias voltage to complete the Read / Program / Erase operation. When the gates 141 and 142 apply a high voltage, the electrons will generate a positive voltage due to the applied voltage. The electric field causes the electrons to tunnel from the substrate 110 through the tunneling oxide layer (not shown in FIG. 1) to the charge storage structures 143 and 144 to complete the writing operation. At this time, the electrons are blocked and stored in the charge storage structure 143 by the two oxide layers. , 144 in. At this time, the critical voltage of the device will rise. Electronic writing can also generate a hot carrier injection effect through the high current of the channel. Since the gates 141 and 142 can operate independently, we can choose to inject charge into the charge storage structure on the side of the gate 141 or the charge storage structure 144 on the side of the 143 gate 142.

After the write operation is completed, when a low voltage is applied to the gates 141 and 142, the electrons will generate a negative electric field due to the applied voltage, so that the electrons stored in the charge storage structures 143 and 144 pass through the tunneling oxide layer (not shown in FIG. 1). (Out) tunneling to the substrate 110, there will be no electrons in the charge storage structures 143, 144, and the erasing operation is completed. At this time, the critical voltage of the device will decrease.

The presence or absence of electrons in the charge storage structures 143 and 144 in the above action will change the critical voltage of this element. The critical potential of the element can be determined by the channel current by applying a lower voltage to the gates 141 and 142 It is then possible to determine whether a charge is stored in the element to complete the reading operation. Since the gates 141 and 142 can be operated independently, one of the two gates 141 and 142 can be selected to read the threshold voltage, so that the structure disclosed by the present invention can store two different information.

Please refer to FIG. 2, which is a second embodiment of a flash memory with a plurality of control gates according to the present invention. The fin field-effect transistor 200 includes a substrate 210, a silicon oxide layer 220, a fin-shaped channel layer 230, a substrate conductive pillar 235, a gate 241, 242, a spacer 250, a character conductive pillar 261, 262, and a character line 271, 272. , Bit conductive pillars 280, bit lines 290, and charge storage structures 243 and 244.

In FIG. 2, the arrangement of the components is substantially the same as that of the first figure. However, the second embodiment is different from the first embodiment in that the bit line 290 of the second embodiment is located between the word lines 271 and 272 and the silicon oxide layer 220. The bit conductive pillar 290 is long. Thereby, the relative positions of the word lines 271 and 272 and the bit line 290 can be adjusted according to the overall setting requirements.

Please refer to FIGS. 3A to 3H. In order to understand the production of the above-mentioned flash memory, the following is a description of the manufacturing process by taking the first embodiment of the flash memory with multiple control gates of the present invention as an example.

See Figure 3A. A device is fabricated using an SOI wafer, and a silicon oxide layer 120 is formed on the substrate 110.

See Figure 3B. In a lithography and etching manner, a rectangular fin-shaped channel layer 130 is formed on the silicon oxide layer 120.

Referring to FIG. 3C, a gate structure 300 is formed. First, a tunnel oxide layer 310, a charge storage layer 320, and a blocking insulating layer 330 are deposited from the inside to the outside and are covered on the fin-shaped channel layer 130. The gate material 340 is re-deposited, and then the gate shape is defined by lithography and etching. At this time, the gate structure 300 is a rectangle perpendicular to the fin-shaped channel layer 130.

Referring to FIG. 3D, the gate is divided into two gates 141 and 142 by a chemical-mechanical planarization (CMP) process.

Referring to FIG. 3E, the gate electrodes 141 and 142 are perpendicular to the fin channel layer 130. On both sides, spacers 150 are formed by deposition and plasma etching.

Referring to FIG. 3F, word conductive pillars 161 and 162 are formed above the gate electrodes 141 and 142, respectively.

Referring to FIG. 3G, a character line 171, 172 is formed above the character conductive pillars 161, 162 by using a subsequent process.

Referring to FIG. 3H, a one-bit conductive pillar 180 is formed above the first end portion of the fin-shaped channel layer 130. Then, a bit line 190 is formed above the bit conductive pillar 180.

Compared with the manufacturing process of the first embodiment shown in FIGS. 3A to 3H described above, the second embodiment of the present invention is different from the first embodiment in that when manufacturing the second embodiment, After the spacers 150 are formed by deposition and plasma etching, a one-bit conductive pillar 180 is first formed above the first end portion of the fin-shaped channel layer 130. Then, a bit line 190 is formed above the bit conductive pillar 180. Then, word conducting pillars 161 and 162 are formed above the gate electrodes 141 and 142, respectively. Next, word lines 171 and 172 are formed above the word conductive pillars 161 and 162, respectively.

FIG. 4 is a flash memory array device composed of a plurality of flash memories having a plurality of control gates according to the present invention. The flash memory array device includes a first flash memory M1 and a second flash memory. Memory M2, third flash memory M3, and fourth flash memory M4. The direction connecting the first flash memory and the second flash memory is the X direction, and the direction connecting the first flash memory and the third flash memory is the Y direction. In practice, you can expand and connect more flash memory along these two directions as needed to form a larger flash memory array and provide greater memory capacity. In addition, the substrates 110 and the silicon oxide layer 120 of all the flash memories M1 to M4 are all connected to each other.

Specifically, in FIG. 4, in the longitudinal direction (as shown in the Y direction shown in FIG. 4), the character line 171 of the first flash memory M1 and the character line of the third flash memory M3 171 are connected to each other to form a first word line; word lines 172 of the first flash memory M1 and word lines 172 of the third flash memory M3 are connected to each other to form a second word line. Similarly, the second fastest The character line 171 of the flash memory M2 and the character line 171 of the fourth flash memory M4 are connected to each other to form a third word line. The character line 172 of the second flash memory M2 and the fourth flash memory. The word lines 172 of the memory M4 are connected to each other to form a fourth word line.

In addition, in a lateral direction (X direction shown in FIG. 4), the fin-shaped channel layer 130 of the first flash memory M1 and the fin-shaped channel layer 130 of the second flash memory M2 are connected to each other. The bit line 190 of the flash memory M1 and the bit line 190 of the second flash memory M2 are connected to each other to form a first bit line. The fin channel layer 130 of the third flash memory M3 and the fin channel layer 130 of the fourth flash memory M4 are also connected to each other. The bit line 190 of the third flash memory M3 and the fourth flash memory The bit lines 190 are connected to each other to form a second bit line.

Generally non-volatile memory can be used in artificial intelligence (AI) applications of neural morphology (Neuromorphic) and deep learning. Due to its artificial intelligence algorithm's algorithmic characteristics, it is necessary to complete the learning by weight. The weight value depends on the memory array memory to complete the learning process. This memory array can complete the weight calculation internally first, thereby overcoming The computer moves data between the central device (CPU) and the memory (the so-called von Neumann bottleneck). Traditional flash memory can also achieve this function, but because the array must be connected in parallel in NOR form, it cannot be implemented in 3D memory structure. FIG. 5 is a circuit diagram of a neural network or the like constituted by the flash memory array device of the present invention. In the longitudinal direction, the two word lines of each flash memory are connected to each other to form a first word line and a second word line that are parallel to each other. In the lateral direction, the bit lines of each flash memory are connected to each other to form a first bit line. During operation, each memory has a front gate and a rear gate, which are respectively connected to external circuits through different word lines. Therefore, each flash memory transistor can store two weights. FIG. 6 is a simulation using TCAD (Technology Computer Aided Design) to simulate the programming of the front gate of the fin channel layer only, the distribution of doping inside the fin channel layer, and the change in V _t of the rear gate. It can be seen from FIG. 7 that the gates on the two sides of the fin channel layer operate independently, for example, the threshold voltage of the front gate is not affected by the bias of the rear gate. Therefore, under the same area, the number of weights that can be stored by the neural network-like circuit composed of the flash memory of the present invention is twice that of the conventional one. Therefore, the present invention is implemented through a two-dimensional memory array, and the dual gates help reduce the area of the memory array, and its storage density is about twice that of a conventional flash memory. Moreover, the two word lines across the fin-shaped channel layer can achieve the purpose of individually controlling the two gates with a very simplified structure.

Claims (16)

A flash memory with multiple control gates includes: a substrate; a silicon oxide layer disposed on the substrate; a fin-shaped channel layer disposed on the silicon oxide layer; the fin-shaped channel layer includes a A first end portion, a second end portion, a top surface and two side surfaces, and the top surface and the two side surfaces are both located between the first end portion and the second end portion, the top surface facing away from the silicon oxide layer and The two sides are separated; two charge storage structures are disposed on the silicon oxide layer and are respectively coupled to the two sides of the fin-shaped channel layer; two gates are disposed on the silicon oxide layer and are respectively disposed on the silicon oxide layer One side of the two-character storage structure; two-character conductive pillars respectively connected to the two gates and extending from the two gates in a direction away from the charge storage structure; and two-character lines respectively connected to the two-character conductive Column, the orthographic projection of the two-character line on the substrate intersects the orthographic projection of the fin-shaped channel layer on the substrate. The flash memory with multiple control gates as described in claim 1, further comprising a one-bit conductive post and a one-bit wire, the bit conductive post is connected to the top surface and is adjacent to the first end and away from At the second end, the orthographic projection of the bit line on the substrate intersects with the orthographic projection of the word lines on the substrate. The flash memory with a plurality of control gates according to claim 2, wherein the word lines are located between the bit lines and the two gates. The flash memory with a plurality of control gates according to claim 2, wherein the bit line is located between the word lines and the two gates. The flash memory with a plurality of control gates according to claim 2, wherein the two word lines are parallel to each other, and the orthographic projection of the bit lines on the substrate and the word lines are on the substrate The orthogonal projection is orthogonal. The flash memory with a plurality of control gates according to claim 2, wherein the bit lines and the word lines are parallel to the silicon oxide layer. The flash memory with a plurality of control gates according to claim 1, further comprising a substrate conductive pillar passing through the silicon oxide layer, one end of the substrate conductive pillar is connected to the fin-shaped channel layer and is adjacent to the second end. Away from the first end, and the other end of the conductive pillar of the substrate is connected to the substrate. The flash memory with a plurality of control gates according to claim 1, wherein the charge storage structure includes a tunneling oxide layer, a charge storage layer, and a blocking insulating layer (positional relationship of three layers). The flash memory with a plurality of control gates according to claim 1, further comprising a plurality of spacers disposed on the silicon oxide layer, and the spacers are attached to the gates and the charge storage structures. A plurality of sidewalls, and the spacers are connected to the fin-shaped channel layer. The flash memory with a plurality of control gates according to claim 1, wherein a doping concentration of the fin channel layer between two projections of the two-word line on the fin channel layer It is between 5 * 10 ²⁰ cm ^-1 and 2 * 10 ¹⁹ cm ^-1 . A flash memory array device includes: a first flash memory, the first flash memory system according to claim 1, a flash memory having a plurality of control gates; and a second flash memory Memory, the second flash memory system is the flash memory having a plurality of control gates as described in claim 1, wherein one of the two word lines of the first flash memory and the second flash memory One of the two character lines of the flash memory forms a first character line, the other of the two character lines of the first flash memory and the two character line of the second flash memory The other is to form a second word line. The substrates of the first and second flash memories are the same substrate, and the silicon oxide layers of the first and second flash memories are the same silicon oxide layer. The flash memory array device according to claim 11, wherein the first word line and the second word line both extend straight along a direction. A flash memory array device includes: a first flash memory, the first flash memory system described in claim 2 having a plurality of control gates, and a second flash memory; Memory, the second flash memory system is the flash memory having a plurality of control gates as described in claim 2; wherein the bit line of the first flash memory and the second flash memory The bit lines form a first bit line, the substrates of the first and second flash memories are the same substrate, and the silicon oxide layers of the first and second flash memories are the same silicon oxide layer . The flash memory array device according to claim 13, wherein the first bit line extends straight in a direction. The flash memory array device according to claim 13, wherein the first end portion of the fin channel layer of the first flash memory is connected to the fin channel layer of the second flash memory. Second end. The flash memory having a plurality of control gates according to claim 1, wherein the fin-shaped channel layer contains silicon or germanium.