CN212136451U - Memory device - Google Patents
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- CN212136451U CN212136451U CN202021160637.4U CN202021160637U CN212136451U CN 212136451 U CN212136451 U CN 212136451U CN 202021160637 U CN202021160637 U CN 202021160637U CN 212136451 U CN212136451 U CN 212136451U
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- 239000000758 substrate Substances 0.000 claims abstract description 30
- 210000000352 storage cell Anatomy 0.000 claims abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 5
- 210000004027 cell Anatomy 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 15
- 238000010586 diagram Methods 0.000 description 10
- 230000005415 magnetization Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005034 decoration Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
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Abstract
The utility model relates to a semiconductor manufacturing technology field especially relates to a memory. The memory includes: the memory device comprises a substrate, a plurality of storage cells and a plurality of word lines, wherein the substrate is internally provided with a plurality of active regions arranged in an array mode and a plurality of word lines extending along a first direction, the active regions are inclined at preset angles relative to the word lines, and the active regions are internally provided with at least one access transistor; a plurality of bit lines extending in a second direction perpendicular to the first direction; and one end of the magnetic tunnel junction is electrically connected with one bit line, the other end of the magnetic tunnel junction is electrically connected with two access transistors, and the two access transistors electrically connected with one magnetic tunnel junction are respectively positioned in two adjacent active regions. The utility model discloses both guaranteed required big drive current when programming the memory, improved memory cell's storage density simultaneously again, improved the comprehensive properties of memory to strengthen magnetic memory's product competitiveness.
Description
Technical Field
The utility model relates to a semiconductor manufacturing technology field especially relates to a memory.
Background
A Magnetic Random Access Memory (MARM) is based on the integration of silicon-based complementary oxide semiconductor (CMOS) and Magnetic Tunnel Junction (MTJ) technologies, and is a nonvolatile Memory that has high-speed read/write capability of a static Random Access Memory and high integration of a dynamic Random Access Memory. The magnetic tunnel junction generally includes a pinned layer, a tunneling layer, and a free layer. During normal operation of the magnetic random access memory, the magnetization direction of the free layer can change while the magnetization direction of the pinned layer remains unchanged. The resistance of a magnetic random access memory is related to the relative magnetization directions of the free and fixed layers. When the magnetization direction of the free layer changes relative to the magnetization direction of the fixed layer, the resistance value of the magnetic random access memory changes accordingly, corresponding to different stored information.
However, in the conventional magnetic random access memory, due to the limitations of the arrangement of the memory cells and the connection of the magnetic tunnel junction and the transistor, the further improvement of the overall performance of the magnetic random access memory is restricted, thereby limiting the wide application of the magnetic random access memory.
Therefore, how to improve the structure of the memory and enhance the comprehensive performance of the memory is a technical problem to be solved urgently at present.
SUMMERY OF THE UTILITY MODEL
The utility model provides a memory for solve the problem that current memory comprehensive properties remains further to improve.
In order to solve the above problem, the utility model provides a memory, include:
the memory device comprises a substrate, a plurality of storage cells and a plurality of word lines, wherein the substrate is internally provided with a plurality of active regions arranged in an array mode and a plurality of word lines extending along a first direction, the active regions are inclined at preset angles relative to the word lines, and the active regions are internally provided with at least one access transistor;
a plurality of bit lines extending in a second direction perpendicular to the first direction;
and one end of the magnetic tunnel junction is electrically connected with one bit line, the other end of the magnetic tunnel junction is electrically connected with two access transistors, and the two access transistors electrically connected with one magnetic tunnel junction are respectively positioned in two adjacent active regions.
Optionally, the method further includes:
and the conductive contact pad is positioned above the substrate, one end of the conductive contact pad is electrically connected with the magnetic tunnel junction, and the other end of the conductive contact pad is simultaneously electrically connected with the sources of the two access transistors.
Optionally, two of the access transistors electrically connected to one of the magnetic tunnel junctions are respectively located in two of the active regions that are arranged along the second direction and are adjacent to each other; or,
the two access transistors electrically connected with one magnetic tunnel junction are respectively positioned in two adjacent active regions arranged along a third direction, and the third direction is inclined by the preset angle relative to the first direction.
Optionally, each of the active regions has two of the access transistors therein, which are distributed at two opposite ends of the active region;
two of the access transistors electrically connected to one of the magnetic tunnel junctions are respectively located at ends of two adjacent ones of the active regions that are close to each other.
Optionally, one of the active regions overlaps two adjacent word lines;
and the two access transistors positioned in the same active region respectively correspond to the two word lines.
Optionally, the method further includes:
source lines extending in the first direction, and one of the active regions overlapping one of the source lines;
and the drains of the two access transistors positioned in the same active region are electrically connected with the same source line.
Optionally, the source line is curved, and the source line is electrically connected to the access transistor in the active region at a corner.
Optionally, the preset angle is greater than 30 ° and less than 90 °.
The utility model provides a memory sets up to predetermine the angle for the extending direction slope of word line through with the active area, and connects simultaneously through a magnetic tunnel junction and be located adjacent two access transistor in the active area has both guaranteed the required big drive current when programming to the memory, has improved memory cell's storage density simultaneously again, has improved the comprehensive properties of memory to strengthen magnetic memory's product competitiveness.
Drawings
FIG. 1 is a schematic diagram of a memory according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a memory including bit lines and source lines according to an embodiment of the present invention;
FIG. 3 is another schematic diagram of a memory according to an embodiment of the present invention;
FIG. 4 is an equivalent circuit diagram of the access transistor electrically connected to the magnetic tunnel junction in an embodiment of the present invention;
FIG. 5 is a flow chart of a method for forming a memory device according to an embodiment of the present invention;
fig. 6 is a control diagram of the memory during write, read and standby operations according to an embodiment of the present invention.
Detailed Description
The following describes in detail a specific embodiment of the memory according to the present invention with reference to the drawings.
The present embodiment provides a memory. Fig. 1 is a schematic structural diagram of a memory according to an embodiment of the present invention, and fig. 2 is a schematic structural diagram of a memory including bit lines and source lines according to an embodiment of the present invention. As shown in fig. 1 and fig. 2, the memory according to this embodiment includes:
a substrate having a plurality of active regions 10 arranged in an array and a plurality of word lines WL extending in a first direction D1, the active regions 10 being inclined at a predetermined angle with respect to the word lines WL, the active regions 10 having at least one access transistor therein;
a plurality of bit lines BL extending in a second direction D2 perpendicular to the first direction D1;
one end of the magnetic tunnel junction M is electrically connected with one bit line BL, the other end of the magnetic tunnel junction M is electrically connected with two access transistors, and the two access transistors electrically connected with one magnetic tunnel junction M are respectively located in two adjacent active regions 10.
In fig. 2, the active region 10 is shown by a dotted line for clarity of the relationship between the active region 10 and the word line WL and the bit line BL. In particular, the substrate may be, but is not limited to, a silicon substrate. A plurality of the active regions 10 are arranged in an array inside the substrate, for example, but not limited to, a staggered arrangement, so as to increase the arrangement density of the active regions 10. In this embodiment, each of the active regions 10 extends along a third direction D3, each of the word lines WL extends along the first direction D1, and an included angle β between the first direction D1 and the third direction D3 is the predetermined angle. The preset angle is a non-right angle, and optionally, the preset angle is greater than 30 ° and less than 90 °, for example, 45 ° to 75 °, 50 ° to 70 °, or 65 ° to 70 °. In this particular embodiment, the predetermined angle is 68.95 °. The bit line BL is disposed above the magnetic tunnel junction M, and the bit line BL extends in a second direction D2 perpendicular to the first direction D1. One end of one of the magnetic tunnel junctions M is electrically connected to one of the bit lines BL, and the other end is simultaneously electrically connected to two access transistors (not shown) respectively located in two adjacent active regions 10. The specific way of electrically connecting the magnetic tunnel junction M and the access transistor may be direct contact electrical connection, or indirect electrical connection implemented by other electrical elements (such as a plug), which can be selected by those skilled in the art according to actual needs. The specific type of the access transistor can be a transistor with any structure, such as a buried gate structure transistor, a gate-all-around field effect transistor or a planar structure transistor, and the occupied area of the transistor can be reduced by using the buried gate structure transistor under the condition that enough channel length is ensured, so that the storage density is improved.
Fig. 4 is an equivalent circuit diagram of access transistors electrically connected to magnetic tunnel junctions in an embodiment of the invention, AT1 representing one access transistor located in one of the active regions 10 and AT2 representing another access transistor located in an adjacent one of the active regions. The present embodiment provides a new layout manner of electrical elements in a memory, specifically, by providing the active regions 10 inclined by a predetermined angle with respect to the extending direction of the word line WL, and by limiting the positions of the magnetic tunnel junctions M, one of the magnetic tunnel junctions M is electrically connected to the access transistors in two adjacent active regions at the same time, which not only ensures the driving current required for programming the magnetic tunnel junctions M, but also can improve the storage density, thereby improving the overall performance of the memory.
Optionally, the memory further includes:
and the conductive contact pad 11 is positioned above the substrate, one end of the conductive contact pad 11 is electrically connected with the magnetic tunnel junction M, and the other end of the conductive contact pad 11 is simultaneously electrically connected with the sources of the two access transistors.
For example, the projection of the conductive contact pad 11 in the direction perpendicular to the substrate may extend from one of the active regions 10 to another of the active regions 10 adjacent to the active region 10, so as to electrically connect the bottom end of one of the conductive contact pads 11 with the sources of two of the access transistors in two of the adjacent active regions 10, and the top end of the conductive contact pad 11 is electrically connected with one of the magnetic tunnel junctions M. The provision of the conductive contact pad 11 helps to increase the electrical connection area between the access transistor and the magnetic tunnel junction M, thereby ensuring the stability of the electrical connection between the magnetic tunnel junction M and the access transistor.
Alternatively, two of the access transistors electrically connected to one of the magnetic tunnel junctions M are respectively located in two of the active regions 10 aligned and adjacent along the second direction D2, as shown in fig. 1 and 2.
Specifically, as shown in fig. 1 and 2, a plurality of the active regions 10 are arranged in parallel along the second direction D2, and one magnetic tunnel junction M is disposed between two adjacent active regions 10 arranged in parallel along the second direction D2. Between the magnetic tunnel junction M and the active regions 10, in a direction perpendicular to the substrate, there is disposed one of the conductive contact pads 11 extending along the first direction D1, and a projection of the conductive contact pad 11 along the direction perpendicular to the substrate extends from one of the active regions 10 to another of the active regions 10 adjacent thereto. Two access transistors respectively located in Two adjacent active regions 10 arranged along the second direction D2 are electrically connected to one magnetic tunnel junction M through the conductive contact pad 11, so as to form a 2T1MTJ (Two-transistor-one-MTJ, 1 magnetic tunnel junction of 2 transistors). In this arrangement, in order to electrically connect the bit lines BL to the magnetic tunnel junctions M, a projection of one of the bit lines BL in a direction perpendicular to the substrate overlaps all of the magnetic tunnel junctions arranged in parallel in the second direction D2 and electrically connected to the one of the bit lines BL. The arrangement shown in fig. 1 and 2 can reduce the overlap of the conductive contact pad 11 with the word line WL and the bit line BL, reduce the parasitic capacitance, and thus improve the performance. It should be noted that, due to the different size of the active regions, the extending direction of the conductive contact pad 11 may deviate from the first direction D1, and the person skilled in the art can set the extending direction according to actual requirements.
Fig. 3 is another schematic diagram of the memory according to the embodiment of the present invention. Those skilled in the art can also make two access transistors electrically connected to one magnetic tunnel junction M respectively located in two adjacent active regions 10 arranged along a third direction D3, wherein the third direction D3 is inclined by the predetermined angle β with respect to the first direction D1, as shown in fig. 3.
Specifically, as shown in fig. 3, a plurality of the active regions 10 are arranged in parallel in the third direction D3 inclined by the preset angle with respect to the first direction D1, and one magnetic tunnel junction M is disposed between two adjacent active regions 10 arranged in parallel in the third direction D3. Between the magnetic tunnel junction M and the active regions 10, in a direction perpendicular to the substrate, there is disposed one of the conductive contact pads 11 extending along the third direction D3, and a projection of the conductive contact pad 11 along the direction perpendicular to the substrate extends from one of the active regions 10 to another of the active regions 10 adjacent thereto. A 2T1MTJ structure may also be formed by electrically connecting two of the access transistors respectively located in two of the active regions 10 arranged and adjacent along the third direction D3 with one of the magnetic tunnel junctions M through the conductive contact pad 11. In this arrangement, in order to electrically connect the bit lines BL and the magnetic tunnel junctions M, the bit lines BL are correspondingly adjusted so that a projection of one bit line BL in a direction perpendicular to the substrate overlaps all the magnetic tunnel junctions arranged in parallel along the second direction D2 and electrically connected with the one bit line BL.
Optionally, each of the active regions 10 has two of the access transistors distributed at two opposite ends of the active region 10;
two of the access transistors electrically connected to one of the magnetic tunnel junctions M are located at ends of two adjacent active regions 10 close to each other, respectively.
Specifically, within one of the active regions 10 there are two of the access transistors distributed across opposite ends of the active region 10 along the third direction D3. The projection of one magnetic tunnel junction M in the direction perpendicular to the substrate is located between two adjacent active regions, so that two access transistors electrically connected with one magnetic tunnel junction M are respectively located at the ends of two adjacent active regions 10 close to each other, thereby simplifying the circuit structure of the memory.
Optionally, one of the active regions 10 overlaps two adjacent word lines WL;
the two access transistors in the same active region 10 correspond to the two word lines WL, respectively.
Specifically, two adjacent word lines WL pass through the same active region 10, wherein a portion of one word line WL serves as a gate of one access transistor in the active region 10, and a portion of the other word line WL serves as a gate of another access transistor in the active region 10, so that the two access transistors in the same active region 10 can be controlled by the two word lines WL respectively.
Optionally, the memory further includes:
source lines SL extending in the first direction D1, and one of the active regions 10 overlapping one of the source lines SL;
the drains of two access transistors in the same active region 10 are electrically connected to the same source line SL.
Optionally, the source lines SL are bent, and the source lines SL are electrically connected to the access transistors in the active region 10 at corners.
Only a part of the source lines SL is exemplarily shown in fig. 2, and in an actual memory product, drains of all the access transistors inside the substrate are electrically connected to the corresponding source lines SL. In order to simplify the circuit structure of the memory, in this embodiment, the source line SL is bent, for example, folded or wavy, and the source line SL is electrically connected to the drains of two access transistors in the same active region 10 at one corner, for example, the two access transistors are electrically connected to the same source line SL by sharing the drains.
In this embodiment, an electrode of the access transistor electrically connected to the magnetic tunnel junction M through the conductive contact pad 11 is referred to as a source, and an electrode electrically connected to the source line SL is referred to as a drain, only to distinguish the two electrodes of the access transistor, so as to describe the structure of the memory provided in this embodiment more clearly, and not to limit the protection scope. Those skilled in the art can also refer to the electrode of the access transistor electrically connected to the magnetic tunnel junction M through the conductive contact pad 11 as the drain, and correspondingly, the electrode electrically connected to the source line SL as the source, according to the actual requirement.
Moreover, the present embodiment further provides a method for forming a memory. Fig. 5 is a flow chart of a method for forming a memory according to an embodiment of the present invention. The structure of the memory formed by the present embodiment can be seen in fig. 1 to 4. As shown in fig. 1 to fig. 5, the method for forming a memory according to the present embodiment includes the following steps:
step S51, forming a substrate having a plurality of active regions 10 arranged in an array and a plurality of word lines WL extending along a first direction D1, the active regions 10 being inclined with respect to the word lines WL by a predetermined angle β, the active regions 10 having at least one access transistor therein;
step S52, forming a magnetic tunnel junction M on the substrate, where one end of the magnetic tunnel junction M is electrically connected to two access transistors at the same time, and the two access transistors electrically connected to one magnetic tunnel junction M are located in two adjacent active regions 10 respectively;
in step S53, a plurality of bit lines BL extending along a second direction D2 are formed, the other ends of the magnetic tunnel junctions M are electrically connected to the bit lines BL, and the second direction D2 is perpendicular to the first direction D1.
Optionally, the specific step of forming the magnetic tunnel junction M on the substrate includes:
forming a conductive contact pad 11 over the substrate, the conductive contact pad 11 electrically connecting the sources of both of the access transistors simultaneously;
a magnetic tunnel junction M is formed over the conductive contact pad 11, the magnetic tunnel junction M being electrically connected with the conductive contact pad 11.
Optionally, two of the access transistors electrically connected to one of the magnetic tunnel junctions M are respectively located in two of the active regions 10 arranged and adjacent to each other along the second direction D2; or,
two of the access transistors electrically connected to one of the magnetic tunnel junctions M are respectively located in two of the active regions 10 aligned and adjacent in a third direction D3, the third direction D3 being inclined by the preset angle β with respect to the first direction D1.
Optionally, the specific step of forming the substrate includes:
providing a semiconductor substrate;
a plurality of active regions 10 arranged in an array, a plurality of word lines WL extending along a first direction D1, and two access transistors located in each of the active regions 10 are formed in the semiconductor substrate, the active regions 10 are inclined by a predetermined angle β with respect to the word lines WL, and the two access transistors are distributed at two opposite ends of the active regions 10.
Optionally, one of the active regions 10 overlaps two adjacent word lines WL;
the two access transistors in the same active region 10 correspond to the two word lines WL, respectively.
Optionally, the method for forming the memory further includes the following steps:
source lines SL extending in the first direction D1 are formed on the substrate, one active region 10 overlaps one source line SL, and the drains of two access transistors in the same active region 10 are connected to the same source line SL.
Alternatively, the source lines SL are bent, and the source lines SL are connected to the access transistors in the active region 10 at corners.
Optionally, the preset angle is greater than 30 ° and less than 90 °.
Moreover, the present embodiment further provides a method for controlling a memory. Fig. 6 is a control diagram of the memory during write, read and standby operations according to an embodiment of the present invention. The structure of the memory described in this embodiment can be seen in fig. 2. As shown in fig. 2 and 6, the memory includes a plurality of source lines SL extending along the first direction D1; the control method of the memory comprises the following steps:
selecting a target magnetic tunnel junction, wherein one end of the target magnetic tunnel junction is electrically connected with a target bit line, the other end of the target magnetic tunnel junction is simultaneously electrically connected with the source electrodes of two target access transistors, the drain electrodes of the two target access transistors are respectively connected with two target source lines, and the grid electrodes of the two target access transistors are respectively electrically connected with the two target word lines;
transmitting a high level to the target bit line and simultaneously transmitting a low level to the bit lines other than the target bit line, transmitting a high level to the target word line and simultaneously transmitting a low level to the word lines other than the target word line, transmitting a low level to all the source lines, and performing a first write operation.
Optionally, the method for controlling the memory further includes the following steps:
transmitting a low level to all the bit lines, transmitting a high level to two of the target word lines while transmitting a low level to the word lines other than the target word lines, transmitting a high level to the target source line, and transmitting a low level to the source lines other than the target source line, performing a second write operation.
Optionally, the method for controlling the memory further includes the following steps:
transmitting a high level to the target bit line and simultaneously transmitting a low level to the bit lines other than the target bit line, transmitting a high level to the target word line and simultaneously transmitting a low level to the word lines other than the target word line, and transmitting a low level to all the source lines to perform a read operation.
Optionally, the method for controlling the memory further includes the following steps:
transmitting a low level to all the bit lines, transmitting a low level to all the word lines, and transmitting a low level to all the source lines, performing a standby operation.
The following description will be given taking the magnetic tunnel junction M [ ij ] shown in fig. 2 as an example of a target magnetic tunnel junction. Transferring a high level (e.g., a bit line boosting voltage) to the target bit line BL [ i ] while simultaneously transferring a low level (e.g., a ground voltage) lower than the high level to the bit lines BL [ other than the target bit line BL [ i ], e.g., BL [ i-1], BL [ i +1], etc., at the time of performing a first WRITE operation, i.e., a WRITE 1(WRITE 1) operation; transmitting a high level (e.g., a word line boosting voltage) to the target word lines WL [ j-1] and WL [ j ], and simultaneously transmitting a low level (e.g., a ground voltage or a negative voltage lower than the ground voltage) lower than the high level to the word lines WL [ other than the target word lines WL [ j-1] and WL [ j ], such as WL [ j +1], etc.; a low level (e.g., ground voltage) is transmitted to all of the source lines SL, e.g., SL [ k-1], SL [ k +1], etc. Wherein i, j and k are positive integers greater than 1.
Transferring a low level (e.g., ground voltage) to all of the bit lines, including BL [ i ] and BL [ other ], while performing a second WRITE operation, namely a WRITE 0(WRITE 0) operation; transmitting a high level (e.g., a word line boosting voltage) to two of the target word lines WL [ j-1] and WL [ j ], and simultaneously transmitting a low level (e.g., a ground voltage or a negative voltage lower than the ground voltage) to the word lines WL [ other than the target word lines WL [ j-1] and WL [ j ], e.g., WL [ j +1], etc.; transmits a high level (e.g., source line boosting voltage) to the target source lines SL [ k-1] and SL [ k ], and transmits a low level (e.g., ground voltage) lower than the high level to the source lines SL [ other than the target source lines SL [ k-1] and SL [ k ], such as SL [ k +1], etc.
Transferring a high level (e.g., a bit line boosting voltage) to the target bit line BL [ i ] and simultaneously transferring a low level (e.g., a ground voltage) to the bit lines BL [ other than the target bit line, e.g., BL [ i-1], BL [ i +1], etc., when performing a READ operation READ; transmitting a high level (e.g., a word line boosting voltage) to the target word lines WL [ j-1] and WL [ j ], and simultaneously transmitting a low level (e.g., a ground voltage or a negative voltage lower than the ground voltage) to the word lines WL [ other than the target word lines WL [ j-1] and WL [ j ], such as WL [ j +1], etc.; a low level (e.g., ground voltage) is transmitted to all of the source lines SL, e.g., SL [ k-1], SL [ k +1], etc.
Transmitting a low level (e.g., a ground voltage) to all the bit lines BL including BL [ i ] and BL [ other ] when performing the standby operation OFF; transmitting a low level (e.g., a ground voltage or a negative voltage lower than the ground voltage) to all of the word lines WL, including WL [ j-1], WL [ j ], and WL [ other ]; and transmits a low level (e.g., ground voltage) to all of the source lines SL k-1, SL k, and SL other.
It should be noted that, in this embodiment, the high level and the low level are both relative concepts (i.e., the voltage value of the high level is higher than the voltage value of the corresponding low level), and the specific voltage value of the high level and the specific voltage value of the low level are not limited. It is also not limited that the high levels applied to different signal lines in this embodiment are equal, for example, the high level on the bit line and the high level on the word line may be different voltages, or that the high levels of a specific signal line in different phases may be equal, for example, the high levels applied to the bit line in the 1 writing operation and the high levels applied to the bit line in the reading operation may be different voltage values. It will be understood by those skilled in the art that the values of the respective high and low levels may be set on their own, depending on process nodes, speed requirements, reliability requirements, etc.
In the memory and the forming method and the control method thereof provided by the embodiment, the active region is set to be inclined at a preset angle relative to the extending direction of the word line, and the access transistors in two adjacent active regions are simultaneously connected through one magnetic tunnel junction, so that a large driving current required by programming the memory is ensured, the storage density of the memory unit is improved, the comprehensive performance of the memory is improved, and the product competitiveness of the magnetic memory is enhanced.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations should also be regarded as the protection scope of the present invention.
Claims (8)
1. A memory, comprising:
the memory device comprises a substrate, a plurality of storage cells and a plurality of word lines, wherein the substrate is internally provided with a plurality of active regions arranged in an array mode and a plurality of word lines extending along a first direction, the active regions are inclined at preset angles relative to the word lines, and the active regions are internally provided with at least one access transistor;
a plurality of bit lines extending in a second direction perpendicular to the first direction;
and one end of the magnetic tunnel junction is electrically connected with one bit line, the other end of the magnetic tunnel junction is electrically connected with two access transistors, and the two access transistors electrically connected with one magnetic tunnel junction are respectively positioned in two adjacent active regions.
2. The memory of claim 1, further comprising:
and the conductive contact pad is positioned above the substrate, one end of the conductive contact pad is electrically connected with the magnetic tunnel junction, and the other end of the conductive contact pad is simultaneously electrically connected with the sources of the two access transistors.
3. The memory of claim 1, wherein two of said access transistors electrically connected to one of said magnetic tunnel junctions are respectively located in two of said active regions aligned along said second direction and adjacent thereto; or,
the two access transistors electrically connected with one magnetic tunnel junction are respectively positioned in two adjacent active regions arranged along a third direction, and the third direction is inclined by the preset angle relative to the first direction.
4. The memory of claim 3, wherein each of said active regions has two of said access transistors therein distributed across opposite ends of said active region;
two of the access transistors electrically connected to one of the magnetic tunnel junctions are respectively located at ends of two adjacent ones of the active regions that are close to each other.
5. The memory of claim 4, wherein one of said active regions overlaps two adjacent of said word lines;
and the two access transistors positioned in the same active region respectively correspond to the two word lines.
6. The memory of claim 4, further comprising:
source lines extending in the first direction, and one of the active regions overlapping one of the source lines; and the drains of the two access transistors positioned in the same active region are electrically connected with the same source line.
7. The memory of claim 6, wherein the source line is curved and is electrically connected to the access transistor within the active region at a corner.
8. The memory according to claim 1, wherein the preset angle is greater than 30 ° and less than 90 °.
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| WO2021253717A1 (en) * | 2020-06-19 | 2021-12-23 | 长鑫存储技术有限公司 | Memory, and forming method therefor and control method therefor |
| CN114121959A (en) * | 2021-11-19 | 2022-03-01 | 北京超弦存储器研究院 | Memory device, method of manufacturing the same, and electronic apparatus including the same |
| CN114121960A (en) * | 2021-11-19 | 2022-03-01 | 北京超弦存储器研究院 | Memory device, method of manufacturing the same, and electronic apparatus including the same |
| WO2022127029A1 (en) * | 2020-12-15 | 2022-06-23 | 长鑫存储技术有限公司 | Semiconductor structure and storage circuit |
| WO2022127027A1 (en) * | 2020-12-15 | 2022-06-23 | 长鑫存储技术有限公司 | Semiconductor structure, memory cell, and memory array |
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| WO2023029403A1 (en) * | 2021-09-01 | 2023-03-09 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
| US11626558B2 (en) | 2021-09-01 | 2023-04-11 | Changxin Memory Technologies, Inc. | Semiconductor structure and manufacturing method thereof, and memory |
| WO2023097968A1 (en) * | 2021-11-30 | 2023-06-08 | 长鑫存储技术有限公司 | Semiconductor structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2021253717A1 (en) * | 2020-06-19 | 2021-12-23 | 长鑫存储技术有限公司 | Memory, and forming method therefor and control method therefor |
| US11805701B2 (en) | 2020-06-19 | 2023-10-31 | Changxin Memory Technologies, Inc. | Memory and forming methods and control methods thereof |
| EP4044240A4 (en) * | 2020-12-15 | 2023-01-11 | Changxin Memory Technologies, Inc. | Semiconductor structure, memory cell, and memory array |
| WO2022127029A1 (en) * | 2020-12-15 | 2022-06-23 | 长鑫存储技术有限公司 | Semiconductor structure and storage circuit |
| WO2022127027A1 (en) * | 2020-12-15 | 2022-06-23 | 长鑫存储技术有限公司 | Semiconductor structure, memory cell, and memory array |
| EP4044239A4 (en) * | 2020-12-15 | 2022-11-16 | Changxin Memory Technologies, Inc. | Semiconductor structure and storage circuit |
| US11930644B2 (en) | 2020-12-15 | 2024-03-12 | Changxin Memory Technologies, Inc. | Semiconductor structure and storage circuit |
| US12108682B2 (en) | 2020-12-15 | 2024-10-01 | Changxin Memory Technologies, Inc. | Semiconductor structure, memory cell and memory array |
| WO2023029403A1 (en) * | 2021-09-01 | 2023-03-09 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
| US11626558B2 (en) | 2021-09-01 | 2023-04-11 | Changxin Memory Technologies, Inc. | Semiconductor structure and manufacturing method thereof, and memory |
| CN114121960A (en) * | 2021-11-19 | 2022-03-01 | 北京超弦存储器研究院 | Memory device, method of manufacturing the same, and electronic apparatus including the same |
| CN114121959A (en) * | 2021-11-19 | 2022-03-01 | 北京超弦存储器研究院 | Memory device, method of manufacturing the same, and electronic apparatus including the same |
| WO2023097968A1 (en) * | 2021-11-30 | 2023-06-08 | 长鑫存储技术有限公司 | Semiconductor structure |
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