TWI663821B - Bootstrap circuit and associated direct current-to-direct current converter applying the bootstrap circuit - Google Patents

Abstract

A bootstrap circuit is applied to a first transistor of a DC-to-DC converter. The bootstrap circuit includes a second transistor, a bootstrap capacitor, and a clamping circuit. The bootstrap capacitor has a first terminal and a second terminal. The first terminal is coupled to the source terminal of the second transistor, and the source terminal of the second transistor is coupled to the first transistor. The clamp circuit is coupled between the gate terminal of the second transistor and the second terminal of the bootstrap capacitor. The clamp circuit is configured to maintain a distance between the second terminal of the bootstrap capacitor and the gate terminal of the second transistor. Potential difference. The drain terminal of the second transistor is coupled to the first reference voltage, and the maximum value of the voltage level of the gate terminal of the first transistor is greater than the first reference voltage.

Description

Bootstrap circuit and associated DC to DC using the bootstrap circuit converter

The invention relates to a bootstrap circuit and an associated DC-to-DC converter using the bootstrap circuit.

Taking a buck converter as an example, it provides current to the inductor and capacitor by switching the on / off states of multiple switching elements, so the input voltage can be reduced to obtain the output voltage, where the input voltage is the highest voltage value in the circuit. In addition, for a buck converter with a high input voltage, in order to reduce power consumption and obtain the required pull-up resistor, an N-type transistor is often used to implement it, where the N-type transistor has between the gate and source terminals. It has the characteristics of smaller potential difference and larger potential difference between the drain terminal and the source terminal. In order to enable the N-type transistor, the voltage level of the gate terminal of the N-type transistor should be the highest voltage level among the three terminals among the gate terminal, the source terminal, and the drain terminal. Therefore, when the source terminal is charged with the input voltage value, the voltage level of the gate terminal cannot be higher than the voltage level of the source terminal without compensation, and the transistor will be difficult to be enabled.

One object of the present invention is to provide a bootstrap circuit and an associated DC-to-DC converter, so as to solve the aforementioned problems.

According to an embodiment of the present invention, a bootstrap circuit for a first transistor of a DC-to-DC converter is disclosed. The bootstrap circuit includes a second transistor, a bootstrap capacitor, and a clamping circuit. The bootstrap capacitor has a first terminal and a second terminal. The first terminal is coupled to the source terminal of the second transistor. The source terminal is coupled to the first transistor. The clamp circuit is coupled between the gate terminal of the second transistor and the second terminal of the bootstrap capacitor. The clamp circuit is configured to maintain a distance between the second terminal of the bootstrap capacitor and the gate terminal of the second transistor. Potential difference. The drain terminal of the second transistor is coupled to the first reference voltage, and the maximum value of the voltage level of the gate terminal of the first transistor is greater than the first reference voltage.

According to an embodiment of the present invention, a DC-to-DC converter is disclosed. The DC-to-DC converter includes a switching circuit, an inductor-capacitor circuit, a feedback circuit, and a bootstrap circuit. The switching circuit includes a first transistor and a second transistor. The switching terminal is coupled to the source terminal of the first transistor and the drain terminal of the second transistor. The drain terminal of the first transistor is coupled to the first reference voltage. The inductor-capacitor circuit includes at least one inductor and a capacitor. The inductor-capacitor circuit is configured to receive an inductor current from a first reference voltage source through a switch circuit to provide energy to a subsequent load. The feedback circuit is coupled to the inductor-capacitor circuit. The feedback circuit is configured to generate an output voltage at the output terminal and generate a feedback voltage. The bootstrap circuit includes a third transistor, a bootstrap capacitor, and a clamping circuit. The source terminal of the third transistor is coupled to the first transistor. The bootstrap capacitor has a first terminal and a second terminal. The source terminal of the third transistor is coupled. The clamp circuit is coupled between the gate terminal of the third transistor and the second terminal of the bootstrap capacitor. The clamp circuit is configured to maintain a potential difference between the second terminal of the bootstrap capacitor and the gate terminal of the third transistor. . First The drain terminal of the triode is coupled to the first reference voltage, and the maximum value of the voltage level of the gate terminal of the transistor is greater than the first reference voltage.

For those of ordinary skill in the art, these and other objects of the present invention will no doubt become apparent after reading the following detailed drawings and detailed description of the preferred embodiments shown in the accompanying drawings.

10‧‧‧Current Mode Buck Converter

101‧‧‧ input voltage source

102‧‧‧Switch circuit

103‧‧‧Inductive-Capacitor Circuit

104‧‧‧Feedback circuit

105‧‧‧Bootstrap circuit

106‧‧‧Peak current mode control circuit

116‧‧‧Error Amplifier

126‧‧‧ Adder

136‧‧‧Slope Compensation Circuit

146‧‧‧PWM comparator

156‧‧‧Control logic circuit

156_1‧‧‧Buffer

166‧‧‧High-side current sensing circuit

210‧‧‧Clamp circuit

220‧‧‧Boot capacitor

230‧‧‧Drive current source

240, 250‧‧‧ voltage regulation circuit

260‧‧‧Voltage source

C, C'‧‧‧ capacitor

I _d ‧‧‧Drive current

I _L ‧‧‧ inductor current

I _LOAD ‧‧‧Subsequent load current

L‧‧‧Inductance

MD1, MD2, MD3‧‧‧ transistor

N _S ‧‧‧Source Extreme

N _G ‧‧‧ Gate extreme

SD1, SD2‧‧‧‧Schottky Dipole

CT, CT ₁ -CT _n ‧‧‧Clamping transistor

N ₁ , N ₂ ‧‧‧ terminals

PWM‧‧‧PWM signal

R ₁ , R ', R ₂ ‧‧‧ resistance

OUT‧‧‧output

Vin‧‧‧ input voltage

NV _t ‧‧‧potential difference

N _SW ‧‧‧Switch

CTRL‧‧‧Control signal

V _SW ‧‧‧Voltage Level

V _O ‧‧‧ Output voltage

V _ref ‧‧‧ Reference voltage

Vc‧‧‧Output voltage

V _R ‧‧‧ Ramp voltage

V _FB ‧‧‧Feedback voltage

V _SC ‧‧‧ Current Sensing Voltage

V _DD ‧‧‧High power voltage

V _GS ‧‧‧ Potential difference

1 is a schematic diagram of a buck converter using a bootstrap circuit according to an embodiment of the present invention; FIG. 2 is a schematic diagram of a bootstrap circuit according to an embodiment of the present invention; and FIG. 3 is a clamp circuit according to an embodiment of the present invention Schematic.

Certain terms are used throughout the description and claims to refer to particular components. As those skilled in the art will recognize, manufacturers may refer to a component by different names. This manual does not specifically identify components with different names but the same functions. In the following description and claims, the terms "including" and "comprising" are used in an open-ended fashion and therefore should not be interpreted as closed terms such as "consisting of". In addition, the term "coupled" is intended to mean an indirect or direct electrical connection. Therefore, if one device is coupled to another device, this connection may be through a direct electrical connection, or through an indirect electrical connection via the other device and the connection.

As described in the prior art, for a DC-to-DC converter such as a buck converter, it requires a bootstrap circuit. FIG. 1 illustrates a current mode buck converter 10 with a bootstrap circuit 105. The current-mode step-down converter 10 includes an input voltage source 101, a switching circuit 102, an inductor-capacitor circuit 103, and a feedback circuit 104. The input voltage source 101 is used to provide an input voltage Vin. The switching circuit 102 includes transistors MD1 and MD2 used as switches. The inductor-capacitor circuit 103 includes an inductor L and a capacitor C. The inductor-capacitor circuit 103 receives the inductor current I _L from the input voltage source 101 through the switching circuit 102 to provide energy for subsequent loads to use. The feedback circuit 104 includes resistors R ₁ and R _{2. The} feedback circuit 104 is configured to generate a feedback voltage V _FB at the terminal N ₁ according to the inductor current _IL . The terminal N _{1 is} coupled between the resistors R ₁ and R ₂ . In addition, the feedback circuit 104 is configured to generate an output voltage V _O at the output terminal OUT according to the inductor current _IL and the load current I _LOAD . As shown in FIG. 1, the switching circuit 102 further includes a switching terminal N _SW . The switching terminal N _{SW is} coupled between the source terminal of the transistor MD1 and the drain terminal of the transistor MD2. As shown in FIG. The bits are labeled V _SW . In this embodiment, the transistors MD1 and MD2 are implemented by N-type metal-oxide-semiconductor field-effect transistor (MOSFET) with a low pull-up resistance, and a pull-up resistance lower than a specific preset value also indicates that the transistor has Less energy consumption. It should be noted that the foregoing is only for further explanation, and is not intended to limit the present invention. In other embodiments, the transistors MD1 and MD2 may be implemented by other types of transistors. In addition, in other embodiments, the transistor MD2 as a switch may be replaced by a Schottky diode, but not limited thereto.

The bootstrap circuit 105 is coupled to the switch circuit 102. The bootstrap circuit 105 is used to raise the voltage level of the gate terminal of the transistor MD1. The bootstrap circuit 105 is further described in the following paragraphs. The current mode buck converter 10 may further include a peak current mode control circuit 106. The peak current mode control circuit 106 includes an error amplifier 116, an adder 126, a PWM comparator 146, a control logic circuit 156, a resistor R ', and a capacitor C'. The error amplifier 116 includes a negative input terminal, a positive input terminal, and an output terminal. The negative input terminal is used to receive the feedback voltage V _FB and the positive input terminal is used to receive the reference voltage V _ref . The error amplifier 116 is used to receive the feedback voltage V _FB and the reference voltage. V _ref generates an output voltage V _C at the output terminal. The adder 126 is used to receive the current sensing voltage V _SC and the slope voltage V _R , where the current sensing voltage V _SC is generated by the current at the sensing terminal N ₂ of the high-side current sensing circuit 166 and the slope voltage V _R is Generated by the slope compensation circuit 136. The PWM comparator 146 includes an output terminal. The PWM comparator 146 is used to compare the output voltage V _{C of the} error amplifier 116 with the output voltage of the adder 126 and generate a PWM signal at its output terminal accordingly. The control logic circuit 156 is used to generate a control signal CTRL to the switching circuit 102 so that the transistors MD1 and MD2 can be controlled by the PWM signal to operate. In this embodiment, the control logic circuit 156 may include a buffer 156_1 (refer to FIG. 2). The buffer 156_1 is used to receive the PWM signal and generate and transmit the control signal CTRL to the transistor MD1 of the switching circuit 102. The resistor R ′ and the capacitor C ′ are connected in series with each other and are coupled to the output terminal of the error amplifier 116. The resistor R ′ and the capacitor C ′ are formed as a compensation circuit. However, the compensation circuit is not limited to be implemented with a resistor R ′ and a capacitor C ′. Those skilled in the art should understand that the compensation circuit can be implemented by different architectures. Meanwhile, the current mode buck converter 10 with a slope compensation mechanism should be well known to those skilled in the art.

The present invention focuses on a bootstrap circuit 105 having the voltage level of the gate extreme of the transistor MD1 to solve the problems mentioned in the prior art. Please note that the bootstrap circuit 105 disclosed in the present invention is not limited to applications. For the buck converter shown in Figure 1.

FIG. 2 is a schematic diagram of a bootstrap circuit 105 according to an embodiment of the present invention. The bootstrap circuit 105 is coupled to the transistor MD1 of the switching circuit 102. As shown in FIG. 2, the bootstrap circuit 105 includes a transistor MD3, a clamp circuit 210, a bootstrap capacitor 220, a driving current source 230, voltage adjustment circuits 240 and 250, and a voltage source 260. The clamp circuit 210 is coupled between the gate terminal of the transistor MD3 and the switching terminal N _SW . The clamp circuit 210 is used to maintain a potential difference between the two ends. The bootstrap capacitor 220 is coupled between the source terminal N _{S of the} transistor MD3 and the switching terminal N _SW . The bootstrap capacitor 220 is used to receive and charge the current from the input voltage V _in to increase the source terminal N _S Voltage level. The driving current source 230 is coupled between the gate terminal of the transistor MD3 and the input voltage V _in . The driving current source 230 is used to provide a driving current I _d . The voltage regulating circuit 240 includes a Schottky diode SD1. The Schottky diode SD1 is coupled between the drain terminal of the transistor MD3 and the input voltage V _in . Since the Schottky diode SD1 is coupled to the drain terminal of the transistor MD3, the transistor MD3 can be easily maintained in a saturated state and provide sufficient current to the bootstrap capacitor 220. The voltage regulating circuit 250 includes a Schottky diode SD2. The Schottky diode SD2 is coupled between the gate terminal N _G and the voltage source 260. The voltage source 260 is coupled between the voltage adjustment circuit 250 and a reference voltage (ie, a ground voltage). The voltage source 260 is used to provide a reference voltage V _DD . As shown in FIG. 2, the source terminal N _{S of the} transistor MD3 is coupled to the buffer 56_1 of the control logic circuit 156. The buffer 156_1 receives the PWM signal, the buffer 156_1 generates and transmits the control signal CTRL to the transistor MD1. Brake extreme. By providing the transistor MD3 with sufficient current to provide stable energy to the bootstrap capacitor 220, the control logic circuit 156 can easily control the voltage level of the gate extreme of the transistor MD1, so that the voltage level of the gate extreme of the transistor MD1 is increased. To the input voltage V _in to solve the problems mentioned in the prior art.

FIG. 3 is a schematic diagram of a clamping circuit 210 according to an embodiment of the present invention. As shown in FIG. 3, the clamp circuit 210 includes a plurality of clamp transistors CT ₁ -CT _n , wherein each of the plurality of clamp transistors CT ₁ -CT _n is implemented by a diode-type transistor. For example, the gate terminal and the drain plurality of clamping transistor CT ₁ -CT terminal of each of the _n coupled to each other, and a plurality of clamping transistor CT ₁ -CT _n connected in series. In this embodiment, each of the plurality of clamp transistors CT ₁ -CT _n has the same threshold voltage V _t , and the voltage between the gate terminal N _{G of the} transistor MD 3 and the switching terminal N _SW is the same. The potential difference is NV _t . In other embodiments, the threshold voltage V _t of each of the plurality of clamp transistors CT1-CTn is not limited to be the same. It should be noted that the reference voltage V _DD is designed to be larger than the potential difference NV _t between the gate terminal N _{G of the} transistor MD3 and the switching terminal N _SW , that is, V _DD > NV _t . According to the bootstrap circuit 105 disclosed in the embodiment of the present invention, the bootstrap capacitor 220 can be charged in the following states:

(1) When the voltage level V _{SW of the} switching terminal N _SW is greater than zero and the voltage value of the voltage level V _SW plus the potential difference NV _t is smaller than the reference voltage V _DD , that is, V _SW > 0, V _SW + NV _t <V _DD The voltage across the bootstrap capacitor 220 is V _DD -V _SW -V _GS , where V _GS is the potential difference between the gate terminal N _G and the source terminal N _S.

(2) When the voltage level V _SW on the switch end N _SW is greater than zero, and the voltage level V _SW a voltage value of the potential difference NV _t is greater than the reference voltage V _DD, i.e. _{V SW> 0, V SW +} NV t> V _DD , the voltage across the bootstrap capacitor 220 is NV _t -V _GS .

(3) When the voltage level V _SW at the switching terminal N _SW approaches zero, the voltage across the bootstrap capacitor 220 is V _DD -V _GS .

(4) when the voltage level of the switching terminal V _SW N _SW is less than zero, since the pressure across the V _DD -V _SW -V _GS 220 on the bootstrap capacitance.

Except for the case where the voltage level V _{SW is} close to the input voltage V _in , the bootstrap capacitor 220 can be charged under the conditions described above. Therefore, the performance of the bootstrap circuit 105 can be significantly improved. The problems mentioned in the prior art can be effectively solved.

In summary, the present invention discloses a bootstrap circuit that can effectively charge the bootstrap capacitor 220 to provide stable energy between the source terminal N _S and the switching terminal N _{SW of the} transistor MD3, and a control logic circuit. 156 can easily control the voltage level of the gate terminal of the transistor MD1, so that the voltage level of the gate terminal of the transistor MD1 is increased and is higher than the input voltage V _in .

The above are only preferred embodiments of the present invention, and any equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention. Accordingly, the foregoing disclosure should be construed as limited only by the boundaries of the appended claims.

Claims (18)

A bootstrap circuit applied to a first transistor of a DC-DC converter includes: a second transistor; a bootstrap capacitor having a first terminal and a second terminal, wherein the first terminal and A source terminal of the second transistor is coupled, the source terminal of the second transistor is coupled to the first transistor; a voltage regulating circuit is coupled to the gate terminal of the second transistor and a first Between two reference voltages; and a clamp circuit coupled between a gate terminal of the second transistor and the second end of the bootstrap capacitor, the clamp circuit is used to maintain the bootstrap capacitor A potential difference between the second terminal and the gate terminal of the second transistor; wherein a drain terminal of the second transistor is coupled to a first reference voltage, and a voltage of a gate terminal of the first transistor The maximum level is greater than the first reference voltage. The bootstrap circuit according to claim 1, further comprising: a voltage regulating circuit, wherein the voltage regulating circuit is coupled between the drain terminal of the second transistor and the first reference voltage. The bootstrap circuit according to claim 2, wherein the voltage regulating circuit includes a Schottky diode. The bootstrap circuit according to claim 1, further comprising: a driving current source coupled between the first reference voltage and the clamping circuit. The bootstrap circuit according to claim 1, wherein the voltage regulating circuit includes a Schottky diode. The bootstrap circuit according to claim 1, wherein the clamping circuit includes at least one clamping transistor. According to the bootstrap circuit of claim 6, a drain terminal of each of the clamp transistors is coupled to a gate terminal of the clamp transistor. The bootstrap circuit according to claim 6, further comprising: a voltage source configured to provide a second reference voltage, wherein the second reference voltage is greater than a preset value, and the preset value is these Sum of the threshold voltage of the clamp transistor. According to the bootstrap circuit described in claim 8, when the voltage level of the second terminal of the bootstrap capacitor is greater than zero, and the second reference voltage is less than the voltage level of the second terminal of the bootstrap capacitor, and A sum of the preset values, the bootstrap capacitor is charged with a voltage equal to the preset value minus a threshold voltage of the second transistor. A DC-to-DC converter includes a switching circuit including a first transistor and a second transistor. A switching terminal is coupled to a source terminal of the first transistor and a second transistor. Between the drain terminals, a drain terminal of the first transistor is coupled to a first reference voltage; an inductor-capacitor circuit includes at least one inductor and a capacitor, wherein the inductor-capacitor circuit is configured to pass through the switch circuit. Receiving an inductor current of the first reference voltage to provide energy to a subsequent load; a feedback circuit coupled to the inductor-capacitor circuit, wherein the feedback circuit is configured to generate an output voltage at an output terminal and generate an A feedback voltage; and a bootstrap circuit, including: a third transistor, wherein a source terminal of the third transistor is coupled to the first transistor; a clamping circuit is coupled to the third transistor Between a gate terminal of the third transistor and the switching terminal, wherein the clamping circuit is used to maintain the voltage level of the switching terminal; a voltage regulating circuit is coupled to the gate terminal of the third transistor and a Between two reference voltages; and a bootstrap capacitor, wherein the bootstrap capacitor is coupled between the source terminal and the switching terminal of the third transistor; wherein the voltage of the gate terminal of the first transistor is accurate The maximum value of the bits is greater than the first reference voltage. The DC-to-DC converter according to claim 10, wherein the bootstrap circuit further includes a voltage regulating circuit, wherein the voltage regulating circuit is coupled to a drain terminal of the third transistor and the first transistor. Between reference voltages. The DC-to-DC converter according to item 11 of the claim, wherein the voltage adjustment circuit includes a Schottky diode. The DC-to-DC converter according to claim 10, wherein the bootstrap circuit further includes: a driving current source coupled between the first reference voltage and the clamping circuit. The DC-to-DC converter according to claim 10, wherein the voltage adjustment circuit includes a Schottky diode. The DC-to-DC converter according to claim 10, wherein the clamping circuit of the bootstrap circuit includes at least one clamping transistor. The DC-to-DC converter according to claim 15, wherein a drain terminal of each of the clamp transistors is coupled to a gate terminal of the clamp transistor. The DC-to-DC converter according to claim 15, wherein the bootstrap circuit includes: a voltage source configured to provide a second reference voltage, wherein the second reference voltage is greater than a preset value, the The preset value is the sum of the threshold voltages of the clamping transistors. The DC-to-DC converter according to item 17, wherein when the voltage level of the switching terminal is greater than zero, and the second reference voltage is less than the sum of the voltage level of the switching terminal and a preset value, the The lifting capacitor is charged with a voltage equal to the preset value minus a threshold voltage of the third transistor.