TWI662779B - Inverter apparatus and method of controlling the same - Google Patents

Abstract

An inverter device includes a first switch, a second switch, a third switch, a fourth switch, a load detection unit, and a control unit. The first switch and the fourth switch form a first switch group, and the second switch and the third switch form a second switch group. The control unit selects a control mode such that both switches of the first switch group are uninterrupted, and at least one switch of the second switch group is off, or both switches of the second switch group are uninterrupted, and at least one of the first switch group The switches are off, or both switches of the first switch group and two switches of the second switch group are uninterrupted.

Description

Inverter device and control method thereof

The present invention relates to an inverter device and a control method thereof, and more particularly to an inverter device and a control method thereof capable of providing different modulation control based on a load operation state.

The drive control of a common inverter is usually implemented by a pulse-width modulation (PWM) signal generated by a modulation signal and a carrier signal.

Although the PWM control method can improve the efficiency of the inverter, the drive control of existing inverters usually only provides high-frequency switching control for the switching elements of the inverter through a single PWM modulation method. To operate according to different loads The state provides interactive (transition) control of different PWM modulation methods, which requires better and more complex PWM control methods, or even additional feedback control to improve the efficiency of the inverter. Therefore, the drive control of existing inverters The requirements for maintaining high efficiency and good total harmonic distortion (THD%) in the full load range cannot be achieved in a more economical and simple way. Correspondingly, the switching element will not be able to be selected for derating, which not only makes the circuit design lack flexibility and freedom, but also cannot reduce the circuit cost.

The purpose of the present invention is to provide an inverter device, which can solve the problem that the switching loss of the switch cannot be effectively reduced and the overall efficiency cannot be improved.

In order to achieve the purpose of disclosure, the inverter device provided by the present invention converts a DC input voltage to an AC output voltage to power a load. The inverter device includes a first switch, a second switch, a third switch, a fourth switch, a load detection unit, and a control unit. The first switch and the fourth switch form a first switch group, and the second switch and the third switch form a second switch group. The load detection unit detects an operation state of the load to provide a load signal. The control unit receives the load signal and provides a plurality of control signals to control the switches accordingly. The control unit selects the control mode according to the load signal so that both switches of the first switch group are not off, and at least one switch of the second switch group is off, or both switches of the second switch group are not off, and At least one switch of the first switch group is turned off, or both switches of the first switch group and two switches of the second switch group are uninterrupted.

With the proposed inverter device, the switching loss of the switch can be effectively reduced, the overall efficiency is improved, and the requirement of maintaining the output of the inverter device with low total harmonic distortion is maintained.

Another object of the present invention is to provide a control method for an inverter device, which solves the problem that the switching loss of the switch cannot be effectively reduced, so that the overall efficiency cannot be improved.

In order to achieve the purpose of disclosure, the control method for an inverter device provided by the present invention converts a DC input voltage to an AC output voltage to power a load. The inverter device includes a first switch, a second switch, a third switch, and a fourth switch, wherein the first switch and the fourth switch form a first switch group, and the second switch and the third switch form a second switch group. The control method of the inverter device includes: (a) detecting the operation state of the load to provide a load signal; (b) receiving a load signal and providing a plurality of control signals to control the switches accordingly; (c) selecting control based on the load signal The mode is to control both switches of the first switch group without interruption, and at least one switch of the second switch group is to switch off, or to control both switches of the second switch group to be uninterrupted, and the first switch At least one switch of the group is turned off, or both switches of the first switch group and two switches of the second switch group are uninterrupted.

The proposed control method of the inverter device can effectively reduce the switching loss of the switch, improve the overall efficiency, and maintain the output of the inverter device with a low total harmonic distortion requirement.

In order to further understand the technology, means and effects adopted by the present invention to achieve the intended purpose, please refer to the following detailed description and accompanying drawings of the present invention. It is believed that the purpose, features and characteristics of the present invention can be obtained in-depth and Specific understanding, however, the drawings are provided for reference and description only, and are not intended to limit the present invention.

Vi‧‧‧DC input voltage

Vo‧‧‧AC output voltage

20‧‧‧Load detection unit

30‧‧‧Control unit

40‧‧‧Filter

11‧‧‧The first switch bridge arm

12‧‧‧Second switch bridge arm

13‧‧‧The third switch bridge arm

Q1‧‧‧The first switch

Q2‧‧‧Second switch

Q3‧‧‧Third switch

Q4‧‧‧Fourth switch

S1‧‧‧first control signal

S2‧‧‧Second control signal

S3‧‧‧third control signal

S4‧‧‧ Fourth control signal

21‧‧‧The first switch bridge arm

22‧‧‧Second switch bridge arm

23‧‧‧diode bridge arm

31‧‧‧The first switch bridge arm

32‧‧‧Second switch bridge arm

Po‧‧‧ Neutral

Sd‧‧‧Load signal

90‧‧‧ load

Vcon1‧‧‧First Modified Wave

Vcon2‧‧‧Second Modified Wave

Vtri‧‧‧ Carrier

FIG. 1 is a circuit diagram of a first embodiment of an inverter device according to the present invention.

FIG. 2 is a waveform diagram of the first embodiment of the switching control of the inverter device of the present invention.

FIG. 3A is a waveform diagram of a second embodiment of the switch control of the inverter device of the present invention.

FIG. 3B is a waveform diagram of a third embodiment of the switching control of the inverter device of the present invention.

FIG. 3C is a waveform diagram of a fourth embodiment of the switch control of the inverter device of the present invention.

FIG. 3D is a waveform diagram of the fifth embodiment of the switch control of the inverter device of the present invention.

FIG. 4A is a waveform diagram of a sixth embodiment of the switching control of the inverter device of the present invention.

FIG. 4B is a waveform diagram of the seventh embodiment of the switch control of the inverter device of the present invention.

FIG. 5 is a waveform diagram of the eighth embodiment of the switch control of the inverter device of the present invention.

FIG. 6 is a waveform diagram of a ninth embodiment of the switching control of the inverter device of the present invention.

FIG. 7A is a waveform diagram of the tenth embodiment of the switch control of the inverter device of the present invention.

FIG. 7B is a waveform diagram of the eleventh embodiment of the switching control of the inverter device of the present invention.

FIG. 8 is a circuit diagram of a three-bridge arm AC-AC converter device according to the present invention.

FIG. 9 is a circuit diagram of a third embodiment of the inverter device according to the present invention.

FIG. 10 is a circuit diagram of a fourth embodiment of the inverter device according to the present invention.

FIG. 11 is a flowchart of a control method of an inverter device according to the present invention.

FIG. 12 is a flowchart of a first embodiment of an inverter device efficiency control mode according to the present invention.

FIG. 13 is a flowchart of a second embodiment of an inverter device efficiency control mode according to the present invention.

FIG. 14 is a flowchart of a third embodiment of an inverter device efficiency control mode according to the present invention.

FIG. 15 is a flowchart of a fourth embodiment of the inverter device efficiency control mode of the present invention.

FIG. 16 is a flowchart of a fifth embodiment of an inverter device efficiency control mode according to the present invention.

The technical content and detailed description of the present invention are described below with reference to the drawings.

Referring to FIG. 1, the inverter device of this embodiment is a full-bridge inverter device. The full-bridge inverter device converts a DC input voltage Vi into an AC output voltage Vo, and further supplies power to the load 90. In addition, an output filter 40 is provided on the output side of the full-bridge inverter device to filter the AC output voltage Vo. There are two input capacitors on the DC input side, which receive the DC input voltage Vi, and the two input capacitors are connected to the neutral point Po to maintain the voltage across the two capacitors equal to half of the DC input voltage Vi. Incidentally, the output filter 40 provided on the output side is not limited to the embodiment shown in FIG. 1, and may be implemented by other forms of filter circuits, such as an LC filter circuit.

The full-bridge inverter device includes two switching bridge arms 11 and 12, a load detection unit 20, and a control unit 30. Each switch bridge arm 11 and 12 is coupled in parallel, receives a DC input voltage Vi, and includes switches Q1 and Q2 and switches Q3 and Q4.

The load detection unit 20 is coupled to the load 90 and detects an operation state of the load 90 to provide a load signal Sd. For example, the load detection unit 20 may be a current sensor, which detects the output current flowing through the load 90, and further determines the operating state of the load 90. Based on this operating state, the control unit 30 determines the The control mode, for example, uses 30% of the rated load as the basis for switching the control mode, but it is not limited to this. However, for different circuit designs and applications, the current detector is not limited. Incidentally, the position where the load detection unit 20 is set is not limited to the embodiment shown in FIG. 1, and the load detection unit 20 may be provided at the front end of the output filter 40 (compared to that shown in FIG. 1). Rear end) or on either path of the two switch bridge arms 11, 12 can detect the current information and feedback the current information to the control unit 30.

In addition, in addition to the above example, 30% of the rated load is used as the basis for switching the control mode, and a buffer of "load hysteresis zone" can also be introduced as a judgment of the operating state of the load 90. Assumed load hysteresis It is in the range of 2%. Therefore, the switching control mode with a load of 31% or more of the rated load is one type, and the switching control mode with 29% or less of the rated load is another type. In other words, the 29% ~ 31% The load hysteresis zone is the buffer range to reduce the sensitivity of the load variation to the control switching method (because of changes in the load state).

For example, when the load shedding continues to increase from 29% below the rated load to 29% above the rated load but not more than 31% of the rated load, the control unit 30 maintains the original control mode; otherwise, when the load is drawn When the reduction continues from 31% above the rated load to 31% below the rated load but not below 29% of the rated load, the control unit 30 maintains the original control mode. Therefore, compared to a fixed value (such as the above 30%) load judgment, can reduce the sensitivity of the load variation to the load state change, especially when the load situation changes around the above 30%, the buffer of the "load hysteresis zone" can be used to greatly reduce the cause Frequent transitions of control switching modes corresponding to load state changes. In addition, instead of the above-mentioned load hysteresis zone being 2% as a limit, its buffer range can be adjusted according to the actual needs of circuit control. In summary, after the load detection unit 20 detects the operation state of the load 90, the provided load signal Sd includes information on the operation state of the load 90, that is, the operation state of the load 90 can be known according to the load signal Sd.

The control unit 30 receives the load signal Sd, determines the operating state of the load 90 according to the load signal Sd, and provides a control signal to control the switch correspondingly to control the full-bridge inverter device. Incidentally, the switching of the control mode is not limited to only the operating state of one load 90 as the switching basis, and the operating state of two or more loads 90 can also be used as the switching basis, for example, 30% of the rated load is drawn under load Switch the control mode once, and switch the control mode again when the load is 80% of the rated load. The details of the above-mentioned switch control will be described later.

Please refer to FIG. 2. As shown in FIG. 1, the two switching bridge arms 11 and 12 of the full-bridge inverter device are a first switching bridge arm 11 and a second switching bridge arm 12. The first switch bridge arm 11 includes a first switch Q1 and a second switch Q2, and the second switch bridge arm 12 includes a third switch Q3 and a fourth switch Q4. The first switch Q1 and the fourth switch Q4 form a first switch group, and the second switch Q2 and the third switch Q3 form The second switch group. An AC output voltage Vo is provided between the connection points of the first switch Q1, the second switch Q2 and the connection points of the third switch Q3 and the fourth switch Q4. The control unit 30 provides a first control signal S1 that controls the first switch Q1, a second control signal S2 that controls the second switch Q2, a third control signal S3 that controls the third switch Q3, and a fourth control signal that controls the fourth switch Q4. S4.

As shown in FIG. 2, the above-mentioned control signals (S1 to S4) are pulse width modulation (PWM) signals, which are generated by comparing the first modulation wave Vcon1 and the second modulation wave Vcon2 with the carrier Vtri, where: The first modulation wave Vcon1 and the second modulation wave Vcon2 are sine waves, and the carrier Vtri system is a triangle wave, but this is not a limitation. Specifically, the first control signal S1 is obtained by comparing the first modulation wave Vcon1 with the carrier Vtri: when the first modulation wave Vcon1 is greater than the carrier Vtri, the first control signal S1 is at a high level; when the first modulation When the wave Vcon1 is smaller than the carrier Vtri, the first control signal S1 is at a low level, and the first control signal S1 obtained by this comparison is a first high-frequency switching signal. Furthermore, the second control signal S2 is a control signal complementary to the level of the first high-frequency switching signal. Similarly, the third control signal S3 is obtained by comparing the second modulation wave Vcon2 with the carrier Vtri: when the second modulation wave Vcon2 is greater than the carrier Vtri, the third control signal S3 is at a high level; when the second modulation When the wave Vcon2 is smaller than the carrier Vtri, the third control signal S3 is at a low level, and the third control signal S3 obtained by this comparison is a second high-frequency switching signal. Furthermore, the fourth control signal S4 is a control signal complementary to the level of the second high-frequency switching signal. In addition, the level of the control signal obtained after the modulation wave is compared with the carrier can also be reversed. For example, when the modulation wave is larger than the carrier, the control signal is at a low level; when the modulation wave is smaller than the carrier, the control signal is High level. It is worth mentioning that FIG. 2 is a conventional control method of unipolar voltage switching. Although the following description takes the control method of unipolar voltage switching as an example, it is not limited to this. The generation of control signals can also be used. Bipolar voltage switching method.

When the control unit 30 determines that the control mode does not need to perform efficiency optimization control according to the load signal Sd (for example, the load of the load 90 is lower than 30% of the rated load), the control unit 30 outputs the first control signal S1 as a first high-frequency switching signal, The third control signal S3 is a second high-frequency switching signal and a second control The signal S2 is a switching signal complementary to the level of the first high-frequency switching signal and the fourth control signal S4 is a switching signal complementary to the level of the second high-frequency switching signal. Thereby, the output waveform can be maintained in a sine wave in a light-load operation state, and has a better total harmonic distortion (THD%).

As load shedding increases, on the basis that the quality of the output waveform can be maintained as acceptable, efficiency optimization control is performed to reduce the high-frequency switching control of the switching elements of the inverter, while simultaneously improving the efficiency of the inverter.

As shown in FIG. 3A, compared with FIG. 2, during the positive half-cycle operation, the second control signal S2 is turned off; and when the negative half-cycle operation is performed, the fourth control signal S4 is turned off. As shown in FIG. 3B, compared with FIG. 2, during the positive half-cycle operation, the third control signal S3 is made to be an off signal; during the negative half-cycle operation, the first control signal S1 is made to be an off signal. As shown in FIG. 3C, compared to FIG. 2, during the positive half-cycle operation, the second control signal S2 is made to be an off signal; during the negative half-cycle operation, the first control signal S1 is made to be an off signal. As shown in FIG. 3D, compared to FIG. 2, during the positive half-cycle operation, the third control signal S3 is turned off; when the negative half-cycle operation is performed, the fourth control signal S4 is turned off.

In summary, the control mode shown in FIGS. 3A to 3D is an efficiency optimization control, that is, both switches of the first switch group maintain high-frequency switching as shown in FIG. 2, and one of the switches of the second switch group is turned off. , The other switch is high-frequency switching, or both switches of the second switch group maintain high-frequency switching as shown in FIG. 2, and one of the switches of the first switch group is off, and the other switch is high-frequency switching. Moreover, in FIGS. 3A to 3D, compared to the control waveform shown in FIG. 2, the generation of the shutdown signal can be switched by external control or firmware programming to the original high frequency in FIG. The control signal is shielded or similar to make its output a shutdown signal.

It is worth mentioning that in the switching control used in Figs. 3A to 3D and Figs. 4A and 4B (described later), the duty cycle may be changed immediately because the pulse width modulation signal has not ended at the current period. Performing switching control results in waveform distortion at the zero crossing of the output waveform. Therefore, the pulse width modulation signal can be used to change the duty cycle for switching control at the end of the current cycle, which can effectively improve the waveform distortion.

Please refer to FIG. 4A. As the load continues to increase (for example, the load of load 90 is greater than 80% of the rated load), it can also be maintained by reducing the high-frequency switching control of the switching elements of more inverters. The quality of the output waveform and the efficiency of the inverter are improved.

In combination with the control waveform of Figure 2, in order to reduce the high-frequency switching of more switches, during the positive half-cycle operation, the second control signal S2 and the third control signal S3 are off signals (also through the aforementioned external control or firmware) In the programming mode, it is set in a masking or similar manner, which will not be particularly emphasized later, that is, the second switch Q2 and the third switch Q3 (that is, the second switch group) are controlled to be turned off. According to this, under the positive half-cycle operation, the first switch Q1 and the fourth switch Q4 (that is, the first switch group) are controlled only by high-frequency switching to complete the control of the positive half-cycle. During the negative half-cycle operation, the control unit 30 controls the first switch Q1 and the fourth switch Q4 (that is, the first switch group) to be turned off. According to this, under the negative half-cycle operation, the load 90 is switched only through high frequency The second switch Q2 and the third switch Q3 (that is, the second switch group) are controlled to complete the negative half-cycle control.

Please refer to FIG. 4B, which is another control waveform corresponding to FIG. 4A. When the control unit 30 is operating in the positive half cycle, the first control signal S1 and the fourth control signal S4 are turned off signals, and the second control signal S2 and the third control signal S3 maintain the high-frequency switching as shown in Figure 2. During the negative half-cycle operation, the second control signal S2 and the third control signal S3 are turned off, and the first control signal S1 and the fourth control are switched off. The signal S4 maintains the high-frequency switching as shown in FIG. 2 to reduce the high-frequency switching of more switches.

In summary, during positive half-cycle operation and negative half-cycle operation, the control unit 30 only switches and controls the two switching elements at high frequency, thereby reducing the high-frequency switching control of the switching elements of more inverters. In this way, the DC input voltage Vi can be used to supply the AC output voltage Vo to the load 90, and has the effects of reducing switching losses and improving efficiency.

Please refer to FIG. 5, which is another way of generating control signals. The control signals (S1 ~ S4) are pulse width modulation (PWM) signals. Similarly, the first modulation wave Vcon1 and the second modulation wave are transmitted. The comparison between Vcon2 and the carrier Vtri can be referred to the description of FIG. 2, and will not be repeated here. However, the biggest difference between FIG. 5 and FIG. 2 is that the minimum value of the carrier Vtri of the former (ie, FIG. 5) is zero, and the carrier Vtri of the latter (ie, FIG. 2) is positive and negative symmetrical to zero. Thereby, the waveforms of the control signals (S1 to S4) shown in FIG. 5 can be obtained by comparing the first modulated wave Vcon1, the second modulated wave Vcon2, and the carrier Vtri.

As shown in FIG. 1, when the control unit 30 determines that it does not need to perform efficiency optimization control based on the load signal Sd, in the positive half-cycle operation, the first control signal S1 is the first high-frequency switching signal and the fourth control signal S4 is The first low-frequency on signal, the second control signal S2 are switching signals complementary to the level of the first high-frequency switching signal, and the third control signal S3 is an off signal. In the negative half-cycle operation, the second control signal S2 is a second low-frequency on signal, the third control signal S3 is a second high-frequency switching signal, the first control signal S1 is an off signal, and the fourth control signal S4 is A switching signal complementary to the level of the second high-frequency switching signal. It is worth mentioning that the “low frequency” mentioned in the present invention refers to a frequency of about 60 Hz (or 50 Hz), but is not limited thereto; and the “high frequency” refers to a frequency of about 20 kHz or 10 kHz relative to the “low frequency” Of course, this is not a limitation.

As load shedding increases, efficiency optimization control can be performed to reduce the high-frequency switching control of the switching elements of the inverter, which can also maintain the quality of the output waveform and improve the efficiency of the inverter.

Please refer to FIG. 6. Compared with FIG. 5, in order to reduce the high-frequency switching of more switches, during the positive half-cycle operation, the second control signal S2 is an off signal, that is, the second switch Q2 and the third switch. Q3 (that is, the second switch group) is turned off. According to this, during the positive half-cycle operation, the first switch Q1 and the low-frequency on-control fourth switch Q4 are controlled only by high-frequency switching to complete the control of the positive half-cycle. During negative half-cycle operation, the fourth control signal S4 is an off signal, that is, the first switch Q1 and the fourth switch Q4 (that is, the first switch group) are controlled to be in an off state. According to this, under the negative half-cycle operation, the third switch Q3 and the low-frequency on-control second switch Q2 are controlled only by high-frequency switching to complete the negative half-cycle control.

Please refer to FIG. 7A. According to the signal control waveform shown in FIG. 5, during the positive half cycle operation, the control of the first control signal S1, the second control signal S2, the third control signal S3, and the fourth control signal S4 is maintained. Waveform; during negative half-cycle operation, the first control signal S1 and the third control signal S3 are further interchanged, the second control signal S2 and the fourth control signal S4 are interchanged, and the third control signal S3 and the fourth The control waveform of the control signal S4 is inverted. Therefore, during positive and negative half-cycle operation, at least one of the third control signal S3 and the fourth control signal S4 is controlled as an off signal, that is, the third control signal S3 is controlled to be off during a positive half-cycle operation. Signal, during the negative half-cycle operation, the fourth control signal S4 is controlled to be an off signal (as shown in FIG. 7A); or another control waveform may be deformed as follows: FIG. 7A, and then the first control signal S1 and the third The control signal S3 is interchanged, and the second control signal S2 is interchanged with the fourth control signal S4 (not shown).

Please refer to FIG. 7B. Compared with FIG. 7A, the switching element control is optimized for efficiency. During positive half-cycle operation, the second control signal S2 is further switched from high-frequency to off signal, and during negative half-cycle operation, the first control signal S1 is further changed from high-frequency switch to off. Off signal, thereby reducing high-frequency switching of the switching element, and achieving the purpose of efficiency optimization.

Referring to FIG. 8, this is a three-bridge arm AC-AC converter device, which includes an AC-DC conversion stage composed of a third switch bridge arm 13 and a first switch bridge arm 11, a first switch bridge arm 11 and A DC-AC conversion stage (ie, an inverter device) composed of the second switching bridge arm 12, a load detection unit 20, and a control unit 30. The first switch bridge arm 11 is a common bridge arm of the AC-DC conversion stage and the inverter device. The neutral line of the AC input voltage (Neutral) and the neutral line of the AC output voltage are connected to the two switches in the common bridge arm. Common connection point.

According to the operating state of the load 90, the inverter device in the three-bridge arm AC-to-AC converter device can be controlled by a switch as shown in FIG. 7A or FIG. 7B on the common bridge arm (that is, the first switch bridge arm 11). It is a low-frequency operation, and the third switch Q3 and the fourth switch Q4 of the first switch bridge arm 11 are controlled in a control mode in which one switch in each of the positive and negative half cycles is off. The details are as follows: Bridge arm structure The first switch bridge arm 11 in the AC-AC converter device is a common bridge arm between the AC-DC conversion stage and the inverter device, so the third switch Q3 and the fourth switch in the first switch bridge arm 11 The control signal of Q4 must be matched with the AC waveform of the input terminal so that when the input terminal AC current is positive half cycle (the voltage is greater than zero), the upper switch of the common bridge arm (ie the third switch Q3) needs to be turned off, and the input terminal AC voltage When it is a negative half cycle (the voltage is less than zero), the lower switch of the common bridge arm (that is, the fourth switch Q4) needs to be turned off.

As shown in FIG. 9, it is an inverter device according to a third embodiment, which is a neutral point clamped (NPC) inverter device, which includes a first switch bridge arm 21 and a second switch bridge. The arm 22, the diode bridge arm 23, the load detection unit 20, and the control unit 30. The first switch bridge arm 21 includes a first switch Q1 and a second switch Q2, and the second switch bridge arm 22 includes a third switch Q3 and a fourth switch Q4. One end of the diode bridge arm 23 is coupled to the connection point of the first switch Q1 and the fourth switch Q4, and the other end of the diode bridge arm 23 is coupled to the connection point of the second switch Q2 and the third switch Q3. An AC output voltage Vo is provided between the connection point of the second switch Q2 and the fourth switch Q4 and the ground point.

When the control unit 30 determines that it needs to perform efficiency optimization control according to the operating state of the load 90, it controls one of the switches of the first switch group to be switched at a high frequency, the other switch to be turned on at a low frequency, and the two switches of the second switch group Both are turned off, or one switch of the second switch group is switched at high frequency, the other switch is turned on at low frequency, and both switches of the first switch group are turned off, as shown in FIG. 6.

As shown in FIG. 10, it is an inverter device according to a fourth embodiment, which is a T-type neutral point clamped (T-type NPC) inverter device, which includes a first switch The bridge arm 31, the second switch bridge arm 32, the load detection unit 20, and the control unit 30. The first switch bridge arm 31 is coupled to the second switch bridge arm 32. The first switch bridge arm 31 includes a first switch Q1 and a second switch Q2, and the second switch bridge arm 32 includes a third switch Q3 and a fourth switch Q4. An AC output voltage Vo is provided between a common connection point of the first switch Q1, the second switch Q2, and the third switch Q3 and a ground point.

When the control unit 30 determines that it needs to perform efficiency optimization control according to the operating state of the load 90, it controls one of the switches of the first switch group to be switched at a high frequency and the other switch to be turned on at a low frequency, and Both switches of the second switch group are turned off, or one switch of the second switch group is switched at high frequency, and the other switch is turned on at low frequency, and both switches of the first switch group are turned off, as shown in Figure 6. Show.

It is worth mentioning that the switching control strategy shown in FIGS. 2 to 7B can be applied to the inverter device of the full-bridge architecture shown in FIG. 1; the switching control strategy shown in FIGS. 5 and 6 can be applied to FIG. 9. The neutral point clamped inverter device shown and the T-type neutral point clamped inverter device shown in FIG. 10; the switch control shown in FIGS. 3D, 4A, 6, 7, 7A, and 7B The strategy can be applied to the inverter device in the three-bridge arm AC-to-AC converter device shown in FIG. 8.

In summary, the switching control of different PWM modulation modes is provided according to the operating state of the load. The main spirit of the switching element control optimized for efficiency is: during the positive half cycle, the control signal originally output by the first switch group is maintained, and the second The switch group can selectively turn off one of the control signals or turn it off completely. In the negative half cycle, the control signal originally output by the second switch group is maintained, and the first switch group can selectively turn off one of them. Control signal or all-off; or, during the positive half cycle, the control signal originally output by the second switch group is maintained, and the first switch group can selectively turn off one of the control signals or all-off, and in the negative half cycle In this case, the control signal originally output by the first switch group is maintained, and the second switch group can selectively turn off one of the control signals or turn it off completely.

It is worth mentioning that for the same pulse width modulation signal generation method, FIGS. 3A to 3D and FIGS. 4A and 4B are the optimized control of FIG. 2, FIG. 6 is the optimized control of FIG. 5, and FIG. 7B is the optimization of FIG. 7A. The control can actually be controlled in three stages according to the load operation status (for example: Figure 2 → Figure 3A ~ Figure 3D → Figure 4A, Figure 4B), or two-stage control (for example: Figure 2 → Figure 4A, Figure 4B) , Or Figure 3A ~ Figure 3D → Figure 4A, Figure 4B, or Figure 2 → Figure 3A ~ Figure 3D, or Figure 5 → Figure 6, or Figure 7A → Figure 7B), or only use a single control mode (Figure 2 ~ Figure 7B). However, it is not limited to this, and it is also possible to use control waveforms generated by different width modulation signal generation methods to match (for example: when the inverter device can work normally, use any of Figure 2 ~ 7B One or two or more control waveforms are used for matching), thereby achieving the purpose of efficiency optimization.

In addition, the first control signal S1 and the second control signal S2 in the control signal waveform of FIG. 7B and the further optimized control signal waveform of FIG. 7B obtained from the control signal waveform of FIG. When switching from one time to another, they are only concerned with two states of off or low-frequency on. High-frequency switching does not occur. Therefore, the specification of the corresponding switch can be reduced, thereby reducing the circuit cost.

Please refer to FIG. 11, the control method is applicable to a full-bridge inverter device, an inverter device in a three-bridge arm AC-AC converter device, a neutral point clamped inverter device, and T-type neutral point clamped inverter device.

The steps of the control method include: first, detecting an operating state of the load to provide a load signal (S10). Then, the load signal is received and a plurality of control signals are provided to control the switches accordingly (S20). Finally, according to the load signal, the control mode is selected such that both switches of the first switch group are disconnected, and at least one switch of the second switch group is off, or both switches of the second switch group are disconnected, and the first At least one switch of the switch group is turned off, or both switches of the first switch group and the two switches of the second switch group are controlled uninterrupted (S30).

As shown in FIG. 12, one of the control modes of step (S30) may be: controlling both switches of the first switch group to be high-frequency switching, and controlling both switches of the second switch group to be off, or controlling the second switch Both switches of the group are high-frequency switching, and both switches of the first switch group are turned off (S31). For a description, see FIG. 4A and FIG. 4B.

As shown in FIG. 13, one of the control modes of step (S30) may be: controlling both switches of the first switch group to switch at high frequency, and one of the switches of the second switch group is off, and the other switch is high Frequency switching, or both switches controlling the second switch group are high-frequency switching, and one switch of the first switch group is off, and the other switch is high-frequency switching (S32). See Figure 3A ~ Figure 3D for cooperation. instruction of.

As shown in FIG. 14, one of the control modes of step (S30) may be: controlling the two switches of the first switch group and the two switches of the second switch group are high-frequency switching (S33). .

As shown in FIG. 15, one of the control modes of step (S30) may be: controlling one of the switches of the first switch group to be switched at a high frequency, and the other switch to be turned on at a low frequency, and both switches of the second switch group are to be turned off Turn off, or control one switch of the second switch group to switch at high frequency, and the other switch to switch on at low frequency, and both switches of the first switch group are turned off (S34). For a description, see Figure 6 and Figure 7B. .

As shown in FIG. 16, one of the control modes of step (S30) may be: controlling one of the switches of the first switch group to be switched at high frequency, the other switch to be turned on at low frequency, and one of the switches of the second switch group to be off Off, the other switch is turned on at high frequency, or one of the switches in the second switch group is turned on at high frequency, the other switch is turned on at low frequency, and one switch in the first switch group is turned off, and the other switch The high-frequency switching (S35) can cooperate with the description with reference to FIG. 5 and FIG. 7A. In summary, the inverter device and the control method thereof according to the present invention can achieve the requirements of effectively reducing the switching loss of the switch, improving the overall efficiency, and maintaining the output of the inverter device with low total harmonic distortion.

The above are only detailed descriptions and drawings of the preferred embodiments of the present invention, but the features of the present invention are not limited thereto, and are not intended to limit the present invention. The scope of the present invention shall be in the scope of the following patent applications. For the purposes of this disclosure, all embodiments that are within the spirit of the scope of the present invention and similar changes should be included in the scope of the present invention. Any person skilled in the art can easily consider the changes or modifications in the field of the present invention. Both can be covered by the patent scope of this case.

Claims (15)

An inverter device converts a DC input voltage to an AC output voltage to power a load. The inverter device includes a first switch, a second switch, a third switch, and a fourth switch. The first switch and the fourth switch form a first switch group, the second switch and the third switch form a second switch group; a load detection unit detects the operation state of the load, and according to the load's The operating state provides a load signal; and a control unit that receives the load signal and provides a plurality of control signals to control the switches accordingly; wherein the control unit selects a control mode according to the load signal for both switches of the first switch group without Off, and at least one switch of the second switch group is off, or both switches of the second switch group are uninterrupted, and at least one switch of the first switch group is off, or the first switch group The two switches of and the two switches of the second switch group are uninterrupted. According to the inverter device described in the first item of the patent application scope, wherein one of the control modes is that both switches of the first switch group are high-frequency switching, and both switches of the second switch group are off, Alternatively, both switches of the second switch group are switched at high frequency, and both switches of the first switch group are turned off. The inverter device according to item 1 of the scope of patent application, wherein one of the control modes is that both switches of the first switch group are high-frequency switching, and one of the switches of the second switch group is off, The other switch is high-frequency switching, or both switches of the second switch group are high-frequency switching, and one switch of the first switch group is off, and the other switch is high-frequency switching. The inverter device according to item 1 of the scope of the patent application, wherein one of the control modes is that the two switches of the first switch group and the two switches of the second switch group are high-frequency switching. The inverter device according to item 1 of the patent application scope, wherein one of the control modes is that one of the switches of the first switch group is switched at a high frequency, the other switch is switched at a low frequency, and the Both switches are turned off, or one switch of the second switch group is switched at high frequency, the other switch is turned on at low frequency, and both switches of the first switch group are turned off. The inverter device according to item 1 of the patent application scope, wherein one of the control modes is that one of the switches of the first switch group is switched at a high frequency, the other switch is switched at a low frequency, and the One of the switches is off, the other is high-frequency switching, or one of the switches of the second switch group is high-frequency switching, the other switch is of low-frequency conduction, and one of the switches of the first switch group is off , The other switch is high frequency switching. The inverter device according to item 1 of the scope of patent application, wherein the first switch and the second switch form a first switch bridge arm, and the third switch and the fourth switch form a second switch bridge arm; The first switch bridge arm is coupled in parallel with the second switch bridge arm; the AC output voltage is provided between connection points of the first switch, the second switch, and connection points of the third switch, and the fourth switch. The inverter device according to item 1 of the scope of patent application, further comprising: a diode bridge arm, one end of the diode bridge arm is coupled to the connection point of the first switch and the fourth switch, and the two The other end of the pole bridge arm is coupled to the connection point of the second switch and the third switch; the AC output voltage is provided between the connection point of the second switch, the fourth switch and a ground point. The inverter device according to item 1 of the scope of patent application, wherein the first switch and the second switch form a first switch bridge arm, and the third switch and the fourth switch form a second switch bridge arm; The first switch bridge arm is coupled to the second switch bridge arm; the AC output voltage is provided between a connection point of the first switch, the second switch, the third switch, and a ground point. A control method for an inverter device. The inverter device converts a DC input voltage into an AC output voltage to power a load. The inverter device includes a first switch, a second switch, a third switch, and A fourth switch, wherein the first switch and the fourth switch form a first switch group, the second switch and the third switch form a second switch group, and a control method of the inverter device includes: (a ), Detecting the operating state of the load, and providing a load signal according to the operating state of the load; (b) receiving the load signal and providing a plurality of control signals to control the switches accordingly; and (c), according to the load The signal selects a control mode such that both switches of the first switch group are disconnected, and at least one switch of the second switch group is off, or both switches of the second switch group are disconnected, and the first At least one switch of a switch group is turned off, or both switches of the first switch group and the two switches of the second switch group are uninterrupted. According to the control method of the inverter device according to item 10 of the scope of patent application, one of the control modes of step (c) includes: controlling both switches of the first switch group to be high-frequency switching, and the second Both switches of the switch group are turned off, or both switches controlling the second switch group are switched at high frequency, and both switches of the first switch group are turned off. According to the control method of the inverter device according to item 10 of the scope of patent application, one of the control modes of step (c) includes: controlling both switches of the first switch group to be high-frequency switching, and the second One switch of the switch group is off, and the other switch is high-frequency switch, or both switches controlling the second switch group are high-frequency switch, and one of the switches of the first switch group is off, and the other The switch is high frequency switching. The method for controlling an inverter device according to item 10 of the scope of patent application, wherein one of the control modes in step (c) includes: controlling both switches of the first switch group and both switches of the second switch group For high frequency switching. According to the method for controlling an inverter device according to item 10 of the scope of patent application, wherein one of the control modes of step (c) includes: controlling one of the switches of the first switch group to be a high-frequency switch and the other switch to be Low frequency is turned on, and both switches of the second switch group are turned off, or one of the switches of the second switch group is controlled for high frequency switching, and the other switch is turned on for low frequency, and both switches of the first switch group are turned on. Is off. According to the method for controlling an inverter device according to item 10 of the scope of patent application, wherein one of the control modes of step (c) includes: controlling one of the switches of the first switch group to be a high-frequency switch and the other switch to be Low frequency is turned on, and one of the switches of the second switch group is turned off, and the other switch is turned on by high frequency, or one of the switches of the second switch group is turned on by high frequency, and the other switch is turned on by low frequency, and the One of the switches of the first switch group is off, and the other switch is a high-frequency switch.