TWI662601B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A method for manufacturing a semiconductor device includes forming a separation wall between two fin structures, and the material of the separation wall is a dielectric material; forming a dummy gate structure above the separation wall and the two fin structures; Above the gate structure; removing the upper part of the interlayer dielectric layer to expose the dummy gate structure; replacing the dummy gate structure with a metal gate structure; and performing a planarization operation to expose the separation wall, thereby separating the metal gate structure The first gate structure and the second gate structure, wherein the first gate structure and the second gate structure are separated from each other by a separation wall.

Description

   Semiconductor element and manufacturing method thereof   

The present disclosure relates to a semiconductor integrated circuit, and more particularly, to a semiconductor device having a fin structure and a manufacturing method thereof.

As the semiconductor industry has evolved to nanometer (nm) technology process nodes pursuing higher component density, higher efficiency, and lower cost, the design of three-dimensional designs such as fin field effect transistors (Fin FETs) The development process encountered double challenges from manufacturing and design issues. Fin-type field-effect transistor elements generally include semiconductor fins with a large aspect ratio and channels and source / drain regions in which the semiconductor transistor elements are formed. Take advantage of the increased surface area of the channel and source / drain regions to form gates above and along the sides (e.g., packages) of the fin structure to produce faster, more reliable, and more controlled semiconductors Transistor element. Metal gate structures, together with high-dielectric constant-gate dielectrics with high dielectric constants, are commonly used in fin-type field-effect transistor devices, and are manufactured by gate replacement technology.

According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device includes forming a separation wall between two fin structures, and a material of the separation wall is a dielectric material; forming a dummy gate structure above the separation wall and the two fin structures; Forming an interlayer dielectric layer over the dummy gate structure; removing the portion above the interlayer dielectric layer to expose the dummy gate structure; replacing the dummy gate structure with a metal gate structure; and performing a planarization operation to expose the separation wall The metal gate structure is further divided into a first gate structure and a second gate structure, wherein the first gate structure and the second gate structure are separated from each other by a separation wall.

According to other embodiments of the present disclosure, a method for manufacturing a semiconductor device includes forming a first fin structure, a second fin structure, and a third fin structure. The second fin structure is substantially located on the substantially first fin structure. And the third fin structure, the material of each of the substantially first fin structure, the substantially second fin structure, and the substantially third fin structure is a semiconductor material and has an insulating cover layer; Isolate the insulating layer so that the substantially first fin structure, the substantially second fin structure, and the substantially third fin structure are embedded in the substantially isolated insulating layer, and the substantially insulating cover layer is exposed; forming a first shield The mask pattern is above the substantially isolating insulation layer. The first mask pattern has a first opening. The first opening is substantially above the second fin structure. The second fin structure is recessed by an etching process. And substantially the first mask pattern is used as an etching mask; a dielectric separation wall is formed on the substantially second fin structure of the recess; the substantially insulating insulating layer is recessed so that the The plurality of upper portions of the one fin structure and the third fin structure and the substantially upper portion of the dielectric separation wall are exposed; the first dummy gate structure is formed on the exposed substantially first fin structure, the exposed essence The upper third fin structure and the exposed substantially dielectric separation wall; forming an interlayer dielectric layer above the substantially first dummy gate structure; removing the upper portion of the substantially interlayer dielectric layer, thereby exposing the substantially first A dummy gate structure; replacing a substantially first gate structure with a metal gate structure; and performing a planarization operation to expose a substantially dielectric separation wall, thereby separating the substantially metal gate structure into a first gate structure And a second gate structure, wherein the substantially first gate structure and the substantially second gate structure are separated from each other by a substantially dielectric separation wall.

According to still other embodiments of the present disclosure, the semiconductor device includes a first gate electrode, a second gate electrode, and a dielectric separation wall. The first gate electrode is disposed above the isolation insulating layer, and the isolation insulating layer is formed on the substrate. The second gate electrode is disposed above the insulation layer. The first gate electrode and the second gate electrode extend in a first direction and are aligned along the first direction. The dielectric separation wall protrudes from the isolation insulating layer, is disposed between the first gate electrode and the second gate electrode, and separates the first gate electrode from the second gate electrode. The material of the dielectric separation wall is a dielectric material, the material of the isolation insulation layer is a dielectric material, and the dielectric material of the dielectric separation wall is different from the dielectric material of the isolation insulation layer.

10‧‧‧ substrate

20‧‧‧Semiconductor Fin

24‧‧‧ Pad oxide layer

25‧‧‧Mask layer

29‧‧‧ Etching Remains

30‧‧‧Isolation insulation

40‧‧‧ first mask layer

42‧‧‧ second mask layer

45‧‧‧ photoresist layer

46‧‧‧ opening

50‧‧‧ Dielectric separation wall

50H‧‧‧High part

50L‧‧‧Low part

51‧‧‧first cover

52‧‧‧ third mask layer

54‧‧‧ resist pattern

56, 58‧‧‧ opening

65‧‧‧Dummy gate dielectric layer

70‧‧‧ dummy gate electrode

72, 74‧‧‧Mask layer

76‧‧‧ sidewall spacer

80‧‧‧source / drain epitaxial layer

82‧‧‧ Etch stop layer

84‧‧‧ Interlayer dielectric layer

89‧‧‧Gate Pitch

90‧‧‧Gate structure

92‧‧‧Gate dielectric layer

94‧‧‧ work function adjustment layer

96‧‧‧main gate electrode

110‧‧‧ substrate

120‧‧‧Semiconductor Fin

122‧‧‧first cover

124‧‧‧second cover

130‧‧‧Isolation insulation

135‧‧‧oxide

140‧‧‧ sacrificial layer

142‧‧‧First dummy layer

143‧‧‧Second dummy layer

144‧‧‧The third dummy layer

150‧‧‧ Dielectric separation wall

150A‧‧‧The first dielectric separation wall

150B‧‧‧Second dielectric separation wall

152‧‧‧Mask layer

154‧‧‧Photoresist pattern

170‧‧‧ Fourth dummy layer

172, 174‧‧‧‧ layered structure

175‧‧‧Dummy gate electrode

176‧‧‧ sidewall spacer

180‧‧‧source / drain epitaxial layer

182‧‧‧etch stop layer

184‧‧‧Interlayer dielectric layer

189‧‧‧Gate Pitch

190‧‧‧Gate structure

192‧‧‧Gate dielectric layer

194‧‧‧Work function adjustment layer

196‧‧‧main gate electrode

F1‧‧‧First fin

F2‧‧‧Second Fin

F3‧‧‧ third fin

F4‧‧‧ Fourth fin

F11‧‧‧First Fin

F12‧‧‧Second Fin

F13‧‧‧The third fin

F14‧‧‧ Fourth fin

FP‧‧‧Basic Fin Pitch

H1, H2, H4 ‧‧‧ distance

H5, H6, H7, H11, H13, H14, H15, H17, H18, H19, H20‧‧‧ height

H31, H32 ‧‧‧ distance

H42‧‧‧height

L1‧‧‧line

P1, P2, P3, P31, P32, P33‧‧‧ pitch

S1, S2‧‧‧ distance

S11‧‧‧Width

S31, S32‧‧‧ distance

S41, S42, S43, S44, S45‧‧‧Pitch

W31, W32, W41‧‧‧Width

X, Y‧‧‧ directions

X1-X1, X2-X2, Y1-Y1, X11-X11, X12-X12‧‧‧ line segments

This disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with industry standard practice, features are not drawn to scale and are used for illustration purposes only. In fact, for the sake of clarity, the size of each feature can be arbitrarily increased or decreased.

FIG. 1A illustrates a perspective view of a semiconductor device according to some embodiments of the present disclosure.

FIG. 1B is a plan view of a semiconductor device according to some embodiments of the present disclosure.

FIG. 1C is a cross-sectional view taken along line X1-X1 in FIG. 1B.

FIG. 1D is a cross-sectional view taken along line X2-X2 in FIG. 1B.

FIG. 1E is a cross-sectional view taken along line Y1-Y1 in FIG. 1B.

FIG. 1F illustrates a cross-sectional view along line Y1-Y1 in FIG. 1B according to other embodiments of the present disclosure.

Figure 2A, Figure 3A, Figure 4A, Figure 5A, Figure 6A, Figure 7A, Figure 8A, Figure 9A, Figure 10A, Figure 11A, Figure 12A, Figure 13A, Figure 14A FIG. 15A, 16A, 17A, 18A, 19A, 20A, 21A, and 22A respectively illustrate semiconductor devices manufactured in different intermediates according to some embodiments of the present disclosure. Perspective view of the stage.

Figure 2B, Figure 3B, Figure 4B, Figure 5B, Figure 6B, Figure 7B, Figure 8B, Figure 9B, Figure 10B, Figure 11B, Figure 12B, Figure 13B, and Figure 14B Figures 15B, 16B, 17B, 18B, 19B, 20B, 21B, and 22B show Figures 2A, 3A, 4A, and 5A, respectively. Figure 6A, Figure 7A, Figure 8A, Figure 9A, Figure 10A, Figure 11A, Figure 12A, Figure 13A, Figure 14A, Figure 15A, Figure 16A, Figure 17A, 18A, 19A, 20A, 21A, and 22A are cross-sectional views taken along line X1-X1 of the corresponding 1B diagram.

Figures 12C and 14C show cross-sectional views along the corresponding line segments Y1-Y1 in Figure 1B and Figure 14A, respectively, in Figures 12A and 14A.

21C and 22C show plan views of FIGS. 21A and 22A, respectively.

Figure 23A, Figure 24A, Figure 25A, Figure 26A, Figure 27A, Figure 28A, Figure 29A, Figure 30A, Figure 31A, Figure 32A, Figure 33A, Figure 34A, Figure 35A Figure 36A, Figure 37A, Figure 38A, Figure 38A, Figure 39A, Figure 40A, Figure 41A, Figure 42A, Figure 43A, Figure 44A, and Figure 45 respectively show some implementations in accordance with this disclosure. A perspective view of a semiconductor device of a mode.

FIG. 23B is a plan view of a semiconductor device according to some embodiments of the present disclosure.

FIG. 23C is a cross-sectional view taken along line X11-X11 in FIG. 23B.

FIG. 23D is a cross-sectional view taken along line X12-X12 in FIG. 23B.

Figure 24B, Figure 25B, Figure 26B, Figure 27B, Figure 28B, Figure 29B, Figure 30B, Figure 31B, Figure 32B, Figure 33B, Figure 34B, Figure 35B, Figure 36B Figures, 37B, 38B, 39B, 40B, 41B, 42B, 43B, 44B, and 45B show Figures 24A, 25A, and 26A, respectively. Figure 27A, Figure 28A, Figure 29A, Figure 30A, Figure 31A, Figure 32A, Figure 33A, Figure 34A, Figure 35A, Figure 36A, Figure 37A, Figure 38A, 39A, 40A, 41A, 42A, 43A, 44A, and 45A are cross-sectional views taken along line X12-X12 of the corresponding 23B diagram.

Figures 36C, 39C, and 44C show plan views of Figures 36A, 39A, and 44A, respectively.

Figure 39D shows a side view along the axis of the direction Y in Figure 39A.

It should be understood that the following disclosure provides many different implementations or examples for implementing different features of the disclosure. Specific implementations or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the size of the device is not limited to the disclosed range or value, but may depend on the process conditions and / or desired properties of the device. In addition, in the following description, the formation of the first feature above or on the second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an insert that may be formed in the first and second features. An embodiment in which additional features are provided between the second features so that the first and second features may not be in direct contact. For conciseness and clarity, each feature can be arbitrarily drawn at different scales.

In addition, spatially relative terms, such as "below", "below", "lower", "above", "upper" and the like, may be used in this text to describe Draw the relationship between one element or feature and another element (or elements) or feature (or features). In addition to the directions depicted in the figures, spatially relative terms are intended to encompass different orientations of the elements in use or operation. Elements can be in different orientations (rotated 90 degrees or at other orientations) and spatially relative descriptors used herein can be interpreted the same. In addition, the term "made of" may mean "comprising" or "consisting of".

FIG. 1A, FIG. 1B, FIG. 1C, FIG. 1D, and FIG. 1E respectively show views of a fin field effect transistor (FinFET) of a semiconductor fin field effect transistor according to some embodiments of the present disclosure.

In the present disclosure, the two gate patterns extend along the direction X and are aligned, and are physically separated by a separation wall. The material of the aforementioned separation wall is a dielectric material. As shown in FIGS. 1A, 1B, 1C, 1D, and 1E, the semiconductor element includes a substrate 10, a semiconductor fin 20, and a gate structure 90. The bottom of the semiconductor fin 20 is embedded in the isolation insulating layer 30. The isolation insulating layer 30 is also referred to as a shallow trench isolation (STI) layer. In FIGS. 1A, 1B, 1C, 1D, and 1E, the four semiconductor fins 20 include a first fin F1, a second fin F2, a third fin F3, and a fourth fin. The fins F4 are disposed above the substrate 10, but the number of the semiconductor fins 20 is not limited to four. Some gate structures 90 are physically separated by a dielectric separation wall 50. The dielectric separation wall 50 is composed of a dielectric material. In some embodiments, the dielectric separation wall 50 is further covered by the first covering layer 51. On the opposite side of the gate structure 90, a side wall spacer 76 is provided. The gate structure 90 includes a gate dielectric layer 92, a work function adjustment layer 94, and a main gate electrode 96.

A portion of the semiconductor fin 20 that is not covered by the gate structure 90 is a source / drain (S / D) region. A source / drain (S / D) epitaxial layer 80 is formed on the source / drain region of the semiconductor fin 20, and an etch stop layer (ESL) 82 is formed on the source / drain An extremely epitaxial layer 80 is formed. In addition, an interlayer dielectric (ILD) layer 84 is formed to cover the source / drain structure.

In some embodiments, in FIGS. 1A, 1B, 1C, 1D, and 1E, the semiconductor fin 20 (also referred to as a fin structure) includes a first fin disposed in sequence. F1, the second fin F2, the third fin F3, and the fourth fin F4. The second fin F2 is a dummy fin on which the dielectric separation wall 50 is formed. In some embodiments, when the pitch P1 (pitch) between the first fin F1 and the second fin F2 is the base fin pitch FP, the distance between the first fin F1 and the third fin F3 The pitch P2 is twice the base fin pitch FP and the pitch P3 between the third fin F3 and the fourth fin F4 is three times or more the base fin pitch FP. In some embodiments, the fin pitch P1 is about 14 nanometers (nm) to about 30 nanometers (nm).

As shown in FIG. 1C and FIG. 1D, in some embodiments, the distance H1 between the etch stop layer 82 on the source / drain region and the upper surface of the interlayer dielectric layer 84 is about 14 nanometers. In the range of meters (nm) to about 30 nanometers (nm). In some embodiments, the distance H2 between the etch stop layer 82 on the dielectric separation wall 50 and the upper surface of the interlayer dielectric layer 84 is between about 20 nanometers (nm) and about 50 nanometers (nm). Within range. In some embodiments, the distance H3 between the work function adjustment layer 94 on the first fin F1 and the upper surface of the main gate electrode 96 is from about 14 nanometers (nm) to about 30 nanometers (nm). Within range. In some embodiments, the distance H4 between the top position of the first fin F1 and the upper surface of the main gate electrode 96 is in a range from about 18 nanometers (nm) to about 40 nanometers (nm).

In FIGS. 1A, 1B, 1C, 1D, and 1E, the minimum distance S1 between the dielectric separation wall 50 and the adjacent fins is substantially equal to the distance between the fins. The distance S1 may be a plurality of fin pitches. The width of the dielectric separation wall 50 is substantially equal to or slightly smaller than the width of the fins (eg, about 5 nanometers (nm) to about 10 nanometers (nm)).

The width of the dielectric separation wall 50 is in some embodiments from about 4 nanometers (nm) to about 8 nanometers (nm). The minimum distance S1 between the dielectric separation wall 50 and an adjacent fin (for example, the first fin F1 or the third fin F3) (visible in FIG. 1B and FIG. 1C) is about 100 Å in some embodiments. 8 nanometers (nm) to about 16 nanometers (nm). In addition, in some embodiments, the distance S2 between the third fin F3 and the etch stop layer 82, that is, the end of the gate structure is located from about 8 nanometers (nm) to about 16 nanometers (nm). Within range.

As shown in FIGS. 1C and 1D, the bottom of the dielectric separation wall 50 is located below the isolation insulating layer 30. In FIG. 1E, the line L1 corresponds to the upper surface of the isolation insulating layer 30. The dielectric separation wall 50 includes a separation portion 50H and a dummy portion 50L to avoid collapse as shown in FIG. 1E. The gate structure 90 extends above the dummy portion 50L of the dielectric separation wall 50 and generates a gate connection only on top of the metal gate. In this embodiment, there is a "valley" portion, which has a lower height than the dummy portion between the separation portion 50H and the dummy portion 50L.

In FIG. 1E, in some embodiments, the height H5 of the separation site 50H measured from the top position of the second fin F2 is in a range from about 80 nanometers (nm) to about 120 nanometers (nm) . In some embodiments, the height H6 of the dummy portion 50L measured from the top position of the second fin F2 is in a range from about 60 nanometers (nm) to about 100 nanometers (nm). In some embodiments, the height H7 of the bottom position of the dielectric separation wall 50 embedded in the isolation insulation layer 30 measured from the top position of the second fin F2 is from about 5 nanometers (nm) to about 30 nanometers. Within meters (nm).

The material of the dielectric separation wall 50 may be silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and metal oxide (for example, hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3 ) Or any suitable dielectric material. In some embodiments, silicon carbonitride (SiCN) is used as the dielectric separation wall 50.

FIG. 1F is another embodiment of the disclosure. In this embodiment, there is no "valley" portion between the separation portion 50H and the dummy portion 50L.

2A to 22C are schematic diagrams of a semiconductor device according to some embodiments of the present disclosure at different intermediate manufacturing stages. In FIGS. 2A to 22C, “A” (for example, FIG. 1A or 2A, etc.) is shown as a perspective view, and “B” (for example, FIG. 1B or 2B, etc.) is shown along A cross-sectional view corresponding to the direction X of the line segment X1-X1 in FIG. 1B is shown, and the “C” drawing (for example, FIG. 21C, etc.) is shown as a plan view. It should be understood that additional operations may be provided before, during, and after the process illustrated by FIGS. 2A to 22C, and for additional implementations of the method, some operations described below may be replaced or eliminated. The order of operations / processes is interchangeable.

In FIGS. 2A and 2B, the semiconductor fins 20 are formed above the substrate 10. To manufacture the fin structure, a mask layer is formed over the substrate 10 (for example, a semiconductor wafer) by, for example, a thermal oxidation process and / or a chemical vapor deposition (CVD) process. For example, the substrate 10 is a p-type silicon substrate having an impurity concentration, and the impurity concentration is in a range from about 1 × 10 ¹⁵ cm ^-3 and about 5 × 10 ¹⁵ cm ^-3 . In other embodiments, the substrate 10 is an n-type silicon substrate having an impurity concentration, and the impurity concentration is in a range from about 1 × 10 ¹⁵ cm ^-3 and about 5 × 10 ¹⁵ cm ^-3 .

Alternatively, the substrate 10 may include: another element semiconductor such as germanium; a compound semiconductor including a group IV-IV compound semiconductor such as silicon carbide (SiC) and silicon germanium (SiGe); and a compound semiconductor such as gallium arsenide (GaAs), gallium phosphide (GaP), gallium nitride (GaN), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), gallium phosphorus arsenide (GaAsP), aluminum nitride III-V of gallium (AlGaN), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium arsenide (GaInAs), gallium indium phosphide (GaInP) and / or indium gallium arsenide (GaInAsP) Group compound semiconductor; or any combination of the foregoing. In one embodiment, the substrate 10 is a silicon layer of a silicon-on insulator (SOI) substrate. An amorphous substrate (such as amorphous Si or amorphous SiC or an insulating material such as silicon oxide) can also be used as the substrate 10. The substrate 10 may include a region that has been appropriately doped with impurities (for example, P-type or N-type conductivity).

In some embodiments, the masking layer includes a pad oxide layer 24 (eg, silicon oxide) and a silicon nitride masking layer 25. The pad oxide layer 24 may be formed by using a thermal oxidation process or a chemical vapor deposition process. The silicon nitride mask layer 25 may be formed by a physical vapor deposition (PVD) process such as a sputtering method, a chemical vapor deposition (CVD) process, or a plasma enhanced chemical vapor deposition (plasma) process. -enhanced chemical vapor deposition (PECVD) process, atmospheric pressure chemical vapor deposition (APCVD) process, low-pressure chemical vapor deposition (LPCVD) process, high-density plasma chemical vapor deposition ( High density plasma CVD (HDPCVD) process, atomic layer deposition (ALD) process, and / or other processes.

In some embodiments, the thickness of the pad oxide layer 24 is in a range from about 2 nanometers (nm) to about 15 nanometers (nm), and the thickness of the silicon nitride masking layer 25 is in a range from about 2 nanometers. In the range of meters (nm) to about 50 nanometers (nm). A mask pattern is further formed over the mask layer. For example, the mask pattern is a photoresist pattern formed by a photo-etching method.

By using the mask pattern as an etching mask, a hard mask pattern of the pad oxide layer 24 and the silicon nitride mask layer 25 is formed.

The substrate 10 is patterned into the semiconductor fins 20 by using a hard mask pattern as an etching mask and by trench etching using a dry etching method and / or a wet etching method.

In one embodiment, the semiconductor fins 20 disposed above the substrate 10 are composed of the same material as the substrate 10 and continuously extend from the substrate 10. The semiconductor fin 20 may be intrinsic, or appropriately doped with n-type impurities or p-type impurities.

In the figure, four semiconductor fins 20 are provided. The semiconductor fin 20 is used for a p-type fin-type field effect transistor and / or an n-type fin-type field effect transistor. The number of the semiconductor fins 20 is not limited to four. This number can be as small as one or more than four. In addition, one of the plurality of dummy fin structures may be disposed adjacent to both sides of the semiconductor fin 20 to improve pattern fidelity in the patterning process. In some embodiments, the width of the semiconductor fin 20 is in a range from about 5 nanometers (nm) to about 30 nanometers (nm). In some embodiments, the width of the semiconductor fins 20 is in a range from about 7 nanometers (nm) to about 20 nanometers (nm). In some embodiments, the height H11 of the semiconductor fin 20 is in a range from about 100 nanometers (nm) to about 300 nanometers (nm). In some embodiments, the height H11 of the semiconductor fin 20 is in a range of about 50 nanometers (nm) to 100 nanometers (nm). When the height of the semiconductor fins 20 is not uniform, the height of the substrate 10 can be measured from a plane, and this plane corresponds to the average height of the semiconductor fins 20. In some embodiments, the height H12 of the mask pattern after the fin etch is between about 4 nanometers (nm) to about 50 (nm) nanometers.

In FIGS. 3A and 3B, an isolation insulating layer 30 is formed. An insulating material layer for forming the isolation insulating layer 30 is formed over the substrate 10 so as to completely cover the semiconductor fins 20.

For example, the insulating material of the isolation insulating layer 30 may be silicon dioxide. The aforementioned method for forming silicon dioxide includes, for example, a low-pressure chemical vapor deposition (LPCVD) process, a plasma chemical vapor deposition (plasma CVD) process, or a flow chemical vapor deposition ( flowable CVD) process. In a flowable chemical vapor deposition process, a flowable dielectric material is deposited instead of silicon oxide. A flowable dielectric material, as its name implies, can "flow" during deposition to fill gaps or gaps with high aspect ratios. Generally, various chemicals are added to the silicon-containing precursor to allow the deposited film to flow. In some embodiments, a nitrogen hydride bond is added. Examples of flowable dielectric precursors, especially flowable silicon oxide precursors, include silicate, siloxane, methyl silsesquioxane (MSQ), and hydrogen silsesquioxane (Hydrogen silsesquioxane (HSQ), methyl silsesquioxane / hydrogen silsesquioxane (MSQ / HSQ), perhydrosilazane (TCPS), perhydro-polysilazane; (PSZ), tetraethyl orthosilicate (TEOS), or silyl-amine, such as trisilylamine (TSA). These flowable silicon oxide materials are formed in a number of operating processes. After the flowable film is deposited, it is cured and subsequently annealed to remove unwanted elements to form silicon oxide. When unwanted elements are removed, the flowable film is densified and shrunk. In some embodiments, multiple annealing processes are performed. The flowable film can be cured and annealed more than once. The isolation insulating layer 30 may be spin-on-glass (SOG), silicon oxide (SiO), silicon oxynitride (SiON), silicon carbonitride (SiOCN), or fluorine-doped silicate glass (FSG). . The isolation insulating layer 30 may be doped with boron and / or phosphorus.

In addition, a planarization operation such as a chemical mechanical polishing (CMP) method is performed to expose the silicon nitride mask layer 25 as shown in FIGS. 3A and 3B.

In FIGS. 4A and 4B, the first mask layer 40 is formed on the isolation insulating layer 30, and the second mask layer 42 is formed on the first mask layer 40. The first masking layer 40 includes one or more layers of silicon nitride (SiN) and silicon oxynitride (SiON). The second mask layer 42 is composed of an amorphous or polycrystalline material of a group IV material, such as amorphous silicon or poly silicon, silicon germanium, or germanium. In some embodiments, the first masking layer 40 is silicon nitride (SiN) having a thickness of about 5 nanometers (nm) to about 30 nanometers (nm), and the second masking layer 42 is made of amorphous silicon. The amorphous silicon has a thickness of about 5 nanometers (nm) to about 30 nanometers (nm). The first mask layer 40 and the second mask layer 42 are formed by a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or any suitable thin film formation method.

In FIGS. 5A and 5B, a photoresist layer 45 is formed over the second mask layer 42 and is removed from the second fin by using a lithography and etching operation. A portion of the first mask layer 40 and the second mask layer 42 above F2.

In FIGS. 6A and 6B, the pad oxide layer 24 (which can be regarded as a mask layer) and the silicon nitride formed on the second fin F2 are removed by using a suitable etching operation through the opening 46. The mask layer 25 (can be regarded as a mask layer). By this etching, the top surface of the second fin F2 is exposed.

In FIGS. 7A and 7B, the second fin F2 is recessed by appropriate dry etching. With the etching, a U-shaped etching residual portion 29 is formed on the second fin F2, as shown in FIG. 7B.

In FIGS. 8A and 8B, the etching residue 29 is removed by suitable wet etching. In the stage of the manufacturing operation, the etch depth H13 of the second fin F2 is in a range from about 100 nanometers (nm) to about 300 nanometers (nm) in some embodiments.

In FIGS. 9A and 9B, a dielectric material of the dielectric separation wall 50 is formed. A blanket of a dielectric material is formed by a chemical vapor deposition process or an atomic layer deposition process, and then a chemical mechanical polishing or etch-back operation is performed. The dielectric separation wall 50 includes silicon nitride (SiN), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and metal oxides such as hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ) And alumina (Al ₂ O ₃ ) or one or more layers of any suitable dielectric material.

In some embodiments, the first cover layer 51 is formed before the dielectric material of the dielectric separation wall 50 is formed. The first cover layer 51 is made of, for example, oxygen Silicon oxide or other suitable dielectric materials may be formed by a chemical vapor deposition process or an atomic layer deposition process. The thickness of the first cover layer 51 is in a range of about 0.5 nanometers (nm) to about 2 nanometers (nm) in some embodiments.

In FIGS. 10A and 10B, the third mask layer 52 is formed above the isolation insulating layer 30, and a resist pattern 54 having an opening 56 is formed. The third mask layer 52 is composed of an amorphous or polycrystalline material of a group IV material, such as poly silicon or poly silicon, silicon germanium, or germanium. In some embodiments, the third mask layer 52 is composed of amorphous silicon having a thickness of about 5 nanometers (nm) to about 30 nanometers (nm). The size of the opening 56 is substantially equal to the pitch between the gates, and is located at a position where the gates are subsequently separated.

In FIGS. 11A and 11B, the third mask layer 52 is etched by using the resist pattern 54 (which may also be a photoresist pattern) as an etching mask, and then a gate pitch width of An opening 58 is formed in the three masking layers 52. The width S11 of the opening 58 in the direction Y is in a range from about 20 nanometers (nm) to about 50 nanometers (nm) in some embodiments. Subsequently, the resist pattern 54 is removed.

In FIGS. 12A, 12B, and 12C, a portion of the dielectric separation wall 50 is recessed to form a recess 62 by using the patterned third mask layer 52 as an etching mask. Subsequently, the third mask layer 52 is removed. By this recessed etching, the dielectric separation wall 50 has a recessed low portion 50L (also referred to as a dummy portion) and a non-recessed high portion 50H (also referred to as a divided portion) Off part), as shown in Figure 12C. In some embodiments, the amount of etch height H14 is in a range from about 20 nanometers (nm) to about 100 nanometers (nm).

In FIGS. 13A and 13B, the pad oxide layer 24 and the silicon nitride mask layer 25 are removed. With this operation, the isolation insulating layer 30 is also partially etched, and the dielectric separation wall 50 is partially exposed. At this stage of the manufacturing process, the protruding height H15 of the dielectric separation wall 50 (or the high portion without depression 50H) from the upper surface of the isolation insulating layer 30 is located from about 5 nanometers (nm) in some embodiments. To about 20 nanometers (nm). The height difference between the high portion 50H of the dielectric separation wall 50 and the first fin F1 or the third fin F3 is in a range from about 10 nanometers (nm) to about 40 nanometers (nm) in some embodiments. Inside. The difference height H17 between the second fin F2 and the first fin F1 or the third fin F3 is in some embodiments within a range from about 100 nanometers (nm) to about 300 nanometers (nm). In some embodiments, the height H18 of the high portion 50H is in a range from about 150 nanometers (nm) to about 400 nanometers (nm), and the height H19 of the low portion 50L is in a range from about 100 nanometers (nm) to In the range of about 300 nanometers (nm).

In FIGS. 15A and 15B, the isolation insulating layer 30 is further recessed so as to expose the first fin F1, the third fin F3 and the fourth fin F4, and the upper portion of the dielectric separation wall 50. Here, the recessed second fin F2 is not exposed and is still embedded in the isolation insulating layer 30. The first fin F1, the third fin F3, and the fourth fin F4 are exposed at a height H20 of about 50 nanometers (nm) to about 200 nanometers (nm) in some embodiments.

In FIGS. 16A and 16B, a dummy gate dielectric layer 65 is formed on the exposed fins and the dielectric separation wall 50. The dummy gate dielectric layer 65 is, for example, composed of silicon oxide having a thickness of about 0.5 nanometers (nm) to about 2 nanometers (nm) in some embodiments, and may be formed by a chemical vapor deposition process. And / or an atomic layer deposition process. A dummy gate dielectric layer 65 is also formed on the upper surface of the isolation insulating layer 30.

In FIGS. 17A and 17B, a dummy gate electrode layer is formed, and the dummy gate electrode layer is patterned by using a hard mask including a mask layer 72 and a mask layer 74 to form a dummy gate electrode. 70. At least one dummy gate electrode 70 is disposed above the low portion 50L of the first fin F1 and the third fin F3 and the dielectric separation wall 50, and at least one dummy gate electrode 70 is disposed at the first fin F1. And the third fin F3 and above the high portion 50H of the dielectric separation wall 50. In some embodiments, the mask layer 72 is composed of a silicon nitride-based material such as silicon nitride (SiN), and the mask layer 74 is composed of a silicon oxide based material such as silicon oxide (SiO2) Composed of.

In FIGS. 18A and 18B, the sidewall spacer 76 is formed on the opposite side of the dummy gate electrode 70. A blanket layer based on a silicon nitride based material (for example, silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbon nitride (SiCN)) is formed, and then anisotropic etching is performed. By this etching, the dummy gate dielectric layer 65 formed on the exposed fins is removed. In addition, in some embodiments, the exposed dielectric separation wall 50 is recessed. In this case, a structure as shown in FIG. 1E can be obtained. In other embodiments, the dielectric separation wall 50 is not recessed. In this case, a structure as shown in FIG. 1F is obtained.

In FIGS. 19A and 19B, a source / drain epitaxial layer 80 is formed on the exposed fins. The source / drain epitaxial layer 80 is epitaxially formed on the exposed fins, and includes silicon phosphide (SiP), silicon carbide (SiC), silicon carbide phosphide (SiCP), silicon boride (SiB), One or more crystalline layers of germanium (SiGe) and germanium (Ge). In some embodiments, a silicide layer is further formed over the source / drain epitaxial layer 80.

Subsequently, an etch stop layer (ESL) 82 is formed, and an interlayer dielectric layer 84 is formed in the gaps between the dummy gate electrodes 70 having sidewall spacers 76 and above the source / drain regions. The interlayer dielectric layer 84 may include silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon oxynitride (SiOCN), and fluorine-doped glass. silicate glass (FSG) or low-k dielectric material, and may be composed of a chemical vapor deposition process or other suitable processes. The insulating material of the dielectric separation wall 50 is different from the insulating materials of the isolation insulating layer 30 and the interlayer dielectric layer 84.

A planarization operation, such as an etch-back process and / or a chemical mechanical polishing process, is performed in order to expose the portions above the dummy gate electrode 70 and the dielectric separation wall 50. Subsequently, the dummy gate electrode 70 and the dummy gate dielectric layer 65 are removed to form a gate pitch 89, as shown in FIGS. 20A and 20B.

In FIGS. 21A, 21B, and 21C, a metal gate structure 90 including a gate dielectric layer 92 and a main gate electrode 96 (may also be a metal gate electrode layer) is formed in a gate pitch 89. . In some embodiments, the gate dielectric layer 92 includes, for example, silicon oxide, silicon nitride, or high-k dielectric material, other suitable dielectric materials. One or more layers of a material and / or a combination of dielectric materials. Examples of high dielectric constant dielectric materials include hafnium dioxide (HfO2), silicon oxide (HfSiO), silicon oxynitride (HfSiON,), tantalum oxide (HfTaO), titanium oxide (HfTiO), zirconium oxide (HfZrO), zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO ₂ -Al ₂ O ₃ ) alloy, other suitable high dielectrics High-k dielectric material and / or combinations thereof.

The body gate electrode 96 includes any suitable material, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum ( tantalum nitride), nickel silicide, cobalt silicide, titanium nitride (TiN), tungsten nitride (WN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), carbonitride Tantalum (TaCN), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), metal alloys, other suitable materials and / or combinations thereof.

In some embodiments, one or more work function adjustment layers 94 are also disposed between the gate dielectric layer 92 and the main gate electrode 96. The work function adjustment layer 94 is composed of a conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tantalum aluminum carbide (TaAlC), titanium carbide (TiC), tantalum carbide (TaC), cobalt (Co), aluminum (Al), single layer of titanium aluminide (TiAl), hafnium titanate (HfTi), titanium silicide (TiSi), tantalum silicide (TaSi) or titanium aluminum carbide (TiAlC), or two or more of them Of multiple layers. For n-channel fin field effect transistors, tantalum nitride (TaN), tantalum aluminum carbide (TaAlC), titanium nitride (TiN), titanium carbide (TiC), cobalt (Co), titanium aluminide (TiAl), titanium One or more of hafnium (HfTi), titanium silicide (TiSi), and tantalum silicide (TaSi) are used as the work function adjustment layer 94; and for p-channel fin field effect transistors, tantalum aluminum carbide (TiAlC), aluminum (Al) , One or more of titanium aluminum (TiAl), tantalum nitride (TaN), tantalum aluminum carbide (TaAlC), titanium nitride (TiN), titanium carbide (TiC), and cobalt (Co) as a work function adjustment layer 94. The work function adjustment layer 94 may be formed by an atomic layer deposition process, a physical vapor deposition process, a chemical vapor deposition process, an electron beam evaporation process, or other suitable processes. In addition, the successful function adjustment layer 94 may be formed separately for the n-channel fin-type field effect transistor and the p-channel fin-type field effect transistor that can use different metal layers.

When forming the metal gate structure 90, the gate dielectric layer 92, the work function adjustment layer 94, and the main gate electrode 96 (also may be a gate electrode layer) are formed by a suitable thin film forming method, for example, for the main gate The electrode 96 is formed by a chemical vapor deposition process or an atomic layer deposition process, and a chemical vapor deposition process for a metal layer, a physical vapor deposition process, an atomic layer deposition process, or an electroplating process, and subsequently performs a process such as chemical mechanical polishing A planarization operation is performed to remove excess material formed over the interlayer dielectric layer 84.

In FIGS. 22A, 22B, and 22C, the interlayer dielectric layer 84 and the metal gate structure 90 are further depressed by a planarization operation such as chemical mechanical polishing, thereby exposing the high portion of the dielectric separation wall 50. 50H.

In other embodiments, during the operation of FIGS. 20A and 20B, the dielectric separation wall 50 is exposed to separate the dummy gate structure into two sub-dummy gate structures, and in FIGS. 21A to 22C During operation, the two sub-dummy gate structures were replaced with metal gate structures, respectively.

As explained above, the dielectric separation wall 50 forms and forms a metal gate structure before the dummy gate structure. Therefore, the width of the dielectric separation wall 50 can be minimized, and the end sizes of the metal gate electrode and the fin structure can be enlarged.

It should be understood that the structure undergoes another complementary metal-oxide semiconductor (CMOS) process to form features such as interconnect vias, interconnect metal layers, passivation layers, and the like.

23A, 23B, 23C, and 23D illustrate views of a semiconductor fin field effect transistor according to other embodiments of the present disclosure. The same or similar materials, configurations, processes, and / or structures as those in FIGS. 1A to 22C may be applied to the following embodiments, and detailed descriptions may be omitted.

In the following embodiments, the distance between the dielectric separation wall 150 and the semiconductor fin 120 is substantially different. This distance can be defined by the thickness of the dummy layer. The dielectric separation wall 150 is located on the isolation insulating layer 130. A gate dielectric layer 192 (interface silicon oxide and high dielectric constant dielectric material) is deposited on the semiconductor fins 120 and the dielectric separation wall 150.

As shown in FIG. 23A, FIG. 23B, FIG. 23C, and FIG. 23D, the semiconductor element includes a substrate 110, a semiconductor fin 120, and a gate structure 190 (may also be a metal gate structure). The bottom of the semiconductor fin 120 is embedded in the isolation insulating layer 130, which is also referred to as shallow trench isolation (STI). In FIGS. 23A, 23B, 23C, and 23D, the four semiconductor fins 120, that is, the first fin F11, the second fin F12, the third fin F13, and the fourth fin F14, The number of the semiconductor fins 120 is not limited to four. Some of the gate structures 190 are physically separated by a first dielectric separation wall 150A (also referred to as a separation wall) or a second dielectric separation wall 150B (also referred to as a separation wall). This first dielectric The separation wall 150A or the second dielectric separation wall 150B is composed of a dielectric material. On the opposite side of the gate structure 190, a side wall spacer 176 is provided. The gate structure 190 includes a gate dielectric layer 192, a work function adjustment layer 194, and a main gate electrode 196.

The semiconductor fins 120 not covered by the gate structure 190 are source / drain regions. A source / drain (S / D) epitaxial layer 180 is formed on the source / drain region of the semiconductor fin 120, and an etch stop layer 182 is formed over the source / drain epitaxial layer 180. . In addition, an interlayer dielectric layer 184 is formed to cover the source / drain structure.

In FIG. 23A, FIG. 23B, FIG. 23C, and FIG. 23D, the semiconductor fin 120 (also referred to as a fin structure) in some embodiments includes a first fin F11 and a second fin which are sequentially arranged. Sheet F12, third fin F13, and fourth fin F14. The pitch P31 between the first fin F11 and the second fin F12 is twice the base fin pitch FP, and the pitch P32 between the second fin F12 and the third fin F13 is three times And the pitch P33 between the third fin F13 and the fourth fin F14 is four times or more than the basic fin pitch FP. In some embodiments, the base fin pitch FP is the smallest fin pitch defined by design rules. In some embodiments, the base fin pitch FP is about 14 nm (nm) to 30 nm ( nm).

As shown in FIGS. 23C and 23D, in some embodiments, the distance H32 between the etch stop layer 182 on the source / drain region and the upper surface of the interlayer dielectric layer 184 is from about 14 nm. (nm) to about 30 nanometers (nm). In some embodiments, the distance H31 between the top end on the first fin F11 and the upper surface of the main gate electrode 96 is in a range from about 18 nanometers (nm) to about 40 nanometers (nm).

In FIGS. 23A to 23D, in some embodiments, the distance S31 between the first dielectric separation wall 150A and the nearby first fin F11 or second fin F12 is located at about 8 nm ( nm) to about 20 nanometers (nm), and the distance S32 between the second dielectric separation wall 150B and the nearby third fin F13 or fourth fin F14 is located from about 20 nanometers (nm) ) To about 40 nanometers (nm).

The width W31 of the first dielectric separation wall 150A is about 4 nanometers (nm) to about 8 nanometers (nm) in some embodiments. The width W32 of the second dielectric separation wall 150B is about 8 nanometers (nm) to about 40 nanometers (nm) in some embodiments.

As shown in FIGS. 23C and 2D, the bottom of the dielectric separation wall 150 is located on the upper surface of the isolation insulating layer 130.

The material of the dielectric separation wall 150 may be silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and metal oxides, such as hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ), and aluminum oxide. (Al ₂ O ₃ ) or any suitable dielectric material.

FIG. 24A to FIG. 45B illustrate stages of a sequential semiconductor device manufacturing process according to other embodiments of the present disclosure. In FIGS. 24A to 45B, “A” illustrates a perspective view, “B” illustrates a cross-sectional view along a direction X corresponding to a line segment X12-X12 of FIG. 23B, and “C” Show floor plan. It should be understood that additional operations may be provided before, during, and after the process illustrated by FIGS. 24A to 45B; and for additional implementations of the method, some operations described below may be replaced or removed. The order of operations / processes is interchangeable. Structures, configurations, materials, and / or processes that are the same as or similar to those of the above embodiments can be applied to the following embodiments, and detailed descriptions can be omitted.

In FIGS. 24A and 24B, the semiconductor fins 120 are formed above the substrate 110. The first fin F11, the second fin F12, the third fin F13, and the fourth fin F14 include a first cover layer 122 and a second cover layer 124. The first cover layer 122 is composed of a metal oxide such as titanium oxide, hafnium oxide, and zirconium oxide. The thickness of the first cover layer 122 is about 5 nanometers (nm) to about 20 nanometers (nm) in some embodiments. The second cover layer 124 is composed of an amorphous or polycrystalline material of a group IV material, such as amorphous silicon or poly silicon, silicon germanium, or germanium. In some embodiments, the second cover layer 124 is composed of amorphous silicon having a thickness of about 20 nanometers (nm) to about 50 nanometers (nm).

In addition, forming the isolation insulating layer 130 is also referred to as a shallow trench isolation (STI) layer. An insulating material layer of the isolation insulating layer 130 is formed over the substrate 110 so as to completely cover the semiconductor fins 120. A planarization operation such as a chemical mechanical polishing (CMP) method is performed to expose the second cover layer 124.

In FIGS. 25A and 25B, the isolation insulating layer 130 is recessed and an oxide layer 135 is formed. In some embodiments, the oxide layer 135 may be formed by an atomic layer deposition (ALD) process and / or a chemical vapor deposition (CVD) process and has a thickness of about 1 nanometer (nm) to A thickness of about 5 nanometers (nm). After the isolation insulating layer 130 is recessed, the distance between the upper surface of the isolation insulating layer 130 and the top of the second cover layer 124 is in some embodiments from about 100 nanometers (nm) to about 400 nanometers (nm). In range.

In FIGS. 26A and 26B, the sacrificial layer 140 is formed over the recessed insulating layer 130 so that the second covering layer 124 covered with the oxide layer 135 protrudes from the insulating layer 130. In some embodiments, the sacrificial layer 140 is composed of an organic material such as a bottom anti reflective coating (BARC) or a photoresist. A thick layered structure is formed first, and then an etch-back operation is performed to adjust the thickness of the sacrificial layer 140.

In FIGS. 27A and 27B, the oxide layer 135 formed on the second cover layer 124 is removed by wet and / or dry etching, and then the sacrificial layer 140 is removed.

In FIGS. 28A and 28B, the first dummy layer 142 is formed over the semiconductor fin 120. The first dummy layer 142 is composed of an amorphous or polycrystalline material of a group IV material, such as amorphous or poly silicon, silicon germanium, or germanium. In some embodiments, the first dummy layer 142 is composed of amorphous silicon having a thickness of about 5 nanometers (nm) to about 20 nanometers (nm). Here, a space is formed between the first dummy layers 142 formed on the nearby fin structure. A blanket layer of amorphous silicon is formed, and then anisotropic etching is performed. The spacing S41 between the first dummy layer 142 formed on the first fin F11 and the second fin F12 is in a range from about 4 nanometers (nm) to about 14 nanometers (nm) in some embodiments. in. The height H42 between the upper surface of the isolation insulating layer 130 and the top of the first dummy layer 142 is in a range from about 120 nanometers (nm) to about 500 nanometers (nm) in some embodiments. In some embodiments, since the second cover layer 124 and the first dummy layer 142 are made of the same material, such as amorphous Si, there is no visible between the second cover layer 124 and the first dummy layer 142. boundary.

In FIGS. 29A and 29B, the second dummy layer 143 is conformally formed by using an atomic layer deposition process or a chemical vapor deposition process. The second dummy layer 143 is composed of a silicon nitride-based material such as silicon nitride (SiN) and silicon oxynitride (SiON). In some embodiments, the second dummy layer 143 is composed of silicon nitride (SiN) having a thickness of about 5 nanometers (nm) to about 20 nanometers (nm). The second dummy layer 143 completely fills the gap between the first fin F11 and the second fin F12, and the gap is between the second fin F12 and the third fin F13 and between the third fin F13 and Formed between the fourth fins F14.

In FIGS. 30A and 30B, an anisotropic etching is performed to remove unnecessary portions of the second dummy layer 143, and the second remaining in the space between the first fin F11 and the second fin F12 is retained. Dummy layer 143.

In FIGS. 31A and 31B, a third dummy layer 144 is formed. The third dummy layer 144 is composed of an amorphous or polycrystalline material of a Group IV material, such as amorphous silicon or poly silicon, silicon germanium, or germanium. In some embodiments, the third dummy layer 144 is composed of amorphous silicon having a thickness of about 5 nanometers (nm) to about 20 nanometers (nm). Here, a space is formed between the third dummy layers 144 formed on the nearby fins.

In FIGS. 32A and 32B, anisotropic etching is performed. The spacing S42 between the third dummy layer 144 formed on the second fin F12 and the third fin F13 is in a range from about 4 nanometers (nm) to about 14 nanometers (nm) in some embodiments. in. The spacing S43 between the third dummy layer 144 formed on the third fin F13 and the fourth fin F14 is in a range from about 8 nanometers (nm) to about 40 nanometers (nm) in some embodiments. in.

In FIGS. 33A and 33B, the second dummy layer 143 is removed by wet and / or dry etching. The spacing S44 between the third dummy layer 144 formed on the second fin F12 and the third fin F13 is in a range from about 4 nanometers (nm) to about 14 nanometers (nm) in some embodiments. in. The spacing S45 between the third dummy layer 144 formed on the third fin F13 and the fourth fin F14 is in a range from about 8 nanometers (nm) to about 40 nanometers (nm) in some embodiments. in.

In FIGS. 34A and 34B, a dielectric material of the dielectric separation wall 150 is formed. A blanket layer of dielectric material is formed and subsequently subjected to a chemical mechanical polishing or etch-back operation. The dielectric separation wall 150 includes silicon (Si), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), such as hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ), and alumina (Al ₂ O ₃ ) One or more layers of metal oxide, or any other suitable dielectric material. The dielectric material of the dielectric separation wall 150 is formed by a chemical vapor deposition process, an atomic layer deposition process, or any other suitable thin film formation method.

In FIGS. 35A and 35B, a masking layer 152 is formed on the dielectric material of the dielectric separation wall 150 and the first dummy layer 142 and the second dummy layer 143. The mask layer 152 includes one or more layers of silicon oxide-based materials such as silicon oxide (SiO ₂ ) and silicon oxynitride (SiON). In some embodiments, the masking layer 152 is silicon oxide (SiO ₂ ) having a thickness of about 5 nanometers (nm) to about 30 nanometers (nm).

In FIGS. 36A, 36B, and 36C, the mask layer 152 is patterned by using the photoresist pattern 154. One of the photoresist patterns 154 is located above a region, and two gate electrode groups are separately formed in this region; and one of the photoresist patterns 154 is located above a region, separately in this region Ground forms another gate electrode group. See Figure 23B.

In FIGS. 37A and 37B, by using the patterned masking layer 152 as an etching mask, the dielectric material of the dielectric separation wall 150 is patterned to form a first dielectric separation wall 150A and a second dielectric. Electric separation wall 150B. The first dielectric separation wall 150A has a width different from that of the second dielectric separation wall 150B. In some embodiments, the width of the first dielectric separation wall 150A is twice or more than the width of the second dielectric separation wall 150B.

In FIGS. 38A and 38B, a fourth dummy layer 170 is formed. The fourth dummy layer 170 is composed of an amorphous or polycrystalline material of a group IV material, such as amorphous silicon or poly silicon, silicon germanium, or germanium. In some embodiments, the fourth dummy layer 170 is composed of polycrystalline silicon. In some embodiments, since the second cover layer 124, the first dummy layer 142, the third dummy layer 144, and the fourth dummy layer 170 are made of the same material, such as amorphous silicon, they serve as a dummy gate electrode layer. .

In FIGS. 39A, 39B, 39C, and 39D, the dummy gate electrode layer (for example, the second cover layer 124) is patterned by using a hard mask including the layered structure 172 and the layered structure 174. , The first dummy layer 142, the third dummy layer 144, and the fourth dummy layer 170) to form a dummy gate electrode 175. At least one dummy gate electrode 175 is disposed above the first fin F11 and the second fin F12 and the first dielectric separation wall 150A, and at least one dummy gate electrode 175 is disposed at the third fin F13 and the fourth fin. F14 and the second dielectric separation wall 150B are above. In some embodiments, as shown in FIG. 39C, two dummy gate electrodes 175 are disposed above the first to fourth fins F11 to F14 and the first dielectric separation wall 150A, and one dummy gate The electrode 175 is disposed above the first fin F11, the second fin F12, the third fin F13, the fourth fin F14, and the second dielectric separation wall 150B. The width W41 of the dummy gate electrode 175 is in a range from about 4 nanometers (nm) to about 20 nanometers (nm) in some embodiments.

In FIGS. 40A and 40B, the sidewall spacer 176 is formed on the opposite side of the dummy gate electrode 175. A blanket layer based on a silicon nitride material (silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbon nitride (SiCN)) is formed, and then anisotropic etching is performed. By this etching, the silicon nitride-based material formed on the exposed fins is removed. In some embodiments, the dielectric separation wall 150 which is not covered by the dummy gate electrode and the sidewall spacer is recessed. In other embodiments, the dielectric separation wall 150 is not recessed.

In FIGS. 41A and 41B, a source / drain epitaxial layer 180 is formed on the exposed fins. The epitaxial source / drain layer includes one of silicon phosphide (SiP), silicon carbide (SiC), silicon carbon phosphide (SiCP), silicon boride (SiB), silicon germanium (SiGe), and germanium (Ge) or Multiple crystalline layers. In some embodiments, a silicide layer is further formed over the source / drain epitaxial layer 180.

In FIGS. 42A and 42B, an etch stop layer 182 is formed, and an interlayer dielectric layer 184 is formed in a space between the dummy gate electrodes 175 having the sidewall spacers 176. The interlayer dielectric layer 184 may include silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon oxynitride (SiOCN), and fluorine-doped glass. silicate glass (FSG) or low-k dielectric material, and can be made by chemical vapor deposition process or other suitable processes. The insulating material of the dielectric separation wall 150 is different from the insulating materials of the isolation insulating layer 130 and the interlayer dielectric layer 184.

A planarization operation, such as an etch-back process and / or a chemical mechanical polishing process, is performed to expose the dummy gate electrode 175 and the portions above the first dielectric separation wall 150A and the second dielectric separation wall 150B.

In FIGS. 43A and 43B, the dummy gate electrode 175, the first cover layer 122, the second cover layer 124, and the oxide layer 135 are removed to form a gate gap 189.

In FIGS. 44A, 44B, and 44C, a metal gate structure 190 including a gate dielectric layer 192, a work function adjustment layer 194, and a main gate electrode 96 is formed in a gate space 189. When the metal gate structure 190 is formed, the gate dielectric layer 192, the work function adjustment layer 194, and the gate electrode layer are formed by a suitable thin film method, such as a chemical vapor deposition process or atom for the gate dielectric layer 192. Formed by a layer deposition process, and a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or an electroplating process for a metal layer, and subsequently performing a planarization operation such as chemical mechanical polishing to remove interlayer dielectric Excess material formed over layer 184.

In FIGS. 45A and 45B, a planarization operation such as chemical mechanical polishing is performed to expose the first dielectric separation wall 150A and the second dielectric separation wall 150B.

In some embodiments, at least one of the gate structure 190 and the sidewall spacing 176 is separated from at least one of the other second gate structure 190 and the sidewall spacer 176 by the first dielectric separation wall 150A. In addition, in some embodiments, the side wall spacer 176 is continuously formed on the side wall of the first dielectric separation wall 150A, and other side wall spacers 176 are continuously formed on the other side wall of the first dielectric separation wall 150A.

In other embodiments, during the operation of FIGS. 42A and 42B, the dielectric separation wall 150 is exposed to separate the dummy gate structure into two sub-dummy gate structures, and in FIGS. 43A to 45B During operation, the two sub-dummy gate structures were replaced with metal gate structures, respectively.

As explained above, the dielectric separation wall 150 is formed before the dummy gate structure, and a metal gate structure 190 is formed. Therefore, the width of the dielectric separation wall 150 and the size of the ends of the metal gate electrode and the fin structure can be controlled more accurately.

It should be understood that the structure undergoes another complementary metal oxide semiconductor process to form features such as interconnect vias, interconnect metal layers, passivation layers, and the like.

The embodiments or examples described herein provide several advantages over the prior art. By using the dielectric separation wall as described above, it is possible to fix an appropriate number (size) of end caps (the distance between the dielectric separation wall and the nearest fin) and reduce the fin-to-fin pitch.

It should be understood that it is not necessary to discuss all advantages herein, and that no particular advantage is necessary for all embodiments or examples, and that other embodiments or examples may provide different advantages.

The features of several embodiments or examples are summarized above, so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that the disclosure can be easily used as a basis for designing or modifying other processes and structures in order to implement the same purpose and / or achieve the same advantages of the embodiments or examples described herein. Those skilled in the art should also realize that such equivalent structures have not deviated from the spirit and scope of this disclosure, and can make various changes, substitutions and alterations without departing from the spirit and scope of this disclosure.

Claims (10)

A method for manufacturing a semiconductor element includes: forming a separation wall between two fin structures, and the material of the separation wall is a dielectric material; forming a dummy gate structure above the separation wall and the two fin structures; Forming an interlayer dielectric layer over the dummy gate structure; removing an upper part of the interlayer dielectric layer to expose the dummy gate structure; replacing the dummy gate structure with a metal gate structure; and performing A planarization operation is performed to expose the separation wall, and then the metal gate structure is divided into a first gate structure and a second gate structure, wherein the first gate structure and the second gate structure are separated by the The walls are separated from each other. The method for manufacturing a semiconductor device according to claim 1, further comprising: forming the two fin structure; and forming an isolation insulating layer so that a plurality of upper portions of the two fin structure protrude from the isolation insulating layer, wherein the A bottom portion of the separation wall is embedded in the isolation insulation layer. The method for manufacturing a semiconductor device according to claim 1, further comprising: forming the two fin structure; and forming an isolation insulating layer so that a plurality of upper portions of the two fin structure protrude from the isolation insulating layer, wherein the A bottom position of the separation wall is located on or above an upper surface of the isolation insulation layer. The method for manufacturing a semiconductor device according to claim 1, further comprising: forming a plurality of sidewall spacers on opposite sides of the dummy gate structure, wherein after forming the first gate structure and the second gate structure The sidewall spacers on the first gate structure are separated from the sidewall spacers on the second gate structure by the separation wall. The method for manufacturing a semiconductor device according to claim 1, wherein the first gate structure and the second gate structure include a gate dielectric layer and a gate electrode layer, respectively, and the gate dielectric layer is It is formed on a plurality of side walls of the separation wall. A method for manufacturing a semiconductor device includes forming a first fin structure, a second fin structure, and a third fin structure. The second fin structure is located on the first fin structure and the third fin structure. In between, the material of each of the first fin structure, the second fin structure, and the third fin structure is a semiconductor material and has an insulating cover layer; an isolation insulating layer is formed so that the first A fin structure, the second fin structure, and the third fin structure are embedded in the isolation insulation layer, and the insulation cover layer is exposed; a first mask pattern is formed over the isolation insulation layer, and the The first mask pattern has a first opening, which is located above the second fin structure; the second fin structure is recessed by an etching process, and the first mask pattern serves as an etching mask; A dielectric separation wall is formed on the recessed second fin structure; the isolation insulating layer is recessed so that a plurality of upper portions of the first fin structure and the third fin structure and the upper portion of the dielectric separation wall The part is exposed; A dummy gate structure above the exposed first fin structure, the exposed third fin structure, and the exposed dielectric separation wall; forming an interlayer dielectric layer over the first dummy gate structure; Removing an upper portion of the interlayer dielectric layer to expose the first dummy gate structure; replacing the first gate structure with a metal gate structure; and performing a planarization operation to expose the dielectric separation wall, The metal gate structure is further divided into a first gate structure and a second gate structure, wherein the first gate structure and the second gate structure are separated from each other by the dielectric separation wall. The method for manufacturing a semiconductor device according to claim 6, further comprising: between the step of forming the first dummy gate structure and the step of forming the interlayer dielectric layer: forming a plurality of sidewall spacers on the first fin Sheet structure, the third fin structure, and the dielectric separation wall on opposite sides; removing a plurality of portions of the sidewall gap on the first fin structure and the third fin structure, thereby exposing the first A plurality of source / drain regions of the fin structure and a third fin structure; and a plurality of source / drain epitaxial layers are formed on the exposed source / drain regions. A semiconductor element includes: a first gate electrode disposed above an isolation insulating layer formed on a substrate; a second gate electrode disposed above the isolation insulating layer; the first gate An electrode and the second gate electrode extend in a first direction and are aligned along the first direction; and a dielectric separation wall passes through the isolation insulating layer, protrudes from the isolation insulating layer, and is disposed at The first gate electrode is separated from the second gate electrode, and the first gate electrode is separated from the second gate electrode. The dielectric material of the dielectric separation wall is different from the isolation insulation. Layer of dielectric material. The semiconductor device according to claim 8, further comprising: a first fin structure protruding from the isolation insulating layer; and a second fin structure protruding from the isolation insulating layer, wherein the first gate electrode system Is disposed above the first fin structure, the second gate electrode is disposed above the second fin structure, and a center distance between the dielectric separation wall and the first fin structure is substantially the same as A central distance between the dielectric separation wall and the second fin structure. The semiconductor device according to claim 8, further comprising: a first fin structure protruding from the isolation insulating layer; and a second fin structure protruding from the isolation insulating layer, wherein the first gate electrode system Is disposed above the first fin structure, the second gate electrode is disposed above the second fin structure, a first distance between the first fin structure and the dielectric separation wall is substantially the same as A base fin pitch or a multiple of the base fin pitch, and a second pitch between the second fin structure and the dielectric separation wall is equal to the base fin pitch or a multiple of the base fin pitch .