TWI662349B - Pixel structure - Google Patents

Abstract

A pixel structure includes a substrate, a scanning line, a first data line, a second data line, a first switching element, a second switching element, a first main pixel electrode, a second main pixel electrode, a common line, and a light-shielding layer. . The second data line is located between the first main pixel electrode and the second main pixel electrode. The common line includes a main portion provided along the extending direction of the scanning line, and a first extension portion and a second extension portion that are electrically connected to the main portion and are located on both sides of the second data line, respectively. The light-shielding layer includes a first light-shielding pattern and a second light-shielding pattern respectively located on two sides of the second data line, wherein the first light-shielding pattern is located between the second data line and the first extension portion, and the second light-shielding pattern is located on the second data Between the line and the second extension.

Description

Pixel structure

The present invention relates to a pixel structure, and more particularly, to a pixel structure that can improve the problem of abnormal light leakage.

In the manufacturing process of a large-sized display panel, because the panel size is too large, the entire panel cannot be exposed at the same time, and the display panel needs to be divided into at least two regions for exposure. However, this approach will cause obvious exposure lines in the center of the display panel due to the difference between the two exposure conditions, and make the terrain near the data line uneven, which will cause abnormal light leakage near the data line.

Therefore, how to solve the problem of abnormal light leakage in the display panel is really one of the problems that the current R & D personnel want to solve.

In view of this, the present invention provides a pixel structure that can improve the problem of abnormal light leakage in the prior art.

An embodiment of the present invention provides a pixel structure including a substrate, a scanning line, a first data line, a second data line, a first switching element, a second switching element, a first main pixel electrode, and a second main pixel. Electrodes, common lines, and light-shielding layers. The scan lines are disposed on the substrate. The first data line and the second data line are disposed on the substrate and intersect with the scanning line. The first switching element is electrically connected to the scanning line and the first data line. The second switching element is electrically connected to the scanning line and the second data line. The first main pixel electrode is electrically connected to the first switching element and is located on a first side of the scan line. The second main pixel electrode is electrically connected to the second switching element and is located on the first side of the scan line, wherein the second data line is located between the first main pixel electrode and the second main pixel electrode. The common line is disposed on the substrate and is located on the first side of the scan line, and the common line includes a trunk portion provided along the extending direction of the scan line, and the main line electrically connected to the main body portion and located on both sides of the second data line, respectively. The first extension portion and the second extension portion. The light-shielding layer includes a first light-shielding pattern and a second light-shielding pattern respectively located on two sides of the second data line, wherein the first light-shielding pattern is located between the second data line and the first extension portion, and the second light-shielding pattern is located on the second data Between the line and the second extension.

Based on the above, in the pixel structure of the present invention, the transmissive light-shielding layer includes a first light-shielding pattern and a second light-shielding pattern respectively located on two sides of the second data line, and the first light-shielding pattern is located between the second data line and the first extension And the second shading pattern is located between the second data line and the second extension, so that the terrain on both sides of the second data line is flat, so when the pixel structure is applied to a liquid crystal display panel, it corresponds to the second data line The liquid crystal molecules arranged nearby can have a good alignment, thereby improving the problem of abnormal light leakage near the second data line.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

In the following, multiple embodiments of the present invention will be disclosed graphically. For the sake of clarity, many practical details will be described in the following description. It should be understood, however, that these practical details should not be used to limit the invention. That is, in some embodiments of the present invention, these practical details are unnecessary. In addition, to simplify the drawings, some conventional structures and elements will be used in the drawings in a simple and schematic manner.

As used herein, "about," "approximately," "essentially," or "substantially" includes the stated value and an average value within an acceptable deviation range of a particular value determined by one of ordinary skill in the art, taking into account the The measurement in question and the specific number of measurement-related errors (ie, limitations of the measurement system). For example, "about" may mean within one or more standard deviations of the stated value, or for example within ± 30%, ± 20%, ± 15%, ± 10%, ± 5%. Furthermore, the terms "about", "approximately", "essentially", or "substantially" used herein may be based on optical properties, etching properties, or other properties to select a more acceptable range of deviations or standard deviations without using One standard deviation applies to all properties.

In the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. Throughout the description, the same drawing element symbols indicate the same elements. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intervening elements may be present between the elements. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements in between. As used herein, "connected" may refer to a physical and / or electrical connection (coupled or coupled). Therefore, there may be intermediate components in the electrical connection (or coupling / coupling) between the two components.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted to have meanings consistent with their meanings in the context of the related art and the present invention, and will not be interpreted as idealized or excessive Formal meaning unless explicitly defined as such in this article.

FIG. 1 is a schematic top view of a pixel structure according to an embodiment of the present invention. FIG. 2 is an enlarged view of a region A in FIG. 1. FIG. 3 is an enlarged view of a region B in FIG. 1. Fig. 4 is a schematic cross-sectional view taken along the line I-I 'in Fig. 2.

Please refer to FIGS. 1 to 4 at the same time. The pixel structure 1 includes a substrate 100, a scan line SL, a first data line DL1, a second data line DL2, a first switching element SW1, a second switching element SW2, and a first main pixel. The electrode MPE1, the second main pixel electrode MPE2, the common line CL, and the light shielding layer 400. In addition, in this embodiment, the pixel structure 1 may further include a third data line DL3, a third switching element SW3, a fourth switching element SW4, a first pixel electrode SPE1, a second pixel electrode SPE2, a first An insulating layer 210, a second insulating layer 220, a first filter layer CF1, a second filter layer CF2, a protective layer 230, a common electrode CE, a connection structure CS, a first signal line 130, and a second signal line 140. For convenience of description, components such as the first insulating layer 210, the second insulating layer 220, the first filter layer CF1, the second filter layer CF2, and the protective layer 230 are omitted in FIG. 1.

In this embodiment, the substrate 100 may be a flexible substrate, such as a polymer substrate or a plastic substrate, but the present invention is not limited thereto. In other embodiments, the substrate 100 may be a rigid substrate, such as a glass substrate, a quartz substrate, or a silicon substrate.

In this embodiment, the scan line SL, the first data line DL1, the second data line DL2, and the third data line DL3 are disposed on the substrate 100. In this embodiment, the first data line DL1, the second data line DL2, and the third data line DL3 are respectively arranged to cross the scanning line SL. That is, in this embodiment, the extending direction of the scanning line SL is different from the extending direction of the first data line DL1, the second data line DL2, and the third data line DL3. It is preferable that the extending direction of the scanning line SL Intersect with the extending direction of the first data line DL1, the second data line DL2, and the third data line DL3 (for example, substantially vertical). In addition, the scan lines SL and the first data line DL1, the second data line DL2, and the third data line DL3 may be located in different film layers, respectively, and the scan lines SL and the first data line DL1, the second data line DL2, and the first A first insulating layer 210 is sandwiched between the three data lines DL3 (described in detail later). Based on the consideration of conductivity, the scan line SL, the first data line DL1, the second data line DL2, and the third data line DL3 are generally made of a metal material. However, the present invention is not limited to this. According to other embodiments, the scan line SL, the first data line DL1, the second data line DL2, and the third data line DL3 may also use, for example, an alloy, a nitride of a metal material, a metal material Oxides, oxynitrides of metallic materials, non-metallic materials with conductive properties, or other suitable materials.

In this embodiment, the first data line DL1, the second data line DL2, and the third data line DL3 have different widths, respectively. In detail, as shown in FIG. 1, in this embodiment, the first data line DL1 has a width W1 and a width W2, the second data line DL2 has a width W3 and a width W4, and the third data line DL3 has a width W5 and a width W6, wherein width W1 is smaller than width W2, width W3 is smaller than width W4, and width W5 is smaller than width W6. In one embodiment, the width W1, the width W3, and the width W5 are, for example, between 4 μm and 6 μm, and the width W2, the width W4, and the width W6 are, for example, between 12 μm and 16 μm. In addition, in the present embodiment, the first data line DL1, the second data line DL2, and the third data line DL3 have portions with gradually varying widths, but the present invention is not limited thereto.

In this embodiment, the first switching element SW1 is disposed on the substrate 100 and is electrically connected to the scan line SL and the first data line DL1. In this embodiment, the first switching element SW1 includes a gate G1, a semiconductor pattern layer SM1 provided corresponding to the gate G1, and a source S1 and a drain D1 electrically connected to the semiconductor pattern layer SM1. In this embodiment, a part of the scan line SL is used as the gate G1, which means that the gate G1 is electrically connected to the scan line SL. From another point of view, in the present embodiment, the gate electrode G1 and the scan line SL belong to the same film layer. That is, in this embodiment, the gate electrode G1 and the scan line SL have substantially the same material, and the gate electrode G1 and the scan line SL are formed in the same photolithography and etching process (PEP). It is worth mentioning that a part of the scanning line is a part of the scanning line which can include a part extending from the scanning line or the scanning line itself.

In this embodiment, the source S1 and the first data line DL1 are a continuous conductive pattern, which indicates that the source S1 is electrically connected to the first data line DL1. From another perspective, in this embodiment, the source S1 and the first data line DL1 belong to the same film layer. That is, in this embodiment, the source S1 and the first data line DL1 have substantially the same material, and the source S1 and the first data line DL1 are formed in the same mask process.

In this embodiment, the semiconductor pattern layer SM1 is located above the gate G1, and the source S1 and the drain D1 are located above the semiconductor pattern layer SM1. That is, in this embodiment, the first switching element SW1 is described by taking a bottom-gate thin film transistor as an example, but the present invention is not limited thereto. In other embodiments, the first switching element SW1 may also be a top-gate thin film transistor, a three-dimensional thin film transistor, or another suitable type of thin film transistor.

In this embodiment, the source S1 and the drain D1 belong to the same film layer. That is, in this embodiment, the source S1, the drain D1 and the first data line DL1 have substantially the same material, and the source S1, the drain D1 and the first data line DL1 are in the same mask process. Middle formation.

In this embodiment, the second switching element SW2 is disposed on the substrate 100 and is electrically connected to the scan line SL and the second data line DL2. In this embodiment, the second switching element SW2 includes a gate electrode G2, a semiconductor pattern layer SM2 provided corresponding to the gate electrode G2, and a source S2 and a drain electrode D2 electrically connected to the semiconductor pattern layer SM2. In this embodiment, a part of the scan line SL is used as the gate G2, which means that the gate G2 is electrically connected to the scan line SL. From another viewpoint, in this embodiment, the gate electrode G2 and the scan line SL belong to the same film layer. That is, in this embodiment, the gate electrode G2 and the scan line SL have substantially the same material, and the gate electrode G2 and the scan line SL are formed in the same mask process.

In this embodiment, the source S2 and the second data line DL2 are a continuous conductive pattern, which indicates that the source S2 is electrically connected to the second data line DL2. From another perspective, in this embodiment, the source S2 and the second data line DL2 belong to the same film layer. That is, in this embodiment, the source S2 and the second data line DL2 have substantially the same material, and the source S2 and the second data line DL2 are formed in the same mask process.

In this embodiment, the semiconductor pattern layer SM2 is located above the gate G2, and the source S2 and the drain D2 are located above the semiconductor pattern layer SM2. That is, in this embodiment, the second switching element SW2 is described by taking a bottom-gate thin film transistor as an example, but the present invention is not limited thereto. In other embodiments, the second switching element SW2 may also be a top-gate thin film transistor, a three-dimensional thin film transistor, or another suitable type of thin film transistor.

In this embodiment, the source S2 and the drain D2 belong to the same film layer. That is, in this embodiment, the source S2, the drain D2 and the second data line DL2 have substantially the same material, and the source S2, the drain D2 and the second data line DL2 are in the same mask process. Middle formation.

In this embodiment, the third switching element SW3 is disposed on the substrate 100 and is electrically connected to the scan line SL and the first data line DL1. In this embodiment, the third switching element SW3 includes a gate electrode G3, a semiconductor pattern layer SM3 provided corresponding to the gate electrode G3, a source S3 and a drain electrode D3 electrically connected to the semiconductor pattern layer SM3. In this embodiment, a part of the scan line SL is used as the gate G3, which means that the gate G3 is electrically connected to the scan line SL. From another point of view, in this embodiment, the gate electrode G3 and the scanning line SL belong to the same film layer. That is, in this embodiment, the gate electrode G3 and the scan line SL have substantially the same material, and the gate electrode G3 and the scan line SL are formed in the same mask process.

In this embodiment, the source S3 and the source S1 are a continuous conductive pattern. In detail, as described above, the source S1 and the first data line DL1 are a continuous conductive pattern, so the source S3, the source S1, and the first data line DL1 are electrically connected to each other. From another perspective, in this embodiment, the source S3 and the first data line DL1 belong to the same film layer. That is, in this embodiment, the source S3 and the first data line DL1 have substantially the same material, and the source S3 and the first data line DL1 are formed in the same mask process.

In this embodiment, the semiconductor pattern layer SM3 is located above the gate G3, and the source S3 and the drain D3 are located above the semiconductor pattern layer SM3. That is, in the present embodiment, the third switching element SW3 is described using a bottom-gate thin film transistor as an example, but the present invention is not limited thereto. In other embodiments, the third switching element SW3 may also be a top-gate thin film transistor, a three-dimensional thin film transistor, or another suitable type of thin film transistor.

In this embodiment, the source S3 and the drain D3 belong to the same film layer. That is, in this embodiment, the source S3, the drain D3 and the first data line DL1 have substantially the same material, and the source S3, the drain D3 and the first data line DL1 are in the same mask process. Middle formation.

In particular, in this embodiment, the source S3 and the source S1 are a continuous conductive pattern, the semiconductor pattern layer SM3 and the semiconductor pattern layer SM1 form a continuous semiconductor pattern, and the gate G3 and the gate G1 As a continuous conductive pattern, the first switching element SW1 and the third switching element SW3 can form a thin-film transistor with a double-drain design together, but the present invention is not limited thereto.

In this embodiment, the fourth switching element SW4 is disposed on the substrate 100 and is electrically connected to the scan line SL and the second data line DL2. In this embodiment, the fourth switching element SW4 includes a gate electrode G4, a semiconductor pattern layer SM4 provided corresponding to the gate electrode G4, a source S4 and a drain electrode D4 electrically connected to the semiconductor pattern layer SM4. In this embodiment, a part of the scan line SL is used as the gate G4, which means that the gate G4 is electrically connected to the scan line SL. From another point of view, in the present embodiment, the gate G4 and the scan line SL belong to the same film layer. That is, in this embodiment, the gate electrode G4 and the scan line SL have substantially the same material, and the gate electrode G4 and the scan line SL are formed in the same mask process.

In this embodiment, the source S4 and the source S2 are a continuous conductive pattern. In detail, as described above, the source S2 and the second data line DL2 are a continuous conductive pattern, so the source S4, the source S2, and the second data line DL2 are electrically connected to each other. From another point of view, in this embodiment, the source S4 and the second data line DL2 belong to the same film layer. That is, in this embodiment, the source S4 and the second data line DL2 have substantially the same material, and the source S4 and the second data line DL2 are formed in the same mask process.

In this embodiment, the semiconductor pattern layer SM4 is located above the gate G4, and the source S4 and the drain D4 are located above the semiconductor pattern layer SM4. That is, in this embodiment, the fourth switching element SW4 is described by taking a bottom-gate thin film transistor as an example, but the present invention is not limited thereto. In other embodiments, the fourth switching element SW4 may also be a top-gate thin film transistor, a three-dimensional thin film transistor, or another suitable type of thin film transistor.

In this embodiment, the source S4 and the drain D4 belong to the same film layer. That is, in this embodiment, the source S4, the drain D4, and the second data line DL2 have substantially the same material, and the source S4, the drain D4, and the second data line DL2 are in the same mask process. Middle formation.

In particular, in this embodiment, the source S4 and the source S2 are a continuous conductive pattern, the semiconductor pattern layer SM4 and the semiconductor pattern layer SM2 form a continuous semiconductor pattern, and the gate G4 and the gate G2 As a continuous conductive pattern, the second switching element SW2 and the fourth switching element SW4 can form a thin-film transistor with a double-drain design together. However, the present invention is not limited thereto.

In addition, in this embodiment, the materials of the semiconductor pattern layer SM1, the semiconductor pattern layer SM2, the semiconductor pattern layer SM3, and the semiconductor pattern layer SM4 may include (but are not limited to): amorphous silicon, nanocrystalline silicon, and microcrystalline silicon. , Polycrystalline silicon, single crystal silicon, carbon nanotubes / rods, oxide semiconductor materials (such as: Indium-Gallium-Zinc Oxide (IGZO), zinc oxide (ZnO), tin oxide (SnO), indium oxide Indium-Zinc Oxide (IZO), Gallium-Zinc Oxide (GZO), Zinc-Tin Oxide (ZTO) or Indium-Tin Oxide (ITO), or other suitable Materials), organic semiconductor materials, or other suitable materials, or a combination or stack of at least two of the foregoing.

In this embodiment, the first main pixel electrode MPE1 is electrically connected to the first switching element SW1 and is located on the first side 112 of the scan line SL. In this embodiment, the first main pixel electrode MPE1 can be electrically connected to the drain electrode D1 of the first switching element SW1 through the contact window C1. In this embodiment, the material of the first main pixel electrode MPE1 may be a transparent conductive material (for example, indium tin oxide, indium zinc oxide, aluminum tin oxide (ATO), aluminum zinc oxide, AZO), indium gallium zinc oxide, metal or alloy less than 60 angstroms, or other suitable oxides, or a stack of at least two of the above), other suitable materials, or a combination / stack of at least two of the foregoing materials .

In this embodiment, the second main pixel electrode MPE2 is electrically connected to the second switching element SW2 and is located on the first side 112 of the scan line SL. In this embodiment, the second main pixel electrode MPE2 can be electrically connected to the drain electrode D2 of the second switching element SW2 through the contact window C2. In this embodiment, the material of the second main pixel electrode MPE2 may be a transparent conductive material (for example, indium tin oxide, indium zinc oxide, aluminum oxide tin, aluminum oxide zinc, indium gallium zinc oxide, and less than 60 Angstroms). Metal or alloy, or other suitable oxides, or stacked layers of at least two of the foregoing), other suitable materials, or a combination / stacking of at least two of the foregoing materials.

In addition, in this embodiment, the first main pixel electrode MPE1 is located on the first side 116 of the second data line DL2, and the second main pixel electrode MPE2 is located on the second side 118 of the second data line DL2. That is, in this embodiment, the first main pixel electrode MPE1 and the second main pixel electrode MPE2 are located on both sides of the second data line DL2, respectively. From another perspective, in this embodiment, the second data line DL2 is located between the first main pixel electrode MPE1 and the second main pixel electrode MPE2.

In this embodiment, the first pixel electrode SPE1 is electrically connected to the third switching element SW3 and is located on the second side 114 of the scan line SL. That is, in this embodiment, the first pixel electrode SPE1 and the first main pixel electrode MPE1 electrically connected to the first data line DL1 are located on both sides of the scanning line SL, but the present invention is not limited to this. . In other embodiments, the first pixel electrode SPE1 and the first main pixel electrode MPE1 electrically connected to the first data line DL1 may be located on the same side of the scan line SL (for example, the first side 112 or the second side). Side 114). In this embodiment, the first pixel electrode SPE1 can be electrically connected to the drain electrode D3 of the third switching element SW3 through the contact window C3. In this embodiment, the material of the first pixel electrode SPE1 may be a transparent conductive material (for example, indium tin oxide, indium zinc oxide, tin alumina tin, alumina zinc, indium gallium zinc oxide, metal less than 60 angstroms, or Alloys, or other suitable oxides, or stacked layers of at least two of the foregoing), other suitable materials, or a combination / stacking of at least two of the foregoing materials.

In this embodiment, the second pixel electrode SPE2 is electrically connected to the fourth switching element SW4 and is located on the second side 114 of the scan line SL. That is, in this embodiment, the second pixel electrode SPE2 and the second main pixel electrode MPE2 electrically connected to the second data line DL2 are located on both sides of the scan line SL, but the present invention is not limited to this. . In other embodiments, the second pixel electrode SPE2 and the second main pixel electrode MPE2 electrically connected to the second data line DL2 may be located on the same side of the scan line SL (for example, the first side 112 or the second side). Side 114). In this embodiment, the second pixel electrode SPE2 can be electrically connected to the drain electrode D4 of the fourth switching element SW4 through the contact window C4. In this embodiment, the material of the second pixel electrode SPE2 may be a transparent conductive material (for example, indium tin oxide, indium zinc oxide, aluminum oxide tin, aluminum oxide zinc, indium gallium zinc oxide, metal less than 60 angstroms, or Alloys, or other suitable oxides, or stacked layers of at least two of the foregoing), other suitable materials, or a combination / stacking of at least two of the foregoing materials.

In addition, in this embodiment, the first pixel electrode SPE1 is located on the first side 116 of the second data line DL2, and the second pixel electrode SPE2 is located on the second side 118 of the second data line DL2. That is, in this embodiment, the first pixel electrode SPE1 and the second pixel electrode SPE2 are located on both sides of the second data line DL2, respectively. From another point of view, in this embodiment, the second data line DL2 is actually located between the first pixel electrode SPE1 and the second pixel electrode SPE2.

In this embodiment, in the vertical projection direction N of the substrate 100, the first main pixel electrode MPE1 and the second main pixel electrode MPE2 are not overlapped with the second data line DL2, and the first pixel electrode SPE1 and The second pixel electrode SPE2 is disposed overlapping the second data line DL2, but the present invention is not limited thereto. In addition, as shown in FIG. 1, in this embodiment, in the vertical projection direction N of the substrate 100, the first main pixel electrode MPE1 is not overlapped with the first data line DL1, and the second main pixel electrode MPE2 is also It is not overlapped with the third data line DL3, the first pixel electrode SPE1 is also overlapped with the first data line DL1, and the second pixel electrode SPE2 is also overlapped with the third data line DL3.

In this embodiment, as shown in FIGS. 1 and 2, the second data line DL2 correspondingly disposed between the first main pixel electrode MPE1 and the second main pixel electrode MPE2 is a portion having a width W3, and as As shown in FIGS. 1 and 3, in the vertical projection direction N of the substrate 100, the first pixel electrode SPE1 and the second pixel electrode SPE2 overlap the second data line DL2 having a width W4. That is, in this embodiment, compared with the second data line DL2 correspondingly provided between the first main pixel electrode MPE1 and the second main pixel electrode MPE2, the first pixel electrode SPE1 is correspondingly provided. The second data line DL2 and the second pixel electrode SPE2 have a larger width.

In addition, in this embodiment, as shown in FIG. 1, a portion corresponding to the first data line DL1 and the first main pixel electrode MPE1 is a portion having a width W1, and a third data line DL3 is connected to the second main picture. The portion corresponding to the element electrode MPE2 is a portion having a width W5. In this embodiment, as shown in FIG. 1, in the vertical projection direction N of the substrate 100, the first pixel electrode SPE1 overlaps with the first data line DL1 having a width W2, and the second pixel electrode SPE2 Would overlap the third data line DL3 with a width W6.

In this embodiment, the first primary pixel electrode MPE1, the first primary pixel electrode SPE1, and the second primary pixel electrode MPE2 belong to the same film layer as the second primary pixel electrode SPE1. That is, in this embodiment, the first primary pixel electrode MPE1, the first primary pixel electrode SPE1, the second primary pixel electrode MPE2, and the second primary pixel electrode SPE1 have substantially the same material, and the first A main pixel electrode MPE1, a first pixel electrode SPE1, a second main pixel electrode MPE2, and a second pixel electrode SPE1 are formed in the same mask process.

In this embodiment, the common line CL is disposed on the substrate 100 and is located on the first side 112 of the scan line SL. In this embodiment, the common line CL and the scan line SL belong to the same film layer. That is, in this embodiment, the common line CL and the scan line SL have substantially the same material, and the common line CL and the scan line SL are formed in the same mask process. In addition, in this embodiment, the common line CL is electrically connected to the first common voltage, for example, about -10.5 volts to 27 volts.

In the present embodiment, the common line CL includes a trunk 120, a first extension 121, and a second extension 122. The trunk section 120 is provided along the extending direction of the scanning line SL. The first extension portion 121 and the second extension portion 122 are electrically connected to the trunk portion 120, respectively, and are located on both sides of the second data line DL2. In detail, in this embodiment, the first extension portion 121 is located on the first side 116 of the second data line DL2, and the second extension portion 122 is located on the second side 118 of the second data line DL2. In this embodiment, the first extension portion 121 and the second extension portion 122 are provided along the extension direction of the second data line DL2. As shown in FIGS. 1 and 2, in this embodiment, the second data line DL2 correspondingly provided between the first extension portion 121 and the second extension portion 122 is a portion having a width W3.

In addition, in this embodiment, the common line CL may further include a third extension portion 123 and a fourth extension portion 124 that are electrically connected to the trunk portion 120, respectively. In this embodiment, the first extension portion 121 and the third extension portion 123 are located on both sides of the first main pixel electrode MPE1, and the second extension portion 122 and the fourth extension portion 124 are located on the second main pixel electrode MPE2. On both sides. From another perspective, as shown in FIG. 1, the first extending portion 121 and the third extending portion 123 are disposed between the first data line DL1 and the second data line DL2, and the second extending portion 122 and the fourth extending portion The part 124 is provided between the second data line DL2 and the third data line DL3. In this embodiment, the first extension portion 121 and the third extension portion 123 partially overlap the first main pixel electrode MPE1; the second extension portion 122 and the fourth extension portion 124 partially overlap the second main pixel electrode MPE2. In this embodiment, the third extension portion 123 is provided along the extension direction of the first data line DL1, and the fourth extension portion 124 is provided along the extension direction of the third data line DL3. As shown in FIG. 1, in this embodiment, a portion corresponding to the third extension portion 123 of the first data line DL1 is a portion having a width W1, and a portion corresponding to the fourth extension portion 124 of the third data line DL3 is provided. The part is a part having a width W5.

In this embodiment, the light-shielding layer 400 includes a first light-shielding pattern 410 and a second light-shielding pattern 420 located on two sides of the second data line DL2, respectively. In detail, in this embodiment, the first light-shielding pattern 410 is located on the first side 116 of the second data line DL2, and the second light-shielding pattern 420 is located on the second side 118 of the second data line DL2. In this embodiment, the first light-shielding pattern 410 and the second light-shielding pattern 420 are disposed along the extending direction of the second data line DL2. In this embodiment, the first light-shielding pattern 410 is located between the second data line DL2 and the first extension portion 121, and the second light-shielding pattern 420 is located between the second data line DL2 and the second extension portion 122. From another point of view, as shown in FIGS. 1 and 2, in the present embodiment, the second data line DL2 correspondingly disposed between the first light-shielding pattern 410 and the second light-shielding pattern 420 is a portion having a width W3 .

In addition, in this embodiment, the light-shielding layer 400 may further include a third light-shielding pattern 430 and a fourth light-shielding pattern 440, wherein the third light-shielding pattern 430 is located between the first data line DL1 and the third extension portion 123, and the fourth The light-shielding pattern 440 is located between the third data line DL3 and the fourth extension portion 124. In this embodiment, the third light-shielding pattern 430 is disposed along the extending direction of the first data line DL1, and the fourth light-shielding pattern 440 is disposed along the extending direction of the third data line DL3. As shown in FIG. 1, in this embodiment, a portion corresponding to the first data line DL1 and the third light shielding pattern 430 is a portion having a width W1, and a portion corresponding to the third data line DL3 and the fourth light shielding pattern 440 is provided. It is the part with width W5.

In this embodiment, in the vertical projection direction N of the substrate 100, the first light-shielding pattern 410 does not overlap with the first main pixel electrode MPE1, and the second light-shielding pattern 420 does not overlap with the second main pixel electrode MPE2. The third light-shielding pattern 430 is not overlapped with the first main pixel electrode MPE1, and the fourth light-shielding pattern 440 is not overlapped with the second main pixel electrode MPE2. From another perspective, in this embodiment, the first light-shielding pattern 410 and the third light-shielding pattern 430 are located on both sides of the first main pixel electrode MPE1, and the second light-shielding pattern 420 and the fourth light-shielding pattern 440 are located on the second Both sides of the main pixel electrode MPE2.

In this embodiment, the light shielding layer 400 and the semiconductor pattern layer SM1 of the first switching element SW1, the semiconductor pattern layer SM2 of the second switching element SW2, the semiconductor pattern layer SM3 of the third switching element SW3, and the semiconductor of the fourth switching element SW4. The pattern layer SM4 belongs to the same film layer. That is, in this embodiment, the light shielding layer 400, the semiconductor pattern layer SM1, the semiconductor pattern layer SM2, the semiconductor pattern layer SM3, and the semiconductor pattern layer SM4 have substantially the same material, and the light shielding layer 400, the semiconductor pattern layer SM1, and the like. The semiconductor pattern layer SM2, the semiconductor pattern layer SM3, and the semiconductor pattern layer SM4 are formed in the same mask process. From another perspective, in this embodiment, the first light-shielding pattern 410, the second light-shielding pattern 420, the third light-shielding pattern 430, and the fourth light-shielding pattern 440 are formed on the first extension portion 121 and the second extension portion 122. , The third extension portion 123 and the fourth extension portion 124 are formed later.

In this embodiment, the first insulating layer 210 is entirely formed on the substrate 100 and covers the scan lines SL and the common lines CL. As described above, part of the scan line SL is used as the gate electrode G1, the gate electrode G2, the gate electrode G3, and the gate electrode G4. Therefore, in this embodiment, the first insulating layer 210 functions as a gate insulating layer. In this embodiment, the first insulating layer 210 may have a single-layer or multi-layer structure, and the material of the first insulating layer 210 may include an inorganic material, an organic material, or other suitable materials. The inorganic material includes, for example, (but not limited to) ): Silicon oxide, silicon nitride, or silicon oxynitride; organic materials include (but are not limited to): polyimide resin, epoxy resin, or acrylic resin. In this embodiment, the first data line DL1, the second data line DL2, the third data line DL3, and the light shielding layer 400 are disposed on the first insulating layer 210.

In this embodiment, the second insulating layer 220 is entirely formed on the substrate 100 and is disposed on the first data line DL1, the second data line DL2, the third data line DL3, and the first insulation layer 210. As described above, the source S1, the source S3, and the first data line DL1 are a continuous conductive pattern, the source S2, the source S4, and the second data line DL2 are a continuous conductive pattern, and the light shielding layer 400, The semiconductor pattern layer SM1, the semiconductor pattern layer SM2, the semiconductor pattern layer SM3, and the semiconductor pattern layer SM4 belong to the same film layer. Therefore, in this embodiment, the second insulating layer 220 can provide insulation and protection for the first switching element SW1, the second switch The functions of the element SW2, the third switching element SW3, and the fourth switching element SW4. In this embodiment, the second insulating layer 220 may have a single-layer or multi-layer structure, and the material of the second insulating layer 220 may include an inorganic material, an organic material, or other suitable materials. The inorganic material includes, for example, but is not limited to ): Silicon oxide, silicon nitride, or silicon oxynitride; organic materials include (but are not limited to): polyimide resin, epoxy resin, or acrylic resin.

In this embodiment, the first filter layer CF1 is disposed on the second insulating layer 220 and is located below the first main pixel electrode MPE1 and the first pixel electrode SPE1. In this embodiment, the first filter layer CF1 may be any one of the filter layers for display panels known to those having ordinary skill in the art. For example, the color of the first filter layer CF1 may be red, green, or blue. In one embodiment, the first filter layer CF1 is, for example, a green filter layer.

In this embodiment, the second filter layer CF2 is disposed on the second insulating layer 220 and is located below the second main pixel electrode MPE2 and the second pixel electrode SPE2. In this embodiment, the second filter layer CF2 may be any one of the filter layers for display panels known to those having ordinary skill in the art. For example, the color of the second filter layer CF2 may be red, green, or blue. In addition, in this embodiment, the colors of the second filter layer CF2 and the first filter layer CF1 are different, but the present invention is not limited thereto. In one embodiment, the second filter layer CF2 is, for example, a red filter layer.

In addition, in this embodiment, a part of the first filter layer CF1 and a part of the second filter layer CF2 overlap each other above the second data line DL2 to form a stacked structure 300. That is, in this embodiment, the first filter layer CF1 and the second filter layer CF2 are partially overlapped to form a stacked structure 300 located on the second data line DL2.

In this embodiment, the protective layer 230 is entirely formed on the substrate 100 and is disposed on the first filter layer CF1 and the second filter layer CF2 to provide protection for the first filter layer CF1 and the second filter layer. CF2 function. In this embodiment, the protective layer 230 may have a single-layer or multi-layer structure, and its material may include inorganic materials (for example, silicon oxide, silicon nitride, silicon oxynitride, other suitable materials), organic materials, or other suitable materials. s material.

In this embodiment, the first primary pixel electrode MPE1, the first primary pixel electrode SPE1, the second primary pixel electrode MPE2, and the second primary pixel electrode SPE2 are located on the protective layer 230. In this embodiment, a contact window C1 for electrically connecting the first main pixel electrode MPE1 and the drain electrode D1 may be formed in the second insulating layer 220, the first filter layer CF1, and the protective layer 230 for electrical connection. A contact window C3 for firstly connecting the first pixel electrode SPE1 and the drain electrode D3 may be formed in the second insulating layer 220, the first filter layer CF1, and the protective layer 230 to electrically connect the second main pixel electrode MPE2. A contact window C2 with the drain electrode D2 may be formed in the second insulating layer 220, the second filter layer CF2, and the protective layer 230. The contact window C4 for electrically connecting the second pixel electrode SPE2 and the drain electrode D4 may be The second insulating layer 220, the second filter layer CF2, and the protective layer 230 are formed, but the present invention is not limited thereto.

In this embodiment, the common electrode CE is disposed on the first data line DL1, the second data line DL2, and the third data line DL3, so that when the pixel structure 1 is applied to a liquid crystal display panel, liquid crystal can be well avoided. The molecules are disturbed by the display signal and have a good liquid crystal alignment. In this embodiment, the first primary pixel electrode MPE1, the first primary pixel electrode SPE1, the second primary pixel electrode MPE2, and the second primary pixel electrode SPE1 belong to the same film layer as the common electrode CE. That is, in this embodiment, the first primary pixel electrode MPE1, the first primary pixel electrode SPE1, the second primary pixel electrode MPE2, and the second primary pixel electrode SPE1 and the common electrode CE have substantially the same The material, and the first primary pixel electrode MPE1, the first primary pixel electrode SPE1, the second primary pixel electrode MPE2, and the second primary pixel electrode SPE1 and the common electrode CE are formed in the same mask process.

In addition, in this embodiment, the common electrode CE is electrically connected to the common line CL through the connection structure CS. That is, in this embodiment, the common electrode CE and the common line CL are electrically connected to the same first common voltage.

In this embodiment, the first signal line 130 is disposed between the first data line DL1 and the second data line DL2, and the second signal line 140 is disposed between the second data line DL2 and the third data line DL3. In this embodiment, the first signal line 130 and the second signal line 140 respectively extend from the second side 114 of the scan line SL toward the first side 112 of the scan line SL. From another point of view, in this embodiment, the first signal line 130 and the second signal line 140 are staggered with the scanning line SL, and are staggered with the common line CL, respectively.

In this embodiment, the first signal line 130 and the second signal line 140 belong to the same film layer as the first data line DL1, the second data line DL2, and the third data line DL3. That is, in this embodiment, the first signal line 130 and the second signal line 140 have substantially the same material as the first data line DL1, the second data line DL2, and the third data line DL3, and the first signal The line 130 and the second signal line 140 are formed in the same mask process with the first data line DL1, the second data line DL2, and the third data line DL3. As such, in this embodiment, the first signal line 130 and the second signal line 140 are disposed on the first insulating layer 210 and below the second insulating layer 220.

In this embodiment, the first signal line 130 is electrically connected to the fifth switching element SW5, and the fifth switching element SW5 is electrically connected to the third switching element SW3. The second signal line 140 is electrically connected to the sixth switching element SW6, and the sixth switching element SW6 is electrically connected to the third switching element SW4. The first signal line 130 and the second signal line 140 are electrically connected to a second common voltage, wherein the second common voltage is different from the first common voltage to which the common line CL is electrically connected, and the second common voltage is, for example, about 0.3. Volts to 16.3 volts. It is worth mentioning that, in this embodiment, the pixel structure 1 is electrically connected to the first common voltage through the common electrode CE and the common line CL, and the first signal line 130 and the second signal line 140 are electrically connected to different The second common voltage at the first common voltage enables the pixel structure 1 to increase the voltage difference applied to the liquid crystal molecules when the pixel structure 1 is applied to a liquid crystal display panel, and effectively improves the transmittance of the liquid crystal display panel.

It is worth noting that, as mentioned above, in this embodiment, the first light-shielding pattern 410 and the second light-shielding pattern 420 through the light-shielding layer 400 are respectively located on the first main pixel electrode MPE1 and the second main pixel electrode MPE2 The two data lines DL2 between the two sides, and the first light-shielding pattern 410 is located between the second data line DL2 and the first extension 121 of the common line CL, and the second light-shielding pattern 420 is located between the second data line DL2 and the common Between the second extensions 122 of the line CL, the flatness of the terrain on both sides of the second data line DL2 in the pixel structure 1 is better than that of the pixel structure without a light-shielding layer (as shown in FIG. 5). This is because in a pixel structure without a light-shielding layer, a terrain defect area DF is generated on both sides of the second data line DL2, so that the terrain change on both sides of the second data line DL2 is large, as shown in FIG. 5. In this way, compared with the pixel structure without a light-shielding layer (as shown in FIG. 5), when the pixel structure 1 is applied to a liquid crystal display surface, the flatness on both sides of the second data line DL2 is better. , So that the correspondingly arranged liquid crystal molecules can have a good alignment, thereby improving the problem of abnormal light leakage near the second data line DL2.

In addition, as described above, in this embodiment, the light shielding layer 400 and the semiconductor pattern layer SM1, the semiconductor pattern layer SM2, the semiconductor pattern layer SM3, and the semiconductor pattern layer SM4 belong to the same film layer, and thus may have about 10% to about 40 % Light transmittance. In this way, the first light-shielding pattern 410 and the second light-shielding pattern 420 passing through the light-shielding layer 400 are respectively located on two sides of the second data line DL2 between the first main pixel electrode MPE1 and the second main pixel electrode MPE2. And the first light-shielding pattern 410 is located between the second data line DL2 and the first extension 121 of the common line CL, and the second light-shielding pattern 420 is located between the second data line DL2 and the second extension 122 of the common line CL, so that When the pixel structure 1 is applied to a liquid crystal display surface, the light-shielding layer 400 can effectively shield light incident between the second data line DL2 and the first extension 121 and between the second data line DL2 and the second extension 122 , Thereby improving the problem of abnormal light leakage near the second data line DL2.

In addition, in the embodiment of FIGS. 1 to 4, the light shielding layer 400 in the pixel structure 1 and the semiconductor pattern layer SM1, the semiconductor pattern layer SM2, the semiconductor pattern layer SM3, and the semiconductor pattern layer SM4 belong to the same film layer, but the present invention It is not limited to this. Hereinafter, other variations will be described in detail with reference to FIG. 6. It must be noted here that the following embodiments inherit the component symbols and parts of the foregoing embodiments, in which the same or similar symbols are used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments are not repeatedly described.

6 is a schematic cross-sectional view of a pixel structure according to another embodiment of the present invention. It should be noted that the cross-sectional position of FIG. 6 may correspond to the position of the cross-sectional line I-I 'of FIG. 2, and the top view of the pixel structure 2 of FIG. 6 corresponds to FIG. 1.

Please refer to FIG. 6 and FIG. 4 at the same time. The pixel structure 2 of FIG. 6 is similar to the pixel structure 1 of FIG. For the description of the omitted parts, reference may be made to the foregoing embodiments in FIGS. 1 to 4. Hereinafter, differences between the pixel structure 2 of FIG. 6 and the pixel structure 1 of FIG. 4 will be described.

Referring to FIG. 6, in this embodiment, the first light-shielding pattern 410 and the second light-shielding pattern 420 of the light-shielding layer 400 are disposed on the second insulating layer 220. That is, in this embodiment, the light shielding layer 400 is formed after the first extension portion 121 and the second extension portion 122 are formed and after the second data line DL2 is formed. From another point of view, in this embodiment, the light shielding layer 400 does not belong to the same film layer as the semiconductor pattern layer SM1 and the semiconductor pattern layer SM2, and does not belong to the same film layer as the first extension portion 121 and the second extension portion 122. Nor does it belong to the same film layer as the second data line DL2. Specifically, in one embodiment, the light shielding layer 400 may be made of another metal layer, and the material of the light shielding layer 400 may include (but is not limited to): aluminum, molybdenum, or titanium.

It is worth noting that, as described above, in this embodiment, the first light-shielding pattern 410 and the second light-shielding pattern 420 through the light-shielding layer 400 are respectively located on the first main pixel electrode MPE1 and the second main pixel electrode MPE2. The two data lines DL2 between the two sides, and the first light-shielding pattern 410 is located between the second data line DL2 and the first extension 121 of the common line CL, and the second light-shielding pattern 420 is located between the second data line DL2 and the common Between the second extensions 122 of the line CL, compared with a pixel structure (as shown in FIG. 5) without a light-shielding layer, when the pixel structure 2 is applied to a liquid crystal display surface, the second data line The topography on both sides of DL2 is better, so that the correspondingly arranged liquid crystal molecules can have a good alignment, thereby improving the problem of abnormal light leakage near the second data line DL2.

In addition, as described above, in this embodiment, the material of the light shielding layer 400 may include metal, so the first light shielding pattern 410 and the second light shielding pattern 420 passing through the light shielding layer 400 are respectively located on the first main pixel electrode MPE1 and Both sides of the second data line DL2 between the second main pixel electrode MPE2, and the first light-shielding pattern 410 is located between the second data line DL2 and the first extension 121 of the common line CL, and the second light-shielding pattern 420 is located Between the second data line DL2 and the second extension 122 of the common line CL, when the pixel structure 2 is applied to the liquid crystal display surface, the light shielding layer 400 can effectively shield the incident on the second data line DL2 and the first extension The light between 121 and the second data line DL2 and the second extension 122 further improves the problem of abnormal light leakage near the second data line DL2.

In summary, the pixel structure according to the embodiment of the present invention includes a light-shielding layer, a first main pixel electrode and a second main pixel electrode located on a first side of a scan line, and a common line located on a first side of the scan line. , Wherein a second data line is provided between the first main pixel electrode and the second main pixel electrode, and the common line includes a main part disposed along the extending direction of the scanning line, and is electrically connected to the main part and located at the second The first extension portion and the second extension portion on both sides of the data line. The light-shielding layer includes a first light-shielding pattern and a second light-shielding pattern on the two sides of the second data line. And the second light-shielding pattern is located between the second data line and the second extension portion. Through the above pixel structure, the flatness of the terrain on both sides of the second data line is good. Therefore, when the pixel structure is applied to a liquid crystal display panel, the liquid crystal molecules corresponding to the second data line can have a good alignment, thereby improving the second Abnormal light leakage near the data line.

Although the present invention has been disclosed as above in the embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouches without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

1‧‧‧ pixel structure

100‧‧‧ substrate

112, 116‧‧‧ First side

114, 118‧‧‧ second side

120‧‧‧ Leader

121‧‧‧First extension

122‧‧‧Second Extension

123‧‧‧Third Extension

124‧‧‧Fourth Extension

130‧‧‧The first signal line

140‧‧‧The second signal line

210‧‧‧The first insulation layer

220‧‧‧Second insulation layer

230‧‧‧ protective layer

300‧‧‧ stacked structure

400‧‧‧ light-shielding layer

410‧‧‧first shading pattern

420‧‧‧Second shading pattern

430‧‧‧ third shade pattern

440‧‧‧Fourth shading pattern

Areas A and B‧‧‧

C1, C2, C3, C4‧‧‧ contact windows

CE‧‧‧Common electrode

CF1‧‧‧first filter layer

CF2‧‧‧Second filter layer

CL‧‧‧ shared line

CS‧‧‧ Connection Structure

D1, D2, D3, D4‧‧‧ Drain

DF‧‧‧ terrain defect area

DL1‧‧‧The first data line

DL2‧‧‧Second Data Line

DL3‧‧‧Third Data Line

G1, G2, G3, G4‧‧‧ Gate

MPE1‧‧‧The first main pixel electrode

MPE2‧‧‧Second main pixel electrode

N‧‧‧ vertical projection direction

S1, S2, S3, S4‧‧‧ source

SL‧‧‧scan line

SM1, SM2, SM3, SM4‧‧‧ semiconductor pattern layer

SPE1‧‧‧The first pixel electrode

SPE2‧‧‧Second pixel electrode

SW1‧‧‧The first switching element

SW2‧‧‧Second switching element

SW3‧‧‧The third switching element

SW4‧‧‧Fourth switching element

SW5‧‧‧The fifth switching element

SW6‧‧‧ Sixth switching element

W1, W2, W3, W4, W5, W6‧‧‧Width

FIG. 1 is a schematic top view of a pixel structure according to an embodiment of the present invention. FIG. 2 is an enlarged view of a region A in FIG. 1. FIG. 3 is an enlarged view of a region B in FIG. 1. Fig. 4 is a schematic cross-sectional view taken along the line I-I 'in Fig. 2. FIG. 5 is a schematic cross-sectional view of a pixel structure without a light-shielding layer. 6 is a schematic cross-sectional view of a pixel structure according to another embodiment of the present invention.

Claims (11)

A pixel structure includes: a substrate; a scan line disposed on the substrate; a first data line and a second data line disposed on the substrate and intersecting the scan line; a first A switching element is electrically connected to the scanning line and the first data line; a second switching element is electrically connected to the scanning line and the second data line; a first main pixel electrode is connected to the first The switching element is electrically connected and located on a first side of the scanning line; a second main pixel electrode is electrically connected to the second switching element and is located on the first side of the scanning line, wherein the second The data line is located between the first main pixel electrode and the second main pixel electrode; a common line is disposed on the substrate and is located on the first side of the scan line, and includes: a main part, along the It is disposed along the extension direction of the scanning line; and a first extension portion and a second extension portion are electrically connected to the trunk portion and are respectively located on both sides of the second data line; and a light shielding layer including: a The first light-shielding pattern and a second light-shielding pattern Respectively located on two sides of the second data line, wherein the first light-shielding pattern is located between the second data line and the first extension portion, and the second light-shielding pattern is located on the second data line and the second extension portion between. The pixel structure described in item 1 of the patent application scope further includes: a third switch element electrically connected to the scan line and the first data line; a fourth switch element connected to the scan line and the first data line; Two data lines are electrically connected; a first pixel electrode is electrically connected to the third switching element and is located on a second side of the scan line; and a second pixel electrode is connected to the fourth switch The components are electrically connected and located on the second side of the scan line, wherein the second data line is located between the first pixel electrode and the second pixel electrode. The pixel structure according to item 2 of the scope of patent application, wherein the common line further includes a third extension portion and a fourth extension portion, which are electrically connected to the trunk portion, the first extension portion and the third extension portion. Parts are located on both sides of the first main pixel electrode and partially overlap with the first main pixel electrode, and the second extension part and the fourth extension part are located on both sides of the second main pixel electrode and are connected to the The second main pixel electrode partially overlaps. The pixel structure according to item 2 of the scope of patent application, wherein in a vertical projection direction of the substrate, the first main pixel electrode and the second main pixel electrode are not overlapped with the second data line, The first pixel electrode and the second pixel electrode are disposed overlapping the second data line. The pixel structure according to item 2 of the scope of patent application, wherein a width of the second data line between the first main pixel electrode and the second main pixel electrode is smaller than that of the first pixel electrode. The width of the second data line from the second pixel electrode. The pixel structure according to item 2 of the patent application scope further includes: a first insulating layer covering the scanning line and the common line, and the first data line, the second data line and the light shielding layer are disposed On the first insulating layer; a second insulating layer is disposed on the first data line, the second data line, the light shielding layer and the first insulating layer; a first filter layer is disposed on the first Two insulating layers, and the first main pixel electrode and the first pixel electrode are located on the first filter layer; and a second filter layer is disposed on the second insulating layer, and the The second main pixel electrode and the second pixel electrode are located on the second filter layer. The pixel structure according to item 6 of the patent application scope further includes: a protective layer disposed on the first filter layer and the second filter layer, and the first main pixel electrode, the first The secondary pixel electrode, the second primary pixel electrode and the second secondary pixel electrode are located on the protective layer. The pixel structure according to item 6 of the application, wherein the second filter layer and the first filter layer partially overlap to form a laminated structure, and the laminated structure is located on the second data line. The pixel structure according to item 1 of the patent application scope further includes: a common electrode disposed on the second data line; and a connection structure for electrically connecting the common line and the common electrode. The pixel structure according to item 1 of the scope of patent application, wherein in a vertical projection direction of the substrate, the first light-shielding pattern and the first main pixel electrode are not overlapped, and the second light-shielding pattern and the first The two main pixel electrodes are not overlapped. The pixel structure according to item 1 of the patent application scope, wherein the first switching element includes a first semiconductor pattern layer, the second switching element includes a second semiconductor pattern layer, and the light-shielding layer and the first semiconductor The pattern layer and the second semiconductor pattern layer belong to the same film layer.