TW202004311A - Pixel structure - Google Patents
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- TW202004311A TW202004311A TW107117076A TW107117076A TW202004311A TW 202004311 A TW202004311 A TW 202004311A TW 107117076 A TW107117076 A TW 107117076A TW 107117076 A TW107117076 A TW 107117076A TW 202004311 A TW202004311 A TW 202004311A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
Abstract
Description
本發明是有關於一種畫素結構,且特別是有關於一種可改善異常漏光問題的畫素結構。The invention relates to a pixel structure, and in particular to a pixel structure that can improve the problem of abnormal light leakage.
在大尺寸的顯示面板的製程中,由於面板尺寸過大,無法對整個面板同時進行曝光,而需要將顯示面板分為至少兩個區域以進行曝光。但是,這樣的做法會因為兩次曝光條件的差異,使得在顯示面板中央產生明顯的接曝線,並使得資料線附近的地形不平坦,進而導致資料線附近發生異常漏光。In the manufacturing process of a large-sized display panel, because the size of the panel is too large, the entire panel cannot be exposed at the same time, and the display panel needs to be divided into at least two areas for exposure. However, this method will cause obvious exposure lines in the center of the display panel due to the difference in the two exposure conditions, and make the terrain near the data line uneven, which will cause abnormal light leakage near the data line.
因此,如何解決顯示面板中的異常漏光問題,實為目前研發人員亟欲解決的問題之一。Therefore, how to solve the problem of abnormal light leakage in the display panel is actually one of the problems that the R&D personnel urgently want to solve.
有鑑於此,本發明提供一種畫素結構,能夠改善先前技術中存在的異常漏光問題。In view of this, the present invention provides a pixel structure that can improve the problem of abnormal light leakage in the prior art.
本發明的一實施方式提供一種畫素結構,包括基板、掃描線、第一資料線、第二資料線、第一開關元件、第二開關元件、第一主畫素電極、第二主畫素電極、共用線、以及遮光層。掃描線設置於基板之上。第一資料線與第二資料線設置於基板之上並與掃描線交叉設置。第一開關元件與掃描線以及第一資料線電性連接。第二開關元件與掃描線以及第二資料線電性連接。第一主畫素電極與第一開關元件電性連接且位於掃描線的第一側。第二主畫素電極與第二開關元件電性連接且位於掃描線的第一側,其中第二資料線位於第一主畫素電極與第二主畫素電極之間。共用線設置於基板之上並位於掃描線的第一側,且共用線包括沿著掃描線的延伸方向設置的主幹部,以及與主幹部電性連接且分別位於第二資料線的兩側的第一延伸部與第二延伸部。遮光層包括分別位於第二資料線的兩側的第一遮光圖案與第二遮光圖案,其中第一遮光圖案位於第二資料線與第一延伸部之間,且第二遮光圖案位於第二資料線與第二延伸部之間。An embodiment of the present invention provides a pixel structure including a substrate, a scanning line, a first data line, a second data line, a first switching element, a second switching element, a first main pixel electrode, and a second main pixel The electrode, the common line, and the light shielding layer. The scanning line is disposed on the substrate. The first data line and the second data line are disposed on the substrate and cross the scanning line. The first switching element is electrically connected to the scan line and the first data line. The second switching element is electrically connected to the scan line and the second data line. The first main pixel electrode is electrically connected to the first switching element and is located on the first side of the scan line. The second main pixel electrode is electrically connected to the second switching element and located on the first side of the scan line, wherein the second data line is located between the first main pixel electrode and the second main pixel electrode. The common line is disposed on the substrate and located on the first side of the scan line, and the common line includes a trunk portion provided along the extending direction of the scan line, and electrical connections to the trunk portion on both sides of the second data line The first extension and the second extension. The light shielding layer includes a first light shielding pattern and a second light shielding pattern located on both sides of the second data line, wherein the first light shielding pattern is located between the second data line and the first extension, and the second light shielding pattern is located on the second data Between the line and the second extension.
基於上述,在本發明的畫素結構中,透過遮光層包括分別位於第二資料線兩側的第一遮光圖案與第二遮光圖案,第一遮光圖案位於第二資料線與第一延伸部之間,且第二遮光圖案位於第二資料線與第二延伸部之間,使得位於第二資料線兩旁的地形平坦性良好,因而將畫素結構應用於液晶顯示面板時,對應第二資料線附近設置的液晶分子能夠具有良好排列,藉以改善第二資料線附近的異常漏光問題。Based on the above, in the pixel structure of the present invention, the light-shielding layer includes a first light-shielding pattern and a second light-shielding pattern respectively located on both sides of the second data line, and the first light-shielding pattern is located between the second data line and the first extension And the second light-shielding pattern is located between the second data line and the second extension portion, so that the terrain on both sides of the second data line has good flatness, so when the pixel structure is applied to the liquid crystal display panel, it corresponds to the second data line The liquid crystal molecules arranged nearby can have good alignment, thereby improving the problem of abnormal light leakage near the second data line.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施方式,並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the embodiments are specifically described below and described in detail in conjunction with the accompanying drawings.
以下將以圖式揭露本發明的多個實施方式,為明確說明起見,許多實務上的細節將在以下敘述中一併說明。然而,應瞭解到,這些實務上的細節不應用以限制本發明。也就是說,在本發明部分實施方式中,這些實務上的細節是非必要的。此外,為簡化圖式起見,一些習知慣用的結構與元件在圖式中將以簡單示意地方式為之。In the following, various embodiments of the present invention will be disclosed in the form of diagrams. For the sake of clear description, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present invention. That is to say, in some embodiments of the present invention, these practical details are unnecessary. In addition, for the sake of simplifying the drawings, some conventionally used structures and elements will be shown in a simple and schematic manner in the drawings.
本文使用的「約」、「近似」、「本質上」、或「實質上」包括所述值和在本領域普通技術人員確定的特定值的可接受的偏差範圍內的平均值,考慮到所討論的測量和與測量相關的誤差的特定數量(即,測量系統的限制)。例如,「約」可以表示在所述值的一個或多個標準偏差內,或例如±30%、±20%、±15%、±10%、±5%內。再者,本文使用的「約」、「近似」、「本質上」、或「實質上」可依光學性質、蝕刻性質或其它性質,來選擇較可接受的偏差範圍或標準偏差,而可不用一個標準偏差適用全部性質。As used herein, "about", "approximately", "essentially", or "substantially" includes the stated value and the average value within the acceptable deviation range of the specific value determined by those of ordinary skill in the art, considering The measurement in question and the specific number of errors associated with the measurement (ie, the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or for example within ±30%, ±20%, ±15%, ±10%, ±5%. Furthermore, the terms "approximately", "approximately", "essentially", or "substantially" as used herein can be based on optical properties, etching properties, or other properties to select a more acceptable range of deviation or standard deviation, instead of One standard deviation applies to all properties.
在附圖中,為了清楚起見,放大了層、膜、面板、區域等的厚度。在整個說明書中,相同的附圖元件符號表示相同的元件。應當理解,當諸如層、膜、區域或基板的元件被稱為在另一元件「上」或「連接到」另一元件時,其可以直接在另一元件上或與另一元件連接,或者與來一元件之間可以存在中間元件。相反地,當元件被稱為「直接在另一元件上」或「直接連接到」另一元件時,其間不存在中間元件。如本文所使用的,「連接」可以指物理及/或電性連接(耦接或耦合)。因此,二元件間之電性連接(或耦接/耦合)可存在中間元件。In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Throughout the specification, the same drawing element symbol indicates the same element. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected" to another element, it can be directly on or connected to the other element, or There may be an intermediate element between one element and the next. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connections (coupled or coupled). Therefore, the electrical connection (or coupling/coupling) between the two elements may exist in the intermediate element.
除非另有定義,本文使用的所有術語(包括技術和科學術語)具有與本發明所屬領域的普通技術人員通常理解的相同的含義。將進一步理解的是,諸如在通常使用的字典中定義的那些術語應當被解釋為具有與它們在相關技術和本發明的上下文中的含義一致的含義,並且將不被解釋為理想化的或過度正式的意義,除非本文中明確地這樣定義。Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology and the present invention, and will not be interpreted as idealized or excessive Formal meaning unless explicitly defined as such in this article.
圖1是本發明的一實施方式的畫素結構的上視示意圖。圖2是圖1中的區域A的放大圖。圖3是圖1中的區域B的放大圖。圖4是沿圖2中的剖線I-I’的剖面示意圖。FIG. 1 is a schematic top view of a pixel structure according to an embodiment of the present invention. FIG. 2 is an enlarged view of the area A in FIG. 1. FIG. 3 is an enlarged view of the area B in FIG. 1. Fig. 4 is a schematic cross-sectional view taken along line I-I' in Fig. 2.
請同時參照圖1至圖4,畫素結構1包括基板100、掃描線SL、第一資料線DL1、第二資料線DL2、第一開關元件SW1、第二開關元件SW2、第一主畫素電極MPE1、第二主畫素電極MPE2、共用線CL以及遮光層400。此外,在本實施方式中,畫素結構1可更包括第三資料線DL3、第三開關元件SW3、第四開關元件SW4、第一次畫素電極SPE1、第二次畫素電極SPE2、第一絕緣層210、第二絕緣層220、第一濾光層CF1、第二濾光層CF2、保護層230、共用電極CE、連接結構CS、第一訊號線130以及第二訊號線140。為了方便說明起見,圖1中省略繪示第一絕緣層210、第二絕緣層220、第一濾光層CF1、第二濾光層CF2以及保護層230等構件。Please refer to FIGS. 1 to 4 at the same time. The
在本實施方式中,基板100可為可撓性基板,例如聚合物基板或塑膠基板,但本發明並不限於此。在其他實施方式中,基板100也可以是剛性基板,例如玻璃基板、石英基板或矽基板。In this embodiment, the
在本實施方式中,掃描線SL、第一資料線DL1、第二資料線DL2以及第三資料線DL3設置於基板100之上。在本實施方式中,第一資料線DL1、第二資料線DL2以及第三資料線DL3分別與掃描線SL交叉設置。也就是說,在本實施方式中,掃描線SL的延伸方向與第一資料線DL1、第二資料線DL2以及第三資料線DL3的延伸方向不相同,較佳的是掃描線SL的延伸方向與第一資料線DL1、第二資料線DL2以及第三資料線DL3的延伸方向交叉(例如:實質上垂直)。此外,掃描線SL與第一資料線DL1、第二資料線DL2以及第三資料線DL3可分別位於不相同的膜層,且掃描線SL與第一資料線DL1、第二資料線DL2以及第三資料線DL3之間夾有第一絕緣層210(於後文進行詳細描述)。基於導電性的考量,掃描線SL、第一資料線DL1、第二資料線DL2以及第三資料線DL3一般是使用金屬材料來製作。然而,本發明並不限於此,根據其他實施方式,掃描線SL、第一資料線DL1、第二資料線DL2以及第三資料線DL3也可以使用例如合金、金屬材料之氮化物、金屬材料之氧化物、金屬材料之氮氧化物、非金屬但具導電特性的材料、或是其它合適的材料。In this embodiment, the scan line SL, the first data line DL1, the second data line DL2, and the third data line DL3 are disposed on the
在本實施方式中,第一資料線DL1、第二資料線DL2與第三資料線DL3分別具有不同的寬度。詳細而言,如圖1所示,在本實施方式中,第一資料線DL1具有寬度W1及寬度W2,第二資料線DL2具有寬度W3及寬度W4,第三資料線DL3具有寬度W5及寬度W6,其中寬度W1小於寬度W2,寬度W3小於寬度W4,寬度W5小於寬度W6。在一實施方式中,寬度W1、寬度W3及寬度W5分別例如是介於4 μm至6 μm之間,寬度W2、寬度W4及寬度W6分別例如是介於12 μm至16 μm之間。另外,在本實施方式中,第一資料線DL1、第二資料線DL2與第三資料線DL3分別具有寬度漸變的部分,但本發明並不限於此。In this embodiment, the first data line DL1, the second data line DL2, and the third data line DL3 have different widths. In detail, as shown in FIG. 1, in this embodiment, the first data line DL1 has a width W1 and a width W2, the second data line DL2 has a width W3 and a width W4, and the third data line DL3 has a width W5 and a width W6, wherein the width W1 is smaller than the width W2, the width W3 is smaller than the width W4, and the width W5 is smaller than the width W6. In one embodiment, the width W1, the width W3 and the width W5 are respectively between 4 μm and 6 μm, and the width W2, the width W4 and the width W6 are respectively between 12 μm and 16 μm. In addition, in the present embodiment, the first data line DL1, the second data line DL2, and the third data line DL3 each have a gradual width portion, but the present invention is not limited to this.
在本實施方式中,第一開關元件SW1設置於基板100之上,且與掃描線SL以及第一資料線DL1電性連接。在本實施方式中,第一開關元件SW1包括閘極G1、與閘極G1對應設置的半導體圖案層SM1、電性連接於半導體圖案層SM1的源極S1和汲極D1。在本實施方式中,掃描線SL的部分區域是作為閘極G1,此表示閘極G1與掃描線SL電性連接。從另一觀點而言,在本實施方式中,閘極G1與掃描線SL屬於同一膜層。也就是說,在本實施方式中,閘極G1與掃描線SL具有實質上相同的材質,以及閘極G1與掃描線SL是在同一道光罩製程(photolithography and etching process,PEP)中形成。值得一提的是,掃描線的部分區域是作為閘極可包含從掃描線延伸出的一部份或者是掃描線本身之一部份。In this embodiment, the first switching element SW1 is disposed on the
在本實施方式中,源極S1與第一資料線DL1為一連續的導電圖案,此表示源極S1與第一資料線DL1電性連接。從另一觀點而言,在本實施方式中,源極S1與第一資料線DL1屬於同一膜層。也就是說,在本實施方式中,源極S1與第一資料線DL1具有實質上相同的材質,以及源極S1與第一資料線DL1是在同一道光罩製程中形成。In this embodiment, the source S1 and the first data line DL1 are a continuous conductive pattern, which means that the source S1 and the first data line DL1 are electrically connected. From another viewpoint, in this embodiment, the source S1 and the first data line DL1 belong to the same film layer. That is to say, in this embodiment, the source S1 and the first data line DL1 have substantially the same material, and the source S1 and the first data line DL1 are formed in the same mask process.
在本實施方式中,半導體圖案層SM1位於閘極G1的上方,且源極S1和汲極D1位於半導體圖案層SM1的上方。也就是說,在本實施方式中,第一開關元件SW1是以底部閘極型薄膜電晶體為例來說明,但本發明不限於此。在其他實施方式中,第一開關元件SW1也可以是頂部閘極型薄膜電晶體、立體型薄膜電晶體、或其它合適類型之薄膜電晶體。In this embodiment, the semiconductor pattern layer SM1 is located above the gate electrode G1, and the source electrode S1 and the drain electrode D1 are located above the semiconductor pattern layer SM1. That is, in the present embodiment, the first switching element SW1 is explained by taking the bottom gate type thin film transistor as an example, but the present invention is not limited to this. In other embodiments, the first switching element SW1 may also be a top gate thin film transistor, a three-dimensional thin film transistor, or other suitable types of thin film transistors.
另外,在本實施方式中,源極S1和汲極D1屬於同一膜層。也就是說,在本實施方式中,源極S1、汲極D1與第一資料線DL1具有實質上相同的材質,以及源極S1、汲極D1與第一資料線DL1是在同一道光罩製程中形成。In this embodiment, the source S1 and the drain D1 belong to the same film layer. That is to say, in this embodiment, the source S1, the drain D1 and the first data line DL1 have substantially the same material, and the source S1, the drain D1 and the first data line DL1 are in the same mask process中 Formation.
在本實施方式中,第二開關元件SW2設置於基板100之上,且與掃描線SL以及第二資料線DL2電性連接。在本實施方式中,第二開關元件SW2包括閘極G2、與閘極G2對應設置的半導體圖案層SM2、電性連接於半導體圖案層SM2的源極S2和汲極D2。在本實施方式中,掃描線SL的部分區域是作為閘極G2,此表示閘極G2與掃描線SL電性連接。從另一觀點而言,在本實施方式中,閘極G2與掃描線SL屬於同一膜層。也就是說,在本實施方式中,閘極G2與掃描線SL具有實質上相同的材質,以及閘極G2與掃描線SL是在同一道光罩製程中形成。In this embodiment, the second switching element SW2 is disposed on the
在本實施方式中,源極S2與第二資料線DL2為一連續的導電圖案,此表示源極S2與第二資料線DL2電性連接。從另一觀點而言,在本實施方式中,源極S2與第二資料線DL2屬於同一膜層。也就是說,在本實施方式中,源極S2與第二資料線DL2具有實質上相同的材質,以及源極S2與第二資料線DL2是在同一道光罩製程中形成。In this embodiment, the source S2 and the second data line DL2 are a continuous conductive pattern, which means that the source S2 and the second data line DL2 are electrically connected. From another viewpoint, in this embodiment, the source S2 and the second data line DL2 belong to the same film layer. That is to say, in this embodiment, the source S2 and the second data line DL2 have substantially the same material, and the source S2 and the second data line DL2 are formed in the same mask process.
在本實施方式中,半導體圖案層SM2位於閘極G2的上方,且源極S2和汲極D2位於半導體圖案層SM2的上方。也就是說,在本實施方式中,第二開關元件SW2是以底部閘極型薄膜電晶體為例來說明,但本發明不限於此。在其他實施方式中,第二開關元件SW2也可以是頂部閘極型薄膜電晶體、立體型薄膜電晶體、或其它合適類型之薄膜電晶體。In the present embodiment, the semiconductor pattern layer SM2 is located above the gate electrode G2, and the source electrode S2 and the drain electrode D2 are located above the semiconductor pattern layer SM2. That is, in the present embodiment, the second switching element SW2 is explained by taking the bottom gate type thin film transistor as an example, but the present invention is not limited to this. In other embodiments, the second switching element SW2 may also be a top gate thin film transistor, a three-dimensional thin film transistor, or other suitable types of thin film transistors.
另外,在本實施方式中,源極S2和汲極D2屬於同一膜層。也就是說,在本實施方式中,源極S2、汲極D2與第二資料線DL2具有實質上相同的材質,以及源極S2、汲極D2與第二資料線DL2是在同一道光罩製程中形成。In this embodiment, the source S2 and the drain D2 belong to the same film layer. In other words, in this embodiment, the source S2, the drain D2 and the second data line DL2 have substantially the same material, and the source S2, the drain D2 and the second data line DL2 are in the same mask process中 Formation.
在本實施方式中,第三開關元件SW3設置於基板100之上,且與掃描線SL以及第一資料線DL1電性連接。在本實施方式中,第三開關元件SW3包括閘極G3、與閘極G3對應設置的半導體圖案層SM3、電性連接於半導體圖案層SM3的源極S3和汲極D3。在本實施方式中,掃描線SL的部分區域是作為閘極G3,此表示閘極G3與掃描線SL電性連接。從另一觀點而言,在本實施方式中,閘極G3與掃描線SL屬於同一膜層。也就是說,在本實施方式中,閘極G3與掃描線SL具有實質上相同的材質,以及閘極G3與掃描線SL是在同一道光罩製程中形成。In this embodiment, the third switching element SW3 is disposed on the
在本實施方式中,源極S3與源極S1為一連續的導電圖案。詳細而言,如前文所述,源極S1與第一資料線DL1為一連續的導電圖案,因此源極S3、源極S1與第一資料線DL1彼此電性連接。從另一觀點而言,在本實施方式中,源極S3與第一資料線DL1屬於同一膜層。也就是說,在本實施方式中,源極S3與第一資料線DL1具有實質上相同的材質,以及源極S3與第一資料線DL1是在同一道光罩製程中形成。In this embodiment, the source S3 and the source S1 are a continuous conductive pattern. In detail, as described above, the source S1 and the first data line DL1 are a continuous conductive pattern, so the source S3, the source S1, and the first data line DL1 are electrically connected to each other. From another viewpoint, in this embodiment, the source S3 and the first data line DL1 belong to the same film layer. That is to say, in this embodiment, the source S3 and the first data line DL1 have substantially the same material, and the source S3 and the first data line DL1 are formed in the same mask process.
在本實施方式中,半導體圖案層SM3位於閘極G3的上方,且源極S3和汲極D3位於半導體圖案層SM3的上方。也就是說,在本實施方式中,第三開關元件SW3是以底部閘極型薄膜電晶體為例來說明,但本發明不限於此。在其他實施方式中,第三開關元件SW3也可以是頂部閘極型薄膜電晶體、立體型薄膜電晶體、或其它合適類型之薄膜電晶體。In this embodiment, the semiconductor pattern layer SM3 is located above the gate electrode G3, and the source electrode S3 and the drain electrode D3 are located above the semiconductor pattern layer SM3. That is, in the present embodiment, the third switching element SW3 is explained by taking the bottom gate type thin film transistor as an example, but the present invention is not limited to this. In other embodiments, the third switching element SW3 may also be a top gate thin film transistor, a three-dimensional thin film transistor, or other suitable types of thin film transistors.
另外,在本實施方式中,源極S3和汲極D3屬於同一膜層。也就是說,在本實施方式中,源極S3、汲極D3與第一資料線DL1具有實質上相同的材質,以及源極S3、汲極D3與第一資料線DL1是在同一道光罩製程中形成。In this embodiment, the source S3 and the drain D3 belong to the same film layer. That is to say, in this embodiment, the source S3, the drain D3 and the first data line DL1 have substantially the same material, and the source S3, the drain D3 and the first data line DL1 are in the same mask process中 Formation.
特別一提的是,在本實施方式中,源極S3與源極S1為一連續的導電圖案、半導體圖案層SM3與半導體圖案層SM1構成一連續的半導體圖案、且閘極G3與閘極G1為一連續的導電圖案,因此第一開關元件SW1與第三開關元件SW3可一起構成一雙汲極設計的薄膜電晶體,然而本發明並不限於此。In particular, in this embodiment, the source S3 and the source S1 are a continuous conductive pattern, the semiconductor pattern layer SM3 and the semiconductor pattern layer SM1 constitute a continuous semiconductor pattern, and the gate G3 and the gate G1 It is a continuous conductive pattern. Therefore, the first switching element SW1 and the third switching element SW3 together can form a dual-drain thin film transistor, but the invention is not limited thereto.
在本實施方式中,第四開關元件SW4設置於基板100之上,且與掃描線SL以及第二資料線DL2電性連接。在本實施方式中,第四開關元件SW4包括閘極G4、與閘極G4對應設置的半導體圖案層SM4、電性連接於半導體圖案層SM4的源極S4和汲極D4。在本實施方式中,掃描線SL的部分區域是作為閘極G4,此表示閘極G4與掃描線SL電性連接。從另一觀點而言,在本實施方式中,閘極G4與掃描線SL屬於同一膜層。也就是說,在本實施方式中,閘極G4與掃描線SL具有實質上相同的材質,以及閘極G4與掃描線SL是在同一道光罩製程中形成。In this embodiment, the fourth switching element SW4 is disposed on the
在本實施方式中,源極S4與源極S2為一連續的導電圖案。詳細而言,如前文所述,源極S2與第二資料線DL2為一連續的導電圖案,因此源極S4、源極S2與第二資料線DL2彼此電性連接。從另一觀點而言,在本實施方式中,源極S4與第二資料線DL2屬於同一膜層。也就是說,在本實施方式中,源極S4與第二資料線DL2具有實質上相同的材質,以及源極S4與第二資料線DL2是在同一道光罩製程中形成。In this embodiment, the source S4 and the source S2 are a continuous conductive pattern. In detail, as described above, the source S2 and the second data line DL2 are a continuous conductive pattern, so the source S4, the source S2, and the second data line DL2 are electrically connected to each other. From another point of view, in this embodiment, the source S4 and the second data line DL2 belong to the same film layer. That is to say, in this embodiment, the source S4 and the second data line DL2 have substantially the same material, and the source S4 and the second data line DL2 are formed in the same mask process.
在本實施方式中,半導體圖案層SM4位於閘極G4的上方,且源極S4和汲極D4位於半導體圖案層SM4的上方。也就是說,在本實施方式中,第四開關元件SW4是以底部閘極型薄膜電晶體為例來說明,但本發明不限於此。在其他實施方式中,第四開關元件SW4也可以是頂部閘極型薄膜電晶體、立體型薄膜電晶體、或其它合適類型之薄膜電晶體。In this embodiment, the semiconductor pattern layer SM4 is located above the gate electrode G4, and the source electrode S4 and the drain electrode D4 are located above the semiconductor pattern layer SM4. That is, in the present embodiment, the fourth switching element SW4 is explained by taking the bottom gate thin film transistor as an example, but the present invention is not limited to this. In other embodiments, the fourth switching element SW4 may also be a top gate thin film transistor, a three-dimensional thin film transistor, or other suitable types of thin film transistors.
另外,在本實施方式中,源極S4和汲極D4屬於同一膜層。也就是說,在本實施方式中,源極S4、汲極D4與第二資料線DL2具有實質上相同的材質,以及源極S4、汲極D4與第二資料線DL2是在同一道光罩製程中形成。In this embodiment, the source S4 and the drain D4 belong to the same film layer. That is to say, in this embodiment, the source S4, the drain D4 and the second data line DL2 have substantially the same material, and the source S4, the drain D4 and the second data line DL2 are in the same mask process中 Formation.
特別一提的是,在本實施方式中,源極S4與源極S2為一連續的導電圖案、半導體圖案層SM4與半導體圖案層SM2構成一連續的半導體圖案、且閘極G4與閘極G2為一連續的導電圖案,因此第二開關元件SW2與第四開關元件SW4可一起構成一雙汲極設計的薄膜電晶體,然而本發明並不限於此。In particular, in this embodiment, the source S4 and the source S2 are a continuous conductive pattern, the semiconductor pattern layer SM4 and the semiconductor pattern layer SM2 form a continuous semiconductor pattern, and the gate G4 and the gate G2 It is a continuous conductive pattern. Therefore, the second switching element SW2 and the fourth switching element SW4 can together form a thin film transistor with a double drain design, however, the invention is not limited thereto.
另外,在本實施方式中,半導體圖案層SM1、半導體圖案層SM2、半導體圖案層SM3及半導體圖案層SM4的材質分別可包括(但不限於):非晶矽、奈米晶矽、微晶矽、多晶矽、單晶矽、奈米碳管/桿、氧化物半導體材料(例如:氧化銦鎵鋅(Indium-Gallium-Zinc Oxide,IGZO)、氧化鋅(ZnO)、氧化錫(SnO)、氧化銦鋅(Indium-Zinc Oxide,IZO)、氧化鎵鋅(Gallium-Zinc Oxide,GZO)、氧化鋅錫(Zinc-Tin Oxide,ZTO)或氧化銦錫(Indium-Tin Oxide,ITO)、或是其它合適的材質)、有機半導體材質、或其它合適的材質、或前述至少二種之組合或堆疊。In addition, in this embodiment, the materials of the semiconductor pattern layer SM1, the semiconductor pattern layer SM2, the semiconductor pattern layer SM3, and the semiconductor pattern layer SM4 may include (but not limited to): amorphous silicon, nanocrystalline silicon, microcrystalline silicon , Polysilicon, monocrystalline silicon, carbon nanotubes/rods, oxide semiconductor materials (for example: Indium-Gallium-Zinc Oxide (IGZO), zinc oxide (ZnO), tin oxide (SnO), indium oxide Zinc (Indium-Zinc Oxide, IZO), Gallium-Zinc Oxide (GZO), Zinc-Tin Oxide (ZTO) or Indium-Tin Oxide (ITO), or other suitable Materials), organic semiconductor materials, or other suitable materials, or a combination or stack of at least two of the foregoing.
在本實施方式中,第一主畫素電極MPE1與第一開關元件SW1電性連接,且位於掃描線SL的第一側112。在本實施方式中,第一主畫素電極MPE1可透過接觸窗C1而與第一開關元件SW1的汲極D1電性連接。在本實施方式中,第一主畫素電極MPE1的材質可為透明導電材料(例如:氧化銦錫、氧化銦鋅、氧化鋁錫(aluminum tin oxide,ATO)、氧化鋁鋅(aluminum zinc oxide,AZO)、氧化銦鎵鋅、小於60埃的金屬或合金、或其它合適的氧化物、或者是上述至少二者之堆疊層)、其它合適的材質、或前述至少二種材料的之組合/堆疊。In this embodiment, the first main pixel electrode MPE1 is electrically connected to the first switching element SW1 and is located on the
在本實施方式中,第二主畫素電極MPE2與第二開關元件SW2電性連接,且位於掃描線SL的第一側112。在本實施方式中,第二主畫素電極MPE2可透過接觸窗C2而與第二開關元件SW2的汲極D2電性連接。在本實施方式中,第二主畫素電極MPE2的材質可為透明導電材料(例如:氧化銦錫、氧化銦鋅、氧化鋁錫、氧化鋁鋅、氧化銦鎵鋅、小於60埃(Angstrom)的金屬或合金、或其它合適的氧化物、或者是上述至少二者之堆疊層)、其它合適的材質、或前述至少二種材料的之組合/堆疊。In this embodiment, the second main pixel electrode MPE2 is electrically connected to the second switching element SW2 and is located on the
另外,在本實施方式中,第一主畫素電極MPE1位於第二資料線DL2的第一側116,而第二主畫素電極MPE2位於第二資料線DL2的第二側118。也就是說,在本實施方式中,第一主畫素電極MPE1與第二主畫素電極MPE2分別位於第二資料線DL2的兩側。從另一觀點而言,在本實施方式中,第二資料線DL2位於第一主畫素電極MPE1與第二主畫素電極MPE2之間。In addition, in this embodiment, the first main pixel electrode MPE1 is located on the
在本實施方式中,第一次畫素電極SPE1與第三開關元件SW3電性連接,且位於掃描線SL的第二側114。也就是說,在本實施方式中,電性連接於第一資料線DL1的第一次畫素電極SPE1與第一主畫素電極MPE1分別位於掃描線SL的兩側,但本發明不限於此。在其他實施方式中,電性連接於第一資料線DL1的第一次畫素電極SPE1與第一主畫素電極MPE1也可以是位於掃描線SL的同一側(例如第一側112或第二側114)。在本實施方式中,第一次畫素電極SPE1可透過接觸窗C3而與第三開關元件SW3的汲極D3電性連接。在本實施方式中,第一次畫素電極SPE1的材質可為透明導電材料(例如:氧化銦錫、氧化銦鋅、氧化鋁錫、氧化鋁鋅、氧化銦鎵鋅、小於60埃的金屬或合金、或其它合適的氧化物、或者是上述至少二者之堆疊層)、其它合適的材質、或前述至少二種材料的之組合/堆疊。In this embodiment, the first pixel electrode SPE1 is electrically connected to the third switching element SW3 and is located on the
在本實施方式中,第二次畫素電極SPE2與第四開關元件SW4電性連接,且位於掃描線SL的第二側114。也就是說,在本實施方式中,電性連接於第二資料線DL2的第二次畫素電極SPE2與第二主畫素電極MPE2分別位於掃描線SL的兩側,但本發明不限於此。在其他實施方式中,電性連接於第二資料線DL2的第二次畫素電極SPE2與第二主畫素電極MPE2也可以是位於掃描線SL的同一側(例如第一側112或第二側114)。在本實施方式中,第二次畫素電極SPE2可透過接觸窗C4而與第四開關元件SW4的汲極D4電性連接。在本實施方式中,第二次畫素電極SPE2的材質可為透明導電材料(例如:氧化銦錫、氧化銦鋅、氧化鋁錫、氧化鋁鋅、氧化銦鎵鋅、小於60埃的金屬或合金、或其它合適的氧化物、或者是上述至少二者之堆疊層)、其它合適的材質、或前述至少二種材料的之組合/堆疊。In this embodiment, the second pixel electrode SPE2 is electrically connected to the fourth switching element SW4 and is located on the
另外,在本實施方式中,第一次畫素電極SPE1位於第二資料線DL2的第一側116,而第二次畫素電極SPE2位於第二資料線DL2的第二側118。也就是說,在本實施方式中,第一次畫素電極SPE1與第二次畫素電極SPE2分別位於第二資料線DL2的兩側。從另一觀點而言,在本實施方式中,第二資料線DL2事實上位於第一次畫素電極SPE1與第二次畫素電極SPE2之間。In addition, in this embodiment, the first pixel electrode SPE1 is located on the
在本實施方式中,在基板100的垂直投影方向N上,第一主畫素電極MPE1和第二主畫素電極MPE2不與第二資料線DL2重疊設置,而第一次畫素電極SPE1和第二次畫素電極SPE2與第二資料線DL2重疊設置,但本發明並不限於此。另外,如圖1所示,在本實施方式中,在基板100的垂直投影方向N上,第一主畫素電極MPE1也不與第一資料線DL1重疊設置,第二主畫素電極MPE2也不與和第三資料線DL3重疊設置,第一次畫素電極SPE1也與第一資料線DL1重疊設置,且第二次畫素電極SPE2也與第三資料線DL3重疊設置。In this embodiment, in the vertical projection direction N of the
在本實施方式中,如圖1及圖2所示,對應設置於第一主畫素電極MPE1與第二主畫素電極MPE2之間的第二資料線DL2是具有寬度W3的部分,而如圖1及圖3所示,在基板100的垂直投影方向N上,第一次畫素電極SPE1和第二次畫素電極SPE2會與具有寬度W4的第二資料線DL2重疊。也就是說,在本實施方式中,與對應設置於第一主畫素電極MPE1與第二主畫素電極MPE2之間的第二資料線DL2相比,對應設置在第一次畫素電極SPE1與第二次畫素電極SPE2之間的第二資料線DL2會具有較大的寬度。In this embodiment, as shown in FIGS. 1 and 2, the second data line DL2 correspondingly disposed between the first main pixel electrode MPE1 and the second main pixel electrode MPE2 is a portion having a width W3, and as As shown in FIGS. 1 and 3, in the vertical projection direction N of the
另外,在本實施方式中,如圖1所示,第一資料線DL1與第一主畫素電極MPE1對應設置的部分是具有寬度W1的部分,以及第三資料線DL3之與第二主畫素電極MPE2對應設置的部分是具有寬度W5的部分。在本實施方式中,如圖1所示,在基板100的垂直投影方向N上,第一次畫素電極SPE1會與具有寬度W2的第一資料線DL1重疊,以及第二次畫素電極SPE2會與具有寬度W6的第三資料線DL3重疊。In addition, in this embodiment, as shown in FIG. 1, the portion corresponding to the first data line DL1 and the first main pixel electrode MPE1 is a portion having a width W1, and the third data line DL3 and the second main picture The portion corresponding to the element electrode MPE2 is a portion having a width W5. In this embodiment, as shown in FIG. 1, in the vertical projection direction N of the
在本實施方式中,第一主畫素電極MPE1、第一次畫素電極SPE1、第二主畫素電極MPE2與第二次畫素電極SPE1屬於同一膜層。也就是說,在本實施方式中,第一主畫素電極MPE1、第一次畫素電極SPE1、第二主畫素電極MPE2與第二次畫素電極SPE1具有實質上相同的材質,以及第一主畫素電極MPE1、第一次畫素電極SPE1、第二主畫素電極MPE2與第二次畫素電極SPE1是在同一道光罩製程中形成。In this embodiment, the first main pixel electrode MPE1, the first primary pixel electrode SPE1, the second main pixel electrode MPE2 and the second secondary pixel electrode SPE1 belong to the same film layer. That is, in this embodiment, the first main pixel electrode MPE1, the first primary pixel electrode SPE1, the second main pixel electrode MPE2 and the second secondary pixel electrode SPE1 have substantially the same material, and the first A main pixel electrode MPE1, a first pixel electrode SPE1, a second main pixel electrode MPE2 and a second pixel electrode SPE1 are formed in the same mask process.
在本實施方式中,共用線CL設置於基板100之上,且位於掃描線SL的第一側112。在本實施方式中,共用線CL與掃描線SL屬於同一膜層。也就是說,在本實施方式中,共用線CL與掃描線SL具有實質上相同的材質,以及共用線CL與掃描線SL是在同一道光罩製程中形成。另外,在本實施方式中,共用線CL電性連接至第一共用電壓,例如約-10.5伏特至27伏特。In this embodiment, the common line CL is provided on the
在本實施方式中,共用線CL包括主幹部120、第一延伸部121以及第二延伸部122。主幹部120沿著掃描線SL的延伸方向設置。第一延伸部121以及第二延伸部122分別與主幹部120電性連接,且分別位於第二資料線DL2的兩側。詳細而言,在本實施方式中,第一延伸部121位於第二資料線DL2的第一側116,而第二延伸部122位於第二資料線DL2的第二側118。在本實施方式中,第一延伸部121以及第二延伸部122沿著第二資料線DL2的延伸方向設置。如圖1及圖2所示,在本實施方式中,對應設置於第一延伸部121與第二延伸部122之間的第二資料線DL2是具有寬度W3的部分。In this embodiment, the common line CL includes a
此外,在本實施方式中,共用線CL可更包括分別與主幹部120電性連接的第三延伸部123以及第四延伸部124。在本實施方式中,第一延伸部121與第三延伸部123位於第一主畫素電極MPE1的兩側,而第二延伸部122與第四延伸部124位於第二主畫素電極MPE2的兩側。從另一觀點而言,如圖1所示,第一延伸部121與第三延伸部123設置在第一資料線DL1與第二資料線DL2之間,而第二延伸部122與第四延伸部124設置在第二資料線DL2與第三資料線DL3之間。在本實施方式中,第一延伸部121與第三延伸部123與第一主畫素電極MPE1部分重疊;第二延伸部122與第四延伸部124與第二主畫素電極MPE2部分重疊。在本實施方式中,第三延伸部123沿著第一資料線DL1的延伸方向設置,以及第四延伸部124沿著第三資料線DL3的延伸方向設置。如圖1所示,在本實施方式中,第一資料線DL1之與第三延伸部123對應設置的部分是具有寬度W1的部分,以及第三資料線DL3之與第四延伸部124對應設置的部分是具有寬度W5的部分。In addition, in this embodiment, the common line CL may further include a
在本實施方式中,遮光層400包括分別位於第二資料線DL2兩側的第一遮光圖案410與第二遮光圖案420。詳細而言,在本實施方式中,第一遮光圖案410位於第二資料線DL2的第一側116,而第二遮光圖案420位於第二資料線DL2的第二側118。在本實施方式中,第一遮光圖案410以及第二遮光圖案420沿著第二資料線DL2的延伸方向設置。在本實施方式中,第一遮光圖案410位於第二資料線DL2與第一延伸部121之間,且第二遮光圖案420位於第二資料線DL2與第二延伸部122之間。從另一觀點而言,如圖1及圖2所示,在本實施方式中,對應設置於第一遮光圖案410與第二遮光圖案420之間的第二資料線DL2是具有寬度W3的部分。In this embodiment, the
此外,在本實施方式中,遮光層400可更包括第三遮光圖案430與第四遮光圖案440,其中第三遮光圖案430位於第一資料線DL1與第三延伸部123之間,且第四遮光圖案440位於第三資料線DL3與第四延伸部124之間。在本實施方式中,第三遮光圖案430沿著第一資料線DL1的延伸方向設置,以及第四遮光圖案440沿著第三資料線DL3的延伸方向設置。如圖1所示,在本實施方式中,第一資料線DL1與第三遮光圖案430對應設置的部分是具有寬度W1的部分,以及第三資料線DL3與第四遮光圖案440對應設置的部分是具有寬度W5的部分。In addition, in this embodiment, the
在本實施方式中,在基板100的垂直投影方向N上,第一遮光圖案410不與第一主畫素電極MPE1重疊設置,第二遮光圖案420不與第二主畫素電極MPE2重疊設置,第三遮光圖案430不與第一主畫素電極MPE1重疊設置,第四遮光圖案440不與第二主畫素電極MPE2重疊設置。從另一觀點而言,在本實施方式中,第一遮光圖案410與第三遮光圖案430位於第一主畫素電極MPE1的兩側,第二遮光圖案420與第四遮光圖案440位於第二主畫素電極MPE2的兩側。In this embodiment, in the vertical projection direction N of the
在本實施方式中,遮光層400與第一開關元件SW1的半導體圖案層SM1、第二開關元件SW2的半導體圖案層SM2、第三開關元件SW3的半導體圖案層SM3以及第四開關元件SW4的半導體圖案層SM4屬於同一膜層。也就是說,在本實施方式中,遮光層400、半導體圖案層SM1、半導體圖案層SM2、半導體圖案層SM3與半導體圖案層SM4具有實質上相同的材質,以及遮光層400、半導體圖案層SM1、半導體圖案層SM2、半導體圖案層SM3與半導體圖案層SM4是在同一道光罩製程中形成。從另一觀點而言,在本實施方式中,第一遮光圖案410、第二遮光圖案420、第三遮光圖案430及第四遮光圖案440是在形成第一延伸部121、第二延伸部122、第三延伸部123及第四延伸部124之後形成的。In this embodiment, the
在本實施方式中,第一絕緣層210全面地形成在基板100上,且覆蓋於掃描線SL與共用線CL上。如前文所述,掃描線SL的部分區域分別是作為閘極G1、閘極G2、閘極G3及閘極G4,因此在本實施方式中,第一絕緣層210是作為閘絕緣層。在本實施方式中,第一絕緣層210可為單層或多層結構,且第一絕緣層210的材質可包括無機材料、有機材料、或其它合適的材料,其中無機材料例如包括(但不限於):氧化矽、氮化矽或氮氧化矽;有機材料例如包括(但不限於):聚醯亞胺系樹脂、環氧系樹脂或壓克力系樹脂。另外,在本實施方式中,第一資料線DL1、第二資料線DL2、第三資料線DL3、與遮光層400是設置於第一絕緣層210上。In this embodiment, the first insulating
在本實施方式中,第二絕緣層220全面地形成在基板100上,且設置於第一資料線DL1、第二資料線DL2、第三資料線DL3與第一絕緣層210上。如前文所述,源極S1、源極S3與第一資料線DL1為一連續的導電圖案,源極S2、源極S4與第二資料線DL2為一連續的導電圖案,且遮光層400、半導體圖案層SM1、半導體圖案層SM2、半導體圖案層SM3與半導體圖案層SM4屬於同一膜層,因此在本實施方式中,第二絕緣層220可提供絕緣與保護第一開關元件SW1、第二開關元件SW2、第三開關元件SW3以及第四開關元件SW4的功能。在本實施方式中,第二絕緣層220可為單層或多層結構,且第二絕緣層220的材質可包括無機材料、有機材料、或其它合適的材料,其中無機材料例如包括(但不限於):氧化矽、氮化矽或氮氧化矽;有機材料例如包括(但不限於):聚醯亞胺系樹脂、環氧系樹脂或壓克力系樹脂。In this embodiment, the second insulating
在本實施方式中,第一濾光層CF1設置於第二絕緣層220上,且位於第一主畫素電極MPE1與第一次畫素電極SPE1之下。在本實施方式中,第一濾光層CF1可以是本技術領域中具有通常知識者所周知的用於顯示面板中的任一種濾光層。舉例而言,第一濾光層CF1的顏色可以是紅色、綠色、或藍色。在一實施方式中,第一濾光層CF1例如是綠色濾光層。In this embodiment, the first filter layer CF1 is disposed on the second insulating
在本實施方式中,第二濾光層CF2設置於第二絕緣層220上,且位於第二主畫素電極MPE2與第二次畫素電極SPE2之下。在本實施方式中,第二濾光層CF2可以是本技術領域中具有通常知識者所周知的用於顯示面板中的任一種濾光層。舉例而言,第二濾光層CF2的顏色可以是紅色、綠色、或藍色。另外,在本實施方式中,第二濾光層CF2與第一濾光層CF1的顏色不相同,但本發明並不限於此。在一實施方式中,第二濾光層CF2例如是紅色濾光層。In this embodiment, the second filter layer CF2 is disposed on the second insulating
另外,在本實施方式中,第一濾光層CF1之一部分與第二濾光層CF2之一部分於第二資料線DL2之上方彼此重疊而形成疊層結構300。也就是說,在本實施方式中,第一濾光層CF1與第二濾光層CF2部分重疊以形成於位於第二資料線DL2之上的疊層結構300。In addition, in the present embodiment, a part of the first filter layer CF1 and a part of the second filter layer CF2 overlap each other above the second data line DL2 to form a
在本實施方式中,保護層230全面地形成在基板100上,且設置於第一濾光層CF1與第二濾光層CF2上,以提供保護第一濾光層CF1與第二濾光層CF2的功能。在本實施方式中,保護層230可為單層或多層結構,且其材質可包括無機材料(例如:氧化矽、氮化矽、氮氧化矽、其他合適的材料)、有機材料、或其它合適的材料。In this embodiment, the
在本實施方式中,第一主畫素電極MPE1、第一次畫素電極SPE1、第二主畫素電極MPE2與第二次畫素電極SPE2位於保護層230之上。在本實施方式中,用以電性連接第一主畫素電極MPE1與汲極D1的接觸窗C1可形成在第二絕緣層220、第一濾光層CF1及保護層230中,用以電性連接第一次畫素電極SPE1與汲極D3的接觸窗C3可形成在第二絕緣層220、第一濾光層CF1及保護層230中,用以電性連接第二主畫素電極MPE2與汲極D2的接觸窗C2可形成在第二絕緣層220、第二濾光層CF2及保護層230中,用以電性連接第二次畫素電極SPE2與汲極D4的接觸窗C4可形成在第二絕緣層220、第二濾光層CF2及保護層230中,然本發明並不限於此。In this embodiment, the first main pixel electrode MPE1, the first primary pixel electrode SPE1, the second main pixel electrode MPE2, and the second secondary pixel electrode SPE2 are located on the
在本實施方式中,共用電極CE設置於第一資料線DL1、第二資料線DL2、第三資料線DL3之上,使得當畫素結構1應用於液晶顯示面板中時,可良好地避免液晶分子受到顯示訊號干擾而具有良好的液晶排列。在本實施方式中,第一主畫素電極MPE1、第一次畫素電極SPE1、第二主畫素電極MPE2、第二次畫素電極SPE1與共用電極CE屬於同一膜層。也就是說,在本實施方式中,第一主畫素電極MPE1、第一次畫素電極SPE1、第二主畫素電極MPE2、第二次畫素電極SPE1與共用電極CE具有實質上相同的材質,以及第一主畫素電極MPE1、第一次畫素電極SPE1、第二主畫素電極MPE2、與第二次畫素電極SPE1與共用電極CE是在同一道光罩製程中形成。In this embodiment, the common electrode CE is disposed on the first data line DL1, the second data line DL2, and the third data line DL3, so that when the
另外,在本實施方式中,共用電極CE透過連接結構CS而與共用線CL電性連接。也就是說,在本實施方式中,共用電極CE與共用線CL電性連接至相同的第一共用電壓。In addition, in the present embodiment, the common electrode CE is electrically connected to the common line CL through the connection structure CS. That is, in this embodiment, the common electrode CE and the common line CL are electrically connected to the same first common voltage.
在本實施方式中,第一訊號線130配置於第一資料線DL1與第二資料線DL2之間,以及第二訊號線140配置於第二資料線DL2與第三資料線DL3之間。在本實施方式中,第一訊號線130與第二訊號線140分別自掃描線SL的第二側114朝向掃描線SL的第一側112延伸。從另一觀點而言,在本實施方式中,第一訊號線130與第二訊號線140分別與掃描線SL交錯設置,且分別與共用線CL交錯設置。In this embodiment, the
在本實施方式中,第一訊號線130及第二訊號線140與第一資料線DL1、第二資料線DL2及第三資料線DL3屬於同一膜層。也就是說,在本實施方式中,第一訊號線130及第二訊號線140與第一資料線DL1、第二資料線DL2及第三資料線DL3具有實質上相同的材質,以及第一訊號線130及第二訊號線140與第一資料線DL1、第二資料線DL2及第三資料線DL3是在同一道光罩製程中形成。如此一來,在本實施方式中,第一訊號線130及第二訊號線140設置於第一絕緣層210之上且設置於第二絕緣層220之下。In this embodiment, the
在本實施方式中,第一訊號線130電性連接至第五開關元件SW5,第五開關元件SW5與第三開關元件SW3電性連接。第二訊號線140電性連接至第六開關元件SW6,第六開關元件SW6與第三開關元件SW4電性連接。第一訊號線130及第二訊號線140電性連接至第二共用電壓,其中第二共用電壓不同於共用線CL所電性連接至的第一共用電壓,且第二共用電壓例如是約0.3伏特至16.3伏特。值得一提的是,在本實施方式中,畫素結構1透過共用電極CE與共用線CL電性連接至第一共用電壓,而第一訊號線130及第二訊號線140電性連接至不同於第一共用電壓的第二共用電壓,使得當畫素結構1應用於液晶顯示面板中時,能提高施加於液晶分子的電壓差,有效提高液晶顯示面板的穿透率。In this embodiment, the
值得說明的是,如前文所述,在本實施方式中,透過遮光層400之第一遮光圖案410與第二遮光圖案420分別位於在第一主畫素電極MPE1與第二主畫素電極MPE2之間的第二資料線DL2的兩側,且第一遮光圖案410位於第二資料線DL2與共用線CL之第一延伸部121之間,第二遮光圖案420位於第二資料線DL2與共用線CL之第二延伸部122之間,使得與未設置有遮光層的畫素結構(如圖5所示)相比,畫素結構1中位於第二資料線DL2兩旁的地形平坦性較佳,這是由於未設置有遮光層的畫素結構中於第二資料線DL2兩旁會產生地形缺陷區域DF,使得第二資料線DL2兩旁的地形變化大,如圖5所示。如此一來,與未設置有遮光層的畫素結構(如圖5所示)相比,當畫素結構1應用於液晶顯示面中時,因第二資料線DL2兩旁的地形平坦性較佳,使得對應設置的液晶分子能夠具有良好排列,因而改善第二資料線DL2附近的異常漏光問題。It is worth noting that, as described above, in this embodiment, the first light-
另外,如前文所述,在本實施方式中,遮光層400與半導體圖案層SM1、半導體圖案層SM2、半導體圖案層SM3以及半導體圖案層SM4屬於同一膜層,因而可具有約10%至約40%的透光率。如此一來,透過遮光層400之第一遮光圖案410與第二遮光圖案420分別位於在第一主畫素電極MPE1與第二主畫素電極MPE2之間的第二資料線DL2的兩側,且第一遮光圖案410位於第二資料線DL2與共用線CL之第一延伸部121之間,第二遮光圖案420位於第二資料線DL2與共用線CL之第二延伸部122之間,使得當畫素結構1應用於液晶顯示面中時,遮光層400能有效遮蔽入射到第二資料線DL2與第一延伸部121之間以及第二資料線DL2與第二延伸部122之間的光線,進而改善第二資料線DL2附近的異常漏光問題。In addition, as described above, in this embodiment, the
另外,在圖1至圖4的實施方式中,畫素結構1中的遮光層400與半導體圖案層SM1、半導體圖案層SM2、半導體圖案層SM3以及半導體圖案層SM4屬於同一膜層,但本發明並不限於此。以下,將參照圖6對其他變化態樣進行詳細說明。在此必須說明的是,下述實施方式沿用了前述實施方式的元件符號與部分內容,其中採用相同或相似的符號來表示相同或相似的元件,並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施方式,下述實施方式不再重複贅述。In addition, in the embodiments of FIGS. 1 to 4, the
圖6是本發明的另一實施方式的畫素結構的剖面示意圖。值得注意的是,圖6的剖面位置可對應至圖2的剖線I-I’的位置,且圖6之畫素結構2的上視示意圖請對應參考圖1。6 is a schematic cross-sectional view of a pixel structure according to another embodiment of the present invention. It is worth noting that the cross-sectional position of FIG. 6 may correspond to the position of the cross-sectional line I-I' of FIG. 2, and the top view of the pixel structure 2 of FIG. 6 corresponds to FIG. 1.
請同時參照圖6與圖4,圖6的畫素結構2與圖4的畫素結構1相似,因此相同或相似的元件以相同或相似的符號表示,並且省略了相同技術內容的說明。關於省略部分的說明可參考前述圖1至圖4的實施方式。以下,將就圖6的畫素結構2與圖4的畫素結構1間的差異處做說明。Please refer to FIG. 6 and FIG. 4 at the same time. The pixel structure 2 of FIG. 6 is similar to the
請參照圖6,在本實施方式中,遮光層400之第一遮光圖案410以及第二遮光圖案420設置於第二絕緣層220上。也就是說,在本實施方式中,遮光層400是在形成第一延伸部121及第二延伸部122之後且在形成第二資料線DL2之後形成的。從另一觀點而言,在本實施方式中,遮光層400不與半導體圖案層SM1以及半導體圖案層SM2屬於同一膜層,不與第一延伸部121及第二延伸部122屬於同一膜層,也不與第二資料線DL2屬於同一膜層。具體而言,在一實施方式中,遮光層400可以另一金屬層製作,且遮光層400的材質可包括(但不限於):鋁、鉬或鈦。Referring to FIG. 6, in this embodiment, the first light-
值得說明的是,如前文所述,在本實施方式中,透過遮光層400之第一遮光圖案410與第二遮光圖案420分別位於在第一主畫素電極MPE1與第二主畫素電極MPE2之間的第二資料線DL2的兩側,且第一遮光圖案410位於第二資料線DL2與共用線CL之第一延伸部121之間,第二遮光圖案420位於第二資料線DL2與共用線CL之第二延伸部122之間,使得與未設置有遮光層的畫素結構(如圖5所示)相比,當畫素結構2應用於液晶顯示面中時,因第二資料線DL2兩旁的地形平坦性較佳,使得對應設置的液晶分子能夠具有良好排列,因而改善第二資料線DL2附近的異常漏光問題。It is worth noting that, as described above, in this embodiment, the first light-
另外,如前文所述,在本實施方式中,遮光層400的材質可包括金屬,故透過遮光層400之第一遮光圖案410與第二遮光圖案420分別位於在第一主畫素電極MPE1與第二主畫素電極MPE2之間的第二資料線DL2的兩側,且第一遮光圖案410位於第二資料線DL2與共用線CL之第一延伸部121之間,第二遮光圖案420位於第二資料線DL2與共用線CL之第二延伸部122之間,使得當畫素結構2應用於液晶顯示面中時,遮光層400能有效遮蔽入射到第二資料線DL2與第一延伸部121之間以及第二資料線DL2與第二延伸部122之間的光線,進而改善第二資料線DL2附近的異常漏光問題。In addition, as described above, in this embodiment, the material of the light-
綜上所述,本發明實施方式的畫素結構包括遮光層、位於掃描線之第一側的第一主畫素電極及第二主畫素電極、以及位於掃描線的第一側的共用線,其中第一主畫素電極及第二主畫素電極之間設置有第二資料線,共用線包括沿著掃描線的延伸方向設置的主幹部以及與主幹部電性連接且分別位於第二資料線兩側的第一延伸部與第二延伸部,遮光層包括分別位於第二資料線兩側的第一遮光圖案與第二遮光圖案,第一遮光圖案位於第二資料線與第一延伸部之間,且第二遮光圖案位於第二資料線與第二延伸部之間。透過上述畫素結構,使得位於第二資料線兩旁的地形平坦性良好,因而將畫素結構應用於液晶顯示面板時,對應第二資料線附近設置的液晶分子能夠具有良好排列,藉以改善第二資料線附近的異常漏光問題。In summary, the pixel structure of the embodiment of the present invention includes the light shielding layer, the first main pixel electrode and the second main pixel electrode on the first side of the scan line, and the common line on the first side of the scan line , Where a second data line is provided between the first main pixel electrode and the second main pixel electrode, and the common line includes a trunk portion provided along the extending direction of the scanning line and is electrically connected to the trunk portion and respectively located at the second The first extension portion and the second extension portion on both sides of the data line, the light-shielding layer includes a first light-shielding pattern and a second light-shielding pattern on both sides of the second data line And the second light-shielding pattern is located between the second data line and the second extending portion. Through the above pixel structure, the terrain flatness on both sides of the second data line is good. Therefore, when the pixel structure is applied to a liquid crystal display panel, the liquid crystal molecules arranged near the second data line can have a good arrangement, thereby improving the second Abnormal light leakage near the data line.
雖然本發明已以實施方式揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed as above in the embodiments, it is not intended to limit the present invention. Anyone who has ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.
1‧‧‧畫素結構100‧‧‧基板112、116‧‧‧第一側114、118‧‧‧第二側120‧‧‧主幹部121‧‧‧第一延伸部122‧‧‧第二延伸部123‧‧‧第三延伸部124‧‧‧第四延伸部130‧‧‧第一訊號線140‧‧‧第二訊號線210‧‧‧第一絕緣層220‧‧‧第二絕緣層230‧‧‧保護層300‧‧‧疊層結構400‧‧‧遮光層410‧‧‧第一遮光圖案420‧‧‧第二遮光圖案430‧‧‧第三遮光圖案440‧‧‧第四遮光圖案A、B‧‧‧區域C1、C2、C3、C4‧‧‧接觸窗CE‧‧‧共用電極CF1‧‧‧第一濾光層CF2‧‧‧第二濾光層CL‧‧‧共用線CS‧‧‧連接結構D1、D2、D3、D4‧‧‧汲極DF‧‧‧地形缺陷區域DL1‧‧‧第一資料線DL2‧‧‧第二資料線DL3‧‧‧第三資料線G1、G2、G3、G4‧‧‧閘極MPE1‧‧‧第一主畫素電極MPE2‧‧‧第二主畫素電極N‧‧‧垂直投影方向S1、S2、S3、S4‧‧‧源極SL‧‧‧掃描線SM1、SM2、SM3、SM4‧‧‧半導體圖案層SPE1‧‧‧第一次畫素電極SPE2‧‧‧第二次畫素電極SW1‧‧‧第一開關元件SW2‧‧‧第二開關元件SW3‧‧‧第三開關元件SW4‧‧‧第四開關元件SW5‧‧‧第五開關元件SW6‧‧‧第六開關元件W1、W2、W3、W4、W5、W6‧‧‧寬度1‧‧‧Pixel structure 100‧‧‧Substrate 112, 116‧‧‧ First side 114, 118‧‧‧Second side 120‧‧‧ Main part 121‧‧‧First extension part 122‧‧‧Second Extension part 123‧‧‧ Third extension part 124‧‧‧ Fourth extension part 130‧‧‧ First signal line 140‧‧‧ Second signal line 210‧‧‧ First insulation layer 220‧‧‧ Second insulation layer 230‧‧‧Protection layer 300‧‧‧Layer structure 400‧‧‧Shading layer 410‧‧‧First shading pattern 420‧‧‧Second shading pattern 430‧‧‧ Third shading pattern 440‧‧‧ Fourth shading Patterns A, B‧‧‧ Areas C1, C2, C3, C4 ‧‧‧ Contact window CE‧‧‧ Common electrode CF1‧‧‧ First filter layer CF2‧‧‧ Second filter layer CL‧‧‧ Common line CS‧‧‧ Connection structure D1, D2, D3, D4 ‧‧‧ Drain DF‧‧‧ Topography defect area DL1‧‧‧ First data line DL2‧‧‧Second data line DL3‧‧‧ Third data line G1 , G2, G3, G4 ‧‧‧‧ gate MPE1‧‧‧ first main pixel electrode MPE2‧‧‧ second main pixel electrode N‧‧‧vertical projection direction S1, S2, S3, S4‧‧‧ source SL‧‧‧ Scanning lines SM1, SM2, SM3, SM4 ‧‧‧ Semiconductor pattern layer SPE1‧‧‧ First pixel electrode SPE2‧‧‧Second pixel electrode SW1‧‧‧First switching element SW2‧‧ ‧Second switching element SW3‧‧‧ Third switching element SW4‧‧‧ Fourth switching element SW5‧‧‧Fifth switching element SW6‧‧‧Sixth switching element W1, W2, W3, W4, W5, W6‧‧ ‧width
圖1是本發明的一實施方式的畫素結構的上視示意圖。 圖2是圖1中的區域A的放大圖。 圖3是圖1中的區域B的放大圖。 圖4是沿圖2中的剖線I-I’的剖面示意圖。 圖5是一種未設置遮光層的畫素結構的剖面示意圖。 圖6是本發明的另一實施方式的畫素結構的剖面示意圖。FIG. 1 is a schematic top view of a pixel structure according to an embodiment of the present invention. FIG. 2 is an enlarged view of the area A in FIG. 1. FIG. 3 is an enlarged view of the area B in FIG. 1. Fig. 4 is a schematic cross-sectional view taken along line I-I' in Fig. 2. 5 is a schematic cross-sectional view of a pixel structure without a light-shielding layer. 6 is a schematic cross-sectional view of a pixel structure according to another embodiment of the present invention.
1‧‧‧畫素結構 1‧‧‧ pixel structure
100‧‧‧基板 100‧‧‧ substrate
112、116‧‧‧第一側 112, 116‧‧‧ First side
114、118‧‧‧第二側 114、118‧‧‧Second side
120‧‧‧主幹部 120‧‧‧ Main Staff
121‧‧‧第一延伸部 121‧‧‧First Extension
122‧‧‧第二延伸部 122‧‧‧Second Extension
123‧‧‧第三延伸部 123‧‧‧The third extension
124‧‧‧第四延伸部 124‧‧‧The fourth extension
130‧‧‧第一訊號線 130‧‧‧ First signal line
140‧‧‧第二訊號線 140‧‧‧Second signal line
400‧‧‧遮光層 400‧‧‧shading layer
410‧‧‧第一遮光圖案 410‧‧‧The first shading pattern
420‧‧‧第二遮光圖案 420‧‧‧Second shading pattern
430‧‧‧第三遮光圖案 430‧‧‧The third shading pattern
440‧‧‧第四遮光圖案 440‧‧‧The fourth shading pattern
A、B‧‧‧區域 A, B‧‧‧ area
C1、C2、C3、C4‧‧‧接觸窗 C1, C2, C3, C4 ‧‧‧ contact window
CE‧‧‧共用電極 CE‧‧‧Common electrode
CL‧‧‧共用線 CL‧‧‧Common line
CS‧‧‧連接結構 CS‧‧‧ connection structure
D1、D2、D3、D4‧‧‧汲極 D1, D2, D3, D4 ‧‧‧ Drain
DL1‧‧‧第一資料線 DL1‧‧‧First data line
DL2‧‧‧第二資料線 DL2‧‧‧Second data cable
DL3‧‧‧第三資料線 DL3‧‧‧third data line
G1、G2、G3、G4‧‧‧閘極 G1, G2, G3, G4 ‧‧‧ gate
MPE1‧‧‧第一主畫素電極 MPE1‧‧‧The first main pixel electrode
MPE2‧‧‧第二主畫素電極 MPE2‧‧‧Second main pixel electrode
N‧‧‧垂直投影方向 N‧‧‧Vertical projection direction
S1、S2、S3、S4‧‧‧源極 S1, S2, S3, S4 ‧‧‧ source
SL‧‧‧掃描線 SL‧‧‧scan line
SM1、SM2、SM3、SM4‧‧‧半導體圖案層 SM1, SM2, SM3, SM4 ‧‧‧ semiconductor pattern layer
SPE1‧‧‧第一次畫素電極 SPE1‧‧‧The first pixel electrode
SPE2‧‧‧第二次畫素電極 SPE2‧‧‧Second pixel electrode
SW1‧‧‧第一開關元件 SW1‧‧‧ First switching element
SW2‧‧‧第二開關元件 SW2‧‧‧Second switching element
SW3‧‧‧第三開關元件 SW3‧‧‧The third switching element
SW4‧‧‧第四開關元件 SW4‧‧‧The fourth switching element
SW5‧‧‧第五開關元件 SW5‧‧‧ fifth switching element
SW6‧‧‧第六開關元件 SW6‧‧‧Sixth switching element
W1、W2、W3、W4、W5、W6‧‧‧寬度 W1, W2, W3, W4, W5, W6‧‧‧Width
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CN110703526A (en) * | 2019-10-30 | 2020-01-17 | 深圳市华星光电半导体显示技术有限公司 | Liquid crystal display panel and liquid crystal display device |
CN114387937B (en) * | 2022-02-17 | 2023-05-02 | 深圳市华星光电半导体显示技术有限公司 | Pixel structure and display panel |
CN114387936B (en) * | 2022-02-17 | 2023-05-02 | 深圳市华星光电半导体显示技术有限公司 | Pixel structure and display panel |
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JP2004354553A (en) * | 2003-05-28 | 2004-12-16 | Hitachi Displays Ltd | Liquid crystal display device |
US7884364B2 (en) * | 2006-12-12 | 2011-02-08 | Lg Display Co., Ltd. | Array substrate, method of manufacturing the same, and method of repairing line in the same |
TWI350004B (en) * | 2008-01-17 | 2011-10-01 | Au Optronics Corp | Pixel structure of liquid crystal display panel and method of making the same |
CN101221961B (en) * | 2008-01-22 | 2010-06-23 | 友达光电股份有限公司 | Pixel structure and its production method |
CN101526706B (en) * | 2008-03-07 | 2011-09-28 | 瀚宇彩晶股份有限公司 | Pixel structure of liquid crystal display |
CN101598877B (en) * | 2009-07-07 | 2011-05-04 | 友达光电股份有限公司 | Active element matrix substrate |
CN101718932B (en) * | 2009-12-10 | 2011-10-05 | 友达光电股份有限公司 | Displaying panel |
KR101237791B1 (en) * | 2010-04-29 | 2013-02-28 | 엘지디스플레이 주식회사 | Array substrate for In-Plane switching mode LCD |
KR102095027B1 (en) * | 2013-07-12 | 2020-04-16 | 삼성디스플레이 주식회사 | Liquid crystal display |
TWI626498B (en) * | 2014-11-10 | 2018-06-11 | 友達光電股份有限公司 | Display panel |
TWI551921B (en) * | 2015-12-17 | 2016-10-01 | 友達光電股份有限公司 | Display panel |
TWI609219B (en) * | 2017-02-10 | 2017-12-21 | 友達光電股份有限公司 | Pixel unit, pixel-array structure, and display panel |
CN107490912A (en) * | 2017-09-06 | 2017-12-19 | 深圳市华星光电技术有限公司 | A kind of array base palte, display panel and display device |
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