TWI660484B - Fan-out semiconductor package - Google Patents

Abstract

A fan-out type semiconductor package includes: a first connection member having a through hole; a first semiconductor wafer and a second semiconductor wafer disposed in the through hole; an encapsulation body that encloses at least a portion of the first connection member, the first At least a portion of the semiconductor wafer and at least a portion of the second semiconductor wafer; and a second connection member disposed on the first connection member and disposed on the active surface of the first semiconductor wafer and the active surface of the second semiconductor. The redistribution layer of the second connection member is connected to the plurality of first connection pads and the plurality of second connection pads through a plurality of first conductors and a plurality of second conductors, respectively. The height of the second conductor is greater than the height of the first conductor.

Description

Fan-out semiconductor package

The present disclosure relates to a semiconductor package, and more specifically, to a fan-out type semiconductor package in which a connection terminal can extend outside a region where a semiconductor wafer is disposed. [Cross Reference of Related Applications] This application claims the priority of Korean Patent Application No. 10-2016-0153544, filed at the Korean Intellectual Property Office on November 17, 2016, and on December 5, 2016. Priority of Korean Patent Application No. 10-2016-0164516 filed by the Korean Intellectual Property Office, the disclosure content of each of the Korean patent applications mentioned herein is incorporated in this case for reference.

Recently, an important trend in the development of related technologies of semiconductor wafers is to reduce the size of semiconductor wafers. Therefore, in the field of packaging technology, with the rapid increase in demand for small-sized semiconductor wafers and the like, it is urgent to implement a small-sized semiconductor package including a plurality of pins.

Fan-out semiconductor packaging is a packaging technology proposed to meet the above technical requirements. Such a semiconductor fan-out package has a small size and can realize multiple pins by redistributing the connection terminals outside the area where the semiconductor wafer is arranged.

One aspect of the present disclosure can provide a fan-out semiconductor package. Although a plurality of semiconductor wafers are used, the package can still be thinned, with improved efficiency and excellent reliability.

According to an aspect of the present disclosure, a fan-out semiconductor package in which a plurality of semiconductor wafers are stacked and packaged can be provided, and the plurality of semiconductor wafers are connected to each other by a plurality of multi-stage conductors having different heights. Redeploy the layers instead of via wire bonding.

According to an aspect of the present disclosure, a fan-out semiconductor package includes: a first connection member, a first semiconductor wafer, a second semiconductor wafer, an encapsulation body, and a second connection member; the first connection member has a through hole; the first semiconductor The wafer is disposed in the through hole and has an active surface on which a plurality of first connection pads are disposed and a non-active surface opposite to the active surface; the second semiconductor wafer is disposed on the first semiconductor wafer in the through hole and has thereon An active surface and a non-active surface opposite to the active surface configured with a plurality of second connection pads; the encapsulation body encloses at least part of the first connection member, at least part of the first semiconductor wafer, and at least part of the second semiconductor wafer; and The second connection member is disposed on the first connection member and on the active surface of the first semiconductor wafer and the active surface of the second semiconductor wafer. The first connection member and the second connection member respectively include a plurality of redistribution layers electrically connected to the plurality of first connection pads and the plurality of second connection pads; the second semiconductor wafer is disposed on the first semiconductor wafer to communicate with the first semiconductor. The chip does not match, thereby exposing a plurality of second connection pads; the rewiring layers of the second connection member are connected to the plurality of first connection pads and the plurality of second connections through the plurality of first conductors and the plurality of second conductors, respectively. Pad, and the height of the second conductor is greater than the height of the first conductor.

Hereinafter, exemplary embodiments in the present disclosure will be explained with reference to the drawings. In the drawings, the shape, size, etc. of each component may be exaggerated or reduced for clarity.

The term "exemplary embodiment" used herein does not refer to the same exemplary embodiment, but is provided to emphasize a particular feature or characteristic that is different from a particular feature or characteristic of another exemplary embodiment. However, the exemplary embodiments provided herein are considered to be able to be implemented by being combined with each other in whole or in part. For example, even if an element set forth in a particular exemplary embodiment is not set forth in another exemplary embodiment, the element is not described unless a contrary or contradictory description is provided in another exemplary embodiment. It can also be understood as a description related to another exemplary embodiment.

The meaning of "connection" between a component and another component in the description includes an indirect connection via a third component and a direct connection between two components. In addition, "electrical connection" means the concept of physical connection and physical disconnection. It should be understood that when an element is referred to by "first" and "second", the element is not limited thereby. The use of "first" and "second" may only be used for the purpose of distinguishing the elements from other elements, and may not limit the order or importance of the elements. In some cases, a first element may be referred to as a second element without departing from the scope of the patentable scope set forth herein. Likewise, the second element may be referred to as a first element.

Herein, the upper part, the lower part, the upper side, the lower side, the upper surface, the lower surface, and the like are identified in the drawings. For example, the first connection member is disposed at a level higher than the redistribution layer. However, the scope of this application patent is not limited to this. In addition, the vertical direction means the above-mentioned upward and downward directions, and the horizontal direction means the directions perpendicular to the above-mentioned upward and downward directions. In this case, the vertical cross-section means a case of being taken along a plane in a vertical direction, and an embodiment of the vertical cross-section may be a cross-sectional view shown in a drawing. In addition, the horizontal cross section means a case of being taken along a plane in a horizontal direction, and an embodiment of this horizontal cross section may be a plan view shown in the drawings.

The terminology used herein is for the purpose of illustrating exemplary embodiments only and is not a limitation on the present disclosure. In this case, the singular includes the plural unless otherwise explained in context. Electronic device

FIG. 1 is a block diagram illustrating an embodiment of an electronic device system.

Referring to FIG. 1, a motherboard 1010 can be housed in the electronic device 1000. The motherboard 1010 may include a chip-related component 1020, a network-related component 1030, other components 1040, and the like, which are physically or electrically connected to the motherboard 1010. These components can be connected to other components described below to form various signal lines 1090.

The chip-related component 1020 may include a memory chip, such as volatile memory (such as dynamic random access memory (DRAM)), non-volatile memory (such as read only memory (ROM) )), Flash memory, etc .; application processor chips, such as central processing units (for example: central processing unit (CPU)), graphics processors (for example: graphic processing unit (GPU)) , Digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc .; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits ( application-specific integrated circuit (ASIC), etc. However, the wafer-related component 1020 is not limited to this, and may include other types of wafer-related components. In addition, the wafer-related components 1020 may be combined with each other.

The network related component 1030 may include, for example, the following protocols: wireless fidelity (Wi-Fi) (Institute of Electrical And Electronics Engineers (IEEE) 802.11 family, etc.), worldwide interoperable microwave access (worldwide interoperability for microwave access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, long term evolution (LTE), evolution data only (Ev-DO), high-speed packet access + (high speed packet access + (HSPA +), high speed downlink packet access + (HSDPA +), high speed uplink packet access + (HSUPA +), enhanced data GSM environment (enhanced data GSM environment (EDGE), global system for mobile communications (GSM), global positioning system (GPS), general packet radio service (GPRS), code division multiple access (code division multiple access (CDMA), Time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, 3G, 4G, 5G, and any other wireless protocol specified after the above And cable agreements. However, the network related component 1030 is not limited to this, but may include various other wireless standards or protocols or wired standards or protocols. In addition, the network related components 1030 may be combined with each other together with the chip related components 1020 described above.

Other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, and low temperature co-fired ceramics; LTCC), electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, the other components 1040 are not limited to this, but may include passive components and the like for various other purposes. In addition, other components 1040 may be combined with each other together with the chip-related component 1020 or the network-related component 1030 described above.

Depending on the type of the electronic device 1000, the electronic device 1000 may include other components that may be physically connected or electrically connected to the motherboard 1010, or other components that may not be physically connected or electrically connected to the motherboard 1010. The other components may include, for example, a camera module 1050, an antenna 1060, a display device 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown), Compass (not shown), accelerometer (not shown), gyroscope (not shown), speaker (not shown), mass storage unit (such as hard drive) (not shown), compact disc (compact disk (CD) drive (not shown), digital versatile disk (DVD) drive (not shown), etc. However, these other components are not limited to this, but may include other components for various purposes depending on the type of the electronic device 1000 and the like.

The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet PC, and a notebook. Personal computer, netbook PC, TV, video game machine, smart watch or car component, etc. However, the electronic device 1000 is not limited to this, and may be any other electronic device that processes data.

FIG. 2 is a schematic perspective view illustrating an embodiment of an electronic device.

Referring to FIG. 2, the semiconductor package may be used for various purposes in the electronic device described above. For example, the motherboard 1110 can be accommodated in the body 1101 of the smart phone 1100, and various electronic components 1120 can be physically connected to or electrically connected to the motherboard 1110. In addition, other components that can be physically connected or electrically connected to the motherboard 1110, or other components that cannot be physically connected or electrically connected to the motherboard 1110 (eg, the camera module 1130) can be housed in the body 1101. Some electronic components in the electronic component 1120 may be chip related components, and the semiconductor package 100 may be, for example, an application processor among chip related components, but is not limited thereto. The electronic device need not be limited to the smart phone 1100, but may be other electronic devices as described above. Semiconductor package

Generally speaking, many precision circuits are integrated in a semiconductor wafer. However, the semiconductor wafer itself cannot serve as a completed semiconductor product, and may be damaged due to external physical or chemical influences. Therefore, the semiconductor wafer itself cannot be used alone, but can be packaged in an electronic device or the like and used in a packaged state in the electronic device or the like.

Here, since there is a difference in circuit width in terms of electrical connection between the semiconductor wafer and the motherboard of the electronic device, a semiconductor package is required. In detail, the size of the connection pads of the semiconductor wafer and the interval between the connection pads of the semiconductor wafer are extremely precise, but the size of the component mounting pads of the motherboard used in electronic devices and the interval between the component mounting pads of the motherboard are significantly Larger than the size and spacing of the connection pads of the semiconductor wafer. Therefore, it may be difficult to directly mount a semiconductor wafer on a motherboard, and a packaging technology for buffering a difference in circuit width between the semiconductor wafer and the motherboard may be required.

Depending on the structure and purpose of the semiconductor package, the semiconductor package manufactured by the packaging technology can be classified into a fan-in semiconductor package or a fan-out semiconductor package.

The fan-in type semiconductor package and the fan-out type semiconductor package will be explained in more detail below with reference to the drawings. Fan-in semiconductor package

3A and 3B are schematic cross-sectional views illustrating states of a fan-in semiconductor package before and after packaging.

FIG. 4 is a schematic cross-sectional view illustrating a packaging process of a fan-in semiconductor package.

Referring to the drawings, the semiconductor wafer 2220 may be, for example, an integrated circuit (IC) in an exposed state. The semiconductor wafer 2220 includes a body 2221 including silicon (Si), germanium (Ge), and gallium arsenide (GaAs). Connection pad 2222 is formed on one surface of the body 2221 and includes a conductive material such as aluminum (Al); and a protective layer 2223 is, for example, an oxide film or a nitride film, and is formed on one surface of the body 2221 And cover at least a part of the connection pad 2222. In this case, since the connection pad 2222 is small, it is difficult to mount the integrated circuit (IC) on an intermediate printed circuit board (PCB) or a motherboard of an electronic device.

Therefore, depending on the size of the semiconductor wafer 2220, the connection members 2240 are formed on the semiconductor wafer 2220 to redistribute the connection pads 2222. The connecting member 2240 can be formed by the following steps: forming an insulating layer 2241 on the semiconductor wafer 2220 using an insulating material such as a photoimagable dielectric (PID) resin; forming a through hole 2243h of the exposed connection pad 2222; and then A wiring pattern 2242 and a through hole 2243 are formed. Next, a passivation layer 2250 for protecting the connection member 2240 may be formed, an opening 2251 may be formed, and a metal layer 2260 under the bump may be formed. That is, the fan-in type semiconductor package 2200 including, for example, the semiconductor wafer 2220, the connection member 2240, the passivation layer 2250, and the under bump metal layer 2260 may be manufactured through a series of processes.

As described above, the fan-in semiconductor package may have a packaging form in which all connection pads such as input / output (I / O) terminals of the semiconductor wafer are arranged in the semiconductor wafer, and Can have excellent electrical characteristics and can be produced at low cost. As a result, many components mounted in smart phones have been manufactured in fan-in semiconductor packages. In detail, many components installed in a smart phone have been developed to implement fast signal transmission while having a small size.

However, since all the input / output terminals need to be arranged inside the semiconductor wafer in the fan-in semiconductor package, the space requirement of the fan-in semiconductor package is great. Therefore, it is difficult to apply this structure to a semiconductor wafer having a large number of input / output terminals or a semiconductor wafer having a smaller size. In addition, due to the above disadvantages, a fan-in semiconductor package cannot be directly mounted and used on a motherboard of an electronic device. This is because even if the size of the input / output terminals of the semiconductor wafer and the interval between the input / output terminals of the semiconductor wafer are increased by the rewiring process, in this case, the size and The interval between the input / output terminals of the semiconductor wafer may still not be sufficient for the fan-in semiconductor package to be directly mounted on the motherboard of the electronic device.

5 is a schematic cross-sectional view illustrating a case where a fan-in semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic device.

FIG. 6 is a schematic cross-sectional view illustrating a case where a fan-in semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic device.

Referring to the drawing, in the fan-in semiconductor package 2200, the connection pads 2222 (ie, input / output terminals) of the semiconductor wafer 2220 can be redistributed again via the interposer 2301, and the fan-in semiconductor package 2200 can be mounted on The interposer substrate 2301 is finally mounted on the motherboard 2500 of the electronic device. In this case, the solder balls 2270 and the like can be fixed by underfilling the resin 2280 and the like, and the outside of the semiconductor wafer 2220 can be covered with a molding material 2290 and the like. The fan-in semiconductor package 2200 may be embedded in a separate interposer substrate 2302, and the connection pads 2222 (ie, input / output terminals) of the semiconductor wafer 2220 may be in a state where the fan-in semiconductor package 2200 is embedded in the interposer substrate 2302 by an intermediary The substrates 2302 are redistributed again, and the fan-in semiconductor package 2200 can be finally mounted on the motherboard 2500 of the electronic device.

As described above, it may be difficult to directly mount and use a fan-in semiconductor package on a motherboard of an electronic device. Therefore, the fan-in semiconductor package can be mounted on a separate interposer substrate and then mounted on the motherboard of the electronic device through a packaging process; or the fan-in semiconductor package can be in a state where the fan-in semiconductor package is embedded in the interposer substrate. Install and use on the motherboard of the electronic device. Fan-out semiconductor package

FIG. 7 is a schematic cross-sectional view illustrating a fan-out type semiconductor package.

Referring to the drawings, in the fan-out semiconductor package 2100, for example, the outside of the semiconductor wafer 2120 is protected by the encapsulation body 2130, and a plurality of connection pads 2122 of the semiconductor wafer 2120 may be connected to the semiconductor by the connection member 2140. Redistribution is performed outside the wafer 2120. In this case, a passivation layer 2150 may be further formed on the connection member 2140, and an under bump metal layer 2160 may be further formed in the opening of the passivation layer 2150. A solder ball 2170 may be further formed on the under bump metal layer 2160. The semiconductor wafer 2120 may be an integrated circuit including a body 2121, a plurality of connection pads 2122, a passivation layer (not shown), and the like. The connection member 2140 may include an insulating layer 2141, a redistribution layer 2142 formed on the insulating layer 2141, and a through hole 2143 for electrically connecting the connection pad 2122 and the redistribution layer 2142 to each other.

As described above, the fan-out type semiconductor package may have a form in which input / output terminals of a semiconductor wafer are redistributed via a connection member formed on the semiconductor wafer and are disposed in a direction outside the semiconductor wafer. As described above, in a fan-in type semiconductor package, all input / output terminals of a semiconductor wafer need to be arranged in the semiconductor wafer. Therefore, when the size of the semiconductor wafer is reduced, the size and pitch of the balls must be reduced, thereby making standardized ball layouts unusable in fan-in semiconductor packages. On the other hand, the fan-out type semiconductor package has a form in which input / output terminals of a semiconductor wafer are redistributed by a connection member formed on the semiconductor wafer and disposed outside the semiconductor wafer, as described above. Therefore, even when the size of the semiconductor wafer is reduced, the standardized ball layout can still be used in a fan-out semiconductor package, so that the fan-out semiconductor package can be installed on the motherboard of an electronic device without using a separate interposer substrate. As described below.

FIG. 8 is a schematic cross-sectional view illustrating a case where a fan-out semiconductor package is mounted on a motherboard of an electronic device.

Referring to the drawings, the fan-out type semiconductor package 2100 can be mounted on the motherboard 2500 of the electronic device via a solder ball 2170 or the like. That is, as described above, the fan-out semiconductor package 2100 includes the connection member 2140 formed on the semiconductor wafer 2120 and capable of redistributing the connection pad 2122 to a fan-out area having an area larger than that of the semiconductor wafer 2120. Furthermore, the standardized ball layout can be used in the fan-out semiconductor package 2100 without modification. Therefore, the fan-out semiconductor package 2100 can be mounted on the motherboard 2500 of the electronic device without using a separate interposer or the like.

As described above, since a fan-out semiconductor package can be mounted on a main board of an electronic device without using a separate interposer, the thickness of the fan-out semiconductor package can be smaller than that of a fan-in semiconductor package using an interposer. Next implementation. Therefore, the fan-out type semiconductor package can be miniaturized and thinned. In addition, the fan-out semiconductor package has excellent thermal and electrical characteristics, which makes the fan-out semiconductor package particularly suitable for mobile products. Therefore, the fan-out semiconductor package can be implemented in a smaller form than a general stacked package (POP) type using a printed circuit board (PCB), and can solve problems caused by the occurrence of a warpage phenomenon.

Meanwhile, a fan-out type semiconductor package means a packaging technology for mounting a semiconductor wafer on a motherboard of an electronic device or the like as described above and protecting the semiconductor wafer from external influences, and it is similar to a printed circuit board such as an intermediate substrate ( (PCB) is conceptually different. PCBs have different specifications and purposes than fan-out semiconductor packages, and have fan-in semiconductor packages embedded in them.

A fan-out type semiconductor package will be described below with reference to the drawings. Although a plurality of semiconductor wafers are used, the package can still be thinned, with improved efficiency and excellent reliability.

FIG. 9 is a schematic cross-sectional view illustrating an embodiment of a fan-out semiconductor package.

FIG. 10 is a schematic plan view of the fan-out semiconductor package of FIG. 9.

Referring to the drawings, a fan-out type semiconductor package 100A according to an exemplary embodiment in the present disclosure may include a first connection member 110, a first semiconductor wafer 121, a second semiconductor wafer 122, an encapsulation body 130, and a second connection member 140. The first connection member 110 has a through hole 110H; the first semiconductor wafer 121 is disposed in the through hole 110H and has an active surface on which the first connection pad 121P is disposed and a non-active surface opposite to the active surface; a second semiconductor wafer 122 The first semiconductor wafer 121 disposed in the through hole 110H has an active surface on which the second connection pad 122P is disposed and a non-active surface opposite to the active surface; the encapsulation body 130 encapsulates at least the first connection member 110 Part, at least part of the first semiconductor wafer 121 and at least part of the second semiconductor wafer 122; and the second connection member 140 is disposed on the first connection member 110, the active surface of the first semiconductor wafer 121, and the second semiconductor wafer 122 Active face. The first connection member 110 may include a redistribution layer 112a, a redistribution layer 112b, and a redistribution layer 112c electrically connected to the plurality of first connection pads 121P and the plurality of second connection pads 122P. The second connection member 140 may include a redistribution layer 142 electrically connected to the plurality of first connection pads 121P and the plurality of second connection pads 122P. The active surface of the second semiconductor wafer 122 may be attached to the inactive surface of the first semiconductor wafer 121, and the second semiconductor wafer 122 may be disposed on the first semiconductor wafer 121 to be mismatched with the first semiconductor wafer 121, Further, the second connection pad 122P is exposed. The term “arranged to be mismatched” here means that the side surface of the first semiconductor wafer 121 and the side surface of the second semiconductor wafer 122 do not coincide with each other. The redistribution layer 142 of the second connection member 140 may be connected to the plurality of first connection pads 121P and the plurality of second connection pads 122P through the plurality of first conductors 121v and the plurality of second conductors 122v, respectively. The height of the second conductor 122v may be greater than the height of the first conductor 121v.

Meanwhile, a technology of stacking a plurality of memory chips into multiple stages has recently been developed in order to increase the memory capacity. For example, as shown on the left side of FIGS. 29 and 30, there may be a technology that can stack multiple memory chips into two (or three) levels, and then mount multiple stacked memory chips on the interposer substrate. Then, a plurality of stacked memory chips mounted on the interposer substrate are molded using a molding material to form a package. In this case, the plurality of stacked memory chips are electrically connected to the interposer substrate via bonding wires. However, in this structure, since the thickness of the interposer substrate is significant, the thinness of the structure is limited. In addition, when the interposer substrate is manufactured based on silicon, a large amount of cost is required. Moreover, when the reinforcing material supporting a plurality of stacked memory chips is not included separately, a reliability problem may occur due to a warpage phenomenon. Finally, because multiple stacked memory chips are electrically connected to the interposer substrate via wire bonding, the inputs and outputs are redistributed, and the signal path is significantly longer, which may cause frequent signal loss.

On the other hand, in the fan-out type semiconductor package 100A according to an exemplary embodiment, a first connection member 110 having a redistribution layer 112a, a redistribution layer 112b, and a redistribution layer 112c may be introduced, and a plurality of stacked memories The chip 121 and the memory chip 122 may be disposed in the through hole 110H of the first connection member 110. In addition, the second connection member 140 including the redistribution layer 142 may be formed without introducing an interposer. Specifically, the stacked memory chip 121 and the memory chip 122 may be connected to the redistribution layer 142 of the second connection member 140 through the multi-level conductor 121v and the conductor 122v having different heights, instead of being bonded via a bonding wire. Therefore, as shown on the right side of FIG. 29, the rewiring can be distributed to various locations, so that the thickness of the second connection member 140 can be significantly reduced, and the backside encapsulation thickness or the thickness of multiple stacked wafers can also be reduced. Significantly reduced. In addition, as shown on the right side of FIG. 30, the message path from the stacked semiconductor wafer 121 and the semiconductor wafer 122 to the connection terminal 170 can be significantly reduced, so that signal loss can be reduced, and the electrical characteristics of the signal can be improved. In addition, the warping phenomenon can be controlled through the first connection member 110, and reliability can be improved accordingly.

Hereinafter, each component included in the fan-out type semiconductor package 100A according to an exemplary embodiment will be explained in more detail.

The first connection member 110 may include a redistribution layer 112a, a redistribution layer 112b, and a redistribution layer 112c to redistribute the plurality of connection pads 121P of the semiconductor wafer 121 and the plurality of connection pads 122P of the semiconductor wafer 122, thereby reducing the second connection. The number of layers of the member 140. When necessary, the first connection member 110 can maintain the rigidity of the fan-out semiconductor package 100A according to a specific material, and is used to ensure the thickness uniformity of the encapsulation body 130. In addition, due to the first connection member 110, the fan-out type semiconductor package 100A according to the exemplary embodiment may be used as a part of a package-on-package. The first connection member 110 may have a through hole 110H. The stacked semiconductor wafer 121 and the semiconductor wafer 122 may be disposed in the through hole 110H so that the stacked semiconductor wafer 121 and the semiconductor wafer 122 and the first connection member 110 may be spaced apart from each other by a predetermined distance. The side surfaces of the semiconductor wafer 121 and the semiconductor wafer 122 may be surrounded by the first connection member 110. However, this form is merely an example, and may be variously modified to have other forms, and the first connection member 110 may perform another function in this form.

The first connection member 110 may include a first insulation layer 111a, a first redistribution layer 112a, a second redistribution layer 112b, a second insulation layer 111b, and a third redistribution layer 112c. The first insulation layer 111a contacts the second connection member 140. The first redistribution layer 112a contacts the second connection member 140 and is embedded in the first insulating layer 111a. The second redistribution layer 112b is disposed on the other surface of the first insulating layer 111a. A redistribution layer 112a is embedded on the surface of the first insulation layer 111a, a second insulation layer 111b is disposed on the first insulation layer 111a and covers the second redistribution layer 112b, and a third redistribution layer 112c is disposed on the second insulation layer 111b. The first redistribution layer 112a, the second redistribution layer 112b, and the third redistribution layer 112c may be electrically connected to the plurality of connection pads 121P and the plurality of connection pads 122P. Specifically, the first redistribution layer 112a and the second redistribution layer 112b may be electrically connected to each other through the first through hole 113a penetrating the first insulating layer 111a, and the second redistribution layer 112b and the third redistribution layer 112c may be electrically connected to each other. The second through holes 113b penetrating through the second insulating layer 111b are electrically connected to each other.

Since the first redistribution layer 112a is embedded in the first insulation layer 111a, the insulation distance of the insulation layer 141 of the second connection member 140 may be substantially constant. Since the first connection member 110 may include a large number of redistribution layers 112a, redistribution layers 112b, and redistribution layers 112c, the second connection member 140 may be simplified. Therefore, after the semiconductor wafer 121 and the semiconductor wafer 122 are configured, the problem of a decrease in yield due to a defect occurring in the formation process of the second connection member 140 can be suppressed. The first redistribution layer 112a may be recessed in the first insulating layer 111a, so that there may be a step between the lower surface of the first insulating layer 111a and the lower surface of the first redistribution layer 112a. Therefore, when the encapsulation body 130 is formed, the phenomenon that the material of the encapsulation body 130 penetrates and contaminates the first redistribution layer 112a can be prevented.

The thicknesses of the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c of the first connection member 110 may be greater than the thickness of the redistribution layer 142 of the second connection member 140. Since the thickness of the first connection member 110 may be greater than or equal to the thickness of the stacked semiconductor wafer 121 and semiconductor wafer 122, depending on the specifications of the first connection member 110, a redistribution layer 112a and a redistribution layer 112b having a larger size may be formed. And a redistribution layer 112c. On the other hand, in consideration of thinness, the redistribution layer 142 of the second connection member 140 having a relatively small size may be formed.

The material of each of the first insulating layers 111a and the material of each of the second insulating layers 111b are not particularly limited. For example, an insulating material may be used as the material of each insulating layer. In this case, the insulating material may be a thermosetting resin such as epoxy resin; a thermoplastic resin such as polyimide resin; a thermosetting resin or thermoplastic resin with an inorganic filler or, for example, glass fiber (or glass cloth or glass fiber) Cloth) and other core materials such as prepreg, prepreg, Ajinomoto Build up Film (ABF), FR-4, bismaleimide triazine (Bismaleimide Triazine, BT) and so on. Alternatively, a photoimagable dielectric (PID) resin may be used as a material of each of the first insulating layers 111a and a material of each of the second insulating layers 111b.

The plurality of redistribution layers 112a, the plurality of redistribution layers 112b, and the plurality of redistribution layers 112c may be used to redistribute the connection pads 121P of the semiconductor wafer 121 and the connection pads 122P of the semiconductor wafer 122, and each of the redistribution layers 112a and each redistribution The material of the layer 112b and each of the redistribution layers 112c may be a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and lead (Pb). , Titanium (Ti) or its alloy. The redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c may perform various functions depending on the design of their corresponding layers. For example, the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c may include a ground pattern, a power pattern, a signal pattern, and the like. Here, the signal pattern may include various signals other than a ground pattern and a power pattern, such as a data signal. In addition, the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c may include various via pad patterns and the like.

The plurality of through holes 113a and the plurality of through holes 113b may electrically connect the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c formed on different layers to form an electrical path in the first connection member 110 ( electrical path). The material of each through hole 113a and the material of each through hole 113b may be a conductive material. Each through hole 113a and each through hole 113b may be completely filled with a conductive material, or the conductive material may be formed along a wall surface of each through hole hole. In addition, each through hole 113a and each through hole 113b may have any shape known in the related art, such as a cone shape, a cylindrical shape, or the like. At the same time, each of the through-hole 113a and the through-hole 113b may have a tapered shape with an upper surface width greater than a lower surface width, thereby facilitating the manufacturing process.

The semiconductor wafer 121 and the semiconductor wafer 122 may be integrated circuits in which hundreds to millions or more of components are integrated in a single wafer. Integrated circuit can be volatile memory (such as dynamic random access memory (DRAM)), non-volatile memory (such as read only memory (ROM)), flash memory Style, but not limited to this. The active surface of the semiconductor wafer 121 means the surface of the semiconductor wafer 121 on which the plurality of connection pads 121P are disposed, the active surface of the semiconductor wafer 122 means the surface of the semiconductor wafer 122 on which the plurality of connection pads 122P are disposed, and the semiconductor wafer 121 And the inactive surface of the semiconductor wafer 122 means a surface opposite to the active surface.

The semiconductor wafer 121 and the semiconductor wafer 122 may be formed on the basis of an active wafer. In this case, the base material of the semiconductor wafer 121 and the semiconductor wafer 122 may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Various circuits can be formed on the body. The plurality of connection pads 121P and the plurality of connection pads 122P can electrically connect the semiconductor wafer 121 and the semiconductor wafer 122 to other components. The material of each connection pad 121P and each connection pad 122P may be, for example, a conductive material such as aluminum (Al). A passivation layer (not shown) that exposes the connection pad 121P and the connection pad 122P may be formed on the body, and the passivation layer may be an oxide film, a nitride film, or the like, or a double layer composed of an oxide layer and a nitride layer . The insulation layer (not shown) can be further arranged in other required positions.

The semiconductor wafer 121 and the semiconductor wafer 122 may be connected to the redistribution layer 142 of the second connection member 140 through a plurality of conductors 121v and conductors 122v having different heights. In this case, the first conductor 121 v may not penetrate the encapsulation body 130, and the second conductor 122 v may penetrate the encapsulation body 130. That is, the first conductor 121v may not contact the encapsulation body 130, and the second conductor 122v may contact the encapsulation body 130. The active surface of the second semiconductor wafer 122 may include a first side portion facing the non-active surface of the first semiconductor wafer 121, a middle portion facing the non-active surface of the first semiconductor wafer 121, and a second side portion. The middle portion of the two side portions with respect to the active surface of the second semiconductor wafer 122 is symmetrical to the first side portion, and the second side portion is at least partially not on the non-active surface of the first semiconductor wafer 121. In this case, the plurality of second connection pads 122P may be disposed on the second side portion of the active surface of the second semiconductor wafer 122. That is, the semiconductor wafer 121 and the semiconductor wafer 122 may be configured so as not to match each other in a step form, and a plurality of second connection pads 122P may be disposed on the second side portion of the active surface of the second semiconductor wafer 122, and may further be applied with Multi-level conductors 121v and 122v of different heights.

The semiconductor wafer 121 and the semiconductor wafer 122 can be attached to each other by an adhesive member 180. The adhesive member 180 is not particularly limited, but may be a material that allows the semiconductor wafer 121 and the semiconductor wafer 122 to be attached to each other, such as a known tape, an adhesive, or the like. In some cases, the adhesive member 180 may also be omitted. Meanwhile, the configurations of the semiconductor wafer 121 and the semiconductor wafer 122 are not limited to the forms shown in the drawings. That is, the semiconductor wafer 121 and the semiconductor wafer 122 can also be configured in a form different from that shown in the plan view, as long as the semiconductor wafer 121 and the semiconductor wafer 122 can be configured so as not to match each other and a multi-level conductor 121v and a conductor 122v can be applied. .

The encapsulation body 130 can protect the first connection member 110 and / or the semiconductor wafer 121 and the semiconductor wafer 122. The encapsulation form of the encapsulation body 130 is not particularly limited, but may be in the form that the encapsulation body 130 surrounds at least part of the first connection member 110 and / or at least part of the semiconductor wafer 121 and at least part of the semiconductor wafer 122. For example, the encapsulation body 130 may cover at least a portion of the first connection member 110 and at least a portion of the inactive surface of the semiconductor wafer 121 and at least a portion of the inactive surface of the semiconductor wafer 122, and may be filled in a plurality of through-holes 110H. A space between each wall surface and a plurality of side surfaces of the semiconductor wafer 121 and the semiconductor wafer 122. At the same time, the encapsulation body 130 can fill the through-hole 110H, thus acting as an adhesive, and reducing buckling of the semiconductor wafer 121 and the semiconductor wafer 122 depending on a specific material.

The insulating layer 130 may include an insulating material. The insulating material may be a material including an inorganic filler and an insulating resin, for example, a thermosetting resin such as epoxy resin; a thermoplastic resin such as polyimide resin; an inorganic filler immersed in the thermosetting resin and the thermoplastic resin, etc. Resin for reinforcing materials, such as Ajinomoto constituent film (ABF), FR-4, bismaleimide triazine (BT), photosensitive imaging dielectric (PID) resin, etc. In addition, known molding materials such as epoxy molding compound (EMC) can also be used. Alternatively, if a thermosetting resin or a thermoplastic resin is immersed in the inorganic filler and / or the core material, and the core material is glass fiber (or glass cloth, or glass fiber cloth), the material can be used as an insulating material.

The second connection member 140 may be configured to redistribute the plurality of connection pads 121P of the semiconductor wafer 121 and the plurality of connection pads 122P of the semiconductor wafer 122. Dozens to hundreds of connection pads 121P and 122P with various functions can be redistributed by the second connection member 140, and depending on the function, they can be physically connected or electrically connected via the connection terminal 170 (described below). Sexually connected to external sources. The second connection member 140 may include a plurality of insulation layers 141, a plurality of redistribution layers 142 disposed on the plurality of insulation layers 141, and a plurality of through holes penetrating the plurality of insulation layers 141 and connecting the respective redistribution layers 142 to each other. 143. In the fan-out type semiconductor package 100A according to the exemplary embodiment, the second connection member 140 may include a single layer, but may also include multiple layers.

The material of each insulating layer 141 may be an insulating material. In this case, a photosensitive insulating material such as a photosensitive imaging dielectric (PID) resin may be used as the insulating material. That is, the insulating layer 141 may be a photosensitive insulating layer. When the insulating layer 141 has photosensitive characteristics, the insulating layer 141 can be formed with a thinner thickness, and the precise pitch of the through holes 143 can be more easily achieved. The insulating layer 141 may be a photosensitive insulating layer including an insulating resin and an inorganic filler. When the insulating layer 141 is a plurality of layers, the materials of the insulating layers 141 may be the same as each other, and may be different from each other when necessary. When the insulating layer 141 is a plurality of layers, the insulating layers 141 may be integrated with each other according to the manufacturing process, so that the boundaries between the insulating layers may be inconspicuous.

The plurality of redistribution layers 142 may be used to substantially redistribute the plurality of connection pads 121P and the plurality of connection pads 122P. The material of each redistribution layer 142 may be a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium ( Ti) or an alloy thereof. The plurality of rewiring layers 142 may perform various functions depending on the design of their corresponding layers. For example, the plurality of redistribution layers 142 may include a ground pattern, a power pattern, a signal pattern, and the like. Here, the signal pattern may include various signals other than a ground pattern and a power pattern, such as a data signal. In addition, the plurality of redistribution layers 142 may include various pad patterns, such as through-hole pads, connection terminal pads, and the like.

The plurality of through holes 143 may electrically connect the redistribution layers formed on different layers to each other to form an electrical path in the fan-out semiconductor package 100A. The material of each through hole 143 may be a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium (Ti ) Or its alloy. Each through hole 143 may be completely filled with a conductive material, or a conductive material may be formed along a wall surface of each through hole. In addition, each of the through holes 143 may have any shape known in the related art, such as a tapered shape, a cylindrical shape, or the like.

The passivation layer 150 may be additionally configured to protect the second connection member 140 from external physical or chemical damage. The passivation layer 150 may have an opening 151, and the opening 151 exposes at least a part of the redistribution layer 142 of the second connection member 140. The number of openings formed in the passivation layer 150 may be tens to thousands.

The material of the passivation layer 150 is not particularly limited, but may be a photosensitive insulating material such as a photosensitive imaging dielectric (PID) resin. Alternatively, a solder resist may be used as a material of the passivation layer 150. Alternatively, an insulating resin may be used as the material of the passivation layer 150. The insulating resin does not include a core material but includes a filler, such as an ABF including an inorganic filler and an epoxy resin. When an insulating material including an inorganic filler and an insulating resin but not including a core material such as ABF is used as the material of the passivation layer 150, the passivation layer 150 and the resin layer 182 may be symmetrical to each other, which may control warpage dispersion. ) Can be more effective for controlling warpage. When an insulating material including an inorganic filler and an insulating resin, such as ABF, is used as the material of the passivation layer 150, the insulating layer 141 of the second connection member 140 may also include an inorganic filler and an insulating resin. In this case, a weight percentage of the inorganic filler included in the passivation layer 150 may be greater than a weight percentage of the inorganic filler included in the insulating layer 141 of the second connection member 140. In this case, the passivation layer 150 may have a relatively low coefficient of thermal expansion (CTE), and may be used to control warpage.

The under bump metal layer 160 may be configured to improve the connection reliability of the connection terminal 170 and improve the board-level reliability of the fan-out semiconductor package 100A. The under bump metal layer 160 may be connected to the redistribution layer 142 of the second connection member 140 via the opening 151 of the passivation layer 150. A known conductive material (such as a metal) may be used to form the under bump metal layer 160 in the opening 151 of the passivation layer 150 by a conventional metallization method, but is not limited thereto.

A plurality of connection terminals 170 may be additionally configured to physically or electrically connect the fan-out semiconductor package 100A to the outside. For example, the fan-out semiconductor package 100A may be mounted on a motherboard of an electronic device via a plurality of connection terminals 170. Each connection terminal 170 may be formed of a conductive material such as solder. However, this is only an example, and the material of each connection terminal 170 is not particularly limited thereto. Each connection terminal 170 may be a pin, a ball, a pin, or the like. The plurality of connection terminals 170 may be formed in a multilayer structure or a single-layer structure. When the plurality of connection terminals 170 are formed into a multilayer structure, the plurality of connection terminals 170 may include copper (Cu) pillars and solder. When the plurality of connection terminals 170 are formed into a single-layer structure, the plurality of connection terminals 170 may include tin-silver solder or copper (Cu). However, this is merely an example, and the plurality of connection terminals 170 are not limited thereto.

The number, interval, or configuration of the plurality of connection terminals 170 are not particularly limited, and can be sufficiently modified by those having ordinary knowledge in the technical field depending on design details. For example, the plurality of connection terminals 170 may be provided in a number of tens to thousands or thousands, or may be provided in a number of tens to thousands or more or tens to thousands or less. When the plurality of connection terminals 170 are solder balls, the plurality of connection terminals 170 may cover the plurality of side surfaces of the under bump metal layer 160, and the plurality of side surfaces of the under bump metal layer 160 extend to one surface of the passivation layer 150. , And the connection reliability can be more excellent than when other materials are used to connect the terminals.

At least one of the plurality of connection terminals 170 may be disposed in the fan-out area. The fan-out area is an area other than the area where the semiconductor wafer 120 is configured. That is, the fan-out type semiconductor package 100A according to an exemplary embodiment may be a fan-out type package. Compared to a fan-in package, the fan-out package can have excellent reliability, the fan-out package can implement multiple input / output (I / O) terminals, and the fan-out package can Facilitates three-dimensional (3D) interconnection. In addition, compared to a ball grid array (BGA) package, a land grid array (LGA) package, etc., the fan-out package can be mounted on an electronic device without a separate board. . As a result, fan-out packages can be made thin and competitively priced.

Meanwhile, although not shown in the drawings, if necessary, a metal layer may be further disposed on the wall surface of the through hole 110H. The metal layer can be used to efficiently dissipate heat generated from the semiconductor wafer 121 and the semiconductor wafer 122. In addition, the metal layer can also be used to block electromagnetic waves. Furthermore, a separate passive component such as a capacitor, an inductor, etc. may be further disposed in the through hole 110H. In addition to the structure described above, a structure known in the conventional art may be applied.

11A to 11D are schematic diagrams illustrating an embodiment of a fan-out semiconductor packaging process in FIG. 9.

11A, a first connection member 110 having a through hole 110H may be prepared. For example, the first connecting member 110 can be prepared by the following steps: preparing a carrier film having a metal layer, and the metal layer is formed on one surface or an opposite surface of the carrier film; and the metal layer is used as a seed crystal. Layers to form a first redistribution layer 112a; a first insulating layer 111a covering the first redistribution layer 112a on a metal layer; a second redistribution layer 112b to be formed on the first insulating layer 111a; and a first insulating layer 111a Forming a second insulation layer 111b covering the second redistribution layer 112b; forming a third redistribution layer 112c on the second insulation layer 111b to form a first connection member 110; separating the first connection member 110 from the carrier film; and then moving The metal layer remaining on the first redistribution layer 112a is removed. When the metal layer is removed, a recessed portion may be formed in the first connection member 110. The redistribution layer 112a, redistribution layer 112b, and redistribution layer 112c may be formed by patterning using a dry film or the like, and filling the pattern with a known plating process. The first insulating layer 111a and the second insulating layer 111b can be formed by a known lamination method or an applying and hardening method. Then, the adhesive film 210 may be attached to one surface of the first connection member 110. Any material that can fix the first connection member 110 can be used as the adhesive film 210. As a non-limiting example, a known tape or the like may be used. Examples of known tapes may include thermosetting adhesive tapes whose adhesiveness is weakened by heat treatment, ultraviolet-curable adhesive tapes whose adhesiveness is weakened by ultraviolet irradiation, and the like. Next, the stacked semiconductor wafer 121 and the semiconductor wafer 122 may be disposed in the through hole 110H of the first connection member 110. For example, the arrangement method of the stacked semiconductor wafer 121 and the semiconductor wafer 122 may be affixing the stacked semiconductor wafer 121 and the semiconductor wafer 122 to the adhesive film 210 in the through hole 110H. The stacked semiconductor wafer 121 and the semiconductor wafer 122 may be disposed face down, so that the active surfaces of the plurality of connection pads 121P and the plurality of connection pads 122P disposed thereon face the adhesive film 210. Next, the encapsulation body 130 may be used to encapsulate at least a portion of the first connection member 110 and at least a portion of the semiconductor wafer 121 and at least a portion of the semiconductor wafer 122. The encapsulation body 130 can enclose at least part of the first connection member 110 and at least part of the inactive surface of the semiconductor wafer 121 and at least part of the inactive surface of the semiconductor wafer 122, and can fill at least part of the space in the through hole 110H. The encapsulation body 130 can be formed by a known method. For example, the formation method of the encapsulation body 130 may be to laminate a precursor of the encapsulation body 130 and then harden the precursor. Alternatively, the encapsulation body 130 may be formed by applying a pre-encapsulant to the adhesive film 210 to encapsulate the semiconductor wafer 121 and the semiconductor wafer 122, and then curing the pre-encapsulation body.

11B, the adhesive film 210 is peelable. The method for peeling the adhesive film is not particularly limited, but may be a known method. For example, when the thermosetting adhesive tape whose adhesiveness is weakened by heat treatment, the UV-curable adhesive tape whose adhesiveness is weakened by UV irradiation are used as the adhesive film 210, the adhesiveness of the adhesive film 210 can be weakened by heat treatment. After the adhesive film 210 is peeled off, the adhesive film 210 may be peeled off after the adhesiveness of the adhesive film 210 is weakened by ultraviolet irradiation. Then, if necessary, the detachable film 220 may be attached to the encapsulation body 130. The material and the like of the detachable film 220 are not particularly limited. Next, the insulating layer 141 may be formed in a region where the adhesive film 210 is removed. The insulating layer 141 can be formed by a lamination method or an application method using the above-mentioned insulating material. Next, a redistribution layer 142 and a plurality of through holes 143 may be formed. In addition, a multi-level conductor 121v and a conductor 122v can be formed. The method of forming the plurality of through holes 143 and the multi-level conductors 121v and 122v may be to form holes using exposure and development methods, laser drilling, etc., and then perform plating by a known plating process. Known electroplating processes such as subtractive process, addictive process, semi-additive process (SAP), modified semi-additive process (MSAP) Wait. The redistribution layer 142 may also be formed by the above-mentioned known plating process. The second connection member 140 may be formed on the first connection member 110, the active surface of the semiconductor wafer 121, and the active surface of the semiconductor wafer 122 through a series of processes.

Referring to FIG. 11C, a plurality of holes 122vh for the second conductor 122v among the multi-level conductor 121v and the conductor 122v may also be formed to penetrate the encapsulation body 130 before the insulating layer 141 is formed. That is, the formation steps of the second connection member 140 and the multi-level conductor 121v and the conductor 122v may be: peeling the adhesive film 210, attaching the detachable film 220, forming a plurality of holes 112vh for the second conductor 122v, and forming an insulating layer 141. Form a plurality of holes for the plurality of through holes 143 and the multi-level conductor 121v and the conductor 122v in the insulating layer 141, and then perform a plating process.

Referring to FIG. 11D, next, a passivation layer 150 may be formed on the second connection member 140. The formation method of the passivation layer 150 may also be to laminate the precursors of the passivation layer 150 and then harden the precursors, or apply the material for forming the passivation layer 150 and then harden the material, or the like method. A plurality of openings 151 may be formed in the passivation layer 150 to expose at least a portion of the redistribution layer 142 of the second connection member 140, and the under bump metal layer 160 may be formed in the plurality of openings 151 by a conventional metallization method. If necessary, a plurality of connection terminals 170 may be formed on the under bump metal layer 160. The method of forming the plurality of connection terminals 170 is not particularly limited. That is, depending on the structure and form, the plurality of connection terminals 170 may be formed by a method known in this technical field. Multiple connection terminals 170 can be fixed by re-soldering, and parts of the multiple connection terminals 170 can be embedded in the passivation layer 150 to enhance the fixing force, and the rest of the multiple connection terminals 170 can be exposed to the outside, making reliability May increase. In addition, a plurality of openings 131 may be formed, and the plurality of openings 131 penetrate through the encapsulation body 130 and expose at least a portion of the third redistribution layer 112 c of the first connection member 110.

Meanwhile, a series of processes may be the following processes: preparing a carrier film having a larger size, manufacturing a plurality of fan-out semiconductor packages, and then separating the plurality of fan-out semiconductor packages by a sawing process. Integrated into a separate fan-out type semiconductor package to facilitate mass production. In this case, productivity may be excellent.

FIG. 12 is a schematic cross-sectional view illustrating another embodiment of a fan-out semiconductor package.

Referring to the drawings, according to another exemplary embodiment of the present disclosure, in a fan-out type semiconductor package 100B, a plurality of first connection pads 121P of the first semiconductor wafer 121 and a plurality of second connection pads 122P of the second semiconductor wafer 122 It can be configured to face each other in the horizontal direction, which is different from the fan-out type semiconductor package 100A shown in FIG. 9. That is, the plurality of first connection pads 121P of the first semiconductor wafer 121 in the drawing may be disposed on the mismatched side portion of the left side of the active surface of the first semiconductor wafer 121, and the second in the drawing is the second The plurality of second connection pads 122P of the semiconductor wafer 122 may be disposed on the unmatched side portion of the right side portion of the active surface of the second semiconductor wafer 122. The description about the configuration and manufacturing method overlapping with the above will be omitted below.

13 is a schematic cross-sectional view illustrating another embodiment of a fan-out type semiconductor package.

Referring to the drawings, according to another exemplary embodiment of the present disclosure, in the fan-out semiconductor package 100C, the horizontal cross-sectional area of the second semiconductor wafer 122 may be larger than the horizontal cross-sectional area of the first semiconductor wafer 121, which is the same as that shown in FIG. 9. The fan-out type semiconductor package 100A shown is different. That is, the active surface of the second semiconductor wafer 122 may be wider than the inactive surface of the second semiconductor wafer 121. In this case, the active surface of the second semiconductor wafer 122 may include a first side portion, an intermediate portion, and a second side portion. At least part of the first side portion is not on the inactive surface of the first semiconductor wafer 121, and the intermediate portion surface is To the inactive surface of the first semiconductor wafer 121, and the second side portion is symmetrical to the first side portion with respect to the middle portion, and is at least partially not on the inactive surface of the first semiconductor wafer 121, and a plurality of second connections The pad 122P may be disposed on the first side portion and the second side portion of the active surface of the second semiconductor wafer 122. That is, the semiconductor wafer 121 and the semiconductor wafer 122 may be configured so as not to match each other, so that the semiconductor wafer 121 and the semiconductor wafer 122 have different horizontal cross-sectional areas, and a plurality of second connection pads 122P may be disposed on the second semiconductor wafer 122. On the first side portion and the second side portion of the active surface, a multi-level conductor 121v and a conductor 122v can be further applied. The description about the configuration and manufacturing method overlapping with the above will be omitted below.

FIG. 14 is a schematic cross-sectional view illustrating another embodiment of a fan-out semiconductor package.

Referring to the drawings, a fan-out semiconductor package 100D according to another exemplary embodiment of the present disclosure may further include a third semiconductor wafer 123, and the third semiconductor wafer 123 and the second semiconductor wafer 122 are arranged side by side in the first through hole 110H. The semiconductor wafer 121 and the third semiconductor wafer 123 have an active surface on which a plurality of third connection pads 123P are disposed and an inactive surface opposite to the active surface, which are different from the fan-out semiconductor package 100A shown in FIG. 9 . The active surface of the third semiconductor wafer 123 may be attached to the non-active surface of the first semiconductor wafer 121, and the third semiconductor wafer 123 may be disposed on a side opposite to the second semiconductor wafer 122 in the horizontal direction and stepped The pattern is arranged on the first semiconductor wafer 121 so as not to match the first semiconductor wafer 121, so that a plurality of third connection pads 123P are exposed. The horizontal cross-sectional area of the second semiconductor wafer 122 and the horizontal cross-sectional area of the third semiconductor wafer 123 may be smaller than the horizontal cross-sectional area of the first semiconductor wafer 121. The redistribution layer 142 of the second connection member 140 may be connected to the plurality of third connection pads 123P through the plurality of third conductors 123v, and the height of the second conductor 122v and the height of the third conductor 123v may be the same as each other. The term "the heights are the same as each other" means that the heights are substantially the same as each other. This concept includes examples of gaps in the manufacturing process. The first semiconductor wafer 121 may be connected to the second semiconductor wafer 122 and the third semiconductor wafer 123 through the first adhesive member 180a and the second adhesive member 180b, respectively. The description about the configuration and manufacturing method overlapping with the above will be omitted below.

FIG. 15 is a schematic cross-sectional view illustrating another embodiment of a fan-out semiconductor package.

Referring to the drawings, a fan-out semiconductor package 100E according to another exemplary embodiment of the present disclosure may further include a third semiconductor wafer 123, and the third semiconductor wafer 123 and the first semiconductor wafer 121 are arranged side by side in the through hole 110H, and the first The three semiconductor wafer 123 has an active surface on which a plurality of third connection pads 123P are disposed and an inactive surface opposite to the active surface, which is different from the fan-out semiconductor package 100A shown in FIG. 9. The active surface of the second semiconductor wafer 122 may be attached to the inactive surface of the first semiconductor wafer 121 and the inactive surface of the third semiconductor wafer 123, and the second semiconductor wafer 122 may be disposed on the first semiconductor wafer 121 and the third The semiconductor wafer 123 is not matched with the first semiconductor wafer 121 and the third semiconductor wafer 123, so that a plurality of second connection pads 122P are exposed. The redistribution layer 142 of the second connection member 140 may be connected to the plurality of third connection pads 123P through the plurality of third conductors 123v, and the height of the first conductor 121v and the height of the third conductor 123v may be the same as each other. The horizontal cross-sectional area of the second semiconductor wafer 122 may be larger than the horizontal cross-sectional areas of the first semiconductor wafer 121 and the third semiconductor wafer 123. In this case, the active surface of the second semiconductor wafer 122 may include a first side portion, an intermediate portion, and a second side portion. At least part of the first side portion is not on the inactive surface of the first semiconductor wafer 121. At least partly not on the inactive surface of the first semiconductor wafer 121 and the inactive surface of the third semiconductor wafer 123, and the second side portion is symmetrical to the first side portion with respect to the middle portion, and at least part of the second side portion is not on The non-active surface of the third semiconductor wafer 123, and a plurality of second connection pads 122P may be disposed on the first side portion, the second side portion, and the middle portion of the active surface of the second semiconductor wafer 122. That is, the second semiconductor wafer 122 may be in a form having a horizontal cross-sectional area different from that of the first semiconductor wafer 121 and the third semiconductor wafer 123, and configured so as not to match the first semiconductor wafer 121 and the third semiconductor wafer 123, and The plurality of second connection pads 122P may be disposed on the first side portion, the second side portion, and the middle portion of the active surface of the second semiconductor wafer 122. The first semiconductor wafer 121 and the third semiconductor wafer 123 may be connected to the second semiconductor wafer 122 through the first adhesive member 180a and the second adhesive member 180b, respectively. The description about the configuration and manufacturing method overlapping with the above will be omitted below.

FIG. 16 is a schematic cross-sectional view illustrating another embodiment of a fan-out semiconductor package.

Referring to the drawings, a fan-out semiconductor package 100F according to another exemplary embodiment of the present disclosure may further include a third semiconductor wafer 123 and a fourth semiconductor wafer 124. The third semiconductor wafer 123 and the first semiconductor wafer 121 are arranged side by side in a through hole. In the hole 110H, and the third semiconductor wafer 123 has an active surface on which a plurality of third connection pads 123P are disposed and an inactive surface opposite to the active surface, the fourth semiconductor wafer 124 is disposed in the third semiconductor wafer in the through-hole 110H 123, and the fourth semiconductor wafer 124 has an active surface on which a plurality of fourth connection pads 124P are disposed and an inactive surface opposite to the active surface, which are different from the fan-out semiconductor package 100A shown in FIG. 9. The active surface of the fourth semiconductor wafer 124 may be attached to the inactive surface of the third semiconductor wafer 123, and the fourth semiconductor wafer 124 may be arranged on the third semiconductor wafer 123 in a step form so as not to match the third semiconductor wafer 123, and further The plurality of fourth connection pads 124P are exposed. The redistribution layer 142 of the second connection member 140 may be connected to a plurality of third connection pads 123P through a plurality of third conductors 123v, and to a plurality of fourth connection pads 124P through a plurality of fourth conductors 124v. The height of the fourth conductor 124v may be greater than the height of the third conductor 123v. As described above, even in a structure in which the semiconductor wafer 121, the semiconductor wafer 122, the semiconductor wafer 123, and the semiconductor wafer 124 are connected to each other in a two-stage parallel form, the multi-stage conductor 121v and the conductor can be applied. 122v, conductor 123v, and conductor 124v. Respectively, the first semiconductor wafer 121 and the second semiconductor wafer 122 may be connected to each other through the first adhesive member 180a, and the third semiconductor wafer 123 and the fourth semiconductor wafer 124 may be connected to each other through the second adhesive member 180b. The description about the configuration and manufacturing method overlapping with the above will be omitted below.

FIG. 17 is a schematic cross-sectional view illustrating another embodiment of a fan-out type semiconductor package.

Referring to the drawings, according to another exemplary embodiment of the present disclosure, in a fan-out type semiconductor package 100G, a semiconductor wafer 121, a semiconductor wafer 122, a semiconductor wafer 123, and a semiconductor wafer 124 are connected to each other in a two-stage parallel form, which is similar to the figure The form shown in 16 is similar. However, the plurality of first connection pads 121P of the first semiconductor wafer 121 and the plurality of second connection pads 122P of the second semiconductor wafer 122 may be configured to face each other in the horizontal direction. In addition, the plurality of third connection pads 123P of the third semiconductor wafer 123 and the plurality of fourth connection pads 124P of the fourth semiconductor wafer 124 may be configured to face each other in the horizontal direction. That is, the plurality of first connection pads 121P of the first semiconductor wafer 121 in the drawing may be disposed on the unmatched side portion of the left side of the active surface of the first semiconductor wafer 121, and the plurality of second semiconductor wafers 122 in the drawing may The second connection pads 122P may be disposed on unmatched side portions of the right side portion of the active surface of the second semiconductor wafer 122. In addition, the plurality of third connection pads 123P of the third semiconductor wafer 123 in the drawing may be disposed on the unmatched side portion of the left side portion of the active surface of the third semiconductor wafer 123, and a plurality of the fourth semiconductor wafers 124 in the drawing The fourth connection pad 124P may be disposed on an unmatched side portion of a right side portion of the active surface of the fourth semiconductor wafer 124. The description about the configuration and manufacturing method overlapping with the above will be omitted below.

FIG. 18 is a schematic cross-sectional view illustrating another embodiment of a fan-out type semiconductor package.

Referring to the drawings, according to another exemplary embodiment of the present disclosure, in a fan-out type semiconductor package 100H, a semiconductor wafer 121, a semiconductor wafer 122, a semiconductor wafer 123, and a semiconductor wafer 124 are connected to each other in a two-stage parallel form, which is similar to the figure The form shown in 16 is similar. However, the plurality of second connection pads 122P of the second semiconductor wafer 122 in the drawing may be disposed on the unmatched side portions of the left side portion of the active surface of the second semiconductor wafer 122, and the plurality of fourth semiconductor wafers 124 in the drawing may The fourth connection pad 124P may be disposed on an unmatched side portion of a right side portion of the active surface of the fourth semiconductor wafer 124. That is, the mismatched portion between the multi-level conductor 121v and the conductor 122v of the first semiconductor wafer 121 and the second semiconductor wafer 122 may be arranged to match the multi-level conductor 123v and the conductor of the third semiconductor wafer 123 and the fourth semiconductor wafer 124. The mismatched portions between 124v are opposed to each other in the horizontal direction of the fan-out type semiconductor package 100H. The description about the configuration and manufacturing method overlapping with the above will be omitted below.

FIG. 19 is a schematic cross-sectional view illustrating another embodiment of a fan-out type semiconductor package.

Referring to the drawings, according to another exemplary embodiment of the present disclosure, in a fan-out semiconductor package 100I, a semiconductor wafer 121, a semiconductor wafer 122, a semiconductor wafer 123, and a semiconductor wafer 124 are connected to each other in a two-stage parallel form, which is similar to the figure The form shown in 16 is similar. However, the plurality of second connection pads 122P of the second semiconductor wafer 122 in the drawing may be disposed on the unmatched side portion of the right side portion of the active surface of the second semiconductor wafer 122, and the plurality of the fourth semiconductor wafers 124 in the drawing The fourth connection pad 124P may be disposed on an unmatched side portion of a left side portion of the active surface of the fourth semiconductor wafer 124. That is, the mismatched portion between the multi-level conductor 121v and the conductor 122v of the first semiconductor wafer 121 and the second semiconductor wafer 122 may be arranged to match the multi-level conductor 123v and the conductor of the third semiconductor wafer 123 and the fourth semiconductor wafer 124. The mismatches between 124v face each other. The description about the configuration and manufacturing method overlapping with the above will be omitted below.

FIG. 20 is a schematic cross-sectional view illustrating another embodiment of a fan-out semiconductor package.

Referring to the drawings, according to another exemplary embodiment of the present disclosure, in a fan-out type semiconductor package 100J, a semiconductor wafer 121, a semiconductor wafer 122, a semiconductor wafer 123, and a semiconductor wafer 124 are connected to each other in a two-stage parallel form, which is similar to the figure The form shown in 16 is similar. However, the horizontal cross-sectional area of the second semiconductor wafer 122 may be wider than that of the first semiconductor wafer 121. In addition, the horizontal cross-sectional area of the fourth semiconductor wafer 124 may be wider than that of the third semiconductor wafer 123. That is, the active surface of the second semiconductor wafer 122 may be wider than the inactive surface of the second semiconductor wafer 121. In addition, the active surface of the fourth semiconductor wafer 124 may be wider than the inactive surface of the third semiconductor wafer 123. That is, the stacked semiconductor wafer 121, the semiconductor wafer 122, the semiconductor wafer 123, and the semiconductor wafer 124 may have forms with different horizontal cross-sectional areas in a two-stage parallel structure to be configured so as not to match each other. The description about the configuration and manufacturing method overlapping with the above will be omitted below.

FIG. 21 is a schematic cross-sectional view illustrating another embodiment of a fan-out type semiconductor package.

Referring to the drawings, a fan-out semiconductor package 100K according to another exemplary embodiment of the present disclosure may further include a third semiconductor wafer 123 that is disposed on the second semiconductor wafer 122 in the through hole 110H, and the first The three semiconductor wafer 123 has an active surface on which a plurality of third connection pads 123P are disposed and an inactive surface opposite to the active surface, which is different from the fan-out semiconductor package 100A shown in FIG. 9. The active surface of the third semiconductor wafer 123 may be attached to the inactive surface of the second semiconductor wafer 122, and the third semiconductor wafer 123 may be arranged on the second semiconductor wafer 122 in a step form so as not to match the second semiconductor wafer 122, and further A plurality of third connection pads 123P are exposed. The redistribution layer 142 of the second connection member 140 may be connected to the plurality of third connection pads 123P through the plurality of third conductors 123v. The height of the third conductor 123v may be greater than the height of the first conductor 121v and the height of the second conductor 122v. That is, even when the semiconductor wafer 121, the semiconductor wafer 122, and the semiconductor wafer 123 are stacked in a three-stage stack, the multi-stage conductor 121v, the conductor 122v, and the conductor 123v can be applied. Specifically, the first semiconductor wafer 121 and the third semiconductor wafer 123 may be connected to the second semiconductor wafer 122 through the first adhesive member 180a and the second adhesive member 180b, respectively. The description about the configuration and manufacturing method overlapping with the above will be omitted below.

22 is a schematic cross-sectional view illustrating another embodiment of a fan-out type semiconductor package.

Referring to the drawings, according to another exemplary embodiment of the present disclosure, in a fan-out type semiconductor package 100L, the semiconductor wafer 121, the semiconductor wafer 122, and the semiconductor wafer 123 are connected to each other in a three-stage parallel form, It is similar to the form shown in FIG. 21. However, the horizontal cross-sectional area of the second semiconductor wafer 122 may be wider than that of the first semiconductor wafer 121. In addition, the horizontal cross-sectional area of the third semiconductor wafer 123 may be wider than that of the second semiconductor wafer 122. That is, the multi-level conductor 121v, the conductor 122v, and the conductor 123v may be applied to a design in which the semiconductor wafer 121, the semiconductor wafer 122, and the semiconductor wafer 123 having different horizontal cross-sectional areas are configured so as not to match each other. The description about the configuration and manufacturing method overlapping with the above will be omitted below.

FIG. 23 is a schematic cross-sectional view illustrating another embodiment of a fan-out type semiconductor package.

Referring to the drawings, a fan-out semiconductor package 100M according to another exemplary embodiment of the present disclosure may further include a fourth semiconductor wafer 124 and a fifth semiconductor wafer 125. The fourth semiconductor wafer 124 is disposed in the second semiconductor in the through hole 110H. The fourth semiconductor wafer 124 has an active surface on which a plurality of fourth connection pads 124P are disposed and a non-active surface opposite to the active surface. The fifth semiconductor wafer 125 is disposed on the third semiconductor wafer in the through hole 110H. 123, and the fifth semiconductor wafer 125 has an active surface on which a plurality of fifth connection pads 125P are disposed and an inactive surface opposite to the active surface, which are different from the fan-out semiconductor package 100D shown in FIG. 14. The active surface of the fourth semiconductor wafer 124 may be attached to the non-active surface of the second semiconductor wafer 122, and the fourth semiconductor wafer 124 may be disposed on the second semiconductor wafer 122 so as not to match the second semiconductor wafer 122, thereby making the A fourth connection pad 124P is exposed. The active surface of the fifth semiconductor wafer 125 may be attached to the non-active surface of the third semiconductor wafer 123, and the fifth semiconductor wafer 125 may be disposed on the third semiconductor wafer 123 so as not to match the third semiconductor wafer 123, thereby making the A fifth connection pad 125P is exposed. The redistribution layer 142 of the second connection member 140 may be connected to a plurality of fourth connection pads 124P through a plurality of fourth conductors 124v, and to a plurality of fifth connection pads 125P through a plurality of fifth conductors 125v. The height of the fourth conductor 124v and the fifth conductor 125v may be greater than the height of the second conductor 122v and the height of the third conductor 123v. The first to fifth semiconductor wafers 121 to 125 may be connected to each other by a first adhesive member 180a, a second adhesive member 180b, a third adhesive member 180c, and a fourth adhesive member 180d. The description about the configuration and manufacturing method overlapping with the above will be omitted below.

FIG. 24 is a schematic cross-sectional view illustrating another embodiment of a fan-out semiconductor package.

Referring to the drawings, according to another exemplary embodiment of the present disclosure, in the fan-out type semiconductor package 100N, the plurality of second conductors 122v may include a plurality of metal pillars 122v1 connected to the plurality of second connection pads 122P and connected to the second The plurality of through holes 122v2 of the redistribution layer 142 of the connection member 140 are different from the fan-out semiconductor package 100A shown in FIG. 9. The metal pillar 122v1 may be embedded in the encapsulation body 130, and the height of the metal pillar 122v1 may be greater than the thickness of the first semiconductor wafer 121. The through hole 122v2 may penetrate the insulating layer 141 of the second connection member 140, and the height of the through hole 122v may be equal to or smaller than the height of the first conductor 121v. The metal pillar 122v1 and the through hole 122v2 may be connected to each other. The metal pillar 122v1 may be formed before the encapsulation body 130 is formed. For example, the metal pillar 122v1 may be a copper pillar, but is not limited thereto.

The description about the configuration and manufacturing method overlapping with the above will be omitted below. At the same time, the features of the above-mentioned fan-out semiconductor package 100B to 100M, that is, various stacked forms of semiconductor wafers, can also be introduced into the structure of the above-mentioned fan-out semiconductor package 100N.

FIG. 25 is a schematic cross-sectional view illustrating another embodiment of a fan-out type semiconductor package.

Referring to the drawings, according to another exemplary embodiment of the present disclosure, in the fan-out type semiconductor package 100O, the plurality of second conductors 122v may include a plurality of metal pillars 122v1 connected to a plurality of second connection pads 122P and connected to a second The plurality of through holes 122v2 of the redistribution layer 142 of the connection member 140 are similar to the fan-out type semiconductor package 100N shown in FIG. 24. However, the metal pillar 122v1 may be embedded in the encapsulation body 130, and the height of the metal pillar 122v1 may be smaller than the thickness of the first semiconductor wafer 121. Therefore, the through hole 122v2 contacting the metal pillar 122v1 may penetrate the insulating layer 141 of the second connection member 140, and may also penetrate the encapsulation body 130. That is, the height of the through hole 122v2 may be greater than the height of the first conductor 121v.

The description about the configuration and manufacturing method overlapping with the above will be omitted below. At the same time, the features of the above-mentioned fan-out semiconductor package 100B to 100M, that is, various stacked forms of semiconductor wafers, can also be introduced into the structure of the above-mentioned fan-out semiconductor package 100O.

FIG. 26 is a schematic cross-sectional view illustrating another embodiment of a fan-out type semiconductor package.

Referring to the drawings, according to another exemplary embodiment of the present disclosure, in the fan-out semiconductor package 100P, the plurality of second conductors 122v may include side surfaces connected to the plurality of second connection pads 122P and extending to the first semiconductor wafer 121. The plurality of metal pastes 122v1 ′ and the plurality of through-holes 122v2 contacting the redistribution layer 142 of the second connection member 140 are different from the fan-out semiconductor package 100A shown in FIG. 9. The plurality of metal pastes 122v1 ′ may extend to the active surface of the first semiconductor wafer 121, and may also be connected to the plurality of through holes 122v2 in the extension portion. That is, a part of the plurality of metal pastes 122 v 1 ′ may be embedded in the encapsulation body 130, and another part of the plurality of metal pastes 122 v 1 ′ may be embedded in the insulating layer 141 of the second connection member 140. The through hole 122v2 may penetrate the insulating layer 141 of the second connection member 140, and the height of the through hole 122v may be smaller than the height of the first conductor 121v. The plurality of metal pastes 122v1 ′ may be formed by attaching the first semiconductor wafer 121 and the second semiconductor wafer 122 to each other, and arranging the first semiconductor wafer in the through hole 110H of the first connection member 110 to be attached to each other. Before the 121 and the second semiconductor wafer 122, a paste is printed and sintered. The metal paste 122v1 'may include one or more metals selected from the group consisting of silver (Ag), copper (Cu), nickel (Ni), aluminum (Al), and the like, and one or more selected from The binder resin in the group consisting of a cellulose-based resin, an acrylic resin, an imide-based resin, an epoxy-based resin, and the like is not limited thereto.

The description about the configuration and manufacturing method overlapping with the above will be omitted below. At the same time, the features of the above-mentioned fan-out semiconductor package 100B to 100M, that is, various stacked forms of semiconductor wafers, can also be introduced into the structure of the above-mentioned fan-out semiconductor package 100P.

FIG. 27 is a schematic cross-sectional view illustrating another embodiment of a fan-out type semiconductor package.

Referring to the drawings, according to another exemplary embodiment of the present disclosure, in the fan-out type semiconductor package 100Q, the plurality of second conductors 122v may include a plurality of through holes 122v2 connected to the plurality of second connection pads 122P, and the through holes 122v2 The plurality of metal pastes 122 v 1 ′ extending to the side surface of the first semiconductor wafer 121 and the redistribution layer 142 connected to the second connection member 140 are similar to the fan-out type semiconductor package 100P shown in FIG. 26. However, the plurality of metal pastes 122v1 ′ may not extend to the active surface of the first semiconductor wafer 121 and may contact the interfaces of the plurality of through holes 122v2 penetrating the insulating layer 141 of the second connection member 140, the encapsulation body 130, and the second connection. Component 140. For this purpose, the line width of the metal paste 122v1 'of the fan-out semiconductor package 100Q may be larger than the line width of the metal paste 122v1' of the fan-out semiconductor package 100P. The thickness of the through hole 122v2 may be substantially equal to the thickness of the first conductor 121v.

The description about the configuration and manufacturing method overlapping with the above will be omitted below. At the same time, the features of the above-mentioned fan-out semiconductor package 100B to 100M, that is, various stacked forms of semiconductor wafers, can also be introduced into the structure of the above-mentioned fan-out semiconductor package 100Q.

FIG. 28 is a schematic cross-sectional view illustrating another embodiment of a fan-out type semiconductor package.

Referring to the drawings, according to another exemplary embodiment of the present disclosure, in a fan-out type semiconductor package 100R, the first connection member 110 may include a first insulation layer 111a, a first redistribution layer 112a, a second redistribution layer 112b, The second insulation layer 111b, the third redistribution layer 112c, the third insulation layer 111c, and the fourth redistribution layer 112d, and the first redistribution layer 112a and the second redistribution layer 112b are respectively disposed on opposite surfaces of the first insulation layer 111a On the top, a second insulating layer 111b is disposed on the first insulating layer 111a and covers the first rewiring layer 112a, a third rewiring layer 112c is disposed on the second insulating layer 111b, and a third insulating layer 111c is disposed on the first insulating layer The second redistribution layer 112b is covered on 111a, and the fourth redistribution layer 112d is disposed on the third insulating layer 111c, which is different from the fan-out semiconductor package 100A shown in FIG. 9. Since the first connection member 110 may include a large number of redistribution layers 112a, redistribution layers 112b, redistribution layers 112c, and redistribution layers 112d, the second connection member 140 may be further simplified. The first redistribution layer 112a, the second redistribution layer 112b, the third redistribution layer 112c, and the fourth redistribution layer 112d may pass through the first insulation layer 111a, the second insulation layer 111b, and the third insulation layer 111c, respectively. The first through hole 113a, the second through hole 113b, and the third through hole 113c are electrically connected to each other.

The thickness of the first insulating layer 111a may be greater than the thickness of the second insulating layer 111b and the thickness of the third insulating layer 111c. The first insulation layer 111a may be relatively thick to maintain rigidity, and the second insulation layer 111b and the third insulation layer 111c may be introduced to form a larger number of redistribution layers 112c and 112d. The first insulating layer 111a may include an insulating material different from the insulating materials of the second insulating layer 111b and the third insulating layer 111c. For example, the first insulating layer 111a may be a prepreg including, for example, a core material, an inorganic filler, and an insulating resin, and the second insulating layer 111b and the third insulating layer 111c may be Ajinomoto including an inorganic filler and an insulating resin. A film or a photosensitive insulating film. However, the materials of the first insulating layer 111a and the materials of the second insulating layer 111b and the third insulating layer 111c are not limited thereto. Similarly, the diameter of the first through hole 113a may be larger than the diameter of the second through hole 113b and the diameter of the third through hole 113c.

The thicknesses of the redistribution layer 112a, the redistribution layer 112b, the redistribution layer 112c, and the redistribution layer 112d of the first connection member 110 may be greater than the thickness of the redistribution layer 142 of the second connection member 140. Since the thickness of the first connection member 110 may be greater than or equal to the thickness of the stacked semiconductor wafer 121 and the stacked semiconductor wafer 122, a redistribution layer 112a, a redistribution layer 112b, a redistribution layer 112c, and a redistribution layer having a larger size may be formed. 112d. On the other hand, in consideration of thinness, the redistribution layer 142 of the second connection member 140 having a relatively small size may be formed.

The description about the configuration and manufacturing method overlapping with the above will be omitted below. At the same time, the features of the above-mentioned fan-out semiconductor package 100B to 100Q, that is, multiple stacked forms of semiconductor wafers and several forms of multi-level conductors, can also be introduced into the structure of the above-mentioned fan-out semiconductor package 100R .

As described above, according to the exemplary embodiments of the present disclosure, it is possible to provide a fan-out type semiconductor package. Although a plurality of semiconductor wafers are used, the package can still be thinned with improved efficiency and excellent reliability.

Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention.

100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, 100J, 100K, 100L, 100M, 100N, 100O, 100P, 100Q, 100R‧‧‧fan-out semiconductor packages

110‧‧‧first connecting member

110H‧‧‧through hole

111a‧‧‧First insulation layer

111b‧‧‧Second insulation layer

112a‧‧‧First redistribution layer

112b‧‧‧Second redistribution layer

112c‧‧‧ Third wiring layer

113a‧‧‧First through hole

113b‧‧‧Second through hole

121‧‧‧First semiconductor wafer

121P‧‧‧First connection pad

121v‧‧‧First Conductor

122‧‧‧Second semiconductor wafer

122P‧‧‧Second connection pad

122v‧‧‧Second Conductor

122v1‧‧‧ metal pillar

122v1'‧‧‧ metal paste

122v2‧‧‧through hole

122vh‧‧‧hole

123‧‧‧Third semiconductor wafer

123P‧‧‧Third connection pad

123v‧‧‧Third Conductor

124‧‧‧ Fourth semiconductor wafer

124P‧‧‧Fourth connection pad

124v‧‧‧Fourth Conductor

125‧‧‧ fifth semiconductor wafer

125P‧‧‧Fifth connection pad

125v‧‧‧ fifth conductor

130‧‧‧ Encapsulation

131‧‧‧ opening

140‧‧‧Second connection member

141‧‧‧Insulation

142‧‧‧ redistribution layer

143‧‧‧through hole

150‧‧‧ passivation layer

160‧‧‧ metal layer under bump

170‧‧‧connection terminal

180‧‧‧ Adhesive member

180a‧‧‧first adhesive member

180b‧‧‧Second adhesive member

180c‧‧‧The third adhesive member

180d‧‧‧Fourth adhesive member

210‧‧‧ Adhesive film

220‧‧‧ Removable film

1000‧‧‧ electronic device

1010‧‧‧Motherboard

1020‧‧‧Chip-related components

1030‧‧‧Network related components

1040‧‧‧Other components

1050‧‧‧ Camera Module

1060‧‧‧antenna

1070‧‧‧Display device

1080‧‧‧ battery

1090‧‧‧Signal line

1100‧‧‧Smartphone

1110‧‧‧ Motherboard

1101‧‧‧Body

1130‧‧‧ Camera Module

2100‧‧‧fan-out semiconductor package

2120‧‧‧Semiconductor wafer

2121‧‧‧ Ontology

2122‧‧‧Connecting pad

2130‧‧‧Encapsulation body

2140‧‧‧Connecting member

2141‧‧‧Insulation

2142‧‧‧ Redistribution Layer

2143‧‧‧through hole

2150‧‧‧ passivation layer

2200‧‧‧fan-in semiconductor package

2220‧‧‧Semiconductor wafer

2221‧‧‧ Ontology

2222‧‧‧Connecting pad

2223‧‧‧ passivation layer

2240‧‧‧Connecting member

2241‧‧‧Insulation

2242‧‧‧Wiring pattern

2243‧‧‧through hole

2243h‧‧‧Through Hole

2250‧‧‧ passivation layer

2251‧‧‧ opening

2260‧‧‧Under bump metal layer

2270‧‧‧Solder Ball

2280‧‧‧ underfill resin

2290‧‧‧Molding material

2301, 2302‧‧‧ interposer

2500‧‧‧ Motherboard

In order to make the above and other aspects, features, and advantages of this disclosure more comprehensible, embodiments are described below in detail with the accompanying drawings as follows. FIG. 1 is a block diagram illustrating an embodiment of an electronic device system. FIG. 2 is a schematic perspective view illustrating an embodiment of an electronic device. 3A and 3B are schematic cross-sectional views illustrating states of a fan-in semiconductor package before and after packaging. FIG. 4 is a schematic cross-sectional view illustrating a packaging process of a fan-in semiconductor package. 5 is a schematic cross-sectional view illustrating a case where a fan-in semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic device. FIG. 6 is a schematic cross-sectional view illustrating a case where a fan-in semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic device. FIG. 7 is a schematic cross-sectional view illustrating a fan-out type semiconductor package. FIG. 8 is a schematic cross-sectional view illustrating a case where a fan-out semiconductor package is mounted on a motherboard of an electronic device. FIG. 9 is a schematic cross-sectional view illustrating an embodiment of a fan-out semiconductor package. FIG. 10 is a schematic plan view of the fan-out semiconductor package of FIG. 9. 11A to 11D are schematic diagrams illustrating an embodiment of a fan-out semiconductor packaging process in FIG. 9. FIG. 12 is a schematic cross-sectional view illustrating another embodiment of a fan-out semiconductor package. 13 is a schematic cross-sectional view illustrating another embodiment of a fan-out type semiconductor package. FIG. 14 is a schematic cross-sectional view illustrating another embodiment of a fan-out semiconductor package. FIG. 15 is a schematic cross-sectional view illustrating another embodiment of a fan-out semiconductor package. FIG. 16 is a schematic cross-sectional view illustrating another embodiment of a fan-out semiconductor package. FIG. 17 is a schematic cross-sectional view illustrating another embodiment of a fan-out type semiconductor package. FIG. 18 is a schematic cross-sectional view illustrating another embodiment of a fan-out type semiconductor package. FIG. 19 is a schematic cross-sectional view illustrating another embodiment of a fan-out type semiconductor package. FIG. 20 is a schematic cross-sectional view illustrating another embodiment of a fan-out semiconductor package. FIG. 21 is a schematic cross-sectional view illustrating another embodiment of a fan-out type semiconductor package. 22 is a schematic cross-sectional view illustrating another embodiment of a fan-out type semiconductor package. FIG. 23 is a schematic cross-sectional view illustrating another embodiment of a fan-out type semiconductor package. FIG. 24 is a schematic cross-sectional view illustrating another embodiment of a fan-out semiconductor package. FIG. 25 is a schematic cross-sectional view illustrating another embodiment of a fan-out type semiconductor package. FIG. 26 is a schematic cross-sectional view illustrating another embodiment of a fan-out type semiconductor package. FIG. 27 is a schematic cross-sectional view illustrating another embodiment of a fan-out type semiconductor package. FIG. 28 is a schematic cross-sectional view illustrating another embodiment of a fan-out type semiconductor package. FIG. 29 is a schematic cross-sectional view illustrating an effect of a fan-out type semiconductor package according to an exemplary embodiment of the present disclosure. FIG. 30 is a schematic cross-sectional view illustrating another effect of a fan-out type semiconductor package according to an exemplary embodiment of the present disclosure.

Claims (20)

A fan-out semiconductor package includes: a core member having a through hole; a first semiconductor wafer disposed in the through hole and having an active surface and a non-active surface, and a plurality of first connection pads are disposed on the active surface And the non-active surface is opposite to the active surface; a second semiconductor wafer is disposed on the first semiconductor wafer in the through hole and has an active surface and a non-active surface, and the active surface is provided with A plurality of second connection pads, and the non-active surface is opposite to the active surface; an encapsulation body encapsulating at least a portion of the core member, at least a portion of the first semiconductor wafer, and the second semiconductor wafer At least a portion of; and a connecting member disposed on the core member and on the active surface of the first conductor wafer and the active surface of the second semiconductor wafer, wherein the connecting members each include an electrical A redistribution layer that is electrically connected to the plurality of first connection pads and the plurality of second connection pads, and the second semiconductor wafer is disposed on the first semiconductor wafer to communicate with the first The conductor wafers do not match, thereby exposing the plurality of second connection pads, and the redistribution layers of the connection member are connected to the plurality of first conductors through a plurality of first conductors and a plurality of second conductors, respectively. A connection pad and the plurality of second connection pads, a height of the second conductor is greater than a height of the first conductor and a thickness of the first semiconductor wafer, and the second conductor is located at a position of the core member The penetrating hole is in contact with the second connection pad, and the second conductor passes through a part of the encapsulation body. The fan-out type semiconductor package according to item 1 of the patent application scope, wherein the first conductor does not contact the encapsulation body, and the second conductor contacts the encapsulation body. The fan-out semiconductor package according to item 1 of the scope of patent application, wherein the first semiconductor wafer and the second semiconductor wafer are memory chips. The fan-out type semiconductor package according to item 1 of the patent application scope, wherein the plurality of second conductors include a plurality of metal posts connected to the plurality of second connection pads and the connection member connected to the connection member. Redistribution of a plurality of via holes of the layer, and the plurality of metal pillars and the plurality of via holes are connected to each other. The fan-out type semiconductor package according to item 4 of the scope of patent application, wherein a height of the metal pillar is greater than a thickness of the first semiconductor wafer, and a height of the through hole is equal to or less than a height of the first conductor . The fan-out type semiconductor package according to item 4 of the scope of the patent application, wherein a height of the metal pillar is smaller than a thickness of the first semiconductor wafer, and a height of the through hole is greater than a height of the first conductor. The fan-out type semiconductor package according to item 1 of the patent application scope, wherein the plurality of second conductors include a plurality of second conductors connected to the plurality of second connection pads and extending to a plurality of side surfaces of the first semiconductor wafer. A plurality of metal pastes and a plurality of through holes contacting the redistribution layer of the connection member, and the plurality of metal pastes and the plurality of through holes are connected to each other. The fan-out semiconductor package according to item 7 of the patent application scope, wherein the metal paste extends to the active surface of the first semiconductor wafer. The fan-out semiconductor package according to item 1 of the patent application scope, further comprising a third semiconductor wafer, the third semiconductor wafer being disposed on the first semiconductor wafer in the through hole and having an active surface and a non- An active surface, wherein a plurality of third connection pads are arranged on the active surface, and the non-active surface is opposite to the active surface, wherein the active surface of the third semiconductor wafer is attached to the first semiconductor The non-active surface of the wafer, and the third semiconductor wafer is disposed on the first semiconductor wafer so as not to match the first semiconductor wafer, thereby further exposing the plurality of third connection pads, the The redistribution layer of the connection member is connected to the plurality of third connection pads by a plurality of third conductors, and the second conductor and the third conductor have the same height. The fan-out semiconductor package according to item 9 of the patent application scope, further comprising: a fourth semiconductor wafer disposed on the second semiconductor wafer in the through hole and having an active surface and a non-active surface, the A plurality of fourth connection pads are disposed on the active surface, and the non-active surface is opposite to the active surface; and a fifth semiconductor wafer is disposed on the third semiconductor wafer in the through hole and has an active surface. And a non-active surface, wherein a plurality of fifth connection pads are arranged on the active surface, and the non-active surface is opposite to the active surface, wherein the active surface of the fourth semiconductor wafer is attached to the first surface; The non-active surfaces of two semiconductor wafers, and the fourth semiconductor wafer is arranged on the second semiconductor wafer so as not to match the second semiconductor wafer, so that the plurality of fourth connection pads are exposed, The active surface of the fifth semiconductor wafer is attached to the non-active surface of the third semiconductor wafer, and the fifth semiconductor wafer is disposed on the third semiconductor wafer to communicate with the first semiconductor wafer. The three semiconductor wafers do not match, thereby exposing the plurality of fifth connection pads, and the redistribution layers of the connection member are connected to the plurality of fourth conductors through a plurality of fourth conductors and a plurality of fifth conductors, respectively. Four connection pads and the plurality of fifth connection pads, and a height of the fourth conductor and a height of the fifth conductor are greater than a height of the second conductor and a height of the third conductor. The fan-out semiconductor package according to item 1 of the scope of patent application, further comprising a third semiconductor wafer, the third semiconductor wafer and the first semiconductor wafer are arranged side by side in the through hole and have an active surface and a non- An active surface, wherein a plurality of third connection pads are arranged on the active surface, and the non-active surface is opposite to the active surface, wherein the active surface of the second semiconductor wafer is attached to the first semiconductor The inactive surface of the wafer and the inactive surface of the third semiconductor wafer, and the second semiconductor wafer is disposed on the first semiconductor wafer and on the third semiconductor wafer to communicate with the first semiconductor wafer. A semiconductor wafer and the third semiconductor wafer do not match, thereby exposing the plurality of second connection pads, and the rewiring layer of the connection member is connected to the plurality of third conductors through a plurality of third conductors. Three connection pads, and the first conductor and the third conductor have the same height. The fan-out semiconductor package according to item 1 of the scope of patent application, further comprising a third semiconductor wafer, the third semiconductor wafer being disposed on the second semiconductor wafer in the through hole and having an active surface and a non- An active surface on which multiple third connection pads are arranged, and the non-active surface is opposite to the active surface, wherein the active surface of the third semiconductor wafer is attached to the second semiconductor The non-active surface of the wafer, and the third semiconductor wafer is disposed on the second semiconductor wafer so as not to match the second semiconductor wafer, thereby further exposing the plurality of third connection pads, The redistribution layer of the connection member is connected to the plurality of third connection pads by a plurality of third conductors, and a height of the third conductor is greater than a height of the first conductor and a height of the second conductor . The fan-out semiconductor package according to item 1 of the scope of patent application, further comprising a third semiconductor wafer, the third semiconductor wafer and the first semiconductor wafer are arranged side by side in the through hole and have an active surface and a non- An active surface, wherein a plurality of third connection pads are arranged on the active surface, and the non-active surface is opposite to the active surface; a fourth semiconductor wafer is disposed on the third semiconductor wafer in the through hole; And has an active surface and a non-active surface, a plurality of fourth connection pads are arranged on the active surface, and the non-active surface is opposite to the active surface, wherein the active surface of the fourth semiconductor wafer is attached To the non-active surface of the third semiconductor wafer, and the fourth semiconductor wafer is arranged on the third semiconductor wafer so as not to match the third semiconductor wafer, thereby making the plurality of fourth connections The pad is exposed, and the redistribution layer of the connection member is connected to the plurality of third connection pads and the plurality of fourth connection pads by a plurality of third conductors and a plurality of fourth conductors, respectively, and The height of the fourth conductor is greater than the height of the third conductor. The fan-out type semiconductor package according to item 1 of the scope of patent application, wherein the plurality of first connection pads and the plurality of second connection pads are opposed to each other in a horizontal direction. The fan-out semiconductor package according to item 1 of the patent application scope, wherein a horizontal cross-sectional area of the second semiconductor wafer is larger than a horizontal cross-sectional area of the first semiconductor wafer. The fan-out type semiconductor package according to item 1 of the patent application scope, wherein the core member includes a first insulating layer; a first redistribution layer that contacts the connection member and is embedded in a first surface of the first insulating layer And a second redistribution layer disposed on the second surface of the first insulating layer, and the second surface is opposite to the first surface of the first insulating layer. The fan-out type semiconductor package according to item 16 of the patent application scope, wherein the core member further includes a second insulating layer disposed on the first insulating layer and covering the second redistribution layer, and disposed on the second insulating layer. The third redistribution layer on the second insulating layer is described. The fan-out type semiconductor package according to item 1 of the patent application scope, wherein the core member includes a first insulating layer, a first redistribution layer and a second redistribution layer respectively disposed on opposite surfaces of the first insulating layer. Layer, a second insulation layer disposed on the first insulation layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulation layer. The fan-out semiconductor package according to item 18 of the scope of patent application, wherein the core component further includes a third insulating layer disposed on the first insulating layer and covering the second redistribution layer, and disposed on the first insulating layer. The fourth redistribution layer on the third insulating layer is described. The fan-out type semiconductor package according to item 1 of the patent application scope, wherein the active surface of the second semiconductor wafer is attached to the non-active surface of the first semiconductor wafer.