TWI659507B - Semiconductor package structure and manufacturing method thereof - Google Patents

Abstract

A semiconductor package structure includes a wafer, a patterned dielectric layer, a plurality of second wafers, and an underfill. The wafer includes a plurality of first wafers and a plurality of scribe lines separating the first wafers. Each first wafer has a wafer bonding area thereon. The patterned dielectric layer is disposed on the wafer and includes a plurality of openings, a plurality of dispensing grooves, and a plurality of flow channels. The openings respectively expose the wafer bonding areas. Dispensing grooves are located on the cutting lanes. The flow channels communicate with the dispensing groove and the wafer bonding area, respectively. Each wafer bonding area communicates with at least one glue groove. The second wafers are respectively disposed in the wafer bonding areas. The underfill colloid is located in the dispensing tank and the flow channel, and is filled between the first wafer and the second wafer. The invention further provides a method for manufacturing a semiconductor package structure.

Description

Semiconductor packaging structure and manufacturing method thereof

The invention relates to a semiconductor package structure and a manufacturing method, and more particularly, to a semiconductor package structure and a manufacturing method thereof for a wafer-level package.

With the demand of electronic products towards higher functionality, higher signal transmission and higher density of circuit components, as well as lighter and thinner electronic products, the current packaging technology is gradually moving towards system integration in a single package system (SIP). In the stage, multiple electronic components are stacked in the same structure. Currently used stacking technologies include, for example, stacked wafer stacking. Take wafer on wafer (Chip on Wafer, CoW) as an example. The wafer (Wafer) has a plurality of first wafers, and a plurality of second wafers are respectively docked to the first wafers of the wafer (Wafer). Then, it is filled with underfill gel and fixed, and then a plurality of semiconductor packaging structures are cut along the scribe line of the wafer. In the conventional semiconductor package structure, a certain size of dispensing area is reserved on each first wafer, and the dispenser needs to be configured with an underfill body one by one corresponding to the dispensing area of each first wafer, so that the size of the first wafer is It is difficult to reduce the size of the conventional semiconductor packaging structure, and the time required for dispensing and the amount of glue used cannot be effectively reduced, making it impossible to improve production efficiency.

The invention provides a semiconductor package structure, which can be reduced in size and has improved production efficiency.

The invention provides a method for manufacturing a semiconductor package structure, which can manufacture the above-mentioned semiconductor package structure.

A semiconductor package structure of the present invention includes a wafer, a patterned dielectric layer, a plurality of second wafers, and an underfill. The wafer includes a plurality of first wafers and a plurality of scribe lines separating the first wafers. Each first wafer has a wafer bonding area thereon. The patterned dielectric layer is disposed on the wafer. The patterned dielectric layer includes a plurality of openings, a plurality of dispensing grooves, and a plurality of flow channels. These openings respectively expose the wafer bonding areas. These dispensing slots are located on these cutting lanes. These runners respectively circulate the dispensing grooves and the wafer bonding areas. Each wafer bonding area communicates with at least one glue groove. The second wafers are respectively disposed in the wafer bonding areas. The underfill colloid is located in the dispensing grooves and the flow channels, and is filled between the first wafers and the second wafers.

A method for manufacturing a semiconductor package structure according to the present invention includes the following steps: providing a wafer including a plurality of first wafers and a plurality of scribe lines separating the first wafers, wherein each first wafer has a Wafer bonding area; forming a patterned dielectric layer on the wafer, wherein the patterned dielectric layer includes a plurality of openings, a plurality of dispensing grooves, and a plurality of flow channels, and these openings respectively expose these wafer bonding areas, and these points The glue grooves are respectively located on the dicing lanes, and the flow channels communicate with the glue grooves and the wafer bonding areas, respectively, and each wafer bonding area is correspondingly connected with at least one glue tank; a plurality of second wafers are respectively arranged to the wafer bonding areas; and An underfill is disposed to the dispensing grooves, so that a portion of the underfill flows from the dispensing grooves along the flow channels to the wafer bonding areas, and is filled between the first wafer and the second wafer. .

Based on the above, the semiconductor package structure and the manufacturing method of the semiconductor package structure of the present invention, by forming a patterned dielectric layer on a wafer, forming an opening, a dispensing groove, and a connection between the dispensing groove and the wafer bonding area, which expose the wafer bonding area. The dispensing channel is arranged on the dicing channel, so that the underfill material disposed in the dispensing channel is guided through the channel to flow into the wafer bonding area. Therefore, there is no need to reserve a dispensing area on the first wafer. In this way, the design on the surface of the first wafer can be simplified, and the size of the first wafer can be reduced, so that the size of the semiconductor package structure can be reduced. In addition, since there is no need to reserve a dispensing area on the first wafer, the design of the first wafer on the surface can be more marginal. In addition, a plurality of first wafers can share a dispensing tank for the filling process of underfill. Therefore, the number of dispensing tanks can be reduced, the number and times of dispensing can be reduced, the time required for dispensing can be shortened, and the efficiency of dispensing can be improved to improve the production efficiency of the semiconductor packaging structure.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

FIG. 1A is a schematic top view of a wafer according to an embodiment of the present invention. FIG. 1B is a schematic partial cross-sectional view of the wafer of FIG. 1A. FIG. 2, FIG. 3B, FIG. 4B and FIG. 5B are schematic partial cross-sectional views illustrating a method for manufacturing a semiconductor package structure according to an embodiment of the present invention. 3A, 4A, and 5A are schematic partial enlarged top views of the semiconductor package structure of FIGS. 3B, 4B, and 5B, respectively. Specifically, FIGS. 3B, 4B, and 5B are schematic partial cross-sectional views of the semiconductor package structure of FIG. 3A, FIG. 4A, and FIG. 5A along the section line A-A ', respectively. The manufacturing method of the semiconductor package structure 10 of this embodiment includes the following steps: First, a wafer 100 is provided. In this embodiment, the wafer 100 includes a plurality of first wafers 110 and a plurality of scribe lines 120 separating the first wafers 110. Each of the first wafers 110 has a wafer bonding area 112. It must be noted here that FIG. 1A schematically illustrates a plurality of first wafers 110 arranged in a matrix and a plurality of scribe lines 120 surrounding each first wafer 110, but the present invention is not limited thereto. In addition, FIG. 1B schematically illustrates that the two first wafers 110 are separated by a dicing track 120, but the present invention is not limited thereto. That is, the number, arrangement, and size ratio of the first wafers 110 and the scribe lines 120 are not limited to those shown in FIGS. 1A and 1B.

In detail, the first wafers 110 of the wafer 100 are separated by dicing lines 120 so that independent wafers can be formed after dicing. In other words, the dicing track 120 is located in a region between adjacent first wafers 110. In addition, the dicing track 120 surrounds the four sides of the first wafer 110 to form a grid pattern, but the invention is not limited thereto.

Next, a patterned dielectric layer 130 is formed on the wafer 100 (as shown in FIG. 3A). Please refer to FIG. 2 first. The above-mentioned step of forming the patterned dielectric layer 130 includes forming a dielectric layer 130 'on the wafer 100. The material of the dielectric layer 130 'may be a general photosensitive photoresist material, a polyimide (PI) layer or a polybenzoxazole (PBO) layer, and a photomask (not shown) (Shown) on the dielectric layer 130 ', and an exposure process is performed. The pattern of the photomask corresponds to the pattern of the wafer 100 to be exposed.

Next, a development process is performed to dissolve and remove the unexposed dielectric layer 130 'with a developing solution. Please refer to FIGS. 2, 3A, and 3B. For example, a portion of the dielectric layer 130 ′ on the wafer 100 is removed to form a plurality of openings 132, a plurality of dispensing grooves 134, and a plurality of flow channels 136. Next, the unremoved dielectric layer 130 'is cured by heating, and then the cured dielectric layer 130', the openings 132, the dispensing grooves 134, and these are cured by, for example, an oxygen plasma. Surface treatment of the flow channel 136 completes the patterned dielectric layer 130.

In this embodiment, the patterned dielectric layer 130 includes a plurality of openings 132, a plurality of dispensing grooves 134, and a plurality of flow channels 136. The openings 132 respectively expose the wafer bonding regions 112 on the first wafers 110. In addition, the dispensing grooves 134 are respectively disposed on the cutting lanes 120. The flow channels 136 respectively communicate with the dispensing grooves 134 and the wafer bonding areas 112 exposed by the openings 132, and each wafer bonding area 112 communicates with at least one dispensing groove 134.

It is worth noting that, in this embodiment, the plurality of first wafers 110 are divided into a plurality of first wafer group regions 105 by using two adjacent first wafers 110 as a group. For example, as shown in FIG. 3A, taking two first wafers 110 adjacent to each other in a first direction D1 as an example, two first wafers 110 in each first wafer group region 105 are cut by one. The lanes 120 are separated, but the invention is not limited thereto. In other embodiments, the first wafer group region 105 may also be a group of two first wafers 110 adjacent in a second direction D2. The first direction D1 is perpendicular to the second direction D2. In this embodiment, each first wafer group region 105 has a dispensing groove 134 on the dicing track 120 separating the two first wafers 110. For example, the dispensing groove 134 overlaps the dicing track 120 and is located between the two first wafers 110, but the invention is not limited thereto. The two flow channels 136 communicate with the dispensing tank 134 and the wafer bonding areas 112 on the two first wafers 110, respectively. In other words, the wafer bonding regions 112 on the two first wafers 110 of each first wafer group region 105 communicate with a dispensing groove 134. Specifically, the opening 132, the dispensing groove 134, and the flow channel 136 corresponding to the wafer bonding area 112 may communicate with each other in the first direction D1, and a groove pattern is formed on the patterned dielectric layer 130.

Please refer to FIG. 4A and FIG. 4B. Next, a plurality of second wafers 140 to the wafer bonding regions 112 on the first wafers 110 are respectively disposed. In this embodiment, the size of the first wafer 110 is larger than the size of the second wafer 140, and the second wafer 140 with a smaller size is placed on the first wafer 110 with a larger size. As shown in FIG. 4B, the second chip 140 is electrically connected to the first chip 110 with a plurality of bumps 142. Specifically, the first wafer 110 may include a plurality of first pads (not labeled) in the wafer bonding region 112, and the second wafer 140 also includes a plurality of second pads (not labeled). The plurality of bumps 142 may be disposed on the plurality of second pads and electrically connected to the first pads, so as to electrically connect the first pads and the second pads, so that the second chip 140 is electrically connected to the first chip 110. However, the present invention is not limited to this.

In this embodiment, the bump 142 may be a plating bump, a junction bump, or a solder bump, and the material thereof may include gold, silver, copper, tin, nickel, or a combination thereof. In the drawings of the present invention, the bump 142 series is taken as an example of a square shape. However, its appearance shape can not only be formed into a spherical shape, a cylindrical shape, or a dome column shape, and the material selected can also be a single metal material. Or two or more metal materials are used for electroplating, for example, a layer of tin (Solder Cap) is formed on a copper pillar (Copper Pillar), or the outer wall of the copper pillar is covered with a layer of gold.

Please refer to FIG. 5A and FIG. 5B. Finally, an underfill 150 is disposed to the dispensing tank 134, so that part of the underfill 150 flows from the dispensing tank 134 along the flow channel 136 to the connected wafer bonding area 112. . For example, the underfill 150 can be dripped into the dispensing tank 134 through the dispenser 20 (as shown in FIG. 5B), but the invention is not limited thereto. In this embodiment, in each of the first wafer group regions 105, the underfill 150 flows along the two flow channels 136 from the dispensing tank 134 to the corresponding two wafer bonding regions 112, and is filled in the corresponding first wafer bonding regions 112. The gap between the wafer 110 and the second wafer 140 covers the bumps 142 so that the underfill 150 is located in the dispensing tank 134 and the flow channel 136 and filled between the first wafer 110 and the second wafer 140. So far, the fabrication of the semiconductor package structure 10 has been substantially completed. The material of the underfill 150 is, for example, epoxy.

In this embodiment, when the underfill 150 is disposed in the dispensing tank 134 by the dispenser 20, the underfill 150 is first accommodated in the dispensing tank 134, and then flows into the opening 132 exposed along the flow channel 136. Within the wafer bonding area 112. The underfill 150 flowing into the wafer bonding area 112 can contact the tiny gap between the first wafer 110 and the second wafer 140, and is guided by the capillary force between the gaps to fill the gap between the first wafer 110 and the second wafer 140. The gap provides a fixed effect between the first wafer 110 and the second wafer 140. The underfill 150 can further cover the bumps 142 to provide cushioning, dustproof and moisture-proof protection effects, and improve the reliability of the semiconductor package structure 10.

In addition, in this embodiment, as shown in FIG. 5A, one dispensing tank 134 communicates with two wafer bonding regions 112 of two adjacent first wafers 110 through two flow channels 136, but the present invention is not limited thereto. In other words, the number of the flow channels 136 corresponds to the number of the wafer bonding areas 112 (for example, the number of the flow channels 136 is equal to the number of the wafer bonding areas 112), and the number of the flow channels 136 is greater than that of the dispensing grooves 134. Quantity. Thereby, the two adjacent first wafers 110 can be filled into the underfill 150 by a dispensing tank 134.

FIG. 6 is a schematic partial cross-sectional view of the semiconductor package structure of FIG. 5A along a section line B-B '. FIG. 7 is a schematic partial cross-sectional view of the semiconductor package structure of FIG. 5A along a section line C-C '. Please refer to FIG. 5A, FIG. 6 and FIG. 7. In this embodiment, the section lines B-B 'are parallel to the section lines C-C', and all extend along the second direction D2. FIG. 6 shows a dispensing groove 134 formed by the patterned dielectric layer 130 on the scribe line 120. FIG. 7 illustrates the flow channel 136 formed by the patterned dielectric layer 130 on the first wafer 110. In this embodiment, in the second direction D2, the maximum width of the dispensing groove 134 is greater than the maximum width of the flow channel 136. That is, in the second direction D2, the diameter of the flow channel 136 communicating with the dispensing groove 134 is smaller than the maximum width of the dispensing groove 134. However, the present invention is not limited to this. In other embodiments, in the second direction D2, the maximum width of the dispensing groove 134 may be equal to the maximum width of the flow channel 136. In other words, in the second direction D2, the width of the dispensing groove 134 may be greater than or equal to the width of the flow channel 136.

In this way, taking the width of the dispensing tank 134 larger than the width of the flow channel 136 as an example, when the underfill 150 is disposed in the wider dispensing tank 134, the smaller flow channel 136 can guide the underfill through the capillary phenomenon 150 passes from the dispensing tank 134 through the flow channel 136 and then flows into the wafer bonding area 112. Therefore, the flow velocity of the underfill colloid 150 in the flow channel 136 can be increased, increasing the efficiency of filling the underfill colloid 150 between the first wafer 110 and the second wafer 140, and shortening the time required for dispensing. It should be noted that FIG. 5A schematically illustrates that the underfill 150 is partially formed on the patterned dielectric layer 130, but the underfill 150 may not overflow onto the patterned dielectric layer 130. Compared with the conventional dispensing process of the semiconductor package structure, in this embodiment, the underfill 150 can be guided to the wafer bonding region 112 by the dispensing groove 134 and the flow channel 136 of the patterned dielectric layer 130, so It is possible to reduce the degree to which the underfill colloid 150 flows arbitrarily and overflows.

Please refer to FIG. 5A again. In this embodiment, the dispensing groove 134 may extend along the second direction D2. For example, as shown in FIG. 5A, the pattern of the dispensing groove 134 in a plan view may be, for example, a long strip, but the present invention is not limited thereto. In other embodiments, the pattern of the dispensing groove 134 in a plan view may also be circular or oval. Thereby, the extended width of the dispensing tank 134 can provide the cushioning effect of the underfill 150. In this way, when the underfill colloid 150 is disposed in the dispensing tank 134, the underfill colloid 150 can spread evenly in multiple directions, which further reduces the extent to which the underfill colloid 150 overflows the dispensing tank 134 and the flow channel 136.

In summary, the semiconductor package structure 10 of the present invention can arrange the dispensing groove 134 on the cutting path 120 through the patterned dielectric layer 130, and then guide the underfill 150 in the dispensing groove 134 through the flow channel 136. It flows into the wafer bonding area 112, so there is no need to reserve a dispensing area on the first wafer 110. As such, the design on the surface of the first wafer 110 can be simplified, and the size of the first wafer 110 can be reduced, so that the size of the semiconductor package structure 10 can be reduced. In addition, since there is no need to reserve a dispensing area on the first wafer 110, the design of the first wafer 110 on the surface can be made more marginal. In addition, since the number of the above-mentioned flow channels 136 corresponds to the number of the wafer bonding areas 112, and the number of the flow channels 136 is greater than the number of the dispensing grooves 134, that is, a plurality of first wafers 110 can share one dispensing groove 134 for bottom The filling process of the filler 150. In this way, compared with the conventional technique for reserving the dispensing area on each first wafer 110, the semiconductor package structure 10 of the present invention can reduce the number of the dispensing grooves 134 to be less than the number of the first wafer 110. Therefore, it is possible to reduce the number and quantity of dispensing, shorten the time required for dispensing, and improve the efficiency of dispensing, so as to improve the production efficiency of the semiconductor package structure 10. In addition, extending the range of the dispensing tank 134 along the extending direction of the cutting path 120 can also provide a cushioning effect for the underfill 150 to reduce the extent of overflow of the underfill 150 from the dispensing tank 134 and the flow path 136.

It must be noted here that the following embodiments follow the component numbers and parts of the previous embodiments, in which the same reference numerals are used to indicate the same or similar components. For the description of parts that omit the same technical content, refer to the foregoing embodiments. The details are not repeated in the following embodiments.

FIG. 8 is a schematic partially enlarged top view of a first wafer group region according to another embodiment of the present invention. Please refer to FIG. 5A and FIG. 8. The first wafer group region 105 a in this embodiment is similar to the first wafer group region 105 in FIG. 5A. The main difference is that in this embodiment, these first wafers 110 A plurality of first wafer group regions 105 a are divided into a group of four first wafers 110 arranged in a 2 × 2 matrix, respectively. It must be explained here that FIG. 8 of the present invention schematically illustrates that two cutting tracks 120 are located between four first wafers 110 arranged in a matrix for the sake of clarity, and the rest surrounding these four first wafers is omitted. A plurality of scribe lines 120 of the wafer 110.

In this embodiment, in each of the first wafer group regions 105a, there is a dispensing groove 134a at the intersection of the two scribe lines 120 that space the four first wafers 110 and intersect each other, and the four first wafers 110 The wafer bonding areas 112 on the top communicate with the dispensing groove 134a. Specifically, the four flow channels 136a communicate with the wafer bonding area 112 exposed by the dispensing groove 134a and the corresponding four openings 132, respectively. Therefore, when the underfill 150 is disposed in the dispensing tank 134a, the underfill 150 can flow into the wafer bonding area 112 exposed by the communicating opening 132 through the flow channel 136a, and fill the first wafer 110 and the second wafer. A gap between 140. In this way, the first chipset region 105a can obtain the same technical effects as those of the above embodiment.

In this embodiment, the dispensing groove 134 a may extend along the two cutting paths 120 that intersect each other in the first direction D1 and the second direction D2. For example, as shown in FIG. 8, the pattern of the dispensing groove 134 a in a plan view may be, for example, a cross shape, but the present invention is not limited thereto. In other embodiments, the pattern of the dispensing groove 134 a in a plan view may be circular, oval, or star-shaped. Thereby, the extending width of the dispensing groove 134 a in the first direction D1 and the second direction D2 can provide the buffering effect of the underfill 150. In this way, when the underfill colloid 150 is disposed in the dispensing tank 134a, the underfill colloid 150 can spread evenly in multiple directions, reducing the extent that the underfill colloid 150 overflows the dispensing tank 134a and the flow channel 136a.

In summary, in the semiconductor package structure and the manufacturing method of the semiconductor package structure of the present invention, the patterned dielectric layer on the wafer is used to form an opening, a glue groove, and a connection between the glue groove and the wafer to expose the wafer bonding area. The bonding channel is a flow channel, and the dispensing tank is arranged on the dicing path, so that the underfill material disposed in the dispensing tank is guided into the wafer bonding region through the flow channel. Therefore, there is no need to reserve a dispensing area on the first wafer. In this way, the design on the surface of the first wafer can be simplified, and the size of the first wafer can be reduced, so that the size of the semiconductor package structure can be reduced. In addition, since there is no need to reserve a dispensing area on the first wafer, the design of the first wafer on the surface can be more marginal. In addition, a plurality of first wafers can share a dispensing tank for the filling process of underfill. Therefore, the number of dispensing tanks can be reduced, the number and times of dispensing can be reduced, the time required for dispensing can be shortened, and the efficiency of dispensing can be improved to improve the production efficiency of the semiconductor packaging structure. In addition, because the diameter of the flow channel communicating with the dispensing tank is smaller than the maximum width of the dispensing tank, the flow channel can guide the underfill gel through the flow channel and flow into the wafer bonding area, increasing the flow rate of the underfill gel. In addition, the underfill colloid is guided from the dispensing tank to the wafer bonding area by the flow channel, which can reduce the degree of underfill colloid flowing freely and overflowing. In addition, the dispensing tank can also provide a buffer space for the underfill colloid to spread evenly.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

10‧‧‧Semiconductor Package Structure

20‧‧‧ Dispenser

100‧‧‧ wafer

105, 105a ‧‧‧ the first chipset area

110‧‧‧First Chip

112‧‧‧ Wafer Land

120‧‧‧cut road

130‧‧‧ patterned dielectric layer

130’‧‧‧ Dielectric layer

132‧‧‧ opening

134, 134a‧‧‧ Dispenser

136, 136a‧‧‧ runner

140‧‧‧Second chip

142‧‧‧ bump

150‧‧‧ underfill colloid

A-A ’, B-B’, C-C’‧‧‧ hatching

D1‧‧‧ first direction

D2‧‧‧ Second direction

FIG. 1A is a schematic top view of a wafer according to an embodiment of the present invention. FIG. 1B is a schematic partial cross-sectional view of the wafer of FIG. 1A. 2, 3B, 4B, and 5B are schematic partial cross-sectional views illustrating a method for manufacturing a semiconductor package structure according to an embodiment of the present invention. 3A, 4A, and 5A are schematic partial enlarged top views of the semiconductor package structure of FIGS. 3B, 4B, and 5B, respectively. FIG. 6 is a schematic partial cross-sectional view of the semiconductor package structure of FIG. 5A along a section line B-B '. FIG. 7 is a schematic partial cross-sectional view of the semiconductor package structure of FIG. 5A along a section line C-C '. FIG. 8 is a schematic partially enlarged top view of a first wafer group region according to another embodiment of the present invention.

Claims (10)

A semiconductor package structure includes: a wafer including a plurality of first wafers and a plurality of scribe lines separating the first wafers, wherein each of the first wafers has a wafer bonding area; a patterning A dielectric layer is disposed on the wafer. The patterned dielectric layer includes a plurality of openings, a plurality of dispensing grooves, and a plurality of flow channels. The openings respectively expose the wafer bonding areas and the dispensing grooves. They are respectively located on the dicing lanes, and the flow channels are respectively connected to the dispensing grooves and the wafer bonding areas, wherein each of the wafer bonding areas is correspondingly connected to at least one of the dispensing grooves; a plurality of second wafers are respectively disposed in the The wafer bonding areas; and an underfill, located in the dispensing grooves and the flow channels, and filled between the first wafers and the second wafers. According to the semiconductor package structure described in the first item of the patent application scope, wherein the first wafers are respectively divided into a plurality of first wafer group regions by using two adjacent first wafers as a group, A dicing path separating the two first wafers in a wafer group region has the dispensing slot, and the wafer bonding areas on the two first wafers communicate with the dispensing slot. The semiconductor package structure according to item 1 of the scope of patent application, wherein the first wafers are respectively divided into a plurality of first wafer group areas in a 2 × 2 matrix, and the first wafer groups are divided into a plurality of first wafer group regions. The first wafer group region has an adhesive dispensing groove at the intersection of the two first cutting lines that separate the four first wafers and intersect with each other, and the wafer bonding areas on the four first wafers communicate with each other. The dispensing tank. According to the semiconductor package structure described in the first item of the patent application scope, the second chips are electrically connected to the first chips with a plurality of bumps, respectively. According to the semiconductor package structure described in the first item of the patent application scope, the number of the flow channels corresponds to the number of the wafer bonding areas, and the number of the flow channels is greater than the number of the dispensing grooves. A method for manufacturing a semiconductor package structure includes: providing a wafer including a plurality of first wafers and a plurality of dicing tracks separating the first wafers, wherein each of the first wafers has a wafer bonding area; Forming a patterned dielectric layer on the wafer, wherein the patterned dielectric layer includes a plurality of openings, a plurality of dispensing grooves, and a plurality of flow channels, and the openings respectively expose the wafer bonding areas, and The dispensing grooves are respectively located on the cutting lanes, and the flow channels are respectively connected to the dispensing grooves and the wafer bonding areas, wherein each of the wafer bonding areas is correspondingly connected to at least one of the dispensing grooves, and a plurality of second grooves are respectively configured. A wafer to the wafer bonding areas; and disposing an underfill material to the dispensing grooves, so that part of the underfill material flows from the dispensing grooves along the flow channels to the connected wafer bonding areas, And filled between the first wafers and the second wafers. The method for manufacturing a semiconductor package structure according to item 6 of the scope of patent application, wherein the step of forming the patterned dielectric layer further includes: forming a dielectric layer on the wafer; and removing the wafer. Part of the dielectric layer to form the openings, the dispensing grooves, and the flow channels, wherein the first wafers are respectively divided into a plurality of first wafers by using two adjacent first wafers as a group. A wafer group area, the scribe line separating the two first wafers in each of the first wafer group areas has a dispensing slot, and the wafer bonding areas on the two first wafers communicate with the point Plastic tank. The method for manufacturing a semiconductor package structure according to item 6 of the scope of patent application, wherein the step of forming the patterned dielectric layer further includes: forming a dielectric layer on the wafer; and removing the wafer. The dielectric layer forms the openings, the dispensing grooves, and the flow channels. The first wafers are respectively divided into a set of four first wafers arranged in a 2x2 matrix. One first wafer group area, one of the dispensing grooves is provided at the intersection of two of the dicing tracks that separate the four first wafers and intersect each other in each of the first wafer group areas, and the four first The wafer bonding areas on the wafer communicate with the dispensing tank. According to the manufacturing method of the semiconductor package structure described in item 6 of the patent application scope, wherein the second chips are electrically connected to the first chips with a plurality of bumps, respectively. The method for manufacturing a semiconductor package structure according to item 6 of the scope of the patent application, wherein the number of the flow channels corresponds to the number of the wafer bonding areas, and the number of the flow channels is greater than the number of the dispensing grooves.