TWI659495B - Method for semiconductor fabrication and wafer table - Google Patents

Abstract

A semiconductor manufacturing method includes mounting a wafer on a first wafer stage. The first wafer stage includes a first set of pins that support the wafer. The first set of pins has a first distance between adjacent pins. The method further includes forming a first set of stacked pairs of marks on the wafer; and transferring the wafer to a second wafer stage. The second wafer stage includes a second set of pins having a second pitch between adjacent pins. The second set of pins can be moved individually and vertically, and the second interval is smaller than the first interval. The method further includes moving a portion of the second set of pins such that a remaining portion of the second set of pins supports the wafer, and the remaining portion has a first spacing between adjacent pins.

Description

Semiconductor manufacturing method and wafer stage

Embodiments of the present invention relate to a semiconductor manufacturing equipment and method, and more particularly, to a wafer stage and a method for using the same.

Semiconductor integrated circuits have experienced exponential growth. With the development of integrated circuit materials and design technology, multiple generations of integrated circuits have been produced, each of which has smaller and more complex circuits than the previous generation. During the development of integrated circuits, the functional density (i.e., the number of interconnected components in each chip area) generally increases, and the geometric size (i.e., the smallest component (or line) that can be produced in the process) ) Will shrink. Generally speaking, such a reduced size process can provide the benefits of increasing production efficiency and reducing manufacturing costs, but such reduced size will also increase the complexity of manufacturing and producing integrated circuits.

For example, this reduced size process has higher requirements for the flatness of the wafer surface, because relatively small non-flatness (such as dips or bumps) in the wafer surface may cause layer misalignment (layer misalignment) or even circuit defects. As wafer sizes become larger (for example, from 200 millimeters (mm) to 300 millimeters), the problem of local unevenness becomes more apparent. Existing semiconductor manufacturing equipment and methods do not seem to solve this problem satisfactorily, so Improvements need to be made in this regard.

Some embodiments of the present invention provide a semiconductor manufacturing method. The method includes mounting a wafer on a first wafer stage, wherein the first wafer stage includes a first set of pins supporting the wafer, the first set of pins having a first distance between adjacent pins . The method further includes forming a first set of stacked pairs of marks on the wafer; and transferring the wafer to a second wafer stage. The second wafer stage includes a second set of pins having a second pitch between adjacent pins. The second set of pins can be moved individually and vertically, and the second interval is smaller than the first interval. The method further includes moving a portion of the second set of pins such that a remaining portion of the second set of pins supports the wafer, and the remaining portion has a first spacing between adjacent pins.

Some embodiments of the present invention provide a semiconductor manufacturing method. The method includes supporting a wafer with a wafer stage, wherein the wafer stage includes a set of pins that are independently and vertically movable, the set of pins contacting a first side of the wafer. The method further includes detecting a non-planar area on a second side of the wafer opposite to the first side, and moving at least one of the set of pins such that the non-planar area changes on the second side of the wafer. Got flat.

Some embodiments of the present invention provide a wafer stage. The wafer stage includes a flat plate. The top surface of the plate includes a circular area larger than the size of a silicon wafer. The circular area has a plurality of holes uniformly distributed throughout the entire area of the circular area. The wafer stage further includes a plurality of wafer support pins, wherein each of the wafer support pins is vertically movable in one of the holes. The wafer stage further includes a mechanism located below the wafer support pin, and the mechanism is configured to individually vertically move each of the wafer support pins.

10‧‧‧ Wafer Stage

10’‧‧‧ Wafer stage

11‧‧‧ Tablet

12‧‧‧ top surface

13‧‧‧ Tablet

14‧‧‧hole

15‧‧‧ Suction hole

16‧‧‧pin

17‧‧‧pin

18‧‧‧ Agency

20‧‧‧ linkage device

30‧‧‧Method

32‧‧‧Operation

34‧‧‧Operation

40‧‧‧System

50‧‧‧Processing chamber

60‧‧‧Sports Agency

62‧‧‧optical sensor

70‧‧‧ wafer

72‧‧‧Top

73‧‧‧ non-flat area

74‧‧‧ underside

76‧‧‧ stacked mark

78‧‧‧ stacked mark

80‧‧‧controller

92‧‧‧Metal Features

94‧‧‧Circuit Features

96‧‧‧Circuit Features

98‧‧‧Circuit Features

100‧‧‧ Method

102, 104, 106, 108, 110‧‧‧ operation

200‧‧‧ Method

202, 204, 206, 208‧‧‧ operation

300‧‧‧ Method

302, 304, 306, 308, 310, 312, 314‧‧‧ operation

D‧‧‧ diameter

P‧‧‧ pitch, pin pitch

X‧‧‧pin pitch

Y‧‧‧Second pin pitch

FIG. 1A shows a top view of a portion of a wafer stage having a plurality of individually movable support pins according to some embodiments of the disclosure.

FIG. 1B illustrates a side cross-sectional view of a portion of the wafer stage in FIG. 1A according to some embodiments.

Figures 2A, 2B, 2C, 2D, and 2E show the movement mechanism of the individually movable support pins of the wafer stage in Figures 1A and 1B, according to some embodiments.

FIG. 3 shows an example of a semiconductor manufacturing system including the embodiment of the wafer stage in FIGS. 1A and 1B.

FIG. 4 shows a flowchart of a semiconductor manufacturing method using the embodiment of the wafer stage in FIGS. 1A and 1B according to some embodiments of the present disclosure.

Figures 5A, 5B, and 5C show some operations of the method in Figure 4 according to some embodiments.

FIG. 6 shows a flowchart of another semiconductor manufacturing method using the wafer stage in FIGS. 1A and 1B according to some embodiments of the present disclosure.

Figures 7A, 7B, 8A and 8B show some operations of the method in Figure 6 according to some embodiments.

FIG. 9 is a flowchart of still another semiconductor manufacturing method using the wafer stage in FIGS. 1A and 1B according to some embodiments of the present disclosure.

Figures 10A and 10B show some operations of the method in Figure 9 according to some embodiments.

The following disclosure provides many different embodiments or examples to Implementing the different features of the case. The following disclosure describes specific examples of each component and its arrangement to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if this disclosure describes a first feature formed on or above a second feature, it means that it may include embodiments where the first feature is in direct contact with the second feature, or it may include additional feature formation Embodiments in which the first feature and the second feature are not in direct contact between the first feature and the second feature. In addition, different examples of the following disclosures may reuse the same reference symbols and / or marks. These repetitions are for simplicity and clarity, and are not intended to limit the specific relationship between the different embodiments and / or structures discussed.

In addition, spatially related terms such as "below", "below", "lower", "above", "higher" and similar terms are used to facilitate the description of an element in the illustration The relationship between a feature or feature and another element or features. In addition to the orientations shown in the drawings, these spatially related terms are intended to encompass different orientations of the device in use or operation. The device may be turned to different orientations (rotated 90 degrees or other orientations), and the spatially related words used herein can be interpreted the same way.

This disclosure mainly relates to semiconductor manufacturing equipment and methods, and more particularly to wafer stages and methods of using the same. In the embodiment of the present disclosure, the wafer stage is designed to have a plurality of wafer support pins that can be moved individually (independent of each other) and vertically (perpendicular to the surface of the wafer supported thereon). These movable support pins are evenly distributed in an area larger (or slightly larger) than the wafer on the wafer stage. The wafer can have 200 mm, 300 mm, 450 mm, or other suitable sizes, and the wafer stage can be customized for such a size, or compatible with many of these sizes. Each wafer support pin can be discontinuously stepped Adjust or continuous height adjustment to move up and down. In an example of a manufacturing method, a wafer is supported on a wafer stage by a wafer support pin, a non-flatness in a wafer surface opposite to the wafer support pin is detected, and a The height of one or more wafer support pins makes the amplitude of non-flatness decrease or disappear completely. The unevenness in the wafer surface may be caused by particle adsorption or uneven material distribution in the layers of the wafer. Theoretically, wafers are not completely rigid and have some flexibility. By using pins with various heights to support the wafer, the surface of the wafer on the opposite side can be adjusted to offset surface unevenness. Many other semiconductor manufacturing methods according to this disclosure can benefit from this innovative wafer stage. Various embodiments of the wafer stage and methods of using the wafer stage are discussed further below.

FIG. 1A shows a top view of a wafer stage 10 (on the left side of the figure) according to some embodiments of the present disclosure. FIG. 1A also shows an enlarged view of a portion of the wafer stage 10 (on the right side of the figure). FIG. 1B shows a cross-sectional view of a portion of a wafer stage 10 according to some embodiments. Please refer to FIGS. 1A and 1B together. The wafer stage 10 includes a flat plate 11 which can be made of a rigid material, such as SiC, SiC, ceramic silicon carbide, or non-oxidized silicon. Ceramic silicon carbide (SiSiC or SSiC). The upper surface 12 of the flat plate 11 includes a circular area (that is, the left circular area or part thereof in FIG. 1A) larger than the size of a wafer to be supported by the wafer stage 10. For example, the size of the wafer may be 200 mm, 300 mm, or 450 mm in diameter, or other suitable wafer sizes, and the aforementioned circular region has a slightly larger diameter.

The wafer stage 10 includes an array of holes 14 uniformly distributed throughout the entire area of the circular area and passing through the plate 11. Within each hole 14, there is a A pin (or support pin or wafer support pin or dynamic support pin) 16 that moves up or down (out of or into the paper surface of FIG. 1A, or along the vertical direction Z in FIG. 1B). The pins 16 form an array uniformly distributed over the entire area of the circular area. Each pin 16 is made of a rigid material, such as silicon carbide (SiC) including crystalline or polycrystalline silicon carbide, ceramic silicon carbide, or non-oxide ceramic silicon carbide (SiSiC or SSiC). In one embodiment, the flat plate 11 and the pin 16 are made of the same material. In an alternative embodiment, the plate 11 and the pin 16 are made of different materials. In this embodiment, the pins 16 have the same size, and their diameter D may be in the range of less than 1 micrometer to a few millimeters (in different embodiments). The pins 16 are separated by a pitch P, which can range from slightly larger than the diameter D to several times larger than the diameter D.

Please continue to refer to FIG. 1A, the wafer stage 10 further includes a plurality of suction holes 15 passing through the flat plate 11. In this embodiment, the number of the suction holes 15 is much smaller than the number of the pins 16. The suction hole 15 is provided between a selected position of the wafer stage 10 and the hole 14. Further, in this embodiment, the size of the suction hole 15 is smaller than that of the hole 14. The suction hole 15 is used by a vacuum suction system, and can generate a downward suction force on the wafer supported by the pin 16. The vacuum suction system and the pin 16 together hold the wafer stably in place.

Referring to FIG. 1B, the wafer stage 10 further includes another flat plate 13 below the flat plate 11. In some embodiments, the plates 11 and 13 may be connected or even made into a structure, or the plates 11 and 13 are separate plates. The plate 13 includes a mechanism 18 below each pin 16. The mechanism 18 and the corresponding pin 16 are connected by a linkage 20. In some embodiments, the mechanism 18 is directly connected to the corresponding pin 16 without passing through the linkage 20. The mechanism 18 is operable to produce a vertical movement, which is then transmitted to the pin 16 directly or through the linkage 20. In one embodiment, the machine The structure 18 includes a Micro Electro Mechanical System (MEMS) structure capable of generating vertical movement. For example, the MEMS structure may be a MEMS electric actuator, a MEMS magnetic actuator, a MEMS thermal actuator, or other types of MEMS structures. The wafer stage 10 may include a controller (not shown) operable to control various mechanisms 18 based on an input control file to raise or lower the pins 16.

Figures 2A to 2E show the movement mechanism of a separately movable pin 16 driven by the mechanism 18, which changes its volume based on the voltage or current applied to it. FIG. 2A shows a flowchart of a method 30 for adjusting the height of the pin 16. The method 30 includes an operation 32 of applying a voltage or current to the mechanism 18 to cause the mechanism 18 and the pin 16 to move. The method 30 also includes an operation 34 that detects flatness (or non-flatness) in the surface of the wafer supported by the pins 16. The method 30 further includes a feedback loop from operation 34 to operation 32. Figures 2B to 2E show the movement of the pin 16 due to a change in the volume of the mechanism 18. Method 30 is discussed further below in conjunction with Figures 2B to 2E.

In operation 32, a voltage or current is applied to the mechanism 18 (for example, through a controller not shown) to increase its volume from the state in FIG. 2B to the state in FIG. 2C, thus causing the pin 16 to be vertically upward mobile. In operation 34, the flatness of the wafer surface supported by the wafer stage 10 is detected (eg, by an optical sensor or a leveling sensor). The surface unevenness is then fed back to operation 32 to adjust (increase or decrease) the voltage or current applied to the mechanism 18. The adjustment of the voltage or current causes the volume of the mechanism 18 to increase (as shown in FIG. 2D) or decrease (as shown in FIG. 2E). In one embodiment, increasing the voltage or current applied to the mechanism 18 may increase its volume, and decreasing the voltage or current applied to the mechanism 18 may decrease its volume. In an alternative embodiment, the voltage or electricity applied to the mechanism 18 is increased Flow can reduce its volume, and reducing the voltage or current applied to the mechanism 18 can increase its volume. The wafer stage 10 may utilize any embodiment to cause the pins 16 to move vertically.

FIG. 3 shows a wafer manufacturing system 40 using a wafer stage 10 with support pins 16 that can be individually and vertically moved, according to some embodiments. Referring to FIG. 3, the system 40 includes a processing chamber 50, a wafer stage 10 having a pin 16 in the processing chamber 50, a moving mechanism 60 coupled to the wafer stage 10, and one or more optical sensors.器 62。 62. FIG. 3 further shows a wafer 70 supported by the pins 16 in the processing chamber 50. The wafer 70 includes a top surface 72 and a bottom surface 74, wherein the bottom surface 74 is in contact with the pin 16. The system 40 may further include a vacuum suction system (not shown), which generates a downward suction force on the bottom surface 74 through the suction holes 15 (see FIG. 1A) on the wafer stage 10. The downward suction force and the upward support force of the pin 16 together hold the wafer 70 in a proper position.

The processing chamber 50 may be used to perform one or more photolithography operations on the wafer 70, such as photoresist coating, photoresist exposure, material deposition, material etching, epitaxy, and other suitable operations. The movement mechanism 60 is operable to drive the wafer stage 10 and the wafer 70 fixed thereon in various movement modes, such as rotation, lateral (or horizontal) movement, and / or vertical movement. The optical sensor 62 may be a level sensor used in a conventional light lithography scanner. In the present embodiment, the optical sensor 62 is operable to detect the flatness (or non-flatness) of the top surface 72. The system 40 further includes a controller 80. In one embodiment, the controller 80 is operable to communicate with the optical sensor 62 to obtain data about the flatness of the top surface 72. The controller 80 is further operable to communicate with the wafer stage 10 to adjust the height of each independent pin 16. In an embodiment, the system 40 may execute the method 30 in FIG. 2A, and the feedback loop in FIG. 2A may be implemented by the controller 80. In one embodiment, the control The controller 80 can be implemented as a computer with software running on it. For example, the controller 80 may include a microprocessor, input devices, storage devices, and communication devices interconnected through one or more buses, and may execute software instructions to obtain data from the optical sensor 62 and send data to The wafer stage 10 issues a command or directly controls the pins 16 on the wafer stage 10.

FIG. 4 shows a flowchart of a method 100 for manufacturing one or more wafers according to some embodiments of the disclosure. The method 100 utilizes the capabilities of the wafer stage 100 to improve wafer yield. Briefly, the method 100 includes an operation 102 of mounting a wafer on a first wafer stage having a first pin pitch, an operation 104 of forming a first set of overlay marks on the wafer. Operation 106 of transferring a wafer to a second wafer stage having a plurality of dynamic support pins, operation 108 of moving a dynamic support pin on the second wafer stage to match the first pin pitch, and forming A second set of stacked operations 110 are marked on the wafer. The method 100 is only an example, and it is not intended to limit the disclosure to what is explicitly recorded in the scope of the patent application. Additional operations may be provided before, during, and after the method 100, and for the methods in different embodiments, some of the operations described may be replaced, eliminated, or moved. The method 100 is discussed further below in conjunction with Figures 5A-5C.

At operation 102, the method 100 (FIG. 4) mounts a wafer 70 on a wafer stage 10 ', as shown in FIG. 5A. The wafer stage 10 'can be housed in a processing chamber (not shown). The wafer stage 10 'includes a plurality of wafer support pins 17 having a pin pitch X. In one embodiment, the wafer support pin 17 is fixed (e.g., fixedly mounted) on the wafer stage 10 '. In other words, the wafer support pin 17 is immovable. In an alternative embodiment, similar to the wafer support pins 16 on the wafer stage 10, the wafer support The support pins 17 are vertically movable on the wafer stage 10 '. The wafer 70 may have a diameter of 200 mm, 300 mm, 450 mm, or other suitable sizes. The wafer 70 includes one or more layers of material or composition. In some embodiments, the wafer 70 includes a base semiconductor such as silicon or germanium, a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, gallium nitride, and indium phosphide, or silicon germanium carbide ( alloy semiconductor of silicon germanium carbide), gallium arsenic phosphide and gallium indium phosphide. The wafer 70 may also include non-semiconductor materials, including soda-lime glass, fused silica, fused quartz, calcium fluoride (CaF2), metal layers, and / or other The right material. The wafer 70 may include a silicon on insulator (SOI) substrate subjected to strain and / or stress to improve performance, including an epitaxial region, an isolation region, a doped region, and / or other suitable regions. Features and layers.

The wafer 70 has a top surface 72 and a bottom surface 74, wherein the pins 17 contact the bottom surface 74. The wafer 70 is not completely rigid and has a certain flexibility. As shown in FIG. 5A, once supported by the pin 17, the top surface 72 will show some protrusions and depressions (or ridges and valleys) due to the upward support of the pin 17 and the influence of vacuum suction pull down. In particular, the protrusions are located directly above the pins 17 and the depressions are located above the space between the pins 17.

At operation 104, the method 100 (FIG. 4) forms a set of overlapping marks 76 in one or more material layers of the wafer 70, which may include various photolithographic processes such as photoresist coating, photoresist exposure, Photoresist development, material deposition, etching, and planarization. The overlay mark 76 is used to measure overlay deviations between two layers on the wafer 70. The overlay mark 76 may be provided in a unit area of the wafer 70 In a cell region or a scribe line region. The stacked mark 76 may be reflective or diffractive, and may have any suitable size, shape, and configuration, such as box-in-box, frame-in-frame, and box-in-box. Cross-in-box, box-in-bar, bar-in-bar, and diffraction gratings. In this embodiment, each stack of pairs of marks 76 is formed directly above a pin 17, and its geometric centerline is aligned with the geometric centerline of the corresponding pin 17, as shown in FIG. 5A. It should be noted that, for simplicity, FIG. 5A only shows the overlay mark 76, and does not show other features (such as doped regions, gates, contacts, Interconnect, isolation, etc.). Positioning the overlay mark 76 directly above the pin 17 is important for reducing inter-layer misalignment and reducing the number of wafer scraps due to excessive overlay errors.

At operation 106, the method 100 (FIG. 4) transfers the wafer 70 to a second wafer stage with dynamic support pins, which may be an embodiment of the wafer stage 10 as shown in FIG. 5B. It is to be noted that the second wafer stage (hereinafter referred to as the wafer stage 10) can be accommodated in a processing chamber different from the wafer stage 10 '. Two processing chambers can be used to deposit different layers onto the wafer 70. The dynamic support pins 16 of the wafer stage 10 have a second pin pitch Y smaller than the pin pitch X. Because wafer stages 10 'and 10 have different pin pitches, the top surface 72 will show different ridges and valleys when supported by wafer stage 10 than when supported by wafer stage 10'. In particular, the overlay mark 76 formed to be aligned with the pin 17 may not be aligned with the pin 16. If the pin 16 cannot be moved dynamically, this misalignment between the superimposed mark 76 and the pin 16 will cause subsequent superimposed marks to deviate from the superimposed mark 76. In addition, the misalignment between the overlay mark 76 and the pin 16 will also cause the overlay mark 76 to tilt, making it difficult for subsequent overlay marks to align. The mark 76 is aligned. However, the dynamically movable pin 17 according to the present disclosure can solve the above problems, as discussed below.

At operation 108, the method 100 (FIG. 4) moves the individually movable pins 16 so that the pin pitch on the wafer stage 10 substantially matches the pin pitch X, as shown in FIG. 5C. Referring to FIG. 5C, the method 100 reduces a subset of the pins 16 so that a remaining portion of the pins 16 supporting the wafer 70 has a pin pitch X between adjacent pins. In one embodiment, the method 100 uses pin maps of wafer stages 10 'and 10 to determine which pins 16 are to be lowered. In another embodiment, the method 100 monitors one or more overlapping marks 76 and simultaneously adjusts the pin 16 so that the shape and orientation of the one or more overlapping marks 76 match a predetermined shape and orientation. In one embodiment, the method 100 uses a controller built into the wafer stage 10 or an external controller such as the controller 80 (FIG. 3) to move the dynamic support pin 16.

At operation 110, the method 100 (FIG. 4) forms a second set of stacked marks 78 in one or more material layers of the wafer 70, which may include various photolithographic processes, such as photoresist coating, photoresist Exposure, photoresist development, material deposition, etching, and planarization. The overlay mark 78 is provided directly above the overlay mark 76. In this embodiment, the stacking marks 76 and 78 are vertically aligned with the pins 16, which is beneficial to reducing stacking errors and improving wafer yield. As can be seen from the above description, one advantage of the wafer stage 10 is that it can be adapted to work with other wafer stages in order to reduce stacking errors when the wafer is transferred to the wafer stage 10.

FIG. 6 shows a flowchart of a method 200 for manufacturing one or more wafers according to some embodiments of the present disclosure, and shows another application of the wafer stage 10 for improving wafer yield. Briefly, the method 200 includes an operation 202 of supporting a wafer with a wafer stage having a plurality of dynamic support pins, and inspecting wafers on the wafer. An operation 204 of an uneven area (or unevenness), an operation 206 of moving a dynamic support pin on a wafer stage to eliminate or reduce unevenness, and an operation 208 of forming a layer on a wafer. The method 200 is only an example, and is not intended to limit the disclosure to what is explicitly recorded in the scope of the patent application. Additional operations may be provided before, during, and after method 200, and for the methods in different embodiments, some of the operations described may be replaced, eliminated, or moved. The method 200 will be further discussed below in conjunction with FIGS. 7A-7B and 8A-8B.

At operation 202, method 200 (FIG. 6) supports a wafer 70 with wafer stage 10 having pins 16 that can be moved individually and vertically, as shown in FIGS. 7A and 8A. The wafer stage 10 and the wafer 70 can be housed in a processing chamber such as a processing chamber 50 (FIG. 3). The wafer 70 has a top surface 72 and a bottom surface 74. The pin 16 contacts the bottom surface 74. In this embodiment, once supported by the wafer stage 10, the top surface 72 will exhibit a certain degree of unevenness in some uneven regions 73 of the wafer 70. In one embodiment, the unevenness may be caused by pollution, such as foreign particles or chemical residues adsorbed on the bottom surface 74 or on the wafer stage 10 as shown in FIG. 7A. In another embodiment, the unevenness may be caused by uneven thicknesses in various layers of the wafer as shown in FIG. 8A. For example, when material is deposited on the wafer 70, the material distribution may not be ideally uniform, resulting in bumps and / or depressions in the top surface 72. If not properly handled, the unevenness may cause subsequent layers to be misaligned or subsequent features to be tilted, resulting in manufacturing defects. As shown in FIGS. 7A and 8A, the unevenness may cause the overlay mark 76 to be inclined or skewed, making it difficult for subsequent layers to align with the current layer.

At operation 204, the method 200 (FIG. 6) detects a non-flat area 73 on the top surface 72, which may be performed by an optical sensor such as an optical sensor 62 (FIG. 3) or Level sensor to perform. In one embodiment, the method 200 can scan the entire top surface 72 and monitor the coordinates, footprint sizes, and amplitude of the bumps and depressions on the top surface 72. The detected unevenness may be transmitted to a controller or a computer such as the controller 80 (FIG. 3) in a suitable file format, such as a text format or an image format.

At operation 206, the method 200 (FIG. 6) moves the pin 16 based on the detected unevenness so that the magnitude of the unevenness on the top surface 72 can be reduced or completely eliminated. For example, if the unevenness is a protrusion in the top surface 72, the method 200 can reduce the height of one or more pins 16 below the protrusion, so that the protrusion disappears on the top surface 72, as shown in Figures 7B and 8B As shown. In another example, if the unevenness is a depression in the top surface 72, the method 200 may increase the height of one or more pins 16 below the depression. In one embodiment, the method 200 may perform operations 204 and 206 in an iterative manner. For example, after operation 206 has completed one round of pin movement based on the previously measured surface unevenness, method 200 may return to operation 204 and perform another unevenness measurement or detection on top surface 72. The newly measured unevenness may then be used to further adjust the pin 16 in operation 206. In some embodiments, the method 200 may repeatedly perform operations 204 and 206 repeatedly until the unevenness in the top surface 72 is less than a threshold.

At operation 208, the method 200 (FIG. 6) forms a layer on the wafer 70, particularly on the top surface 72. For example, operation 208 may be performed in the processing chamber 50 (FIG. 3). Since the top surface 72 has been flattened by operations 204 and 206, this layer is easier to align with the previous layer (that is, the overlapping marks in the two layers can be aligned), which is helpful to improve the yield of the wafer 70 . The method 20 may repeat operations 204, 206, and 208 to form multiple layers on the wafer 70.

FIG. 9 shows a flowchart of another method 300 using an innovative wafer stage with dynamically adjustable pins according to the present disclosure. Unlike method 200, which measures unevenness on the wafer and adjusts the pins to offset the measured unevenness, method 300 moves the pin first based on features in the layer to be formed on the wafer. In other words, the method 300 generates a one-pin moving scheme corresponding to the next layer to be formed on the wafer, and moves the pins accordingly. In some embodiments, the methods 200 and 300 may be implemented jointly by the same system to improve wafer yield. The method 300 includes operations 302, 304, 306, 308, 310, 312, and 314, discussed further below. The method 300 is only an example, and it is not intended to limit the disclosure to what is explicitly recorded in the scope of the patent application. Additional operations may be provided before, during, and after the method 300, and for the methods in different embodiments, some of the operations described may be replaced, eliminated, or moved.

At operation 302, the method 300 (FIG. 9) provides a wafer stage having a plurality of dynamically supported pins, such as a wafer stage 10 having dynamically adjustable pins 16. The wafer stage 10 may be housed in a processing chamber, such as the processing chamber 50 (FIG. 3). In operation 304, the method 300 obtains data of a layer to be formed on the wafer, which may be implemented by a controller or a computer such as the controller 80 (FIG. 3).

In operation 306, the method 300 identifies features in this layer, which may benefit from the relatively strong support of the wafer stage compared to other features in the same layer. For example, the identified features may have a lower tolerance for overlapping errors than other features in the same layer. For example, the identified features may include vertical metal features (such as metal feature 92 in Figures 10A and 10B), which may tend to collapse or tilt without strong support provided directly below. For another example, the identified features may include overlay marks (such as overlay marks in Figures 10A and 10B). 76). As described above, misalignment (stacking error) between the overlay marks may reduce wafer yield. For yet another example, the identified features may include relatively heavy circuit features (eg, circuit features 94 in FIG. 10A and circuit features 96 and 98 in FIG. 10B). In one embodiment, operation 306 may be implemented by a controller or computer such as controller 80 (FIG. 3).

At operation 308, the method 300 (FIG. 9) determines a scheme for moving the pins 16 on the wafer stage 10 (“pin moving scheme”). In an embodiment, a pin movement scheme is generated based on the coordinates of the identified features, the size of the pins 16, the pin pitch on the wafer stage 10, and / or other information. The pin movement scheme states that those pins 16 will be raised and those pins 16 will be lowered. In one embodiment, operation 308 may be implemented by a controller or computer such as controller 80 (FIG. 3).

In operation 310, the method 300 (FIG. 9) moves the pin 16 based on a pin movement scheme, which can be implemented by a controller or a computer, such as the controller 80 (FIG. 3) or a controller built into the wafer stage 10. (Not shown).

At operation 312, the method 300 (FIG. 9) mounts a wafer (wafer 70) on the wafer stage 10 as shown in FIGS. 10A and 10B, where a subset of the pins 16 may be at operation 310 Has been raised, and another subset of the pins 16 may have been lowered at operation 310.

At operation 314, the method 300 (FIG. 9) forms the layer on the wafer 70, as shown in FIGS. 10A and 10B, where the features identified in operation 306 are formed directly in the pin 16 and are elevated. Above the subset. Since these features are directly supported by the pins 16, the wafer 70 can obtain stable support of the wafer stage 10 during various processes of forming the features.

One or more embodiments of the present disclosure can be provided in wafer manufacturing Many benefits, but not as a limitation. In one embodiment, the wafer stage is designed to have a plurality of individually and vertically movable pins uniformly distributed over an entire area equal to or larger than a wafer supported by the wafer stage. The movable pins can be dynamically adjusted to match the support pin pitch of different wafer stages to offset surface unevenness in the wafer and selectively support certain features in the wafer, including overlapping marks. Using the wafer stage disclosed in this disclosure, a semiconductor manufacturer can ensure a flat surface in the wafer, thereby reducing the misalignment between layers sequentially formed on the wafer.

In an exemplary embodiment, the present disclosure relates to a semiconductor manufacturing method. The method includes mounting a wafer on a first wafer stage, wherein the first wafer stage includes a first set of pins supporting the wafer, the first set of pins having a first distance between adjacent pins . The method further includes forming a first set of stacked pairs of marks on the wafer; and transferring the wafer to a second wafer stage. The second wafer stage includes a second set of pins having a second pitch between adjacent pins. The second set of pins can be moved individually and vertically, and the second interval is smaller than the first interval. The method further includes moving a portion of the second set of pins such that a remaining portion of the second set of pins supports the wafer, and the remaining portion has a first spacing between adjacent pins.

In one embodiment of the method, each of the first set of overlapping marks is formed directly above one of the first set of pins. In another embodiment, each of the first set of overlapping marks is formed directly above one of the remaining portions of the second set of pins.

In an embodiment, the method further includes forming a second set of stacked mark on the wafer, wherein each of the second set of stacked mark is directly formed on each of the first set of stacked mark. Above. In another embodiment of the method Each of the first sets of pins is fixedly mounted on the first wafer stage. In yet another embodiment of the method, a portion of the first set of pins is movable on a first wafer stage.

In another exemplary embodiment, the present disclosure relates to a semiconductor manufacturing method. The method includes supporting a wafer with a wafer stage, wherein the wafer stage includes a set of pins that are independently and vertically movable, the set of pins contacting a first side of the wafer. The method further includes detecting a non-planar area on a second side of the wafer opposite to the first side, and moving at least one of the set of pins such that the non-planar area changes on the second side of the wafer. Got flat.

In one embodiment of the method, the non-planar area is a depression on the second side of the wafer. In a further embodiment, the moving includes increasing the height of the at least one of the pins in the set below the depression.

In another embodiment of the method, the non-planar area is a protrusion on a second side of the wafer. In a further embodiment, the moving includes lowering the height of the at least one of the pins in the set below the protrusion.

In an embodiment of the method, the detecting is performed using one or more optical level sensors. In another embodiment, the moving includes adjusting a height of the at least one of the pins, measuring a flatness of a non-flat area on a second side of the wafer, and readjusting the The height of the at least one of the marketing pins.

In one embodiment of the method, the non-planar area is caused by one or more foreign particles on the first side of the wafer. In another embodiment, the uneven regions are caused by uneven thickness of one or more layers deposited on the wafer.

In another exemplary embodiment, the present disclosure relates to a manufacturing crystal Round approach. The method includes providing a wafer stage, wherein the wafer stage includes a set of pins that can be moved individually and vertically; obtaining information about a layer to be formed on a first side of a wafer; identifying the layer from the data A set of features in which can benefit from the stronger support of the wafer stage compared to other features; based on at least the information and the set of features, a pin moving scheme for moving the set of pins is determined, so that the The set of features will be directly above a first subset of the pins; move the set of pins based on the pin movement scheme; mount the wafer on a wafer stage, where the first subset of the pins are in contact with the first side A second side of the opposite wafer; and forming the layer on the first side of the wafer.

In one embodiment of the method, the set of features has a lower tolerance for overlapping errors than other features. In another embodiment, the set of features includes vertical metal features. In an embodiment, the determining includes calculating coordinates on a wafer stage that is mapped to a geometric center of each of the set of features.

In an embodiment of the method, the moving includes reducing a height of a second subset of the pins, wherein the first subset and the second subset are complementary. In another embodiment, the moving includes increasing the height of the first subset of the pins above the height of other pins in the set of pins.

In another exemplary embodiment, the present disclosure relates to a wafer stage. The wafer stage includes a flat plate. The top surface of the plate includes a circular area larger than the size of a silicon wafer. The circular area has a plurality of holes uniformly distributed throughout the entire area of the circular area. The wafer stage further includes a plurality of wafer support pins, wherein each of the wafer support pins is vertically movable in one of the holes. The wafer stage further includes a mechanism located below the wafer support pin, and the mechanism is configured to separately Move each of the wafer support pins vertically.

In one embodiment of the wafer stage, the mechanism includes a plurality of MEMS (micro-electro-mechanical systems) structures, wherein each of the MEMS structures is located under one of the wafer support pins and is configured to cause a wafer The vertical movement of the one of the support pins. In a further embodiment, each of the MEMS structures is configured to change its volume based on a voltage applied thereto, and the change in its volume causes a vertical movement of a corresponding wafer support pin. In another further embodiment, each of the MEMS structures includes a MEMS magnetic actuator. In addition, each of the wafer support pins may include silicon carbide.

In another exemplary embodiment, the present disclosure relates to a wafer manufacturing system. The system includes a wafer stage to support a wafer thereon. The wafer stage includes a set of wafer support pins that can be moved individually and vertically, and the set of wafer support pins contacts a first surface of the wafer. The system further includes one or more level sensors for detecting unevenness of a second surface of the wafer opposite to the first surface; and a controller based on the one or more levels. A measurement result of the position sensor adjusts the height of the set of wafer support pins, so that the unevenness of the second surface of the wafer disappears due to the adjustment. In an embodiment of the system, the controller is further configured to adjust the height of the set of wafer support pins based on the positions of the overlapping marks on the wafer.

In yet another exemplary embodiment, the present disclosure relates to a wafer manufacturing system. The system includes a wafer stage to support a wafer thereon. The wafer stage includes a set of wafer support pins that can be moved individually and vertically, and the set of wafer support pins contacts a first surface of the wafer. The system further includes a controller for reading a lower surface to be formed on a second surface of the wafer opposite to the first surface. One layer of data identifies the set of features in the next layer, which can benefit from the stronger support of the wafer stage compared to other features, and adjust the height of the set of wafer support pins so that when formed Each of these will be directly above one of the wafer support pins. The system further includes a processing chamber for forming the next layer on the second surface of the wafer. In one embodiment of the system, the wafer stage provides a circular area larger than the size of the wafer, wherein the wafer support pins are evenly placed within the circular area.

The foregoing text summarizes the features of many embodiments so that those having ordinary skill in the art can better understand the disclosure from various aspects. Those with ordinary knowledge in the technical field should understand that other processes and structures can be easily designed or modified based on this disclosure to achieve the same purpose and / or achieve the same as the embodiments and the like described herein. Advantages. Those of ordinary skill in the art should also understand that these equivalent structures do not depart from the spirit and scope of the invention disclosed herein. Without departing from the spirit and scope of the disclosure, various changes, substitutions, or modifications can be made to the disclosure.

Claims (10)

A semiconductor manufacturing method includes: mounting a wafer on a first wafer stage, wherein the first wafer stage includes a first set of pins supporting the wafer, and the first set of pins is adjacent to the pins. There is a first gap between them; forming a first set of stacked marks on the wafer; transferring the wafer to a second wafer stage, wherein the second wafer stage includes A second set of pins with a second pitch, wherein the second set of pins can be moved individually and vertically, and the second pitch is smaller than the first pitch; and moving a portion of the second set of pins such that the second set of pins A remaining portion of the wafer supports the wafer, and the remaining portion has the first distance between adjacent pins. The semiconductor manufacturing method as described in claim 1, wherein each of the first set of stacked marks is formed directly above one of the first set of pins or directly on the second set of pins. Above one of the remaining parts. The semiconductor manufacturing method according to item 1 of the patent application scope, further comprising: forming a second set of stacked pair marks on the wafer, wherein each of the second set of stacked pair marks is directly formed on the first Stack above each of the pair marks. A semiconductor manufacturing method includes: supporting a wafer having a set of overlapping marks by a wafer stage, wherein the wafer stage includes a set of pins that can be independently and vertically moved, and the set of pins contacts a first stage of the wafer; One side; detecting a non-planar area on a second side of the wafer opposite to the first side; and moving at least one of the pins so that the non-flat area is on the second side of the wafer The top is flattened and the set of pins is aligned with the set of stacked pairs of marks. The semiconductor manufacturing method according to item 4 of the scope of patent application, wherein the non-planar region is a depression or a protrusion on the second side of the wafer. The semiconductor manufacturing method according to item 5 of the scope of patent application, wherein the moving includes increasing a height of the at least one of the set of pins below the recess or lowering the set of the set of pins that are below the protrusion. A height of at least one of them. The semiconductor manufacturing method according to item 4 of the scope of patent application, wherein the moving includes: adjusting a height of the at least one of the pins; measuring a flatness of the non-planar area on the second side of the wafer And readjust the height of the at least one of the pins according to a result of the measurement. A wafer stage includes a flat plate, wherein a top surface of the flat plate includes a circular area larger than a size of a wafer, and the circular area has a plurality of uniformly distributed in the entire area of the circular area. Holes; a plurality of wafer support pins, wherein each of the wafer support pins can be vertically moved in one of the holes; and a mechanism located below the wafer support pins and configured For individually vertically moving each of the wafer support pins, so that a part of the wafer support pins supports the wafer, and the part of the wafer support pins and the stacked mark pairs of the wafer quasi. The wafer stage according to item 8 of the patent application scope, wherein the mechanism includes a plurality of MEMS structures, wherein each of the MEMS structures is located below one of the wafer support pins And configured to cause vertical movement of the one of the wafer support pins. The wafer stage according to item 9 of the scope of patent application, wherein each of the MEMS structures is configured to change its volume based on a voltage applied thereto, and the change in its volume causes a corresponding crystal Vertical movement of round support pins.