TWI657643B - Power stage circuit with current charge reduction - Google Patents

Abstract

The invention provides a power stage circuit comprising a plurality of high side MOS field effect transistors and a control circuit. The first end of each of the high-side MOS field-effect transistors is electrically connected to a power source, and the second ends of the high-side MOS field-effect transistors are electrically connected to each other to generate an output signal. The control circuit is electrically connected to the gate terminal of each of the high-side MOSFETs, and the control circuit turns on the high-side MOS field-effect transistor in any order to reduce the turn-on of the high-side gold-oxygen half-field transistor Charge current, thereby reducing power consumption and extending the life of the high-side MOS field effect transistor.

Description

Power stage circuit with reduced charging current

The present invention relates to a power stage circuit, and more particularly to a power stage circuit having a reduced charging current.

Referring to FIG. 1A, FIG. 1A is a schematic diagram of a high side MOSFET of a conventional power stage circuit. The high-side MOS field-effect transistor M _HS has a gate-source inherent capacitance C _GS between its gate and source, and has a gate-drain between the gate and the drain. Capacitor C _GD . As shown in FIG. 1B, in the process in which the high-side MOS field-effect transistor M _{HS is} turned on, the gate-source voltage V _GS first breaks through the threshold voltage V _TH , and then the gate-source inherent capacitance C _GS and the gate-drain-intrinsic capacitance C _GD will be charged at the same time (charging interval A), then charge the gate 固有 inherent capacitance C _GD at the charging interval B near the voltage V _SP , at which time the voltage change approaches a gentle, then the gate source voltage V _GS Only then rises significantly (charge interval C). In general, in order for the power stage circuit to provide a large current, a large high-side gold-oxygen half-field transistor M _{HS is used} , so that the gate-drain internal capacitance C _GD increases. During the charging process of the high-side MOS field-effect transistor M _HS , the charging time B of the charging gate B for the gate-thickness inherent capacitance C _GD increases as the gate-thickness inherent capacitance C _GD increases, making it high. The side MOS half-field effect transistor M _HS consumes a large current i _G during the conduction process.

Therefore, there is an improved circuit of FIG. 2A, which provides two high-side MOS field-effect transistors M _HS1 , M _HS2 , by first conducting one of the high-side MOS field-effect transistors M _HS1 so that the charging interval B is only pole inherent capacitance C _GD1 charging shutter drain the high side mosfets electrically M _HS1 crystals, the metal-oxide-semiconductor field-effect transistor M _HS1 turns on the high side, the splice conducting a high-side metal oxide semiconductor field effect transistor M _HS2, at this time Since the voltage SW of the source terminal has been pulled to the potential of the power source HVin close to the 汲 terminal due to the conduction of the high side MOS field-effect transistor M _HS1 , the conduction process of the high-side MOS field-effect transistor M _{HS2 does} not need to be performed. The gate 汲 固有 inherent capacitance C _{GD2 is} charged, that is, the conduction process of the high-side MOS field-effect transistor M _{HS2 does} not need to pass through the charging interval B, so that in the case of the same current demand, the cost during the conduction process can be saved. The current (the sum of the currents I _G1 and I _G2 of Figure 2B will be smaller than the current I _{G of} Figure 1B). However, the transistor that is turned on first during each turn-on may have a large loss, which may shorten the life of the circuit.

Embodiments of the present invention provide a power stage circuit for reducing a charging current when a high-side gold-oxygen half-field effect transistor is turned on, thereby reducing power consumption and prolonging the service life of a high-side gold-oxygen half-field effect transistor.

Embodiments of the present invention provide a power stage circuit including a plurality of high-side MOSFETs and a control circuit. Each of the high side MOS half field effect transistors has a first end and a second end. The first end of each of the high-side MOS field-effect transistors is electrically connected to a power source, and the second ends of the high-side MOS field-effect transistors are electrically connected to each other to generate an output signal. The control circuit is electrically connected to the gate terminal of each of the high side MOSFETs, and the control circuit turns on the high side MOS field effect transistor in any order.

In summary, the embodiment of the present invention provides a power stage circuit for reducing the charging current of a high-side gold-oxygen half-field effect transistor, and reducing the total number of switching processes by first conducting any high-side gold-oxygen half-field effect transistor. The current consumed, while the high-side MOSFETs that are turned on each time may not be the same, so that each of the plurality of high-side MOSFETs can be turned on (or the number of times) ) can be set (or controlled) to approach the same, thereby extending the life of the power stage circuit.

The detailed description of the present invention and the accompanying drawings are to be understood by the claims The scope is subject to any restrictions.

110‧‧‧Control circuit

BS, SW‧‧‧ voltage

I _G , I _G0 , I _G1 , I _G2 , I _G3 ‧‧‧ Current

HVin‧‧‧ power supply

C _GS , C _GD , C _GS0 , C _GD0 , C _GS1 , C _GD1 , C _GS2 , C _GD2 , C _GS3 , C _GD3 ‧‧‧ Capacitance

M _HS , M _HS0 , M _HS1 , M _HS2 , M _HS3 ‧‧‧ high-side _MOS half-field effect transistor

V _TH , V _SP , V _TH1 , V _SP1 , V _GS , V _GS1 , V _GS2 , V _DS , V _GS0 , V _GS3 ‧‧‧ voltage

A, B, C‧‧‧Charging interval

100, 110, 120, 130‧‧‧ drive circuits

14‧‧‧Selection of the conduction unit

145‧‧‧ counter

140, 141, 142, 143, 154‧‧ and gates

15‧‧‧Logical unit

151, 152‧‧ ‧ anti-gate

153‧‧‧Anti-gate

101, 111, 121, 131‧‧‧ drive amplifiers

102, 112, 122, 132‧‧‧ or gate

V _GH0 , V _GH1 , V _GH2 , V _{GH3 ‧ ‧} first communication number

SecdC‧‧‧Secondary communication number

HSC‧‧‧High Side Signal Communication Number

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments will be briefly described below. Obviously, the drawings in the following description are only some of the present invention. For the embodiments, other drawings may be obtained from those skilled in the art without any inventive labor.

1A is a schematic illustration of a high side MOS field effect transistor of a conventional power stage circuit.

FIG. 1B is a waveform diagram of voltage and current conducted by the high side MOS field effect transistor of FIG. 1A.

2A is a schematic illustration of a high side MOS field effect transistor of a conventional power stage circuit.

2B is a waveform diagram of voltage and current conducted by the high side MOS half field effect transistor of FIG. 2A.

3 is a circuit diagram of a high-side MOSFET and its associated control circuit of a power stage circuit according to an embodiment of the present invention.

4 is a circuit diagram of the select-on unit of FIG. 3.

Figure 5 is a circuit diagram of the logic operation unit of Figure 3.

6 is a waveform diagram of voltage and current when a high-side MOS field-effect transistor of a power stage circuit according to an example of the present invention is turned on.

7 is a voltage waveform diagram of a high-side MOS field-effect transistor of a power stage circuit provided by an example of the present invention in a successive high-side turn-on procedure.

[Embodiment of Power Stage Circuit]

According to the conventional circuit of FIG. 2A, when there are a plurality of high-side MOSFETs, only one of the high-side MOSFETs is turned on first, although the process of conducting the crystals can be reduced. The current consumed in the process, but the transistor that is turned on first during the conduction process is the same, so that the transistor that is turned on first may have a large loss and reduce its lifetime. In response to this problem, the present embodiment provides a power stage circuit that conducts the high side MOS field effect transistor in any order through a circuit design. The part of the relevant control circuit referred to in this embodiment does not refer to the transistor switching control circuit which is designed according to the power output requirement of the general power stage circuit itself. The control circuit part referred to in this embodiment does not affect the power stage circuit. In the original mode of operation, the circuit of this embodiment can be applied to all power stage circuits having high side MOS half field effect transistors.

Please refer to FIG. 3. FIG. 3 is a circuit diagram of a high-side MOSFET and its associated control circuit of a power stage circuit according to an embodiment of the present invention. In the embodiment of Fig. 3, the number of high side MOS field effect transistors is illustrated by four, but the invention is not limited thereto. According to the same principle, the number of high side MOS half field effect transistors can be two, three, five or more.

The power stage circuit of this embodiment includes a plurality of high side _MOS field-effect transistors M _HS0 , M _HS1 , M _HS2 , M _HS3 and corresponding control circuits. In general, the power stage circuit may further include a low side MOSFET, the switching of which is complementary to the high side MOS half field effect transistor, which should be known to those of ordinary skill in the art. The way of working is not repeated. Each of the high-side MOS field-effect transistors of this embodiment has the opportunity to be selectively turned on before conducting other high-side MOS field-effect transistors. Meanwhile, in the operation of the power stage circuit of the embodiment, the high-side MOSFET can be different each time.

The first end of each high side _MOS field effect transistor (M _HS0 or M _HS1 or M _HS2 or M _HS3 ) is electrically connected to the power source HVin, the high side MOS half field effect transistor (M _HS0 , M _{HS1 )} The second ends of the M _HS2 , M _HS3 ) are electrically connected to each other (voltage SW) for generating an output signal. The control circuit is electrically connected to the gate of each of the high-side _MOSFETs M _HS0 , M _HS1 , M _HS2 , M _HS3 , and the control circuit turns on the high-side _MOS field-effect transistor in any order M _HS0 , M _HS1 , M _HS2 , M _HS3 . For detailed implementation of the control circuit, please refer to the subsequent further description.

Before explaining the details of the control circuit of the present embodiment, the operation of the power stage circuit will be briefly described. In the operation of the power stage circuit, the process in which the high-side MOS field-effect transistors are all turned on may be referred to herein as a high-side conduction procedure, and the high-side conduction procedure is sequentially performed during the operation of the power stage circuit (in When the low-side gold-oxygen half-field effect transistor is used, the low-side MOS field effect transistor is turned on every time the high-side conduction process is performed, for example, according to the pulse width modulation method, but the present invention is not limited thereto. According to the design requirements of the power stage circuit, those skilled in the art can design the required circuit according to the conventional technology, and will not be described again.

The first end of the high-side MOS field-effect transistor is Drain, and the second end of the high-side MOS field-effect transistor is the source. The high-side _MOS field-effect transistor M _HS0 has a gate-source inherent capacitance C _GS0 between the gate terminal and the source terminal, and the gate-drain pole between the gate terminal and the 汲 terminal of the high-side _MOS field-effect transistor M _HS0 Capacitor C _GD0 . The high-side MOS field-effect transistor M _HS1 has a gate-source inherent capacitance C _GS1 between the gate terminal and the source terminal, and the high-side MOS half-field effect transistor M _HS1 has a gate-drain between the gate terminal and the 汲 terminal. Capacitor C _GD1 . Having a gate-source intrinsic capacitance C _GS2 between gate terminal and the source terminal of the high side mosfets electrically M _HS2 crystals, having an inherent gate drain and gate terminal and a drain terminal between the high side mosfets electrically M _HS2 crystals Capacitor C _GD2 . The high-side _MOS field-effect transistor M _HS3 has a gate-source intrinsic capacitance C _GS3 between the gate terminal and the source terminal, and the high-side _MOS field-effect transistor M _HS3 has a gate-drain between the gate terminal and the 汲 terminal. Capacitor C _GD3 .

Referring to FIG. 3 again, the control circuit includes, for example, a plurality of driving circuits (four driving circuits 100, 110, 120, and 130 are exemplified in FIG. 3), a selection conducting unit 14, and a logic operation unit 15. Each of the driving circuits 100, 110, 120 or 130 is electrically connected to the gate terminals of the corresponding high-side _MOS field-effect transistors M _HS0 , M _HS1 , M _HS2 or M _HS3 .

Each of the drive circuits (100, 110, 120 or 130) includes a drive amplifier (101, 111, 121 or 131) and an OR gate (OR) (102, 112, 122 or 132). The driving amplifier (101, 111, 121 or 131) is electrically connected to the gate terminal of the corresponding high-side gold-oxygen half field effect transistor for driving the corresponding high-side gold-oxygen half field effect transistor (M _HS0 , M _HS1 , M _{HS2 )} Or M _HS3 ). In detail, the driver amplifiers 101, 111, 121, 131 are connected to the voltages BS, SW and provide current I _G0 for driving the gate terminals of the corresponding high-side _MOS field-effect transistors M _HS0 , M _HS1 , M _HS2 , M _HS3 . , I _G1 , I _G2 , I _G3 .

The output of the OR gate 102 is electrically connected to the drive amplifier 101. The gate 102 performs a logical OR operation on the first pilot communication number V _GH0 and the second pilot communication number SecdC, and turns on the corresponding driver amplifier 101 to turn on the corresponding high-side metal oxide half field effect transistor M when the logical OR operation result is true. _HS0 . Similarly, the gate 112 performs a logical OR operation on the first pilot communication number V _GH1 and the second pilot communication number SecdC, and when the logical OR operation result is true, the corresponding driver amplifier 111 is turned on corresponding to the high side metal oxide half field effect. Transistor M _HS1 . Similarly, the gate 122 performs a logical OR operation on the first pilot communication number V _GH2 and the second pilot communication number SecdC, and when the logical OR operation result is true, the corresponding driver amplifier 121 is turned on to correspond to the high side metal oxide half field effect. Transistor M _HS2 . Similarly, the gate 132 performs a logical OR operation on the first pilot communication number V _GH3 and the second pilot communication number SecdC, and when the logical OR operation result is true, the corresponding driver amplifier 131 is turned on corresponding to the high side metal oxide half field effect. Transistor M _HS3 .

The selection conducting unit 14 has four outputs for outputting four first communication numbers V _GH0 , V _GH1 , V _GH2 , V _GH3 corresponding to the four driving circuits 100, 110, ₁₂₀ , ₁₃₀ , respectively. In detail, the selective conducting unit 14 is electrically connected to the driving circuit 100, 110, ₁₂₀ , ₁₃₀ through the output terminal to generate first guiding communication numbers V _GH0 , V _GH1 , V _GH2 , V _GH3 , and the first communication number V . _GH0 corresponds to the driving circuit 100 and the high-side _MOS field-effect transistor M _HS0 , the first conduction number V _GH1 corresponds to the driving circuit 110 and the high-side _MOS field-effect transistor M _HS1 , and the first conduction number V _GH2 corresponds to the driving circuit 120 and The high-side gold-oxygen half-field effect transistor M _{HS2 has a} first pilot communication number V _GH3 corresponding to the driving circuit 130 and a high-side gold-oxygen half field effect transistor M _HS3 . Each time the high-side _MOS field-effect transistor is to be turned on, the first communication number may be different, and may be one of V _GH0 , V _GH1 , V _GH2 , and V _GH3 . The first communication number V _GH0 or V _GH1 or V _GH2 or V _{GH3 is} used to control the corresponding _height of the driving circuit 100 or 110 or 120 or 130 corresponding to the first communication number V _GH0 or V _GH1 or V _GH2 or V _GH3 . Side gold oxygen half field effect transistor M _HS0 or M _HS1 or M _HS2 or M _HS3 . That is, the selection conduction unit 14 first turns on one of the high side _MOSFETs M _HS0 , M _HS1 , M _HS2 , M _HS3 by using the first communication number V _GH0 or V _GH1 or V _GH2 or V _GH3 .

It is worth mentioning that in FIG. 3, the selection conducting unit 14 further has an input terminal for receiving the second pilot communication number SecdC, but the invention is not limited thereto. The second pilot number SecdC received by the select-on unit 14 of FIG. 3 is used to change the first pilot number of the output of the select-on unit 14 to be V _GH0 , V _GH1 , V _GH2 or V _GH3 . That is to say, the second pilot number SecdC of FIG. 3 is used to change the state of the first pilot number generated by the selection of the conducting unit 14 for the next time. However, the present invention does not limit how the selection of the conduction unit 14 changes the state of the first communication number. The selection of the conduction unit 14 can automatically change the first communication number generated by the next time, or the selection of the conduction unit 14 can be based on other The signal changes the first communication number generated next time.

The logic operation unit 15 is electrically connected to the gate terminals of the high side metal oxide half field effect transistors M _HS0 , M _HS1 , M _HS2 , M _HS3 , and in the high side metal oxide half field effect transistors M _HS0 , M _HS1 , M _HS2 , M _HS3 the first is more than the set value of the high-side metal oxide semiconductor field effect transistor M _HS0 or M _HS1 or M _HS2 or M _HS3 conducting gate terminal voltage V _GS0 or V _GS1 or V _GS2 or V _GS3 (will follow Further, when the second communication number SecdC is generated and transmitted to the driving circuits 100, 110, 120, 130, the other high-side MOS field-effect transistors are turned on. That is to say, in the case where the present embodiment has four high-side _MOS field-effect transistors M _HS0 , M _HS1 , M _HS2 , and M _HS3 , when the high-side _MOS field-effect transistor M _HS0 is turned on first, the other The high-side gold-oxygen half-field effect transistors M _HS1 , M _HS2 , and M _{HS3 are} subsequently turned on. When the high-side _MOS field-effect transistor M _HS1 is turned on first, the other high-side _MOS field-effect transistors M _HS0 , M _HS2 , and M _{HS3 are} subsequently turned on. When the high-side _MOS field-effect transistor M _HS2 is turned on first, the other high-side _MOS field-effect transistors M _HS0 , M _HS1 , and M _{HS3 are} subsequently turned on. When the high-side _MOS field-effect transistor M _HS3 is turned on first, the other high-side _MOS field-effect transistors M _HS0 , M _HS1 , and M _{HS2 are} subsequently turned on.

In other words, the control circuit of the present embodiment charges the gate terminal of one of the high side _MOS transistors M _HS0 , M _HS1 , M _HS2 , M _HS3 until the first side is charged The gate-source voltage of the half-field effect transistor is greater than the set value and then the gate terminals of the other gold-oxygen half-effect transistors are charged. In actual implementation, the high-side MOS field-effect transistor that is turned on first passes through the charging interval B as shown in FIG. 1B and FIG. 2B when conducting, and then turns on other high-side MOS field-effect transistors. . According to the charging interval B, regarding the triggering of the second pilot communication number SecdC to subsequently turn on other high-side MOSFETs, the aforementioned first-side turned-on high-side _MOS field-effect transistor M _HS0 or M _HS1 or M _HS2 or extreme value of the voltage setting M _HS3 brakes may be greater than, for example, in FIG. 1B voltage V _SP (or FIG. 2B voltage V _SP1), the gate voltage V _SP is greater than the source at the gate drain _GD charging the inherent capacitance C Extreme voltage V _GS . That is, the set value can be set to be larger than the gate-source voltage V _GS in the charging section B. For example, when the voltage V _GS0 or V _GS1 or V _GS2 or V _GS3 of the gate terminal of the high-side _MOSFET half-effect transistor M _HS0 or M _HS1 or M _HS2 or M _HS3 that is turned on first is exceeded, the voltage V _SP is generated and transmitted. The second conductive communication number SecdC is applied to the driving circuits 100, 110, 120, 130 to turn on other high-side metal oxide half field effect transistors that have not been turned on.

How to conduct the high side _MOS field effect transistors M _HS0 , M _HS1 , M _HS2 , M _HS3 in any order. Ideally, each of the high-side MOSFETs can be equally shared with the first turn-on work. In this embodiment, the first turn-on unit (for example, including a counter) is used to sequentially generate the first one corresponding to one of the high-side _MOSFETs M _HS0 , M _HS1 , M _HS2 , and M _HS3 , respectively. The communication numbers V _GH0 , V _GH1 , V _GH2 , V _{GH3 are} used so that in the successive high-side conduction procedure, the high-side _{MOSFETs of the} control circuit are turned on differently, thereby sequentially performing the high-side conduction procedure. The number of times the high side MOS field effect transistor is turned on is similar.

In this embodiment, the first communication numbers V _GH0 , V _GH1 , V _GH2 , and V _GH3 generated by the control circuit are used to turn on the high-side _MOSFETs M _HS0 , M _HS1 , M first. _{One of HS2} and M _HS3 , and the voltage of the gate terminal of the high-side MOS field-effect transistor (V _GS0 , V _GS1 , V _GS2 or V _GS3 ) that is turned on first is used to conduct other high-side gold oxides. Half field effect transistor. For example, when the high-side _MOS field-effect transistor M _{HS0 is} first turned on, the voltage V _GS0 of the gate terminal of the high-side _MOS field-effect transistor M _HS0 that is turned on first is used to conduct other high-side _MOSFETs . Crystals M _HS1 , M _HS2 , M _HS3 . When the high-side metal oxide semiconductor field effect transistor M _HSl is first turned on, the first being a high-side metal oxide semiconductor field-effect M _HSl crystal conducting gate terminal voltage V _GS1 to turn on other high-side metal oxide semiconductor field effect transistor M _HS0 , M _HS1 , M _HS3 , and so on.

Please refer to FIG. 3 and FIG. 4 at the same time. 4 is a circuit diagram of the select-on unit of FIG. 3. The select-on unit 14 includes a counter 145 and a plurality of AND gates, four gates 140, 141, 142, 143 in FIG. The counter 145 sequentially generates counting signals corresponding to one of the high side _MOS transistors M _HS0 , M _HS1 , M _HS2 , M _HS3 , respectively. The counter 145 counts each time the second communication number SecdC is received to change the counting signal, thereby changing the high-side MOS field-effect transistor corresponding to the first communication number. AND gates 140, 141, 142, and 143 are electrically connected to the counter 145, and the gates 140, 141, 142, and 143 are in one-to-one correspondence with the driving units 100, 110, 120, and 130, and each gate 140, 141, 142 or 143 is used to logically calculate the counting signal and the high side conduction communication number HSC to generate the first communication number V _GH0 or V _GH1 or V _GH2 or V _GH3 , and the first communication number V _GH0 or V _GH1 or V _GH2 Or V _{GH3 is} output to the corresponding drive circuit 100 or 110 or 120 or 130. It is worth mentioning that the high side conduction communication number HSC here is a signal of the transistor switching control circuit of the general power stage circuit controlling the conduction of the high side metal oxide half field effect transistor, and the high side conduction communication number can be controlled, for example, by A commonly used pulse width modulation signal, that is, a high side conduction communication number HSC is used to trigger the high side conduction procedure, and the control circuit of this embodiment is notified to allow all of the high side _MOS field-effect transistors M _HS0 , M _{HS1 .} M _HS2 and M _{HS3 are} all turned on.

Please refer to FIG. 3 and FIG. 5 simultaneously. FIG. 5 is a circuit diagram of the logic operation unit of FIG. The logic operation unit 15 of FIG. 3 can be replaced by various logic circuits, and the present invention is not limited thereto. The logic operation unit 15 can make the voltages V _GS0 , V _GS1 , V _GS2 , V _GS3 of the gate terminals of any of the high-side _MOSFETs M _HS0 , M _HS1 , M _HS2 , and M _HS3 true (True ) and When the high side conduction communication number HSC is true (True), the second communication number SecdC is generated. In FIG. 5, when either of the voltages V _GS0 and V _GS1 is true, the inverse OR gate (NOR) 151 outputs No (False), and when either of the voltages V _GS2 and V _GS3 is true, the inverse or gate ( NOR) 152 output No (False). The output of the inverse OR gate (NOR) 151 and the reverse OR gate (NOR) 152 is coupled to the input of the NAND gate 153. One input of the gate 154 receives the high side conduction communication number HSC, and the other input end of the gate 154 is connected to the output end of the gate 153, and the output end of the gate 154 outputs the second conduction number SecdC.

Please refer to FIG. 3 and FIG. 6 simultaneously. FIG. 6 is a waveform diagram of voltage and current when the high-side MOS field-effect transistor of the power stage circuit provided by the example of the present invention is turned on. According to the circuit of FIG. 3, any one of the high-side _MOS field-effect transistors M _HS0 , M _HS1 , M _HS2 , M _HS3 can be turned on first, for example, when the high-side _MOS field-effect transistor M _HS0 is turned on first. As shown in FIG. 6, the voltage V _GS0 of the gate terminal rises first, and then turns on other high-side gold-oxygen half field effect transistors M _HS1 , M _HS2 , and M _HS3 .

3 and FIG. 7 are voltage waveform diagrams of the high-side MOS field-effect transistor of the power stage circuit provided by the example of the present invention in successive high-side conduction processes. In each high-side conduction procedure, the high-side MOSFETs that are turned on first can be different, as shown in Figure 7, when the first turn on the leftmost side is turned on, the high side is turned on first. Gold oxygen half field effect transistor M _HS0 . According to the circuit of FIG. 3 and FIG. 4, the counter signal generated by the counter 145 of the turn-on unit 14 is selected to correspondingly generate the first pilot communication number V _GH0 , so that the high-side _MOS field-effect transistor M _HS0 is turned on first. The voltage V _GS0 rises first, and then the logic operation unit 15 generates the second conduction number SecdC due to the trigger of the voltage V _GS0 (the voltage exceeds the set value) to turn on the other high-side MOS field-effect transistors M _HS1 , M _HS2 , M _HS3 . Accordingly, the counter 145 of FIG. 4 receives the second pilot communication number SecdC, so that the counter 145 counts to change the count signal, and the new count signal corresponds to the first pilot communication number V _GH1 . Subsequently, in the second conduction, is turned on first is a high-side metal oxide semiconductor field effect transistor M _HS1, its gate terminal voltage V _GS1 to rise, the voltage V _GS1 for triggering conduction of other high side mosfets The transistors M _HS0 , M _HS2 , M _HS3 , then the first pilot number is changed to V _GH2 . Then, at the third turn-on, the voltage V _{GS2 of the} gate terminal of the high-side MOSFET half-effect transistor M _{HS2 is} first turned on, and the voltage V _{GS2 is} used to trigger the conduction of other high-side MOS field-effect transistors M. _HS0 , M _HS1 , M _HS3 , then the first communication number is changed to V _GH3 . Then, at the fourth turn-on, the voltage V _{GS3 of the} gate terminal of the high-side _MOS field-effect transistor M _{HS3 that} is turned on first rises, and the voltage V _{GS3 is} used to trigger the conduction of other high-side _MOS field-effect transistors M _{HS0 .} , M _HS1 , M _HS2 . However, the above-described order of changing the high-side MOS field-effect transistor that is turned on first can be changed, and the present invention is not limited thereto.

[Possible effects of the examples]

In summary, the power stage circuit provided by the embodiment of the present invention is used for reducing the charging current of the high-side gold-oxygen half-field effect transistor, and can reduce the switching process by first conducting any high-side gold-oxygen half-field effect transistor. The total current consumed, and the high-side MOSFETs that are turned on each time may not be the same, so that a plurality of high-side MOS half-field transistors can be used as a counter. The probability (or number) of each of the first being turned on can be set (or controlled) to be nearly the same, thereby extending the life of the power stage circuit.

The above description is only an embodiment of the present invention, and is not intended to limit the scope of the invention.

Claims (9)

A power stage circuit comprising: a plurality of high-side MOS field-effect transistors, each of the high-side MOS transistors having a first end and a second end, each of the high-side MOS field-effect transistors The first end is electrically connected to a power source, the second ends of the high-side MOS field-effect transistors are electrically connected to each other to generate an output signal, and a control circuit is electrically connected Up to a gate terminal of each of the high-side MOSFETs, the control circuit first conducts any one of the high-side MOS field-effect transistors until the high-side MOSFET is first turned on. After the gate voltage of the transistor is greater than a set value, the other high-side MOSFETs in the high-side MOS field-effect transistors are turned on in any order. The power stage circuit of claim 1, wherein the control circuit generates a first pilot number for first conducting any one of the high side MOSFETs, and the high side gold that is turned on first The voltage at the gate terminal of the oxygen half field effect transistor is used to conduct other high side MOS field effect transistors. According to the power stage circuit of claim 2, wherein the high-side MOS field-effect transistors are all turned on is a high-side conduction process, and the high-side conduction is sequentially performed during the operation of the power stage circuit. a program, wherein the control circuit uses a counter to sequentially generate the first pilot communication numbers respectively corresponding to one of the high side MOSFETs, such that in the successive high side conduction procedure, the control The high side MOS field effect transistors that are first turned on are different, whereby the number of times the high side MOSFETs are turned on the same in the successive high side conduction process. The power stage circuit of claim 1, wherein the first end of the high side MOSFET is a 汲 extreme, and the second end of the high side MOS field is a source terminal. a gate-source inherent capacitance between the gate terminal and the source terminal of each of the high-side MOSFETs, between the gate terminal of the high-side MOS field-effect transistor and the 汲 terminal Has a gated buckling inherent capacitance. The power stage circuit of claim 4, wherein the control circuit charges the gate terminal of one of the metal oxide half field effect transistors until the gate of the high side metal oxide half field effect transistor that is first charged After the source voltage is greater than a set value, the other gate terminals of the other metal oxide half field effect transistors are then charged. The power stage circuit of claim 1, wherein the control circuit comprises: a plurality of driving circuits, each of the driving circuits being electrically connected to the corresponding gate terminal of the high side MOS field effect transistor; The conducting unit is electrically connected to the driving circuits to generate a first communication number to control the high-side MOS field-effect transistor corresponding to the driving circuit corresponding to the first communication number; and a logic operation unit, Electrically connecting the gate terminals of the high-side MOS field-effect transistors, and the gate terminals of the high-side MOSFETs in the high-side MOS field-effect transistors When the voltage exceeds a set value, a second communication signal is generated and transmitted to the driving circuits, so that the other high-side MOSFETs are turned on. The power stage circuit of claim 6, wherein the selection conducting unit comprises: a counter sequentially generating a counting signal respectively corresponding to one of the high side MOS transistors; A plurality of AND gates are electrically connected to the counters, and the gates are in one-to-one correspondence with the driving units, and each of the gates is used for logically calculating the counting signal and a high side guiding communication number. The first communication number is generated, and the first communication number is output to the corresponding driving circuit. The power stage circuit of claim 7, wherein the counter receives the second communication number for counting to change the counting signal, thereby changing the high side metal oxide half field effect transistor corresponding to the first communication number . The power stage circuit of claim 6, wherein the driving circuit comprises: a driving amplifier electrically connected to the corresponding gate terminal of the high side metal oxide half field effect transistor for driving the corresponding high side gold oxide a half field effect transistor; and an OR gate, or an output of the gate is electrically connected to the driver amplifier, and the OR gate logically ORs the first pilot signal number and the second pilot signal number, and is in a logical OR When the operation result is true, the corresponding high-side MOSFET is turned on by the corresponding driving amplifier.