TWI654847B - Comparator and delta-sigma modulation circuit - Google Patents

Abstract

The comparator and the delta-sigma modulation circuit of the present invention reduce the circuit scale of the comparator.

The comparator (1) includes: a differential amplifier (10) that outputs a signal corresponding to the difference of the differential input signals (vp, vn); and an offset generator (11) that is based on the differential digital dither signal (d0) , D1) increases or decreases the offset voltage of the differential amplifier (10). The differential amplifier (10) is composed of a first differential pair transistor (X1, X2) and a second differential pair transistor (X3, X4) arranged in parallel with the first differential pair transistor (X1, X2). The offset generator (11) is connected with the second differential pair transistor (X3, X4) by co-emission-cascode connection, and performs 0N / 0FF according to the differential digital dither signal (d0, d1). The third differential pair transistor (X11, X12) is operated.

Description

Comparator and delta-sigma modulation circuit

The present invention relates to a comparator suitable for a delta-sigma AD converter and the like, and a delta-sigma modulation circuit using the same.

As is known to all, in the delta-sigma AD converter, when converting a DC input signal, there is noise with a specific frequency called "tone noise" at a specific input signal, which results in Deterioration of conversion accuracy. This phenomenon occurs when the level ratio of the input signal and the reference signal is an integer ratio.

Generally, an AD converter is a circuit block that displays a ratio of an input signal to a reference signal to be compared as a digital signal. The delta-sigma AD converter includes a so-called delta-sigma modulation circuit, that is, a modulation circuit that outputs a ratio of an input signal to a reference signal as a dense wave of a digital signal. A digital filter is arranged at the rear stage of the delta-sigma modulation circuit, and a plurality of bits of digital values are obtained by performing an averaging process.

For example, when a delta-sigma modulation circuit is configured with a 1-bit output, the output is represented by two values, High and Low. In the case where the level ratio of the input signal and the reference signal is an integer ratio of 1/3, the delta-sigma modulation circuit generates a pattern that has an average of 1/3, such as a dense wave. However, in a pattern such as a dense wave of 1/3, the delta-sigma modulation circuit is High → Low → Low → High →. ． ． ． Generally, the output becomes High at a ratio of 1 out of 3 times, so the specific frequency is strongly emphasized. When the specific frequency is close to the frequency of the input signal, that is, at the frequency of the low frequency At this time, the specific frequency cannot be removed by the digital filter in the subsequent stage. As a result, the specific frequency exhibits noise with respect to the conversion result. This is called audio noise.

When the input signal changes with time, the probability of the sparse waves of the delta-sigma modulation circuit being a fixed pattern is very low, and the appearance time of the fixed pattern is very short, so the impact of audio noise is small. However, when a DC input signal that hardly changes, such as the output of a temperature sensor, is used as the input signal of a delta-sigma AD converter, audio noise often affects the performance of the AD converter.

In the past, in order to remove this audio noise, it is known to inject a "tremor signal" to be effective. A dithering signal is a signal that falsely (pseudo-likely) overlaps the input signal. Specifically, a method is obtained in which a pseudo-random signal is generated as a dither signal in a digital circuit, and the pseudo-random signal is added to an input signal of an AD converter. Since the average value of the pseudo-random signal is very close to zero, it has little effect on the input signal. If such a pseudo-random signal is added to the input signal, even if the input signal is a fixed value, since the signal applied to the AD converter changes with time, the generation of audio noise can be suppressed.

Due to the relationship between reproducibility and stability, it is very difficult to generate a pseudo-random signal as a dithering signal in an analog circuit. Therefore, there is known a method for generating a pseudo-random signal by a digital circuit called a PN (Pseudo Number) symbol generating circuit using a plurality of flip-flops and feedback circuits. However, digital signals have extremely high signal levels (such as voltage levels) relative to analog input signals that are input to the AD converter. Therefore, if the digital dither signal generated in the digital circuit, that is, the pseudo-random signal is added to the input signal of the AD converter as it is, the original input signal of the AD converter cannot be converted correctly. Therefore, in the prior art, the following method is adopted: the digital dithering signal generated by the digital circuit is temporarily replaced with a signal level that is attenuated The reduced analog signal generates an analog dither signal and then adds it to the input signal of the AD converter.

However, in the prior art, the attenuation rate when a digital dithering signal is converted into an analog signal, that is, the signal level of the analog dithering signal needs to be determined by exploration. In addition, it is necessary to prepare a conversion circuit for converting a digital dither signal into an analog dither signal, which has problems in circuit scale and cost.

As an example of a conversion circuit that converts a digital dither signal into an analog dither signal, FIG. 6 shows a configuration of an analog dither signal generating circuit shown in Patent Document 1. This analog dithering signal generating circuit generates an analog dithering signal with a waveform pattern as shown in FIG. 7 (A) or FIG. 7 (B) by using the resistor divider based on resistors R1 ~ R6 and switches S0 ~ S4. In the technique disclosed in Patent Document 1, the switches S0 to S4 are controlled based on the digital dither signal and an analog dither signal is generated. The input signal of the AD converter and the analog dither signal are added by the comparator 12.

As is known, a pseudo-random number signal generating circuit such as a PN symbol as shown in FIG. 8 is used as a digital dithering signal generating circuit (see Non-Patent Document 1). This circuit is composed of a shift register 100 formed by a plurality of cascade connections, and an exclusive logic AND circuit 101.

Prior art literature Patent literature

[Patent Document 1] Japanese Patent No. 4687512

Non-patent literature

[Non-Patent Document 1] RCDixon, "Latest Decentralized Communication Method (Latest Spectral Diffusion Communication Method) ", JATEC Publishing, P.91, 1978

As described above, in the technique disclosed in Patent Document 1, a resistor divider circuit for generating an analog dither signal based on a digital dither signal is required. This resistor divider circuit is also a DA converter, and its circuit scale cannot be ignored. When an integrated circuit is implemented using an integrated circuit, a resistance element increases the area. Therefore, if a resistor divider circuit is mounted in the integrated circuit, the area of the chip is likely to increase. If the area of the wafer is large, the yield of the integrated circuit and the number of wafers per wafer are also affected, so the economic impact is great.

Furthermore, as in the technique shown in Patent Document 1, in an analog-to-jitter signal generating circuit having a plurality of analog values, it is easy to predict that the average value of the analog-jitter signal is not zero, so this analogy is being used. When the dithering signal is added to the input signal of the AD converter, there may be an error in the AD conversion result. To reduce this error, it is necessary to increase the size of the resistor used in the resistor divider circuit in the integrated circuit to improve the relative accuracy. However, since such an increase in the size of the resistor causes a further increase in the circuit area, the influence of the economy changes greatly.

The present invention has been made to solve the above problems, and an object thereof is to reduce the circuit scale of a comparator used in a delta-sigma AD converter or the like.

The comparator of the present invention is characterized by comprising: a differential amplifier that outputs a signal corresponding to the difference between the differential input signals; and an offset generator that is based on the differential digital dither signal The offset voltage of the differential amplifier is increased or decreased.

In addition, in a configuration example of the comparator of the present invention, the comparator is characterized in that the offset generator causes the size of the non-inverting side and the non-inverting side of the differential amplifier according to the differential digital dither signal. The ratio is changed to increase or decrease the offset voltage.

In addition, in a configuration example of the comparator of the present invention, the comparator is characterized in that the offset generator increases or decreases the offset voltage by changing a current flowing through a transistor constituting the differential amplifier. .

Further, in a configuration example of the comparator of the present invention, the differential digital wobble signal is a pseudo-random number signal.

In addition, in a configuration example of the comparator of the present invention, the comparator is characterized in that the differential amplifier is composed of a first differential pair transistor and a second differential pair transistor, and the second differential pair is The crystal takes the same differential input signal as the first differential pair transistor as an input, and is arranged in parallel with the first differential pair transistor. The offset generator is composed of a third differential pair transistor. 3 The differential pair transistor is connected to the cascode of the second differential pair transistor, and performs ON / 0FF (on / off) operation according to the differential digital dither signal.

In addition, the delta-sigma modulation circuit of the present invention is characterized by comprising: an integrator that integrates a differential input signal; and a comparator that uses the differential output signal output from the integrator as an input.

According to the present invention, by providing an offset generator that increases or decreases the offset voltage of the differential amplifier based on the differential digital dither signal, the dither signal can be superimposed on the input of the comparator without using an analog dither signal generating circuit. Signal, so that The circuit scale of the division modulation circuit becomes smaller. In addition, in the present invention, since the differential digital dither signal is directly input to the comparator without using an analog dither signal generating circuit, performance degradation caused by the analog dither signal can be avoided.

1‧‧‧ Comparator

2‧‧‧ Subtractor

3‧‧‧ Integrator

4‧‧‧Digital chattering signal generating circuit

10‧‧‧ Differential Amplifier

11‧‧‧ Offset Generator

X1 ~ X4, X8 ~ X14‧‧‧P channel MOS transistor

X5 ~ X7‧‧‧N channel MOS transistor

I1‧‧‧ current source

S10, S11‧‧‧ Switch

FIG. 1 is a circuit diagram showing a configuration of a comparator according to an embodiment of the present invention.

FIG. 2 is a diagram showing an increase or decrease in an offset voltage of an output signal in a comparator according to an embodiment of the present invention.

3 is a circuit diagram showing a configuration when a comparator according to an aspect of the present invention is applied to a delta-sigma modulation circuit.

FIG. 4 is a circuit diagram showing another configuration of a comparator according to the embodiment of the present invention.

5 is a circuit diagram showing another configuration of a comparator according to the embodiment of the present invention.

6 is a circuit diagram showing a configuration example of a conventional conversion circuit when a digital wobble signal is converted into an analog wobble signal.

FIG. 7 is a diagram showing a waveform of an analog signal generated in the structure of FIG. 6.

FIG. 8 is a circuit diagram showing a configuration example of a digital wobble signal generating circuit.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of a comparator according to an embodiment of the present invention. The comparator 1 of this embodiment takes as input the differential analog input signals vp and vn and the differential digital dither signals d0 and d1.

The comparator 1 is composed of the following parts: the inverting input signal vn is input to the P-channel MOS transistor X1 of the gate; the non-inverting input signal vp is input to the P-channel of the gate. MOS transistor X2; input the inverting input signal Vn to the gate, and the P-channel MOS transistor X3 whose source is connected to the source of the P-channel MOS transistor X1; input the normal-phase input signal vp to the gate and source P-channel MOS transistor X4 connected to source of P-channel MOS transistor X2; gate and drain N-channel MOS transistor X5 connected to drain of P-channel MOS transistor X1 and source ground: gate and N-channel MOS transistor X5 gate and drain connection, drain connected to P-channel MOS transistor X2 drain connection, source-grounded N-channel MOS transistor X6; gate and P-channel MOS transistor X2 drain And the drain connection of the N-channel MOS transistor X6, the drain connected to the comparator 1 output terminal, and the source-grounded N-channel MOS transistor X7: the source is connected to the supply voltage VDD, and the drain is connected to the P-channel MOS The sources of the crystals X1 ~ X4 are connected to the P-channel MOS transistor X8: the gate is connected to the gate of the P-channel MOS transistor X8, the source is connected to the power supply voltage VDD, and the drain is quickly connected to the output terminal of the comparator 1. P-channel MOS transistor X9; the gate and the drain are connected to the gate of the P-channel MOS transistor X8, X9, the source and the supply voltage VDD Connected P-channel MOS transistor X10; input digital dither signal d1 to the gate, the source is connected to the drain of P-channel MOS transistor X3, and the drain is connected to the gate and drain of N-channel MOS transistor X5 P-channel MOS transistor X11; P-channel MOS with digital dither signal d0 input to the gate, source connected to the drain of P-channel MOS transistor X4, and drain connected to the drain of N-channel MOS transistor X6 Transistor X12: and a current source I1 that is connected at one end to the gate and drain of the P-channel MOS transistor X10, the other end is grounded, and supplies a constant current to the P-channel MOS transistor X10.

The transistors X1 to X4 constitute a differential amplifier 10. The transistors X11 and X12 constitute an offset generator 11 that controls the offset of the differential amplifier.

Digital wobble for generating differential digital wobble signals d0, d1 supplied to the offset generator 11 As the dynamic signal generating circuit, a pseudo-random number signal generating circuit such as that shown in FIG. 8 may be used. Here, since a differential signal is used, a conversion circuit that converts a single-ended output signal of a pseudo-random number signal generating circuit into a differential signal may be used to generate the differential digital dither signals d0, d1.

In the comparator 1 shown in FIG. 1, the transistors X1 and X3 take a common signal vn as an input. However, the drain current of the transistor X3 does not flow when the transistor X11 is not in the ON state. The ON / OFF of the transistor X11 is controlled by a digital dither signal d1.

Similarly, the transistors X2 and X4 take the common signal vp as an input, but the drain current of the transistor X4 does not flow when the transistor X12 is not in the ON state. The ON / OFF of the transistor X12 is controlled by a digital dither signal d0.

In one set of differential pair transistors Xi and X2 and another set of differential pair transistors X3 and X4 constituting the differential amplifier 10, the differential pair transistors X11 and X12 and one set of differential pair transistors X3 are combined. X4 and X4 are co-radiated and cascoded. The ON / OFF of X11 and X12 (ON / OFF of X3 and X4) of this transistor are controlled by differential digital dithering signals d0 and d1. When the transistor X12 is turned to the ON state according to the digital wobble signal d0, the transistor X11 is turned off according to the digital wobble signal d1, and when the transistor X12 is turned to 0FF state according to the digital wobble signal d0, the digital wobble signal is used. d1 turns transistor X11 on.

Therefore, because of the ON / OFF of the transistors X11 and X12, the transistor sizes of the transistors X2 and X4 on the positive side and the transistors X1 and X3 on the reverse side of the differential amplifier 10 increase or decrease in appearance. If transistors X1 to X4 are manufactured in a uniform size, when transistor X12 is ON and transistor X11 is 0FF, transistors X2 and X4 on the positive phase and transistors X1 and X3 on the opposite phase are used. The transistor size ratio is 2: 1. Conversely, when transistor X12 is in the OFF state and transistor X11 is in the ON state, transistors X2 and X4 on the positive phase and transistors on the reverse side are The size ratio of the transistors X1 and X3 is 1: 2.

Due to the apparent increase or decrease in the size ratio of such a transistor, the offset voltage of the differential amplifier increases to 0, and the offset voltage of the output signal out of the comparator 1 increases or decreases. Since the increase or decrease of the offset voltage is controlled by the differential digital dither signals d0 and d1, by applying the differential digital dither signals d0 and d1 directly to the comparator 1, the input signals vp, vn, and dither can be applied. The signals are added.

FIG. 2 is a diagram showing how the offset voltage of the output signal out in the comparator 1 according to the embodiment of the present invention is increased or decreased. In addition, the input signal vn on the inverting side is fixed at 2.5W. The horizontal axis of FIG. 2 is the voltage of the input signal vp, and the vertical axis is the voltage of the output signal out. 200 in FIG. 2 indicates the offset voltage of the output signal out when the transistors X11 and X12 are both 0N, 201 indicates that the transistor X12 is ON and the amount of the transistor X1 is 0FF (the dither signal d0 is Low and the dither signal d1 is High) The offset voltage of the output signal out at time 202 indicates the offset voltage of the output signal out when the transistor X12 is OFF and the transistor X11 is 0N (the dither signal d0 is High and the dither signal d1 is Low).

FIG. 3 is a circuit diagram showing a configuration when the comparator 1 of this embodiment is applied to a delta-sigma modulation circuit. The delta-sigma modulation circuit is composed of the following parts: a 1-bit quantized comparator for the differential analog input signals vp, vn; the delta-sigma modulation before the sampling period is subtracted from the differential analog input signals inp, inn The subtractor 2 of the voltage corresponding to the output signal out of the circuit; the integrator 3 which integrates the differential analog output signal of the subtractor 2 and outputs the differential analog input signals vp, vn to the comparator 1; and the output difference Digital wobble signal generating circuit 4 for moving digital wobble signals d0, d1.

The output signal out of the delta-sigma modulation circuit before 1 sampling period is High At this time, the subtractor 2 subtracts, for example, a predetermined voltage VREF from the input signal inp, and adds the voltage VREF to the input signal inn. Conversely, when the output signal out of the delta-sigma modulation circuit before the sampling period is Low, the subtractor 2 adds the voltage VREF and the input signal inp, and subtracts the voltage VREF from the input signal inn.

If the rear stage of the delta-sigma modulation circuit shown in FIG. 3 is connected to a digital filter, a delta-sigma AD converter can be realized.

In summary, in this embodiment, by using the differential digital dither signal generated by the pseudo-random number signal generating circuit of FIG. 8, the size ratio of the transistor of the differential amplifier in the comparator can be increased or decreased. The analog signal is not used under the dithering signal generation circuit, and the dithering signal is superimposed on the input signal of the comparator. Therefore, the circuit scale of the comparator can be reduced, and the circuit scale of the delta-sigma modulation circuit using the comparator can be reduced Get smaller.

In addition, in the technique disclosed in Patent Document 1, since there is an error factor in the analog chattering signal generating circuit, the analog is that the average value of the chattering signal does not become zero, and the delta integral adjustment is performed due to the offset amount of the offset voltage. Performance degradation occurs in the transformer circuit. In contrast, in the present embodiment, since the differential digital dither signal is directly input to the comparator without using an analog dither signal generating circuit, it is possible to avoid performance degradation caused by the analog dither signal.

In addition, as shown in FIG. 4, transistors X13 and X14 that operate in combination with the transistors X11 and X12 constituting the offset generator 11 may be added. The gate of the P-channel MOS transistor X13 is input with a digital dither signal d0. The source is connected to the drain of the transistor X8, and the drain is connected to the drain of the transistor X3 and the source of the transistor X11. The gate of the P-channel MOS transistor X14 is input with a digital dither signal d1, the source is connected to the drain of the transistor X8, and the drain is connected to the drain of the transistor X4 and the source of the transistor X12.

Transistor X13 turns OFF when transistor X11 is ON, and turns ON when transistor X11 is 0FF. Similarly, the transistor X14 becomes OFF when the transistor X12 is ON, and becomes 0N when the transistor X12 is OFF. In this way, when the transistor X11 is in the OFF state, the source and the drain of the transistor X3 are short-circuited. In addition, when the transistor X12 is in the 0FF state, the source and the drain of the transistor X4 are short-circuited. Ground realizes the reset function without current flowing.

In addition, in this embodiment, the sizes of the transistors X1 to X4 constituting the differential amplifier 10 are all described as being the same, but it is not limited to this, and the size of each transistor may be appropriately set. To adjust the amount of dithering signal, that is, the amount of offset voltage.

In this embodiment, the transistors X3 and X4 for amplifiers and the transistors X11 and X12 for the offset generator are connected in parallel to the differential pair transistors, each having a positive phase side and a reverse phase side. However, it is also possible to connect a plurality of these transistors X3, X4, X11, X12 as shown in FIG.

In addition, a switch S10 may be provided between the drain of each transistor X3 and the source of transistor X11, and a switch S11 may be provided between the drain of transistor X4 and the source of transistor X12. If the switches S10 and S11 are 0FF, the transistors X11 and X12 connected to the switches S10 and S11 do not operate as offset generators. Therefore, it is possible to switch the parallel transistors connected to the differential pair transistors X1 and X2. Number, so that the amount of the wobble signal, that is, the amount of offset voltage can be adjusted.

In addition, since the original d0 and d1 are logical signals, the switches S10 and S11 in FIG. 5 can also be deleted and replaced, and it is prepared to indicate whether d0 and d1 are allowed to be input to each of the X11 and X12 (not shown). The gate signal p (for example, p = 1 if allowed, p = 0 if not allowed), obtain the logical product (AND) of d0, d1, and signal p, and input the result to each of X11, X12 (If p = 0, each X11, X12 is always closed). Then, if the number of transistors used is n, the signal p can also be set to 1 for the n transistors X11 and X12, and the signal p can be set to 0 for the remaining X11 and X12 that are not used.

In this embodiment, although the sigma-delta modulation circuit and the sigma-delta AD converter are described as examples, the invention is not limited to this, and the comparator of the present invention may be used as another AD converter, for example, Comparator for Flash AD converter.

[Industrial possibilities]

The present invention can be applied to a comparator used in a delta-sigma AD converter or the like.

Claims (5)

A comparator is characterized by comprising: a differential amplifier that outputs a signal corresponding to a difference of a differential input signal; and an offset generator that increases or decreases an offset voltage of the differential amplifier according to a differential digital dither signal; The offset generator changes the size ratio of the positive and negative sides of the differential amplifier according to the differential digital dither signal, thereby increasing or decreasing the offset voltage. For example, the comparator of the first scope of the patent application, wherein the offset generator increases or decreases the offset voltage by changing a current flowing through a transistor constituting the differential amplifier. For example, the comparator of the first scope of the patent application, wherein the differential digital dithering signal is a pseudo-random number signal. For example, the comparator of the first scope of the patent application, wherein the differential amplifier is composed of a first differential pair transistor and a second differential pair transistor, and the second differential pair transistor is connected with the first differential pair transistor. 1 The same differential input signal as the differential pair transistor is used as an input and is arranged in parallel with the first differential pair transistor; the offset generator is composed of a third differential pair transistor, and the third differential pair is The transistor is connected to the second differential pair transistor cascode, and performs 0N / 0FF operation according to the differential digital dither signal. A delta-sigma modulation circuit is characterized in that it comprises: an integrator that integrates a differential input signal; and a comparator in any one of the claims 1 to 4 of the patent application scope, which will output from the integrator. The differential output signal is used as an input.