TWI654339B - Wiring film - Google Patents
Wiring filmInfo
- Publication number
- TWI654339B TWI654339B TW105136360A TW105136360A TWI654339B TW I654339 B TWI654339 B TW I654339B TW 105136360 A TW105136360 A TW 105136360A TW 105136360 A TW105136360 A TW 105136360A TW I654339 B TWI654339 B TW I654339B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- wiring film
- atom
- alloy layer
- film
- Prior art date
Links
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 70
- 239000000463 material Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims description 16
- 229910052761 rare earth metal Inorganic materials 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- 229910052750 molybdenum Inorganic materials 0.000 claims description 5
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 4
- 229910052707 ruthenium Inorganic materials 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims 4
- 239000011733 molybdenum Substances 0.000 claims 4
- 229910052684 Cerium Inorganic materials 0.000 claims 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 3
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 claims 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims 2
- 229910052762 osmium Inorganic materials 0.000 claims 1
- SYQBFIAQOQZEGI-UHFFFAOYSA-N osmium atom Chemical compound [Os] SYQBFIAQOQZEGI-UHFFFAOYSA-N 0.000 claims 1
- 239000010410 layer Substances 0.000 description 100
- 239000010408 film Substances 0.000 description 95
- 238000010438 heat treatment Methods 0.000 description 16
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 12
- 239000000203 mixture Substances 0.000 description 11
- 238000004544 sputter deposition Methods 0.000 description 11
- 229910052779 Neodymium Inorganic materials 0.000 description 10
- 239000010409 thin film Substances 0.000 description 10
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 8
- 238000005530 etching Methods 0.000 description 8
- 238000002844 melting Methods 0.000 description 6
- 230000008018 melting Effects 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 229910052757 nitrogen Inorganic materials 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- VZSRBBMJRBPUNF-UHFFFAOYSA-N 2-(2,3-dihydro-1H-inden-2-ylamino)-N-[3-oxo-3-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)propyl]pyrimidine-5-carboxamide Chemical compound C1C(CC2=CC=CC=C12)NC1=NC=C(C=N1)C(=O)NCCC(N1CC2=C(CC1)NN=N2)=O VZSRBBMJRBPUNF-UHFFFAOYSA-N 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 238000005546 reactive sputtering Methods 0.000 description 4
- 238000005477 sputtering target Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910052688 Gadolinium Inorganic materials 0.000 description 2
- AFCARXCZXQIEQB-UHFFFAOYSA-N N-[3-oxo-3-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)propyl]-2-[[3-(trifluoromethoxy)phenyl]methylamino]pyrimidine-5-carboxamide Chemical compound O=C(CCNC(=O)C=1C=NC(=NC=1)NCC1=CC(=CC=C1)OC(F)(F)F)N1CC2=C(CC1)NN=N2 AFCARXCZXQIEQB-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005401 electroluminescence Methods 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 238000005121 nitriding Methods 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 239000013077 target material Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052692 Dysprosium Inorganic materials 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 150000007513 acids Chemical class 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000004993 emission spectroscopy Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000010406 interfacial reaction Methods 0.000 description 1
- 239000005001 laminate film Substances 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- 238000000504 luminescence detection Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000010079 rubber tapping Methods 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 1
- 238000004611 spectroscopical analysis Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Physical Vapour Deposition (AREA)
Abstract
本發明提供一種配線膜，其含有Al合金層，且於所述Al合金層的至少一個面上積層有經氮化的Mo層，並且所述配線膜的特徵在於：所述Al合金層以Al作為母材，且含有0.01原子%以上、0.6原子%以下的Nd。 The present invention provides a wiring film comprising an Al alloy layer, and a nitrided Mo layer is laminated on at least one surface of the Al alloy layer, and the wiring film is characterized in that the Al alloy layer is Al The base material contains 0.01 atom% or more and 0.6 atom% or less of Nd.
Description
本發明是有關於一種具有高耐熱性的配線膜。 The present invention relates to a wiring film having high heat resistance.
關於液晶顯示器、有機電致發光(Electroluminescence，EL)顯示器、觸控面板(touch panel)等顯示元件的電極材料中所使用的配線膜，利用電阻率低、容易進行微細加工的特長而使用Al薄膜或以Al作為母材的Al合金薄膜。 In the wiring film used for the electrode material of a display element such as a liquid crystal display, an electroluminescence (EL) display, or a touch panel, an Al film is used because of its low resistivity and easy handling of fine processing. Or an Al alloy film using Al as a base material.
另一方面，Al的熔點低至660℃，故該些Al薄膜或Al合金薄膜的耐熱性的提昇成為課題。尤其伴隨著所述顯示器或觸控面板的配線膜的細線化，為了防止斷線等而配線膜的高耐熱性極為重要。另外，亦於對應功率元件(power device)的大容量化的方面，高耐熱性是重要的。 On the other hand, since the melting point of Al is as low as 660 ° C, the heat resistance of these Al thin films or Al alloy thin films is an improvement. In particular, as the wiring film of the display or the touch panel is thinned, high heat resistance of the wiring film is extremely important in order to prevent disconnection or the like. In addition, high heat resistance is also important in terms of increasing the capacity of power devices.
對於使用非晶矽的液晶顯示器用薄膜電晶體而言，製造步驟中的熱處理現有最高為350℃左右。於該情形時，藉由使用將Al薄膜與高熔點金屬薄膜積層而成的配線膜，可確保配線膜的耐熱性。相對於此，於如低溫多晶矽或氧化物半導體般於元件的製造步驟中包含400℃~600℃的熱處理的情形時，由於Al的熔點低而於Al與高熔點金屬之間發生相互擴散，而產生Al配線的電阻的增大、由Al薄膜中產生凸起(hillock)所致的Al配線膜的破壞等。為了避免該些情況，現有於薄膜電晶體等的情形時，使用 高熔點金屬作為配線膜。 For a thin film transistor for a liquid crystal display using amorphous germanium, the heat treatment in the production step is currently up to about 350 °C. In this case, the heat resistance of the wiring film can be ensured by using a wiring film in which an Al thin film and a high melting point metal thin film are laminated. On the other hand, when a heat treatment of 400 ° C to 600 ° C is included in the manufacturing steps of the element such as low-temperature polysilicon or an oxide semiconductor, interdiffusion occurs between Al and the high-melting-point metal due to the low melting point of Al. The increase in the electric resistance of the Al wiring, the destruction of the Al wiring film due to the hillock in the Al thin film, and the like. In order to avoid such a situation, it is conventionally used in the case of a thin film transistor or the like. A high melting point metal is used as a wiring film.
另外，配線膜所要求的另一重要條件可列舉蝕刻特性。即，要求藉由蝕刻而使配線膜側面成為光滑的錐形形狀。尤其對決定電晶體的性能的閘極電極用配線膜強烈要求該條件。 Further, another important condition required for the wiring film is etching characteristics. That is, it is required to make the side surface of the wiring film smooth by tapping. In particular, this condition is strongly required for a wiring film for a gate electrode which determines the performance of a transistor.
因此，作為難以產生凸起、且電阻率小的薄膜電晶體中可利用的半導體用電極，於專利文獻1中揭示有一種按總量計以超過1.0原子%且為15原子%以下的範圍而含有Nd、Gd、Dy中的一種或兩種以上的Al合金薄膜。該薄膜為具有高達400℃的耐熱性，且於抑制凸起產生的方面優異的耐熱性配線材料。 Therefore, as an electrode for a semiconductor which can be used in a thin film transistor which is less likely to generate a bump and has a small specific resistance, Patent Document 1 discloses a range of more than 1.0 atomic % and 15 atomic % or less in total. An Al alloy thin film containing one or two or more of Nd, Gd, and Dy. This film is a heat resistant wiring material which is excellent in heat resistance up to 400 ° C and which suppresses generation of bumps.
[現有技術文獻] [Prior Art Literature]
[專利文獻] [Patent Literature]
[專利文獻1]日本專利第2733006號公報 [Patent Document 1] Japanese Patent No. 2737006
然而，於將高熔點金屬用於配線膜的情形時，雖然耐熱性優異，但通常電阻率高。另外，專利文獻1實質上是有關於一種以非晶矽作為對象的技術，提出了實現對配線膜形成後的250℃~400℃的加熱步驟的耐熱性及低電阻率。 However, when a high melting point metal is used for a wiring film, although heat resistance is excellent, it is generally high in electrical resistivity. In addition, Patent Document 1 is a technique related to amorphous ruthenium, and has proposed heat resistance and low electrical resistivity in a heating step of 250° C. to 400° C. after formation of a wiring film.
雖然要求具有500℃以上且600℃以下的更高耐熱性、並且不會使製造成本上升、同時蝕刻特性亦不遜於現有材料的配線膜，但並無與該些配線膜有關的報告。 Although it is required to have a higher heat resistance of 500 ° C or more and 600 ° C or less, and the manufacturing cost is not increased, and the etching characteristics are not inferior to the wiring film of the conventional material, there is no report relating to the wiring films.
因此，本發明的目的在於解決所述課題。即，其目的在 於提供一種對於大幅度地超過現有的耐熱溫度極限的500℃以上且600℃以下的熱處理溫度亦具有充分的耐熱性的高耐熱性的配線膜。 Therefore, an object of the present invention is to solve the above problems. That is, its purpose is A wiring film having high heat resistance which has sufficient heat resistance to a heat treatment temperature of 500 ° C or more and 600 ° C or less which greatly exceeds the conventional heat-resistant temperature limit is provided.
另外，本發明的目的亦在於提供一種維持高耐熱性、且亦不存在電阻的增加或凸起產生等的配線膜。 Further, another object of the present invention is to provide a wiring film which maintains high heat resistance and which does not have an increase in electric resistance or generation of projections.
本發明的配線膜的主要對象為平板顯示器(flat panel display)等顯示元件用的配線膜或低溫多晶矽半導體電晶體的閘極電極，但不限定於該些構件，可應用於廣泛的元件的高耐熱性配線膜及濺鍍靶材料。 The main object of the wiring film of the present invention is a wiring film for a display element such as a flat panel display or a gate electrode of a low-temperature polycrystalline semiconductor transistor, but is not limited to these members and can be applied to a wide range of components. Heat resistant wiring film and sputtering target material.
本發明者等人反覆進行潛心研究，結果發現，藉由在特定組成的Al合金層的至少一個面上積層經氮化的Mo層，可解決所述課題，從而完成了本發明。 As a result of intensive studies, the inventors of the present invention have found that the problem can be solved by laminating a nitrided Mo layer on at least one surface of an Al alloy layer having a specific composition, and completed the present invention.
即，本發明是有關於以下的[1]~[3]。 That is, the present invention relates to the following [1] to [3].
[1]一種配線膜，含有Al合金層，且於所述Al合金層的至少一個面上積層有經氮化的Mo層，並且所述配線膜的特徵在於：所述Al合金層以Al作為母材，且含有0.01原子%以上、0.6原子%以下的Nd。 [1] A wiring film comprising an Al alloy layer, and a nitrided Mo layer is laminated on at least one surface of the Al alloy layer, and the wiring film is characterized in that the Al alloy layer is made of Al The base material contains 0.01 atom% or more and 0.6 atom% or less of Nd.
[2]一種配線膜，含有Al合金層，且於所述Al合金層的至少一個面上積層有經氮化的Mo層，並且所述配線膜的特徵在於：所述Al合金層以Al作為母材，且含有0.01原子%以上、0.1原子%以下的Ni及0.01原子%以上、0.1原子%以下的Nd。 [2] A wiring film comprising an Al alloy layer, and a nitrided Mo layer is laminated on at least one surface of the Al alloy layer, and the wiring film is characterized in that the Al alloy layer is made of Al The base material contains 0.01 atom% or more and 0.1 atom% or less of Ni and 0.01 atom% or more and 0.1 atom% or less of Nd.
[3]如所述[1]或[2]所記載的配線膜，其中所述Al合金層的膜厚為100nm以上、1μm以下，且所述經氮化的Mo層的膜厚為5nm以上、200nm以下。 The wiring film according to the above [1], wherein the thickness of the Al alloy layer is 100 nm or more and 1 μm or less, and the film thickness of the nitrided Mo layer is 5 nm or more. , 200nm or less.
根據本發明的具有高耐熱性的配線膜，可提供如下配線膜：即便受到500℃以上且600℃以下的高溫下的熱歷程，亦未見膜的由熱應力所致的應變、特別是大多情況下以凸形狀而出現的凸起的產生，另外，電阻率的上升極小而具有低配線電阻的配線膜；或蝕刻特性亦優異的配線膜。 According to the wiring film having high heat resistance of the present invention, it is possible to provide a wiring film which does not exhibit strain due to thermal stress of the film even when subjected to a heat history at a high temperature of 500 ° C or more and 600 ° C or less. In the case of a bump which is formed in a convex shape, a wiring film having a low wiring resistance and having a low wiring resistance, or a wiring film having excellent etching characteristics.
另外，本發明的配線膜具有500℃以上且600℃以下的大幅度的耐熱溫度容限，故即便於在製造配線膜的步驟中熱處理溫度意外存在波動(例如瞬間的溫度上升)的情形時，配線膜亦不產生問題，可大幅度地提高製造的良率。再者，其原因在於：藉由利用經氮化的Mo層將Al合金層上覆蓋，該經氮化的Mo層作為600℃以下的熱處理中的保護層而發揮功能，並且防止Al合金層與經氮化的Mo層之間的界面反應，防止配線的斷線或電阻上升。 In addition, since the wiring film of the present invention has a large heat-resistant temperature tolerance of 500 ° C or more and 600 ° C or less, even in the case where the heat treatment temperature unexpectedly fluctuates (for example, instantaneous temperature rise) in the step of manufacturing the wiring film, The wiring film does not cause any problem, and the manufacturing yield can be greatly improved. Further, the reason is that the Al alloy layer is covered with a nitrided Mo layer, and the nitrided Mo layer functions as a protective layer in a heat treatment at 600 ° C or lower, and the Al alloy layer is prevented from being The interfacial reaction between the nitrided Mo layers prevents wire breakage or resistance rise.
1‧‧‧基底 1‧‧‧Base
2‧‧‧Al合金層 2‧‧‧Al alloy layer
3‧‧‧MoN 3‧‧‧MoN
圖1為表示本發明的二層配線膜的構成的概念圖。 Fig. 1 is a conceptual diagram showing the configuration of a two-layer wiring film of the present invention.
圖2為表示本發明的三層配線膜的構成的概念圖。 Fig. 2 is a conceptual diagram showing the configuration of a three-layer wiring film of the present invention.
圖3為將本發明的經蝕刻的配線膜依Al合金層的組成而分別示出的剖面的掃描電子顯微鏡(Scanning Electron Microscope， SEM)像。 3 is a scanning electron microscope (Scanning Electron Microscope) showing a cross section of the etched wiring film of the present invention in accordance with the composition of the Al alloy layer. SEM) like.
圖4為將熱處理試驗中配線膜相對於熱處理溫度的電阻率的變化依Al合金層的組成而分別示出的圖表。 4 is a graph showing changes in the resistivity of the wiring film with respect to the heat treatment temperature in the heat treatment test, depending on the composition of the Al alloy layer.
<配線膜> <wiring film>
本發明的配線膜的特徵在於：含有Al合金層，且於所述Al合金層的至少一個面上積層有經氮化的Mo層(以下有時稱為「MoN」)，所述Al合金層以Al作為母材，且含有0.01原子%以上、0.6原子%以下的Nd，或者所述Al合金層以Al作為母材，且含有0.01原子%以上、0.1原子%以下的Ni及0.01原子%以上、0.1原子%以下的Nd。 The wiring film of the present invention includes an Al alloy layer, and a nitrided Mo layer (hereinafter sometimes referred to as "MoN") laminated on at least one surface of the Al alloy layer, the Al alloy layer In the case where Al is used as the base material, and 0.01% by atom or more and 0.6 atom% or less of Nd is contained, or the Al alloy layer contains Al as a base material, and contains 0.01 atom% or more and 0.1 atom% or less of Ni and 0.01 atom% or more. , 0.1 atomic % or less of Nd.
Al合金層主要作為導電層而發揮功能，經氮化的Mo層保護該Al合金層。 The Al alloy layer functions mainly as a conductive layer, and the nitrided Mo layer protects the Al alloy layer.
藉由利用經氮化的Mo層將Al合金層上覆蓋，該經氮化的Mo層作為600℃以下的熱處理中的保護層而發揮功能，並且防止Al合金層與經氮化的Mo層之間的界面反應，防止配線的斷線或電阻上升。 The Al alloy layer is covered with a nitrided Mo layer, and the nitrided Mo layer functions as a protective layer in a heat treatment of 600 ° C or lower, and prevents the Al alloy layer and the nitrided Mo layer. Inter-interface reaction prevents wire breakage or resistance rise.
另外，於將配線膜用作低溫多晶矽半導體電晶體的閘極電極的情形時，MoN 3較佳為積層於Al合金層2的與基底1為相反側的面上，或積層於Al合金層2的兩面上。具體而言，以基底1/Al合金層2/MoN 3(參照圖1)、或基底1/MoN 3/Al合金層2/MoN 3(參照圖2)的順序積層。 Further, in the case where the wiring film is used as a gate electrode of a low-temperature polycrystalline germanium semiconductor transistor, MoN 3 is preferably laminated on the surface of the Al alloy layer 2 opposite to the substrate 1 or laminated on the Al alloy layer 2 On both sides. Specifically, a layer is deposited in the order of the base 1/Al alloy layer 2/MoN 3 (see FIG. 1) or the base 1/MoN 3/Al alloy layer 2/MoN 3 (see FIG. 2).
進而，有時為了將低溫多晶矽的自然氧化膜去除而進行氫氟酸清洗，但於該氫氟酸清洗時閘極電極表面亦曝露於氫氟酸下。此時MoN 3具有保護Al合金層2的功能，故可防止Al合金層2因氫氟酸而膜薄化的情況。 Further, in order to remove the natural oxide film of the low-temperature polycrystalline silicon, hydrofluoric acid cleaning may be performed. However, the surface of the gate electrode is also exposed to hydrofluoric acid during the hydrofluoric acid cleaning. At this time, since MoN 3 has a function of protecting the Al alloy layer 2, it is possible to prevent the Al alloy layer 2 from being thinned by hydrofluoric acid.
Al合金層以Al作為母材，且含有0.01原子%以上、0.6原子%以下的Nd，較佳為含有0.1原子%以上、0.5原子%以下的Nd。另外，於一併含有Nd與Ni的情形時，含有0.01原子%以上、0.1原子%以下的Ni及0.01原子%以上、0.1原子%以下的Nd，較佳為含有0.02原子%以上、0.1原子%以下的Ni及0.04原子%以上、0.1原子%以下的Nd。 The Al alloy layer contains Al as a base material and contains 0.01 atom% or more and 0.6 atom% or less of Nd, and preferably contains 0.1 atom% or more and 0.5 atom% or less of Nd. In addition, when Nd and Ni are contained together, it is preferable to contain 0.01 atom% or more and 0.1 atom% or less of Ni and 0.01 atom% or more and 0.1 atom% or less of Nd, preferably 0.02 atom% or more and 0.1 atom%. The following Ni and 0.04 atom% or more and 0.1 atom% or less of Nd.
藉由以所述範圍含有Nd或Nd及Ni以及與MoN積層，可進一步防止凸起的產生。另外，可使蝕刻特性更良好，或使高溫下的熱處理後的電阻率更低。 By containing Nd or Nd and Ni in the above range and laminating with MoN, the generation of protrusions can be further prevented. In addition, the etching characteristics can be made better, or the electrical resistivity after heat treatment at a high temperature can be made lower.
本發明的配線膜中，可含有Nd以外的稀土元素，其他元素可列舉La、Gd、Y等稀土元素。其中，就耐熱性的方面而言，較佳為La。 The wiring film of the present invention may contain a rare earth element other than Nd, and examples of other elements include rare earth elements such as La, Gd, and Y. Among them, La is preferred in terms of heat resistance.
於Al合金層中含有Nd以外的稀土元素的情形時，Nd與Nd以外的稀土元素的合計成為0.6原子%以下，或者於含有Ni的情形時，Nd與Nd以外的稀土元素的合計成為0.1原子%以下。 When a rare earth element other than Nd is contained in the Al alloy layer, the total of rare earth elements other than Nd and Nd is 0.6 atom% or less, or when Ni is contained, the total of rare earth elements other than Nd and Nd is 0.1 atom. %the following.
除了Al、Nd、Nd以外的稀土元素及Ni以外Al合金層中可含有的其他元素可列舉Cu、Ge、Co、Ti、Ta、Zr、B等。其他元素合計可含有0.01原子%~0.5原子%。再者，Al合金層的剩 餘部分為Al。 Examples of other elements which may be contained in the rare earth element other than Al, Nd, and Nd and the Al alloy layer other than Ni include Cu, Ge, Co, Ti, Ta, Zr, and B. The other elements may contain 0.01 atom% to 0.5 atom% in total. Furthermore, the remaining of the Al alloy layer The remainder is Al.
Al合金層的組成可藉由感應耦合電漿(Inductively Coupled Plasma，ICP)發光光譜法來鑑定。 The composition of the Al alloy layer can be identified by Inductively Coupled Plasma (ICP) luminescence spectroscopy.
就確保耐熱性、防止Mo及Al間的相互擴散而防止電阻上升的方面而言，經氮化的Mo層較佳為氮為23原子%~55原子%，更佳為接近50原子%。除了Mo及氮以外MoN中可含有的其他元素可列舉作為高熔點元素的Nb、Ti、Ta、W等。其他元素合計可含有0.1原子%~20原子%。再者，除了該些元素以外的MoN的剩餘部分為Mo。 The nitrided Mo layer is preferably 23 atom% to 55 atom%, more preferably 50 atom%, in terms of ensuring heat resistance and preventing mutual diffusion between Mo and Al to prevent electric resistance from rising. Other elements which may be contained in MoN other than Mo and nitrogen include Nb, Ti, Ta, W, etc. which are high melting point elements. The other elements may contain 0.1 atom% to 20 atom% in total. Furthermore, the remainder of the MoN other than the elements is Mo.
關於經氮化的Mo層的組成，金屬元素可藉由ICP發光光譜分析法進行鑑定，氮量可藉由歐傑光譜法進行鑑定。 Regarding the composition of the nitrided Mo layer, the metal element can be identified by ICP emission spectrometry, and the amount of nitrogen can be identified by the Oujie spectroscopy.
Al合金層及經氮化的Mo層的最佳膜厚可根據用途或式樣而選擇。有效的膜厚較佳為Al合金層為100nm以上、1μm以下，且經氮化的Mo層為5nm以上、200nm以下。更佳為Al合金層的膜厚為200nm~500nm，MoN的膜厚為20nm~50nm。Al合金層及經氮化的Mo層的膜厚可藉由剖面SEM、二次離子質譜分析法深度分析、剖面穿透式電子顯微鏡觀察等而測定。 The optimum film thickness of the Al alloy layer and the nitrided Mo layer can be selected depending on the application or the form. The effective film thickness is preferably 100 nm or more and 1 μm or less of the Al alloy layer, and the nitrided Mo layer is 5 nm or more and 200 nm or less. More preferably, the film thickness of the Al alloy layer is 200 nm to 500 nm, and the film thickness of MoN is 20 nm to 50 nm. The film thickness of the Al alloy layer and the nitrided Mo layer can be measured by a cross-sectional SEM, a secondary ion mass spectrometry depth analysis, a cross-section transmission electron microscope observation, or the like.
再者，於將經氮化的Mo層積層於Al合金層的兩面上的情形時，所謂所述經氮化的Mo層的膜厚，是指各MoN的厚度。 In the case where the nitrided Mo layer is laminated on both surfaces of the Al alloy layer, the film thickness of the nitrided Mo layer means the thickness of each MoN.
Al合金層及經氮化的Mo層的膜厚可藉由變更濺鍍的電流值或時間、壓力、靶與基板間的距離、氮化的情形時用於濺鍍的氬氣與氮氣的比率等而調整。 The film thickness of the Al alloy layer and the nitrided Mo layer can be changed by changing the current value or time of sputtering, the pressure, the distance between the target and the substrate, and the ratio of argon to nitrogen used for sputtering in the case of nitriding. Wait and adjust.
積層Al合金層及經氮化的Mo層的基底視元件而不同。關於本發明的配線膜，例如於平板顯示器等顯示元件的情形時將玻璃基板或透明電極膜等用作基底，低溫多晶矽半導體電晶體的情形時將閘極絕緣膜等用作基底。 The base of the laminated Al alloy layer and the nitrided Mo layer differs depending on the element. In the case of a wiring film of the present invention, for example, in the case of a display element such as a flat panel display, a glass substrate, a transparent electrode film, or the like is used as a substrate, and in the case of a low-temperature polycrystalline semiconductor transistor, a gate insulating film or the like is used as a substrate.
基底的較佳厚度視元件而不同，通常透明電極的情形時為50nm~100nm左右，閘極絕緣膜的情形時為200nm~500nm左右。 The preferred thickness of the substrate varies depending on the element, and is usually about 50 nm to 100 nm in the case of a transparent electrode and about 200 nm to 500 nm in the case of a gate insulating film.
本發明的配線膜藉由具有Al合金層/MoN的二層膜、或MoN/Al合金層/MoN的三層膜而獲得本發明的效果，故含有該二層膜或三層膜的結構的配線膜的多種變化(variation)亦為本發明的範疇。 The wiring film of the present invention obtains the effect of the present invention by a two-layer film having an Al alloy layer/MoN or a three-layer film of MoN/Al alloy layer/MoN, and thus contains the structure of the two-layer film or the three-layer film. Various variations of the wiring film are also within the scope of the invention.
本發明的配線膜可利用公知的方法而成膜，其中較佳為藉由濺鍍法將Al合金層及經氮化的Mo層成膜。 The wiring film of the present invention can be formed into a film by a known method. Among them, the Al alloy layer and the nitrided Mo layer are preferably formed by sputtering.
即，例如於設定為基底1/Al合金層2/MoN 3的二層膜的情形時，藉由基底1使用既定的材料組成者，利用濺鍍法將Al合金層2成膜，繼而於氮氣環境中將Mo進行反應性濺鍍成膜，可於Al合金層2的與基底1為相反側的面上積層經氮化的Mo膜(MoN 3)，其後利用通常的光微影法形成配線圖案，藉此可形成具有圖1所示的構成的二層配線膜。 That is, for example, in the case of a two-layer film set as the base 1/Al alloy layer 2/MoN 3 , the Al alloy layer 2 is formed into a film by sputtering, and then nitrogen is used by the substrate 1 using a predetermined material composition. In the environment, Mo is subjected to reactive sputtering to form a film, and a nitrided Mo film (MoN 3 ) may be laminated on the surface of the Al alloy layer 2 opposite to the substrate 1 and then formed by a usual photolithography method. The wiring pattern can thereby form a two-layer wiring film having the configuration shown in FIG. 1.
即，藉由適當變更濺鍍靶的組成或進行濺鍍的順序、次數等，可任意地進行Al合金層與MoN的順序變更或積層數的增減、組成不同的多個Al合金層、MoN的積層等，製作所需構成的配線膜。 In other words, by appropriately changing the composition of the sputtering target, the order of the sputtering, the number of times, and the like, it is possible to arbitrarily change the order of the Al alloy layer and the MoN, or increase or decrease the number of layers, and a plurality of Al alloy layers and MoNs having different compositions. A laminate film or the like is formed to form a wiring film of a desired structure.
再者，經氮化的Mo層亦可藉由在形成Mo膜後利用氮電漿進行氮化等而成膜。 Further, the nitrided Mo layer may be formed by nitriding or the like by using a nitrogen plasma after forming a Mo film.
本發明的配線膜藉由採取所述構成，而具有600℃以下的高耐熱性，視Al合金層的組成不同，有時儘管為多層膜，亦可藉由光微影的濕式蝕刻而形成於蝕刻側面上並無凹凸等的光滑的錐形狀的形狀(參照圖3)。此種配線膜的精密加工性尤其為大幅度地影響低溫多晶矽半導體電晶體的特性的閘極電極配線膜所強烈要求的性能，而本發明的配線膜滿足該要求。 The wiring film of the present invention has a high heat resistance of 600 ° C or less by adopting the above configuration, and depending on the composition of the Al alloy layer, it may be formed by wet etching of photolithography, although it is a multilayer film. There is no smooth tapered shape on the etched side surface such as unevenness (see Fig. 3). The precision workability of such a wiring film is particularly a performance strongly required for a gate electrode wiring film which greatly affects the characteristics of a low-temperature polycrystalline semiconductor transistor, and the wiring film of the present invention satisfies this requirement.
<濺鍍靶材料> <sputter target material>
通常於金屬薄膜的成膜時，多使用生產性、控制性、均勻性優異的濺鍍法。本發明的配線膜中的Al合金層及經氮化的Mo層亦設想藉由濺鍍法而成膜。 In general, when a metal thin film is formed, a sputtering method excellent in productivity, controllability, and uniformity is often used. The Al alloy layer and the nitrided Mo layer in the wiring film of the present invention are also assumed to be formed by sputtering.
關於本發明的Al合金層的成膜用，較佳為設定為以Al作為母材且Nd的添加量為0.01原子%以上、0.6原子%以下的Al合金的濺鍍靶材，或者以Al作為母材且含有0.01原子%以上、0.1原子%以下的Ni及0.01原子%以上、0.1原子%以下的Nd的Al合金的濺鍍靶材。 In the film formation of the Al alloy layer of the present invention, it is preferable to use a sputtering target of Al alloy in which Al is used as a base material and the amount of Nd added is 0.01 atom% or more and 0.6 atom% or less, or Al is used. The base material further contains a sputtering target of 0.01 atom% or more and 0.1 atom% or less of Ni and an atomic alloy of 0.01 atom% or more and 0.1 atom% or less of Nd.
如上文所述，關於經氮化的Mo層的成膜，大多情況下進行於氮氣環境中濺鍍Mo的反應性濺鍍。關於MoN的結晶結構，至少六種結構已為人所知，使用反應性濺鍍法所成膜的MoN為該些結晶結構混合的多晶材料，進而未反應的Mo結晶或非晶質結構亦散佈。此種狀態依存於所使用的濺鍍裝置、濺鍍條件、基 底材料等。 As described above, in the film formation of the nitrided Mo layer, reactive sputtering of Mo is sputtered in a nitrogen atmosphere. Regarding the crystal structure of MoN, at least six structures are known, and the MoN formed by the reactive sputtering method is a polycrystalline material in which the crystal structures are mixed, and the unreacted Mo crystal or amorphous structure is also spread. This state depends on the sputtering device used, the sputtering conditions, and the basis. Bottom material, etc.
因此，為了獲得最佳的經氮化的Mo層，實際上必須變更濺鍍條件、特別是N2/Ar的比來進行成膜，並進行特性評價。再者，如上文所述，經氮化的Mo層較佳為氮為23原子%~55原子%，更佳為接近50原子%。即，經氮化的Mo層中N/Mo的原子量比大致在0.3~1.2的範圍內，大多的情況下可認為是接近1的值。 Therefore, in order to obtain an optimum nitrided Mo layer, it is actually necessary to change the sputtering conditions, particularly the ratio of N 2 /Ar, to form a film, and to evaluate the characteristics. Further, as described above, the nitrided Mo layer preferably has a nitrogen content of 23 atom% to 55 atom%, more preferably nearly 50 atom%. That is, the atomic ratio of N/Mo in the nitrided Mo layer is approximately in the range of 0.3 to 1.2, and in many cases, it is considered to be a value close to 1.
[實施例] [Examples]
以下，列舉實施例對本發明加以更具體說明，但本發明不限定於該些實施例，可於可符合本發明的主旨的範圍內加以變更而實施，該些例子均包含於本發明的技術範圍內。 The present invention will be more specifically described by the following examples, but the present invention is not limited thereto, and may be modified within the scope of the gist of the present invention, and the examples are all included in the technical scope of the present invention. Inside.
於以下的實施例中，對將基底設為玻璃基板、於該玻璃基板上積層Al合金層及經氮化的Mo層而成的配線膜加以描述。根據發明者等人迄今為止的經驗，在各種情況下亦多次確認到，該些實驗中所得的最佳條件在將配線膜用作低溫多晶矽薄膜電晶體的閘極電極的情形時亦最佳。 In the following examples, a wiring film in which a substrate is a glass substrate, and an Al alloy layer and a nitrided Mo layer are laminated on the glass substrate will be described. According to the experience of the inventors and the like so far, it has been confirmed many times in various cases that the optimum conditions obtained in these experiments are also optimal in the case where the wiring film is used as a gate electrode of a low-temperature polycrystalline germanium film transistor. .
[實施例1-1] [Example 1-1]
於玻璃基板上，自基板側起依序藉由磁控濺鍍法以300nm的膜厚將含有0.6原子%的Nd的Al合金層成膜。繼而，藉由使用利用Ar氣體將N2氣體稀釋至約13%的混合氣體的反應性濺鍍法積層MoN。濺鍍條件如下。 On the glass substrate, an Al alloy layer containing 0.6 at% of Nd was formed into a film by a magnetron sputtering method at a film thickness of 300 nm from the substrate side. Then, MoN was deposited by reactive sputtering using a mixed gas in which N 2 gas was diluted to about 13% with Ar gas. The sputtering conditions are as follows.
(濺鍍條件) (sputter condition)
成膜裝置：直流(Direct Current，DC)磁控濺鍍裝置 Film forming device: Direct Current (DC) magnetron sputtering device
靶尺寸：4吋徑×5mm厚 Target size: 4吋 diameter × 5mm thick
Ar氣壓：2mTorr Ar pressure: 2mTorr
DC功率：250W DC power: 250W
極間距離：100mm Distance between poles: 100mm
基板溫度：室溫 Substrate temperature: room temperature
繼而，藉由光微影及蝕刻而形成10μm寬的線與間距圖案。蝕刻液是使用硝酸濃度1.9%的磷酸-醋酸-硝酸(Phosphoric-Acetic-Nitric Acids，PAN)蝕刻劑。將蝕刻後的MoN/Al-0.6Nd膜的剖面SEM照片示於圖3中。藉此，將Al合金層與經氮化的Mo層一起蝕刻，得知側面成為光滑的錐形狀。 Then, a line and pitch pattern of 10 μm width is formed by photolithography and etching. The etching solution was a Phosphoric-Acetic-Nitric Acids (PAN) etchant having a nitric acid concentration of 1.9%. A cross-sectional SEM photograph of the etched MoN/Al-0.6Nd film is shown in FIG. Thereby, the Al alloy layer was etched together with the nitrided Mo layer, and it was found that the side surface became a smooth tapered shape.
除了將Al合金層的組成設為純Al層(以下表述作p-Al)、Al-0.2Nd層、Al-2Nd層或Al-0.02Ni-0.04La層以外，與實施例1-1同樣地製作配線膜，進行蝕刻。將蝕刻後的配線膜的剖面SEM照片示於圖3中。 The same procedure as in Example 1-1 except that the composition of the Al alloy layer was a pure Al layer (hereinafter referred to as p-Al), an Al-0.2 Nd layer, an Al-2 Nd layer, or an Al-0.02Ni-0.04La layer. A wiring film is formed and etched. A cross-sectional SEM photograph of the wiring film after etching is shown in FIG.
結果，p-Al的蝕刻形狀為MoN以房檐狀而殘留，相對於此，Al-0.6Nd及Al-0.2Nd顯示出良好的錐形形狀。比較例1般的形狀的情況下，有時會有積層於電極上的保護膜的覆蓋(coverage)惡化的情形，故欠佳。 As a result, the etching shape of p-Al was such that MoN remained in the shape of an eaves, whereas Al-0.6Nd and Al-0.2Nd showed a good tapered shape. In the case of the shape of the comparative example 1, the coverage of the protective film laminated on the electrode may be deteriorated, which is not preferable.
[熱處理試驗] [heat treatment test]
將於氮氣環境中對實施例1-1、實施例1-2、參考例1-1、參考例1-2及比較例1中製作的配線膜於500℃、550℃或600℃下 進行20分鐘熱處理時的熱處理溫度與電阻率的關係示於圖4及表1中。 The wiring films prepared in Example 1-1, Example 1-2, Reference Example 1-1, Reference Example 1-2, and Comparative Example 1 were placed at 500 ° C, 550 ° C or 600 ° C in a nitrogen atmosphere. The relationship between the heat treatment temperature and the specific resistance at the time of heat treatment for 20 minutes is shown in Fig. 4 and Table 1.
電阻率是使用四探針薄片電阻測定器進行測定而算出，膜厚是利用觸針式階差計進行測定而算出。 The specific resistance was calculated by measurement using a four-probe sheet resistance measuring instrument, and the film thickness was measured by a stylus type step meter.
結果，藉由進行熱處理而電阻率降低，於溫度為500℃~600℃的範圍內，各Al合金層的組成的情況下，配線膜的電阻率大致一定。MoN/Al-2Nd的熱處理後的電阻率稍高於MoN/p-Al，除此以外的配線膜成為低於MoN/p-Al的結果。 As a result, the specific resistance is lowered by the heat treatment, and the resistivity of the wiring film is substantially constant in the case of the composition of each Al alloy layer in the range of the temperature of 500 ° C to 600 ° C. The resistivity after heat treatment of MoN/Al-2Nd was slightly higher than that of MoN/p-Al, and the wiring film other than this was lower than that of MoN/p-Al.
另外，對此時的10μm線與間距的圖案的表面進行SEM觀察，研究凸起的有無。凸起的有無是使用光學顯微鏡於諾馬斯基(Nomarski)型微分干涉及倍率400倍的條件下測定。 Further, SEM observation was performed on the surface of the pattern of 10 μm line and pitch at this time, and the presence or absence of the protrusion was examined. The presence or absence of the bulge was measured using an optical microscope under the condition that the Nomarski type differential dryness involved a magnification of 400 times.
將結果彙總於表2中。 The results are summarized in Table 2.
MoN/p-Al的情形時，於熱處理溫度為500℃的時刻產生凸起，確認到耐熱性低。MoN/Al-0.2Nd的情形時，於500℃時未見凸起，但於550℃以上產生凸起。MoN/Al-0.6Nd及MoN/Al-2Nd的情況下，於600℃以下未產生凸起。另外，MoN/Al-0.02Ni-0.04La 的情形時，於550℃以下未見凸起，於600℃時以對面板的影響可忽視的程度的密度而確認到產生凸起。 In the case of MoN/p-Al, bumps were generated at the time of heat treatment temperature of 500 ° C, and it was confirmed that heat resistance was low. In the case of MoN/Al-0.2Nd, no protrusion was observed at 500 ° C, but protrusion was generated at 550 ° C or higher. In the case of MoN/Al-0.6Nd and MoN/Al-2Nd, no protrusion was generated below 600 °C. In addition, MoN/Al-0.02Ni-0.04La In the case of the case, no protrusion was observed at 550 ° C or lower, and at 600 ° C, it was confirmed that the protrusion was generated at a density which was negligible to the influence of the panel.
對本發明詳細且參照特定的實施態樣進行了說明，但本領域技術人員明確，可於不偏離本發明的精神及範圍的情況下加以各種變更或修正。本申請案是基於2015年11月13日提出申請的日本專利申請案(日本專利特願2015-222872)，將其內容以參照的方式併入至本文中。 The present invention has been described in detail with reference to the specific embodiments thereof, and it is obvious to those skilled in the art that various changes or modifications may be made without departing from the spirit and scope of the invention. The present application is based on Japanese Patent Application No. 2015-222872, filed on Jan.
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| JP2015-222872 | 2015-11-13 | ||
| JP2015222872A JP2017092330A (en) | 2015-11-13 | 2015-11-13 | Wiring film for device |
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| TW201723227A TW201723227A (en) | 2017-07-01 |
| TWI654339B true TWI654339B (en) | 2019-03-21 |
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| JP4044383B2 (en) * | 2002-07-19 | 2008-02-06 | 株式会社神戸製鋼所 | Manufacturing method of semiconductor device electrode / wiring |
| JP4729661B2 (en) * | 2003-07-11 | 2011-07-20 | 奇美電子股▲ふん▼有限公司 | Aluminum layer free from hillocks and method for forming the same |
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