JP2017092330A - Wiring film for device - Google Patents
Wiring film for device Download PDFInfo
- Publication number
- JP2017092330A JP2017092330A JP2015222872A JP2015222872A JP2017092330A JP 2017092330 A JP2017092330 A JP 2017092330A JP 2015222872 A JP2015222872 A JP 2015222872A JP 2015222872 A JP2015222872 A JP 2015222872A JP 2017092330 A JP2017092330 A JP 2017092330A
- Authority
- JP
- Japan
- Prior art keywords
- alloy layer
- wiring film
- layer
- atomic
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 72
- 239000000463 material Substances 0.000 claims abstract description 14
- 238000007669 thermal treatment Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 97
- 239000010408 film Substances 0.000 description 84
- 238000010438 heat treatment Methods 0.000 description 16
- 239000010409 thin film Substances 0.000 description 14
- 239000000203 mixture Substances 0.000 description 12
- 238000004544 sputter deposition Methods 0.000 description 12
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 11
- 229910052779 Neodymium Inorganic materials 0.000 description 11
- 238000005530 etching Methods 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 9
- VZSRBBMJRBPUNF-UHFFFAOYSA-N 2-(2,3-dihydro-1H-inden-2-ylamino)-N-[3-oxo-3-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)propyl]pyrimidine-5-carboxamide Chemical compound C1C(CC2=CC=CC=C12)NC1=NC=C(C=N1)C(=O)NCCC(N1CC2=C(CC1)NN=N2)=O VZSRBBMJRBPUNF-UHFFFAOYSA-N 0.000 description 8
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 8
- 239000000758 substrate Substances 0.000 description 8
- AFCARXCZXQIEQB-UHFFFAOYSA-N N-[3-oxo-3-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)propyl]-2-[[3-(trifluoromethoxy)phenyl]methylamino]pyrimidine-5-carboxamide Chemical compound O=C(CCNC(=O)C=1C=NC(=NC=1)NCC1=CC(=CC=C1)OC(F)(F)F)N1CC2=C(CC1)NN=N2 AFCARXCZXQIEQB-UHFFFAOYSA-N 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 229910052761 rare earth metal Inorganic materials 0.000 description 6
- 238000005477 sputtering target Methods 0.000 description 6
- 239000007789 gas Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 229910052757 nitrogen Inorganic materials 0.000 description 5
- 239000013077 target material Substances 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 238000005546 reactive sputtering Methods 0.000 description 4
- 239000003870 refractory metal Substances 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 239000012299 nitrogen atmosphere Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910052688 Gadolinium Inorganic materials 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004993 emission spectroscopy Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000005121 nitriding Methods 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052692 Dysprosium Inorganic materials 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000007865 diluting Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021424 microcrystalline silicon Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 238000001878 scanning electron micrograph Methods 0.000 description 1
- 238000000682 scanning probe acoustic microscopy Methods 0.000 description 1
- 230000008685 targeting Effects 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
Abstract
Description
本発明は、高耐熱性を有するデバイス用配線膜に関する。 The present invention relates to a device wiring film having high heat resistance.
液晶ディスプレイ、有機ＥＬディスプレイ、タッチパネルなどの表示デバイスの電極材料に用いられる配線膜には、電気抵抗率が低く、微細加工が容易であるという特長を利用してＡｌ薄膜やＡｌを母材としたＡｌ合金薄膜が使用されている。 Wiring films used as electrode materials for display devices such as liquid crystal displays, organic EL displays, and touch panels have an Al thin film or Al as the base material, taking advantage of their low electrical resistivity and easy microfabrication. An Al alloy thin film is used.
一方でＡｌの融点は６６０℃と低いことから、これらＡｌ薄膜やＡｌ合金薄膜の耐熱性の向上が課題となっている。とくに上記のディスプレイやタッチパネルの高精細化・高集積化が進むにつれて配線膜も細線化していることに伴い、デバイス稼働時における配線膜のオーミック抵抗による温度上昇に起因する断線防止等のための配線膜の高耐熱性は極めて重要である。またパワーデバイスの大容量化に対応する際にも、同様の課題がある。 On the other hand, since the melting point of Al is as low as 660 ° C., improving the heat resistance of these Al thin films and Al alloy thin films has been an issue. Wiring to prevent disconnection due to temperature rise due to ohmic resistance of the wiring film during device operation, especially as the above-mentioned displays and touch panels are becoming finer and more integrated, and the wiring film is becoming thinner. High heat resistance of the film is extremely important. Also, there is a similar problem when dealing with the increase in capacity of power devices.
また、例えば液晶ディスプレイ用の低温ポリシリコン半導体は、従来、アモルファスシリコンや微結晶シリコンの半導体薄膜を用いて、５００〜６００℃の結晶化アニールや不純物注入後の活性化アニールなどの熱処理工程が含まれる。これに対し近年では、前記結晶化アニールおよび活性化アニールを４００〜５００℃で実施する技術が開発されている。 Further, for example, low-temperature polysilicon semiconductors for liquid crystal displays conventionally include heat treatment steps such as crystallization annealing at 500 to 600 ° C. and activation annealing after impurity implantation using a semiconductor thin film of amorphous silicon or microcrystalline silicon. It is. On the other hand, in recent years, a technique for performing the crystallization annealing and the activation annealing at 400 to 500 ° C. has been developed.
アモルファスシリコンを用いた薄膜トランジスタにおいては、製造工程における熱処理は従来最高で３５０℃程度であった。この場合、Ａｌ薄膜と高融点金属薄膜を積層した配線膜を用いることで、配線膜の耐熱性を確保することができた。これに対し、低温ポリシリコンや酸化物半導体のように４００〜６００℃の熱処理がデバイスの製造工程に含まれる場合、Ａｌの融点が低いことに起因してＡｌと高融点金属の間に相互拡散が生じ、Ａｌ配線の電気抵抗の増大、Ａｌ薄膜にヒロックが発生することによるＡｌ配線膜の破壊などが生じる。これらを回避するために、従来は配線膜として高融点金属が使われていた。 In a thin film transistor using amorphous silicon, the heat treatment in the manufacturing process is conventionally about 350 ° C. at the maximum. In this case, the heat resistance of the wiring film could be ensured by using a wiring film in which an Al thin film and a refractory metal thin film were laminated. On the other hand, when 400-600 ° C heat treatment is included in the device manufacturing process, such as low-temperature polysilicon or oxide semiconductor, interdiffusion between Al and refractory metal due to the low melting point of Al. As a result, the electrical resistance of the Al wiring is increased, and the Al wiring film is destroyed due to hillocks generated in the Al thin film. In order to avoid these problems, a refractory metal has conventionally been used as a wiring film.
また、配線膜に要求されるもう一つの重要な要件として、エッチング特性が挙げられる。すなわちエッチングにより配線膜側面が滑らかなテーパー形状になることが要求される。この要件は、とくにトランジスタの性能を決めるゲート電極用配線膜に対して強く求められる。 Another important requirement for wiring films is etching characteristics. That is, it is required that the side surface of the wiring film has a smooth tapered shape by etching. This requirement is strongly demanded especially for the gate electrode wiring film that determines the performance of the transistor.
そこで、ヒロックが生じ難く、かつ、比抵抗が小さい薄膜トランジスタに利用可能な半導体用電極として、特許文献１にはＮｄ、Ｇｄ、Ｄｙのうちの１種又は２種以上を総量で１．０原子％超、１５原子％以下の範囲で含有するＡｌ合金薄膜が開示されている。該薄膜は４００℃までの耐熱性を有し、かつ、ヒロック発生抑止に優れた耐熱性配線材料である。 Therefore, Patent Document 1 discloses that one or more of Nd, Gd, and Dy is 1.0 atomic% in total as an electrode for a semiconductor that can be used for a thin film transistor that hardly causes hillocks and has a low specific resistance. There has been disclosed an Al alloy thin film that is contained in an amount exceeding 15 atomic%. The thin film is a heat resistant wiring material having heat resistance up to 400 ° C. and excellent in suppressing hillock generation.
しかしながら高融点金属を配線膜に使用する場合、耐熱性に優れるものの、一般的に電気抵抗率が高く、エネルギーロスが大きい。また特許文献１は、実質的にアモルファスシリコンを対象とした技術に関するもので、配線膜形成後の２５０〜４００℃の加熱工程に対する耐熱性および低抵抗率の実現を提案したものである。
また、５００℃以上６００℃以下というより一層高い耐熱性を有しつつ、製造コストを上昇させることなく、同時にエッチング特性に関しても従来材料に劣らない配線膜が要求されているものの、それらに関する報告はなされていない。
However, when a refractory metal is used for a wiring film, although it has excellent heat resistance, it generally has a high electrical resistivity and a large energy loss. Patent Document 1 relates to a technique substantially targeting amorphous silicon, and proposes the realization of heat resistance and low resistivity for a heating process at 250 to 400 ° C. after the formation of the wiring film.
In addition, while having higher heat resistance of 500 ° C. or more and 600 ° C. or less, a wiring film that is not inferior to conventional materials is also required with respect to etching characteristics without increasing the manufacturing cost, but there are reports on them. Not done.
そこで本発明は上記の課題を解決することを目的とするものである。すなわち、従来の耐熱温度限界を大幅に超える５００℃以上６００℃以下といった熱処理温度に対しても十分な耐熱性を有する高耐熱性のデバイス用配線膜を提供することを目的とする。
また、配線膜の組成によっては、高耐熱性を維持しつつ、電気抵抗の増加やヒロック発生などもないデバイス用配線膜を提供することも目的とする。
本発明に係る配線膜の主たる対象は、フラットパネル・ディスプレイ等の表示デバイス用の配線膜や低温ポリシリコン半導体トランジスタのゲート電極であるが、これらに限定されることなく、広範なデバイスの高耐熱性配線膜およびスパッタリングターゲット材料に適用できる。
Therefore, the present invention aims to solve the above problems. That is, an object of the present invention is to provide a highly heat resistant device wiring film having sufficient heat resistance even at a heat treatment temperature of 500 ° C. or more and 600 ° C. or less, which greatly exceeds the conventional heat resistant temperature limit.
Another object of the present invention is to provide a wiring film for a device that maintains high heat resistance and does not increase electric resistance or generate hillocks depending on the composition of the wiring film.
The main object of the wiring film according to the present invention is a wiring film for a display device such as a flat panel display and a gate electrode of a low-temperature polysilicon semiconductor transistor. Applicable to conductive wiring films and sputtering target materials.
本発明者らは、鋭意研究を重ねた結果、特定組成のＡｌ合金層の少なくとも一方の面に窒化されたＭｏ層を積層することにより上記課題を解決できることを見出し、本発明を完成するに至った。 As a result of extensive research, the present inventors have found that the above problem can be solved by laminating a nitrided Mo layer on at least one surface of an Al alloy layer having a specific composition, and the present invention has been completed. It was.
すなわち、本発明は、以下の［１］〜［３］に係るものである。
［１］ Ａｌ合金層を含み、前記Ａｌ合金層の少なくとも一方の面に窒化されたＭｏ層が積層されたデバイス用配線膜であって、前記Ａｌ合金層がＡｌを母材とし、Ｎｄを０．０１原子％以上、０．６原子％以下含むことを特徴とするデバイス用配線膜。
［２］ Ａｌ合金層を含み、前記Ａｌ合金層の少なくとも一方の面に窒化されたＭｏ層が積層されたデバイス用配線膜であって、前記Ａｌ合金層がＡｌを母材とし、Ｎｉを０．０１原子％以上、０．１原子％以下、及びＮｄを０．０１原子％以上、０．１原子％以下含むことを特徴とするデバイス用配線膜。
［３］ 前記Ａｌ合金層の膜厚が１００ｎｍ以上、１μｍ以下であり、かつ、前記窒化されたＭｏ層の膜厚が５ｎｍ以上、２００ｎｍ以下であることを特徴とする前記［１］又は［２］に記載のデバイス用配線膜。
That is, the present invention relates to the following [1] to [3].
[1] A device wiring film including an Al alloy layer, and a nitrided Mo layer is laminated on at least one surface of the Al alloy layer, wherein the Al alloy layer uses Al as a base material and Nd is 0 A wiring film for a device characterized by containing 0.01 atomic% or more and 0.6 atomic% or less.
[2] A wiring film for a device including an Al alloy layer, wherein a nitrided Mo layer is laminated on at least one surface of the Al alloy layer, wherein the Al alloy layer has Al as a base material and Ni is 0 A device wiring film comprising 0.01 atomic% or more and 0.1 atomic% or less and Nd of 0.01 atomic% or more and 0.1 atomic% or less.
[3] The above [1] or [2], wherein the Al alloy layer has a thickness of 100 nm to 1 μm, and the nitrided Mo layer has a thickness of 5 nm to 200 nm. ] The wiring film for devices as described in above.
本発明によれば、５００℃以上６００℃以下の高温での熱履歴を受けてもヒロック（膜の熱応力による歪み、とくに凸形状として出現することが多い）等の発生が認められない、実用的な高耐熱性を有するデバイス用配線膜を提供することができる。また、配線膜の組成によっては、電気抵抗率の上昇が極めて小さく低配線抵抗を有するデバイス用配線膜や、エッチング特性にも優れたデバイス用配線膜を提供することができる。
また、本発明に係る配線膜は５００℃以上６００℃以下といった大幅な耐熱温度マージンを有することから、配線膜を製造する工程で万一熱処理温度に揺らぎ（例えば瞬間的な温度上昇）があった場合でも配線膜に問題が生じず、製造の歩留まりを大幅に向上することができる。
According to the present invention, even when subjected to a thermal history at a high temperature of 500 ° C. or higher and 600 ° C. or lower, generation of hillocks (distortion due to thermal stress of the film, particularly often appearing as a convex shape) is not observed, A device wiring film having high heat resistance can be provided. In addition, depending on the composition of the wiring film, it is possible to provide a device wiring film having an extremely small increase in electrical resistivity and a low wiring resistance, and a device wiring film excellent in etching characteristics.
In addition, since the wiring film according to the present invention has a large heat-resistant temperature margin of 500 ° C. or more and 600 ° C. or less, the heat treatment temperature fluctuates (for example, instantaneous temperature rise) in the process of manufacturing the wiring film. Even in this case, there is no problem in the wiring film, and the manufacturing yield can be greatly improved.
＜デバイス用配線膜＞
本発明に係るデバイス用配線膜はＡｌ合金層を含み、前記Ａｌ合金層の少なくとも一方の面に窒化されたＭｏ層（以下、「ＭｏＮ」と称することがある。）が積層され、前記Ａｌ合金層がＡｌを母材とし、Ｎｄを０．０１原子％以上、０．６原子％以下含む、又は、前記Ａｌ合金層がＡｌを母材とし、Ｎｉを０．０１原子％以上、０．１原子％以下、及びＮｄを０．０１原子％以上、０．１原子％以下含むことを特徴とする。
Ａｌ合金層は主たる電気伝導層として機能し、窒化されたＭｏ層は該Ａｌ合金層を保護するものである。
<Device wiring film>
The device wiring film according to the present invention includes an Al alloy layer, and a nitrided Mo layer (hereinafter also referred to as “MoN”) is laminated on at least one surface of the Al alloy layer, and the Al alloy is laminated. The layer includes Al as a base material and includes Nd of 0.01 atomic% or more and 0.6 atomic% or less, or the Al alloy layer includes Al as a base material and Ni includes 0.01 atomic% or more, 0.1 It is characterized by containing not more than atomic% and Nd not less than 0.01 atomic% and not more than 0.1 atomic%.
The Al alloy layer functions as a main electrically conductive layer, and the nitrided Mo layer protects the Al alloy layer.
Ａｌ合金層上を窒化されたＭｏ層でキャップすることで、該窒化されたＭｏ層が６００℃以下の熱処理における保護層として機能するとともに、Ａｌ合金層と窒化されたＭｏ層の間の界面反応を防ぎ、配線の断線や抵抗上昇を防ぐことができる。 By capping the Al alloy layer with a nitrided Mo layer, the nitrided Mo layer functions as a protective layer in heat treatment at 600 ° C. or lower, and the interface reaction between the Al alloy layer and the nitrided Mo layer It is possible to prevent disconnection of wiring and increase in resistance.
また、配線膜を低温ポリシリコン半導体トランジスタのゲート電極として用いる場合等において、ＭｏＮは、Ａｌ合金層の下地とは反対側の面に積層されていること、又は、Ａｌ合金層の両面に積層されていることが好ましい。具体的には、下地／Ａｌ合金層／ＭｏＮ、又は、下地／ＭｏＮ／Ａｌ合金層／ＭｏＮの順に積層される。
低温ポリシリコンの自然酸化膜を除去する目的でフッ酸洗浄を行うことがあるが、該フッ酸洗浄時にゲート電極表面もフッ酸に曝される。その際にＭｏＮがＡｌ合金層を保護する役割があるため、Ａｌ合金層がフッ酸によって膜減りすることを防ぐことができる。
Also, when the wiring film is used as a gate electrode of a low-temperature polysilicon semiconductor transistor, MoN is laminated on the surface opposite to the base of the Al alloy layer, or laminated on both surfaces of the Al alloy layer. It is preferable. Specifically, the layers are laminated in the order of underlayer / Al alloy layer / MoN or underlayer / MoN / Al alloy layer / MoN.
Hydrofluoric acid cleaning may be performed for the purpose of removing a natural oxide film of low-temperature polysilicon, and the surface of the gate electrode is also exposed to hydrofluoric acid during the hydrofluoric acid cleaning. At that time, since MoN has a role of protecting the Al alloy layer, the Al alloy layer can be prevented from being reduced by hydrofluoric acid.
Ａｌ合金層は、Ａｌを母材とし、Ｎｄを０．０１原子％以上、０．６原子％以下含むが、０．１原子％以上、０．５原子％以下含むことが好ましい。またＮｄとＮｉを共に含む場合は、Ｎｉを０．０１原子％以上、０．１原子％以下、及びＮｄを０．０１原子％以上、０．１原子％以下含むが、Ｎｉを０．０２原子％以上、０．１原子％以下、及びＮｄを０．０４原子％以上、０．１原子％以下含むことが好ましい。
Ｎｄ又はＮｄ及びＮｉを上記範囲で含むことにより、高温熱処理によってもヒロック（膜の熱応力による変形、凸状の形状が見られる場合が多い）の発生をより防ぐことができる。また、エッチング特性をより良好なものとしたり、高温での熱処理後の電気抵抗率をより低いものとすることができる。
The Al alloy layer contains Al as a base material and contains Nd in an amount of 0.01 atomic% to 0.6 atomic%, but preferably includes 0.1 atomic% to 0.5 atomic%. When both Nd and Ni are contained, Ni is contained in an amount of 0.01 atomic% or more and 0.1 atomic% or less, and Nd is contained in an amount of 0.01 atomic% or more and 0.1 atomic% or less. It is preferable to contain not less than atomic percent and not more than 0.1 atomic percent, and Nd not less than 0.04 atomic percent and not more than 0.1 atomic percent.
By including Nd or Nd and Ni in the above range, the occurrence of hillocks (deformation due to thermal stress of the film, often having a convex shape) can be further prevented even by high-temperature heat treatment. Further, the etching characteristics can be made better, and the electrical resistivity after the heat treatment at high temperature can be made lower.
本発明に係るデバイス用配線膜には、Ｎｄ以外の希土類元素が含まれていてもよいが、その他の希土類元素としては、Ｌａ、Ｇｄ、Ｙ等が挙げられる。中でも耐熱性の点からＬａが好ましい。
Ａｌ合金層にＮｄ以外の希土類元素を含む場合には、ＮｄとＮｄ以外の希土類元素の合計が０．６原子％以下、又は、Ｎｉを含む場合には、ＮｄとＮｄ以外の希土類元素の合計が０．１原子％以下となるようにする。
The device wiring film according to the present invention may contain a rare earth element other than Nd. Examples of other rare earth elements include La, Gd, and Y. Among these, La is preferable from the viewpoint of heat resistance.
When the Al alloy layer contains rare earth elements other than Nd, the total of rare earth elements other than Nd and Nd is 0.6 atomic% or less, or when Ni is contained, the total of rare earth elements other than Nd and Nd Of 0.1 atomic% or less.
Ａｌ、Ｎｄ、Ｎｄ以外の希土類元素及びＮｉ以外にＡｌ合金層に含まれてもよいその他の元素としてＣｕ、Ｇｅ、Ｃｏ、Ｔｉ、Ｔａ、Ｚｒ、Ｂ等が挙げられる。その他の元素は合計で０．０１〜０．５原子％含まれていてもよい。なお、Ａｌ合金層の残部はＡｌである。
Ａｌ合金層の組成はＩＣＰ発光分光法により同定することができる。
Cu, Ge, Co, Ti, Ta, Zr, B, etc. are mentioned as rare earth elements other than Al, Nd, and Nd and other elements that may be included in the Al alloy layer in addition to Ni. Other elements may be contained in a total of 0.01 to 0.5 atomic%. The balance of the Al alloy layer is Al.
The composition of the Al alloy layer can be identified by ICP emission spectroscopy.
窒化されたＭｏ層は窒素が２３〜５５原子％であることが耐熱性の確保と、ＭｏとＡｌ間の相互拡散を防いで低抵抗上昇を防ぐ点から好ましく、５０原子％に近いことがより好ましい。Ｍｏ及び窒素以外にＭｏＮに含まれてもよいその他の元素としてＮｂ、Ｔｉ、Ｔａ、Ｗ等が挙げられる。その他の元素は合計で０．１〜２０原子％含まれていてもよい。なお、これらの元素を除いたＭｏＮの残部はＭｏである。
窒化されたＭｏ層の組成は、金属元素についてはＩＣＰ発光分光分析法、窒素量についてはオージェ分光法により同定することができる。
The nitrided Mo layer preferably has a nitrogen content of 23 to 55 atomic% from the viewpoint of ensuring heat resistance and preventing interdiffusion between Mo and Al to prevent an increase in low resistance, and more preferably close to 50 atomic%. preferable. Other elements that may be contained in MoN besides Mo and nitrogen include Nb, Ti, Ta, W, and the like. Other elements may be contained in a total amount of 0.1 to 20 atomic%. The remainder of MoN excluding these elements is Mo.
The composition of the nitrided Mo layer can be identified by ICP emission spectroscopy for metal elements and Auger spectroscopy for nitrogen content.
Ａｌ合金層と窒化されたＭｏ層の最適な膜厚は用途や仕様により選ぶことができる。効果的な膜厚は、Ａｌ合金層が１００ｎｍ以上、１μｍ以下であり、かつ、窒化されたＭｏ層が５ｎｍ以上、２００ｎｍ以下が好ましい。より好ましくはＡｌ合金層の膜厚は２００ｎｍ〜５００ｎｍであり、ＭｏＮの膜厚は２０ｎｍ〜５０ｎｍである。Ａｌ合金層及び窒化されたＭｏ層の膜厚は断面ＳＥＭ、ＳＩＭＳ深さ分析、断面ＴＥＭ観察等により測定することができる。
なお、窒化されたＭｏ層がＡｌ合金層の両面に積層されている場合、上記窒化されたＭｏ層の膜厚とは、各々のＭｏＮの厚みを意味する。
The optimum film thickness of the Al alloy layer and the nitrided Mo layer can be selected according to the application and specifications. The effective film thickness is preferably 100 nm or more and 1 μm or less for the Al alloy layer, and 5 nm or more and 200 nm or less for the nitrided Mo layer. More preferably, the thickness of the Al alloy layer is 200 nm to 500 nm, and the thickness of MoN is 20 nm to 50 nm. The film thicknesses of the Al alloy layer and the nitrided Mo layer can be measured by cross-sectional SEM, SIMS depth analysis, cross-sectional TEM observation, and the like.
In addition, when the nitrided Mo layer is laminated | stacked on both surfaces of Al alloy layer, the film thickness of the said nitrided Mo layer means the thickness of each MoN.
Ａｌ合金層及び窒化されたＭｏ層の膜厚はスパッタリングの電流値や時間、圧力、ターゲットと基板間の距離、窒化の場合はスパッタに用いるアルゴンガスと窒素ガスの比率等を変更することにより調整することができる。 The film thickness of the Al alloy layer and the nitrided Mo layer is adjusted by changing the sputtering current value, time, pressure, the distance between the target and the substrate, and in the case of nitriding, the ratio of argon gas and nitrogen gas used for sputtering. can do.
Ａｌ合金層と窒化されたＭｏ層を積層する下地はデバイスによって異なる。本発明に係るデバイス用配線膜は、表示デバイス用配線膜として有する表示デバイスや、ゲート電極として有する低温ポリシリコン半導体トランジスタが好ましいデバイスとして挙げられるが、フラットパネル・ディスプレイ等の表示デバイスの場合にはガラス基板や透明電極膜等が用いられ、低温ポリシリコン半導体トランジスタの場合はゲート絶縁膜等が用いられる。
下地の好ましい厚みはデバイスによって異なるが、一般的には透明電極の場合は５０〜１００ｎｍ程度、ゲート絶縁膜の場合は２００〜５００ｎｍ程度である。
The substrate on which the Al alloy layer and the nitrided Mo layer are stacked varies depending on the device. The device wiring film according to the present invention is preferably a display device having a display device wiring film or a low-temperature polysilicon semiconductor transistor having a gate electrode, but in the case of a display device such as a flat panel display. A glass substrate, a transparent electrode film, or the like is used. In the case of a low-temperature polysilicon semiconductor transistor, a gate insulating film or the like is used.
The preferred thickness of the base varies depending on the device, but is generally about 50 to 100 nm for a transparent electrode and about 200 to 500 nm for a gate insulating film.
本発明に係る配線膜はＡｌ合金層／ＭｏＮの２層膜、又はＭｏＮ／Ａｌ合金層／ＭｏＮの３層膜を有することにより本発明の効果を得られることから、該２層膜又は３層膜の構造を含む配線膜の多様なバリエーションも本発明の範疇である。 Since the wiring film according to the present invention has the two-layer film of Al alloy layer / MoN or the three-layer film of MoN / Al alloy layer / MoN, the effect of the present invention can be obtained. Various variations of the wiring film including the film structure are also included in the scope of the present invention.
本発明に係るデバイス用配線膜は公知の方法で成膜することができるが、中でもスパッタ法によりＡｌ合金層及び窒化されたＭｏ層を成膜することが好ましい。
すなわち、例えば下地／Ａｌ合金層／ＭｏＮの２層膜とする場合には、下地に特定の組成のスパッタリングターゲット材料を用いてＡｌ合金層をスパッタ法で成膜し、次いでＭｏを窒素雰囲気中で反応性スパッタ成膜することにより、Ａｌ合金層の下地とは反対側の面に窒化されたＭｏ膜を積層でき、その後、通常のフォトリソグラフィー法で配線パターンを形成することで、図１に示す構成（下地／Ａｌ合金層／ＭｏＮ）を有する２層配線膜が形成できる。
The device wiring film according to the present invention can be formed by a known method, but it is particularly preferable to form an Al alloy layer and a nitrided Mo layer by sputtering.
That is, for example, when a two-layer film of base / Al alloy layer / MoN is used, an Al alloy layer is formed by sputtering using a sputtering target material having a specific composition for the base, and then Mo is deposited in a nitrogen atmosphere. By reactive sputter deposition, a nitrided Mo film can be stacked on the surface opposite to the base of the Al alloy layer, and then a wiring pattern is formed by a normal photolithography method, as shown in FIG. A two-layer wiring film having a configuration (underlayer / Al alloy layer / MoN) can be formed.
すなわち、スパッタリングターゲットの組成やスパッタリングを行う順序、回数等を適宜変更することにより、Ａｌ合金層とＭｏＮの順序変更や、積層数の増減、組成の異なる複数のＡｌ合金層、ＭｏＮの積層等を任意に行い、所望の構成の配線膜を作製することができる。 That is, by appropriately changing the composition of the sputtering target, the order of sputtering, the number of times, etc., the order of Al alloy layers and MoN can be changed, the number of layers can be increased, the number of layers can be increased, the plurality of Al alloy layers can be stacked differently Arbitrarily, a wiring film having a desired configuration can be produced.
なお窒化されたＭｏ層は、Ｍｏ膜を成膜した後に窒素プラズマで窒化すること等によっても成膜することが可能である。 The nitrided Mo layer can also be formed by forming a Mo film and then nitriding with nitrogen plasma.
本発明に係る配線膜は上記の構成を取ることにより、６００℃以下の高耐熱性を有し、Ａｌ合金層の組成によっては、多層膜であるにも関わらず、フォトリソグラフィーにおけるウェットエッチングによりエッチング側面に凹凸等がない、滑らかなテーパー状の形状を形成することができる（図３参照）。このような配線膜の精密な加工性は、とくに低温ポリシリコン半導体トランジスタの特性に大きく影響するゲート電極配線膜に、強く要求されるものであるが、本発明に係る配線膜はこの要求を満たすものである。 The wiring film according to the present invention has a high heat resistance of 600 ° C. or less by adopting the above-described configuration. Depending on the composition of the Al alloy layer, the wiring film is etched by wet etching in photolithography even though it is a multilayer film. A smooth tapered shape with no irregularities on the side surfaces can be formed (see FIG. 3). Such precise processability of the wiring film is strongly demanded particularly for the gate electrode wiring film that greatly affects the characteristics of the low-temperature polysilicon semiconductor transistor, but the wiring film according to the present invention satisfies this requirement. Is.
＜スパッタリングターゲット材料＞
一般に金属薄膜の成膜には、生産性（スループット）・制御性・均一性に優れたスパッタ法が使用されることが多い。本発明に係るデバイス用配線膜におけるＡｌ合金層及び窒化されたＭｏ層もスパッタ法で成膜されることを想定している。
<Sputtering target material>
In general, a sputtering method excellent in productivity (throughput), controllability, and uniformity is often used for forming a metal thin film. It is assumed that the Al alloy layer and the nitrided Mo layer in the device wiring film according to the present invention are also formed by sputtering.
本発明におけるＡｌ合金層の成膜用には、Ａｌを母材とし、Ｎｄの添加量が０．０１原子％以上、０．６原子％以下であるＡｌ合金であるスパッタリングターゲット材、または、Ａｌを母材とし、Ｎｉが０．０１原子％以上、０．１原子％以下およびＮｄが０．０１原子％以上、０．１原子％以下含まれるＡｌ合金であるスパッタリングターゲット材とすることが好ましい。 For the formation of an Al alloy layer in the present invention, a sputtering target material which is an Al alloy having Al as a base material and an Nd addition amount of 0.01 atomic% or more and 0.6 atomic% or less, or Al Is preferably a sputtering target material which is an Al alloy containing Ni in an amount of 0.01 atomic% or more and 0.1 atomic% or less and Nd in an amount of 0.01 atomic% or more and 0.1 atomic% or less. .
前記の通り、窒化されたＭｏ層の成膜には、多くの場合、Ｍｏを窒素雰囲気中で反応性スパッタが行なわれる。窒化されたＭｏ（ＭｏＮ）の結晶構造として少なくとも６つの構造が知られているが、反応性スパッタ法を用いて成膜されたＭｏＮは、これらの結晶構造が混合した多結晶材料であり、さらに未反応のＭｏ結晶や非晶質構造も分散している。このような状態は、使用したスパッタ装置、スパッタ条件、下地材料などに依存する。 As described above, in order to form a nitrided Mo layer, in many cases, reactive sputtering of Mo is performed in a nitrogen atmosphere. At least six structures are known as the crystal structure of nitrided Mo (MoN), but MoN formed by reactive sputtering is a polycrystalline material in which these crystal structures are mixed. Unreacted Mo crystals and amorphous structures are also dispersed. Such a state depends on the sputtering apparatus used, sputtering conditions, base material, and the like.
したがって、最適な窒化されたＭｏ層を得るには、実際にスパッタ条件（とくにＮ２／Ａｒ比）を変えて成膜し、特性評価する必要がある。なお、先述したように、窒化されたＭｏ層は窒素が２３〜５５原子％であることが好ましく、５０原子％に近いことがより好ましい。すなわち、窒化されたＭｏ層ではＮ／Ｍｏの原子量比は概ね０．３〜１．２の範囲にあり、多くの場合、１に近い値であると考えられる。 Therefore, in order to obtain an optimum nitrided Mo layer, it is necessary to actually form a film by changing the sputtering conditions (particularly, the N 2 / Ar ratio) and evaluate the characteristics. As described above, the nitrided Mo layer preferably has a nitrogen content of 23 to 55 atomic%, more preferably close to 50 atomic%. That is, in the nitrided Mo layer, the N / Mo atomic weight ratio is generally in the range of 0.3 to 1.2, and in many cases is considered to be a value close to 1.
以下に、実施例を挙げて本発明をさらに具体的に説明するが、本発明は、これらの実施例に限定されるものではなく、本発明の趣旨に適合し得る範囲で変更を加えて実施することが可能であり、それらはいずれも本発明の技術的範囲に包含される。
以下の実施例では下地をガラス基板とし、該ガラス基板上にＡｌ合金層と窒化されたＭｏ層とを積層した配線膜について述べる。これら実験で得られた最適な条件が、配線膜を低温ポリシリコン薄膜トランジスタのゲート電極として適用した場合でも最適であることは、発明者らのこれまでの経験から様々なケースについて何度も確認されている。
Hereinafter, the present invention will be described in more detail with reference to examples. However, the present invention is not limited to these examples, and may be implemented with modifications within a range that can be adapted to the gist of the present invention. All of which are within the scope of the present invention.
In the following examples, a wiring film in which an underlayer is a glass substrate and an Al alloy layer and a nitrided Mo layer are stacked on the glass substrate will be described. It has been confirmed many times in various cases from the inventors' experience that the optimum conditions obtained in these experiments are optimum even when the wiring film is applied as a gate electrode of a low-temperature polysilicon thin film transistor. ing.
［実施例１−１］
ガラス基板上に、基板側から順に、Ｎｄを０．６原子％含有するＡｌ合金層（Ａｌ−０．６Ｎｄ）をマグネトロンスパッタ法により膜厚３００ｎｍで成膜した。次いでＮ２ガスをＡｒガスで約１３％に希釈した混合ガスを用いた反応性スパッタ法により窒化されたＭｏ層（ＭｏＮ）を積層した。スパッタリング条件は以下の通りである。
[Example 1-1]
On the glass substrate, an Al alloy layer (Al-0.6Nd) containing 0.6 atomic% of Nd was formed in order from the substrate side with a film thickness of 300 nm by a magnetron sputtering method. Next, a Mo layer (MoN) nitrided by reactive sputtering using a mixed gas obtained by diluting N 2 gas with Ar gas to about 13% was stacked. The sputtering conditions are as follows.
（スパッタリング条件）
成膜装置：ＤＣマグネトロンスパッタ装置
ターゲットサイズ：４インチ径×５ｍｍ厚
Ａｒガス圧：２ｍＴｏｒｒ
ＤＣパワー：２５０Ｗ
極間距離：１００ｍｍ
基板温度：室温
(Sputtering conditions)
Deposition apparatus: DC magnetron sputtering apparatus Target size: 4 inch diameter x 5 mm thickness Ar gas pressure: 2 mTorr
DC power: 250W
Distance between electrodes: 100mm
Substrate temperature: room temperature
次に、フォトリソグラフィーおよびエッチングにより、１０μｍ幅のラインアンドスペースパターンを形成した。エッチング液には硝酸濃度１．９％のＰＡＮエッチャントを用いた。エッチング後の配線膜（ＭｏＮ／Ａｌ−０．６Ｎｄ）の断面ＳＥＭ写真を図３に示す。これにより、Ａｌ合金層と窒化されたＭｏ層が一括してエッチングされ、側面が滑らかなテーパー状となっていることが分かる。 Next, a line and space pattern having a width of 10 μm was formed by photolithography and etching. As the etching solution, a PAN etchant having a nitric acid concentration of 1.9% was used. A cross-sectional SEM photograph of the wiring film (MoN / Al-0.6Nd) after etching is shown in FIG. As a result, it can be seen that the Al alloy layer and the nitrided Mo layer are etched together, and the side surface has a smooth taper shape.
［比較例１、実施例１−２、参考例１−１及び参考例１−２］
Ａｌ合金層の組成を純Ａｌ層（ｐ−Ａｌ）（比較例１）、Ｎｄを０．２原子％含有するＡｌ合金層（Ａｌ−０．２Ｎｄ）（実施例１−２）、Ｎｄを２．０原子％含有するＡｌ合金層（Ａｌ−２Ｎｄ）（参考例１−１）又はＬａを０．０４原子％かつＮｉを０．０２原子％含有するＡｌ合金層（Ａｌ−０．０２Ｎｉ−０．０４Ｌａ）（参考例１−２）とした以外は実施例１−１と同様に配線膜を作製し、エッチングを行った。エッチング後の配線膜（ＭｏＮ／ｐ−Ａｌ、ＭｏＮ／Ａｌ−０．２Ｎｄ、ＭｏＮ／Ａｌ−２Ｎｄ又はＭｏＮ／Ａｌ−０．０２Ｎｉ−０．０４Ｌａ）の断面ＳＥＭ写真を図３に示す。
[Comparative Example 1, Example 1-2, Reference Example 1-1, and Reference Example 1-2]
The composition of the Al alloy layer is a pure Al layer (p-Al) (Comparative Example 1), an Al alloy layer containing 0.2 atomic% of Nd (Al-0.2Nd) (Example 1-2), and Nd of 2 Al alloy layer containing 0.0 atomic percent (Al-2Nd) (Reference Example 1-1) or Al alloy layer containing 0.04 atomic percent La and 0.02 atomic percent Ni (Al-0.02Ni-0) 0.04 La) (Reference Example 1-2) except that a wiring film was prepared and etched in the same manner as in Example 1-1. The cross-sectional SEM photograph of the wiring film (MoN / p-Al, MoN / Al-0.2Nd, MoN / Al-2Nd or MoN / Al-0.02Ni-0.04La) after etching is shown in FIG.
その結果、ＭｏＮ／ｐ−Ａｌ（比較例１）のエッチング形状は、ＭｏＮがひさし状に残ったのに対し、Ａｌ−０．６Ｎｄ（実施例１−１）及びＡｌ−０．２Ｎｄ（実施例１−２）は良好なテーパー形状を示した。比較例１のような形状では電極上に積層するＣＶＤ（化学蒸着）膜のカバレッジが悪化する場合があるので、好ましくない。 As a result, the etching shape of MoN / p-Al (Comparative Example 1) was Al-0.6Nd (Example 1-1) and Al-0.2Nd (Example), whereas MoN remained in an eaves shape. 1-2) showed a good taper shape. The shape as in Comparative Example 1 is not preferable because the coverage of the CVD (chemical vapor deposition) film laminated on the electrode may be deteriorated.
［熱処理試験］
実施例１−１、１−２、参考例１−１、１−２及び比較例１において作製した配線膜を、窒素雰囲気中で５００℃、５５０℃又は６００℃で２０分間熱処理したときの熱処理温度と電気抵抗率（μΩ・ｃｍ）の関係を図４および表１に示した。
電気抵抗率は４探針シート抵抗測定器を用い、膜厚は触針式段差計で測定して算出した。
[Heat treatment test]
Heat treatment when the wiring films produced in Examples 1-1, 1-2, Reference Examples 1-1, 1-2 and Comparative Example 1 were heat-treated at 500 ° C., 550 ° C. or 600 ° C. for 20 minutes in a nitrogen atmosphere. The relationship between temperature and electrical resistivity (μΩ · cm) is shown in FIG.
The electrical resistivity was calculated using a 4-probe sheet resistance measuring device and the film thickness was measured with a stylus type step gauge.
その結果、熱処理を行うことによって電気抵抗率は下がり、温度が５００〜６００℃の範囲内においては、Ａｌ合金層それぞれの組成において、配線膜の電気抵抗率はほぼ一定であった。ＭｏＮ／Ａｌ−２Ｎｄ（参考例１−１）の熱処理後の電気抵抗率は、ＭｏＮ／ｐ−Ａｌ（比較例１）と比べて少し高く、それ以外の配線膜はＭｏＮ／ｐ−Ａｌ（比較例１）よりも低い結果となった。 As a result, the electrical resistivity decreased by heat treatment, and the electrical resistivity of the wiring film was almost constant in the composition of each Al alloy layer when the temperature was in the range of 500 to 600 ° C. The electrical resistivity after heat treatment of MoN / Al-2Nd (Reference Example 1-1) is slightly higher than that of MoN / p-Al (Comparative Example 1), and the other wiring films are MoN / p-Al (Comparative). The result was lower than Example 1).
また、このときの、１０μｍラインアンドスペースのパターンの表面をＳＥＭ観察し、ヒロックの有無を調べた。ヒロックの有無は、光学顕微鏡を用いてノマルスキー型微分干渉と倍率４００倍の条件で測定した。
結果を表２にまとめた。
In addition, the surface of the 10 μm line and space pattern at this time was observed with an SEM, and the presence or absence of hillocks was examined. The presence or absence of hillocks was measured using a Nomarski-type differential interference and a magnification of 400 times using an optical microscope.
The results are summarized in Table 2.
ＭｏＮ／ｐ−Ａｌ（比較例１）の場合、熱処理温度が５００℃の時点でヒロックが発生し、耐熱性が低いことが確認された。ＭｏＮ／Ａｌ−０．２Ｎｄ（実施例１−２）の場合、５００℃ではヒロックがみられないが、５５０℃以上ではヒロックが発生した。ＭｏＮ／Ａｌ−０．６Ｎｄ（実施例１−１）と、ＭｏＮ／Ａｌ−２Ｎｄ（参考例１−１）は、６００℃までヒロックが発生しなかった。また、ＭｏＮ／Ａｌ−０．０２Ｎｉ−０．０４Ｌａ（参考例１−２）の場合、５５０℃まではヒロックは見当たらず、６００℃ではパネルへの影響が無視できる程度の密度で、ヒロックの発生が確認された。 In the case of MoN / p-Al (Comparative Example 1), hillocks were generated when the heat treatment temperature was 500 ° C., and it was confirmed that the heat resistance was low. In the case of MoN / Al-0.2Nd (Example 1-2), hillocks were not observed at 500 ° C., but hillocks were generated at 550 ° C. or higher. MoN / Al-0.6Nd (Example 1-1) and MoN / Al-2Nd (Reference Example 1-1) did not generate hillocks up to 600 ° C. In addition, in the case of MoN / Al-0.02Ni-0.04La (Reference Example 1-2), no hillocks are found up to 550 ° C., and hillocks are generated at such a density that the influence on the panel can be ignored at 600 ° C. Was confirmed.
１ 下地
２ Ａｌ合金層
３ 窒化されたＭｏ層
DESCRIPTION OF SYMBOLS 1 Base 2 Al alloy layer 3 Ni nitride layer
Claims (3)
前記Ａｌ合金層がＡｌを母材とし、Ｎｄを０．０１原子％以上、０．６原子％以下含むことを特徴とするデバイス用配線膜。 A wiring film for a device comprising an Al alloy layer, wherein a Mo layer nitrided on at least one surface of the Al alloy layer is laminated,
A wiring film for a device, wherein the Al alloy layer contains Al as a base material and contains Nd in an amount of 0.01 atomic% to 0.6 atomic%.
前記Ａｌ合金層がＡｌを母材とし、Ｎｉを０．０１原子％以上、０．１原子％以下、及びＮｄを０．０１原子％以上、０．１原子％以下含むことを特徴とするデバイス用配線膜。 A wiring film for a device comprising an Al alloy layer, wherein a Mo layer nitrided on at least one surface of the Al alloy layer is laminated,
The Al alloy layer includes Al as a base material, Ni is 0.01 atomic% or more and 0.1 atomic% or less, and Nd is 0.01 atomic% or more and 0.1 atomic% or less. Wiring film.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015222872A JP2017092330A (en) | 2015-11-13 | 2015-11-13 | Wiring film for device |
| PCT/JP2016/081271 WO2017082020A1 (en) | 2015-11-13 | 2016-10-21 | Wiring film |
| TW105136360A TWI654339B (en) | 2015-11-13 | 2016-11-09 | Wiring film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015222872A JP2017092330A (en) | 2015-11-13 | 2015-11-13 | Wiring film for device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2017092330A true JP2017092330A (en) | 2017-05-25 |
Family
ID=58695976
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2015222872A Pending JP2017092330A (en) | 2015-11-13 | 2015-11-13 | Wiring film for device |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2017092330A (en) |
| TW (1) | TWI654339B (en) |
| WO (1) | WO2017082020A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2022004491A1 (en) * | 2020-06-30 | 2022-01-06 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002341367A (en) * | 2001-05-18 | 2002-11-27 | Nec Corp | Liquid crystal display device and its manufacturing method |
| JP2004055842A (en) * | 2002-07-19 | 2004-02-19 | Kobe Steel Ltd | Semiconductor device electrode / wiring, semiconductor device electrode film/ wiring film and sputtering target for forming aluminum alloy thin film |
| JP2005033198A (en) * | 2003-07-11 | 2005-02-03 | Chi Mei Electronics Corp | Hillock-free aluminum layer and its forming method |
| JP2012243878A (en) * | 2011-05-17 | 2012-12-10 | Kobe Steel Ltd | Semiconductor electrode structure |
-
2015
- 2015-11-13 JP JP2015222872A patent/JP2017092330A/en active Pending
-
2016
- 2016-10-21 WO PCT/JP2016/081271 patent/WO2017082020A1/en active Application Filing
- 2016-11-09 TW TW105136360A patent/TWI654339B/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002341367A (en) * | 2001-05-18 | 2002-11-27 | Nec Corp | Liquid crystal display device and its manufacturing method |
| JP2004055842A (en) * | 2002-07-19 | 2004-02-19 | Kobe Steel Ltd | Semiconductor device electrode / wiring, semiconductor device electrode film/ wiring film and sputtering target for forming aluminum alloy thin film |
| JP2005033198A (en) * | 2003-07-11 | 2005-02-03 | Chi Mei Electronics Corp | Hillock-free aluminum layer and its forming method |
| JP2012243878A (en) * | 2011-05-17 | 2012-12-10 | Kobe Steel Ltd | Semiconductor electrode structure |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2022004491A1 (en) * | 2020-06-30 | 2022-01-06 | ||
| WO2022004491A1 (en) * | 2020-06-30 | 2022-01-06 | 株式会社アルバック | Metal wiring structure, manufacturing method for metal wiring structure, and sputtering target |
| JP7133727B2 (en) | 2020-06-30 | 2022-09-08 | 株式会社アルバック | Metal wiring structure and method for manufacturing metal wiring structure |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI654339B (en) | 2019-03-21 |
| TW201723227A (en) | 2017-07-01 |
| WO2017082020A1 (en) | 2017-05-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI413252B (en) | A wiring structure, a thin film transistor substrate, a method of manufacturing the same, and a display device | |
| JP5179604B2 (en) | Al alloy film for display devices | |
| JP5524905B2 (en) | Al alloy film for power semiconductor devices | |
| WO2012132871A1 (en) | Cu ALLOY FILM, AND DISPLAY DEVICE AND ELECTRONIC DEVICE EACH EQUIPPED WITH SAME | |
| WO2017195826A1 (en) | Multilayer wiring film and thin film transistor element | |
| JP6475997B2 (en) | Wiring film for flat panel display and Al alloy sputtering target | |
| WO2013047095A1 (en) | Wiring structure for display device | |
| JP4729661B2 (en) | Aluminum layer free from hillocks and method for forming the same | |
| US20110198617A1 (en) | Electrode, semiconductor device, and method for manufacturing the semiconductor device | |
| JP5491947B2 (en) | Al alloy film for display devices | |
| JP2012189725A (en) | WIRING FILM AND ELECTRODE USING Ti ALLOY BARRIER METAL AND Ti ALLOY SPUTTERING TARGET | |
| JP2010261103A (en) | Sputtering target and semiconductor device manufactured using the same | |
| JP2017092330A (en) | Wiring film for device | |
| JP2012189726A (en) | WIRING FILM AND ELECTRODE USING Ti ALLOY BARRIER METAL AND Ti ALLOY SPUTTERING TARGET | |
| JP2017092331A (en) | Wiring film for device, and aluminum alloy sputtering target material | |
| JP2012109465A (en) | Metal wiring film for display unit | |
| JP6545625B2 (en) | Wiring structure for display | |
| JP2012243878A (en) | Semiconductor electrode structure | |
| JP2012243877A (en) | Semiconductor electrode structure | |
| JP5756319B2 (en) | Cu alloy film and display device or electronic device including the same | |
| JP2021064655A (en) | Wiring structure and target material | |
| TW201928074A (en) | Wiring structure and target material | |
| JP2016157563A (en) | Method for producing conductive film | |
| KR20090026646A (en) | Gate structure and method for manufacturing of the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20170627 |