TWI649742B - Driving method of scan driver and driving method of display panel - Google Patents

Abstract

The present invention relates to a scanning driver and a driving method of the display panel. The scan driver is configured to output a scan drive signal to a plurality of scan lines of a display panel. The driving method includes: providing at least one clock control signal to the scan driver, wherein the clock control signal is a pulse signal; according to the clock control signal, corresponding Each scan line provides a scan driving signal, each scan driving signal includes two driving voltages, the two driving voltages are a first voltage and a second voltage, and the amplitude of the first voltage is greater than the amplitude of the second voltage, wherein The first voltage is output before the second voltage, and an output time of the second voltage is not less than an output time of the first voltage.

Description

Driving method of scan driver and driving method of display panel

The present invention relates to a driving method of a scan driver applied to a display device, and more particularly to a method of driving a Gate On Panel (GOP; Gate On Array, GOA) directly disposed on an array substrate.

Recently, active matrix displays such as liquid crystal display devices and organic light emitting diodes (OLEDs) are widely used in mobile phones (mobile phones, portable phones), notebook PCs, In addition to monitors, the demand for large-screen LCD TVs is also increasing.

Taking a liquid crystal display device as an example, as shown in FIG. 1, the liquid crystal display device 10 has a display panel 100 and a drive circuit 110.

The display panel 100 includes a plurality of scan lines 101 (G1 to Gm) arranged in a first direction (horizontal direction) X and a plurality of data lines arranged in a second direction (vertical direction) Y. 102 (D1-Dn), the scan line 101 is insulated from the data line 102 and forms a pixel matrix Px of a complex matrix arrangement (m×n).

A thin film transistor (TFT) 103, a pixel electrode 104, and a common electrode 105 are provided in each of the pixel units Px. The thin film transistor 103 and the pixel electrode 104 are disposed on a glass or a semiconductor substrate to form an array substrate (not shown). The common electrode 105 is disposed on an opposite substrate or a color filter substrate (not shown) opposite to the array substrate, and the liquid crystal layer is sandwiched between the array substrate and the Between the opposite substrates, of course, the common electrode 105 may be provided on the array substrate, and only needs to be insulated from the pixel electrode 104. The pixel electrode 104 and the common electrode 105 constitute a liquid crystal capacitor LC. The liquid crystal capacitor LC is driven by the driving circuit 110 to cause corresponding deflection of the liquid crystal molecules, thereby displaying an image.

Further, the driving circuit 110 includes a timing controller 112, a scan driver 113, and a data driver 114.

The timing controller 112 is configured to receive the data signal Data (eg, RGB data signal), the system clock signal CLKs, and the synchronization signal S _H/V output by the image processing circuit, and control the scan driver 113 and the data driver according to the signal output control signal. The working timing is also output to the data driver 114.

The scan driver 113 is configured to be electrically connected to the plurality of scan lines 101, and sequentially output corresponding scan drive signals Sg to the scan lines 101 (G1 G Gm), thereby electrically connecting to the scan lines 101 (Gj) correspondingly. Thin film transistor 103, where j is a positive integer and 1 j m.

The data driver 114 is configured to be electrically connected to the plurality of data lines 102 for loading the data signal to be displayed when the scan line 101 (Gj) loads the scan driving signal and causes the corresponding one of the thin film transistors 103 to be in an open state. After processing, the data lines D1-Dn are loaded, and the pixel electrode 104 of one row corresponding to the scanning line Gj loads the data signal Data.

However, when the image display is performed by the display panel 100 and the driving circuit 110 described above, the image displayed on the display panel exhibits insufficient brightness and unevenness.

In view of the above, it is necessary to provide a driving method of a scan driver that makes the display panel display high in quality.

Further, a driving method of a display panel having high display quality is provided.

A scanning driver driving method for outputting a scan driving signal to a plurality of scanning lines of a display panel, the driving method comprising: providing at least one clock control signal to the scan driver, wherein the clock control signal is a pulse signal; According to the clock control signal, a scan driving signal is provided for each scan line, and each scan drive signal includes two driving voltages, and the two driving voltages are a first voltage and a second voltage, and the amplitude of the first voltage is greater than the first a magnitude of the second voltage, wherein the first voltage is output prior to the second voltage, and an output time of the second voltage is not less than an output time of the first voltage.

A display panel driving method, the display panel includes a plurality of scan lines, a plurality of data lines vertically intersecting the scan lines, a data driver for providing data signals for the plurality of data lines, and a scan driver for providing scan signals for the plurality of scan lines a scan line of two adjacent positions and a data line of two adjacent positions define a pixel unit, the pixel unit includes at least one display element for displaying the data signal, and the driving method includes: providing at least one clock control signal to the The scan driver, the clock control signal is a pulse signal; corresponding to the clock control signal, a scan drive signal is provided for each scan line, and each scan drive signal includes two driving voltages, and the two driving voltages are the first voltage and the second voltage. a voltage, the voltage amplitude of the first voltage is greater than a voltage amplitude of the second voltage, wherein the first voltage is output before the second voltage, and an output time of the second voltage is not less than an output of the first voltage time.

Compared with the prior art, each of the thin film transistors can be quickly charged to the turn-on voltage under the first voltage driving during the power-on charging period to be in an on state, and is driven by the second voltage during the stable on-time period. The stable conduction state, so that the pixel unit has sufficient charging time, ensures that the display brightness of the pixel unit is sufficiently uniform, and also makes the scan driver have lower power consumption.

10, 20‧‧‧ liquid crystal display device

100, 200‧‧‧ display panel

110, 210‧‧‧ drive circuit

X‧‧‧ first direction

101, 201, G1~Gm, Gi‧‧ scan lines

Y‧‧‧second direction

102, 202, D1~Dn‧‧‧ data line

Px‧‧‧ pixel unit

103, 203‧‧‧ film transistor

104, 204‧‧‧ pixel electrodes

105, 205‧‧‧ common electrode

LC‧‧‧Liquid Crystal Capacitor

112, 212‧‧‧ timing controller

113, 213‧‧‧ scan drive

114, 214‧‧‧ data drive

CLKs‧‧‧ system clock signal

S _H/V ‧‧‧Synchronous signal

Sg‧‧‧ scan drive signal

Data‧‧‧Information Signal

STV‧‧‧ scan sync signal

200A‧‧‧ display area

200B‧‧‧ non-display area

220‧‧‧Array substrate

Tg‧‧‧effective drive cycle

Ta‧‧‧Powering charging period

Tb‧‧‧ stable conduction period

320‧‧‧Switch Module

321‧‧‧First switch unit

322‧‧‧Second switch unit

323‧‧‧third switch unit

S101, S103‧‧‧ steps

1 is a schematic plan view showing a liquid crystal display device of the prior art.

2 is a schematic plan view showing a liquid crystal display device according to a preferred embodiment of the present invention.

3 is a block diagram of a first embodiment of the scan driver shown in FIG. 2.

4 is a timing chart showing the operation of the scan driver and the display panel shown in FIG. 2.

FIG. 5 is a timing chart showing the operation of the scan driver shown in FIG. 3.

Figure 6 is a block diagram of a second embodiment of the scan driver shown in Figure 2.

FIG. 7 is a timing chart showing the operation of the data driver shown in FIG. 5.

Fig. 8 is a timing chart showing the operation of the third embodiment of the data driver shown in Fig. 6.

With regard to the current active matrix display device, particularly for the large-sized active matrix display device shown in FIG. 1, the cause of the abnormality in image display has been carefully studied and finally found out. The scan driving signals Sg outputted by the scan driver 113 are all the same fixed voltage. In the scan time Ts of one scan line, the thin film transistor 103 needs a longer upper charge time, resulting in the thin film transistor 103 for transmitting data signals. Time is shortened. However, when the charging time is insufficient, the pixel electrode 104 is likely to cause insufficient brightness of the data signal, and the display brightness of the adjacent pixel electrodes 104 is greatly different, thereby causing abnormalities such as insufficient brightness and unevenness on the display screen. .

In order to solve the foregoing problems of the present scanning driver, please refer to FIG. 2, which is a schematic diagram of a planar structure of a liquid crystal display device 20 with better display effect. It should be noted that the present embodiment is described by taking the liquid crystal display device 20 as an example. Alternatively, it may be another active matrix display device, such as an OLED display device, and is not limited thereto.

The liquid crystal display device 20 has a display panel 200 and a drive circuit 210.

The display area 200A of the display panel 200 includes: a plurality of scan lines 201 (G1 to Gm) arranged along the first direction (horizontal direction) X and a plurality of data arranged along the second direction (vertical direction) Y. A data line 202 (D1-Dn), the scanning line 201 at two adjacent positions is insulated from the data line 202 at two adjacent positions to form a pixel unit Px, whereby the display area 200A includes a matrix arrangement m ×n pixel unit Px.

A thin film transistor (TFT) 203, a pixel electrode 204, and a common electrode 205 are disposed in each of the pixel units Px. The thin film transistor 203 and the pixel electrode 204 are disposed on a glass or a semiconductor substrate to form an array substrate 220. The common electrode 205 is disposed on an opposite substrate or a color filter substrate (not shown) opposite to the array substrate, and the liquid crystal layer is interposed between the array substrate and the opposite substrate. The common electrode 205 may also be disposed on the array substrate 220, and only needs to be insulated from the pixel electrode 204. The pixel electrode 204 and the common electrode 205 constitute a liquid crystal capacitor LC. The liquid crystal capacitor LC is driven by the driving circuit 210 to cause corresponding deflection of the liquid crystal molecules, thereby displaying an image.

Further, the driving circuit 210 includes a timing controller 212, a scan driver 213, and a data driver 214.

The timing controller 212 is configured to receive the RGB data signal Data, the system clock signal CLKs, and the synchronization signal S _H/V output by the image processing circuit (not shown), and simultaneously output the corresponding scan synchronization signal STV according to the signal output to synchronize with the data output. A signal (not shown) controls the synchronization operation timing of the scan driver 213 and the data driver 214, and also outputs the data signal Data to the data driver 214.

The scan driver 213 includes a plurality of scan output terminals Ps, which are respectively scan output terminals Ps1 P Psm for electrically connecting to the first to m scan lines G1 G Gm of the plurality of scan lines 201, respectively. And sequentially outputting a corresponding scan driving signal Sg to the scan line 201 (G1~Gm), correspondingly opening the thin film transistor 203 electrically connected to the scan line 201 (Gj), wherein j is a positive integer smaller than m.

In this embodiment, the scan driver 213 is directly disposed on the array substrate corresponding to the non-display area 200B of the display panel 200 by the GOA or GOP technology, thereby simplifying the complexity of the external scan driving circuit and reducing the production cost of the display panel. .

The data driver 214 includes a plurality of data output terminals PD, and the data output terminals PD include data output terminals PD1 PDPDn for electrically connecting to the plurality of data lines 202 (D1 to Dn), respectively. The data driver 214 is configured to process the data signal Data and load it into the data lines D1 D Dn, and then load it into the corresponding pixel electrode 204. The pixel electrode 204 cooperates with the common electrode 205 so that the liquid crystal capacitor LC displays the data signal Data. .

Please refer to FIG. 3, which is a block diagram of a first embodiment of the scan driver 213 shown in FIG. 2. The scan driver 213 includes a scan driving signal generating module 300, a control module 310, a switch module 320, and scan output terminals Ps1 to Psm. The scan output terminals Ps1 to Psm are electrically connected to the scan lines G1 G Gm, respectively.

The scan driving signal generating module 300 is configured to generate and output the complex scan driving signal Sg according to the scan synchronization signal STV outputted by the timing controller 212. The control module 310 is configured to output the scan driving signal Sg to the switch module 320, and output a clock control signal CK to control the on-off state of the switch module 320 to control the output timing of the complex scan driving signal Sg. The scan driving signal Sg is a continuous periodic signal, including a complex effective driving period Tg (see FIG. 4 for details). In each effective driving period Tg, the scan driving signal Sg includes a first voltage V1 and a second voltage V2 having different voltage amplitudes, wherein the voltage amplitude of the first voltage V1 is greater than the voltage amplitude of the second voltage V2. . Preferably, the amplitude of the first voltage V1 is 1.2, 1.4, 1.8 or 2 times the voltage amplitude of the first voltage V2. The first voltage V1 is outputted before the second voltage V2, and the output time of the second voltage V2 is not less than the output time of the first voltage V1.

In this embodiment, the switch module 320 includes a plurality of switch units (not shown), and the plurality of switch units are connected to the scan line output terminals Ps1-Psm of the scan driver 213 one by one. When the control unit 310 outputs the clock control signal CK to the switch module 320 according to the scan synchronization signal STV, the switch module 320 sequentially turns on the switch unit under the control of the clock control signal CK, thereby driving m scan driving signals. Sg is sequentially loaded to the corresponding scan lines G1, G2, G3, ..., Gm.

Please refer to FIG. 4-5. FIG. 4 is a timing chart of the operation of the scan driver 213 shown in FIG. 3. FIG. 5 is a flowchart of the operation of the scan driver 213.

First, it should be noted that the symbol CK in FIG. 4 is a waveform diagram of the clock control signal CK, and G1 to Gm are waveform diagrams in which the scan driving signal Sg is loaded on the first to mth scan lines 201. The clock control signal CK includes two pulse signals of different voltage amplitudes. The effective driving period Tg of the scan driving signal Sg is a time when the scan driving signal Sg drives the thin film transistor 203 electrically connected to the scan line 201 to be powered on, and the effective driving period Tg includes the electric charging above the first voltage V1. The time period Ta and the stable on-period Tb having the second voltage V2. Preferably, the power-on charging period Ta is less than or equal to the stable on-time period Tb. The operation of the display panel 200 and the scan driver 213 will be specifically described below with reference to FIGS. 4-5.

In step S101, at least one clock control signal CK is provided to the scan driver 213, and the clock control signal CK is a pulse signal.

In step S103, a scan driving signal Sg is provided for each scan line 201 according to the clock control signal CK. Each scan driving signal Sg includes two driving voltages, and the two driving voltages are a first voltage V1 and a second voltage V2. The amplitude of the first voltage V1 is greater than the amplitude of the second voltage V2, wherein the first voltage V1 is output before the second voltage V2, and the output time of the second voltage V2 is not less than the first voltage V1. Output time.

Specifically, as shown in FIG. 4, after the scan driver 213 receives a scan sync signal STV, the switch module 320 is turned on at the first rising edge of the clock control signal CK at time t1, and the switch module 320 is turned on. The scan driving signal Sg is loaded to the first scan line G1, so that the thin film transistor 203 connected to the first scan line G1 is electrically turned on.

Wherein, in the power-on charging period Ta, the scan driving signal Sg has a first voltage V1, since the first voltage V1 has a higher amplitude voltage value, thereby enabling the thin film transistor 203 to quickly charge and reach its The threshold voltage Vth (not shown) is turned on, so that the thin film transistor 203 can be turned on quickly. After the thin film transistor 203 is in the on state, the scan driving signal Sg enters the stable on-period Tb. During the stable on-period Tb, the scan driving signal Sg has a second voltage V2, which is smaller than the first voltage V1. The thin film transistor 203 can be maintained in an on state, and the power consumption of the thin film transistor can be made small. It can be seen that the thin film transistor 203 loaded with the scan driving signal has a sufficiently long stable conduction between, so that the pixel electrode 204 has a sufficiently long time to load the data signal Data.

At time t2, on the second rising edge of the clock control signal CK, the switch module 320 loads the scan driving signal Sg to the second scan line G2, and the thin film transistor 203 connected to the second scan line G2 is powered on. The thin film transistor 203 receiving the scan driving signal Sg from the second scanning line G2 is in an on state driven by the scan driving signal Sg.

At time t3, at the third rising edge of the clock control signal CK, the switch module 320 loads the scan driving signal Sg to the third scan line G3, and the thin film transistor 203 connected to the third scan line G3 is powered on. The thin film transistor 203 receiving the scan driving signal Sg from the third scanning line G3 is in an on state driven by the scan driving signal Sg.

And so on, until the mth scan line 201 loads the scan driving signal Sg under the control of the mth rising edge of the clock control signal CK, the liquid crystal display panel 200 completes scanning of one frame of the picture. Show. It can be understood that the foregoing steps are repeated when the scanning of the next frame is displayed, which is not described in this embodiment.

Compared with the prior art, each of the thin film transistors 203 can be quickly charged to the on-voltage under the driving of the first voltage V1 in the power-on charging period Ta to be in an on state, and in the stable on-period Tb in the second. The voltage V2 is driven to be in a stable on state, and the pixel unit Px has sufficient charging time so that the pixel unit Px has sufficiently uniform display brightness, and the scan driver 213 has lower power consumption.

Please refer to FIG. 6, which is a block diagram of a second embodiment of the scan driver 213 shown in FIG. 2.

The scan driver 213 includes a scan driving signal generating module 300, a control module 310, a switch module 320, and scan output terminals Ps1 to Psm. The scan output terminals Ps1 to Psm are electrically connected to the scan lines G1 G Gm, respectively.

The scan driving signal generating module 300 is configured to generate and output the complex scan driving signal Sg according to the scan synchronization signal STV outputted by the timing controller 212. The control module 310 is configured to output the scan driving signal Sg to the switch module 320, and simultaneously output the first, second, and third clock control signals CK1, CK2, and CK3 to the switch module 320, first, second, and The three clock control signals CK1, CK2, and CK3 sequentially control the on/off state of the switch module 320 to control the output timing of the complex scan driving signal Sg. The first, second, and third clock control signals CK1, CK2, and CK3 each include pulse signals of two different voltage amplitudes. The scan driving signal Sg is a continuous periodic signal including a complex effective driving period Tg. The scan driving signal Sg has at least two voltage amplitude different voltages, for example, a first voltage V1 and a second voltage V2, wherein the voltage amplitude of the first voltage V1 is greater than the voltage amplitude of the second voltage V2. Preferably, the amplitude of the first voltage V1 is 1.2, 1.4, 1.8 or 2 times the voltage amplitude of the first voltage V2. The first voltage V1 is outputted before the second voltage V2, and the output time of the second voltage V2 is not less than the output time of the first voltage V1.

The switch module 320 includes a first switch unit 321, a second switch unit 322, and a third open unit 333. Each of the switch units is electrically connected to the i scan outputs, where m=3i. Correspondingly, the first scan output terminal Ps1 is first, and each of the two scan output terminals is a group, and the first scan output terminal Ps1 to the mth scan output terminal Psm are divided into three groups, which are electrically connected to the three groups respectively. The cells 321, 322, 323 are turned on.

In this embodiment, the first switch unit 321 is electrically connected to the first, fourth, ..., m-2 scan output terminals Ps1, Ps4, ..., Psm-2; the second switch unit 322 is connected to the second, fifth, ..., m-1 scan output terminals Ps2, Ps5, ..., Psm-1 are electrically connected; third switch unit 323 and 3, 6, ..., m scan output terminals Ps3, Ps6, ..., Psm Sexual connection.

The control unit 310 outputs the first clock control signal CK1 to the first switch unit 321 according to the scan synchronization signal STV. The first switch unit 321 sequentially loads the i scan drive signals Sg to the corresponding scan according to the first clock control signal CK1. Lines G1, G4, ..., Gm-2.

The control unit 310 outputs the second clock control signal CK2 to the second switching unit 322 after the first time td1 is delayed after receiving the scan synchronization signal STV, and the second switching unit 322 scans the i according to the second clock control signal CK2. The driving signal Sg is sequentially loaded to the corresponding scanning lines G2, G5, ..., Gm-1.

The control unit 310 outputs the third clock control signal CK3 to the third switching unit 323 after the first synchronization time td1 is delayed after receiving the scan synchronization signal STV, and the third switching unit 323 will i according to the third clock control signal CK3. The scan driving signals Sg are sequentially loaded to the corresponding scanning lines G3, G6, ..., Gm.

The rising edge of each pulse of the second clock control signal CK2 is delayed by the first time td1 from the rising edge of each pulse of the first clock control signal CK1, and the rising edge of each pulse of the control clock signal CK3 is controlled by the second clock. The rising edge of each pulse of signal CK2 is delayed by the first time td1. The first time td1 is 1/3 of the startup time Ts occupied by each pulse. In other words, the second clock The control signal CK2 is delayed by 120° from the first clock control signal CK1, and the third clock control signal CK3 is delayed by 120° from the second clock control signal CK2.

Please refer to FIG. 7 , which is an operation timing diagram of the scan driver 213 of FIG. 6 applied to the display panel 200 . Corresponding to FIG. 7 , the symbol CK1 is a waveform diagram of the first clock control signal CK1 , and the symbol CK2 is a second clock control signal CK2 . The waveform diagram CK3 is a waveform diagram of the third clock control signal CK3, wherein the three clock control signals sequentially overlap the delay time td1 in time. G1~Gm is a waveform diagram of the scan driving signal Sg loaded by the first to m scan lines 201 under the control of the corresponding clock control signal, wherein the adjacent scan lines 201 load scan drive signals Sg have partial overlap in time, and Each of the scan driving signals Sg loaded by the scan line 201 has a first voltage V1 and a second voltage V2, and an effective driving period Tg of the scan driving signal Sg, the effective driving period Tg includes an electric charging time above the first voltage V1. The segment Ta and the stable on-period Tb having the second voltage V2. Preferably, the power-on charging period Ta is less than or equal to the stable on-time period Tb.

Specifically, as shown in FIG. 6-7, after the scan driver 213 receives a scan synchronization signal STV, at time t1, the first clock control signal CK1 is at a rising edge, so that the first switch unit 321 is turned on, the first The switching unit 321 loads the scan driving signal Sg to the first scanning line G1, so that the thin film transistor 203 connected to the first scanning line G1 is electrically turned on.

Wherein, in the power-on charging period Ta, the scan driving signal Sg has a first voltage V1, since the first voltage V1 has a higher amplitude voltage value, thereby enabling the thin film transistor 203 to quickly charge and reach its The threshold voltage Vth is turned on, so that the thin film transistor 203 can be turned on quickly. After the thin film transistor 203 is in the on state, the scan driving signal Sg enters the stable on-period Tb. During the stable on-period Tb, the scan driving signal Sg has a second voltage V2, which is smaller than the first voltage V1. The thin film transistor 203 can be maintained in an on state, and the power consumption of the thin film transistor can be made small. It can be seen that the thin film transistor loaded with the scan driving signal 203 has a sufficiently long stable conduction between, so that the pixel electrode 204 has a sufficiently long time to load the data signal Data.

After the time t1 is delayed by the time t2 of the first time td1, the second clock control signal CK2 is at the rising edge, so that the second switching unit 322 is turned on, and the second switching unit 322 loads the scan driving signal Sg to the second scanning line G2. Thereby, the thin film transistor 203 connected to the second scan line G2 is electrically turned on. Similarly, as described above, the thin film transistor 203 receiving the scan driving signal Sg from the second scanning line G2 is in an on state driven by the scan driving signal Sg. It can be seen that the second scan line G2 is also loaded with the scan driving signal Sg after the first scan line G1 is loaded with the scan driving signal Sg, and the second scan line G2 is delayed by 120° from the first scan line G1. Load the scan drive signal Sg.

At time t3 after the delay of the first time td1 after the time t2, the third clock control signal CK3 is at the rising edge, so that the third switching unit 323 is turned on, and the third switching unit 323 loads the scan driving signal Sg to the third scanning line G3. Therefore, the thin film transistor 203 connected to the third scan line G3 is electrically turned on, and the thin film transistor 203 receiving the scan driving signal Sg from the second scan line G2 is in an on state driven by the scan driving signal Sg. It can be seen that the third scan line G3 also loads the scan driving signal Sg after the first scan time Sd1 is delayed after the second scan line G2 is loaded with the scan driving signal Sg, and the third scan line G3 is delayed by 120° from the second scan line G2. Load the scan drive signal Sg.

At time t4, the first clock control signal CK1 is in the second rising edge state, whereby the corresponding fourth scan line G4 is loaded with the scan driving signal Sg, and at time t5, the second clock control signal CK2 is in the rising edge state. Therefore, the corresponding fifth scan line G5 loads the scan driving signal Sg, and at time t6, the third clock control signal CK3 is in the rising edge state, whereby the corresponding sixth scan line G6 loads the scan driving signal Sg. And so on, until the mth scan line is in the third When the scan driving signal Sg is loaded under the control of the clock control signal CK3, the liquid crystal display panel 200 completes the scanning display of one frame of the screen.

The number of the switch units in the switch module 320 is not limited to three, and may be two, four, six, eight, etc., and is not limited to the limit, correspondingly, the scan output terminal Ps1~ Psm can also be divided into corresponding group numbers.

In this implementation, by setting three clock control signals, the timings of loading the scan driving signals Sg by different scan lines 201 are controlled, so that the periods in which the adjacent two scan lines 201 are loaded with the scan driving signals Sg partially overlap in time. Thereby speeding up the scanning speed of the display panel.

Alternatively, as shown in FIG. 8, the three clock control signals may not overlap in time. Correspondingly, the periods in which the adjacent two scan lines 201 load the scan driving signal Sg do not overlap in time, and To this end, the driving mode of the scanning line 201 is simplified.

In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. However, the above description is only the preferred embodiment of the present invention, and the scope of the present invention is not limited to the above-described embodiments, and equivalent modifications or variations made by those skilled in the art in light of the spirit of the present invention are It should be covered by the following patent application.

Claims (14)

A scanning driver driving method for outputting a scan driving signal to a plurality of scanning lines of a display panel, the driving method comprising: providing at least one clock control signal to the scan driver, wherein the clock control signal is a pulse signal; According to the clock control signal, a scan driving signal is provided for each scan line, and each scan drive signal includes two driving voltages, and the two driving voltages are a first voltage and a second voltage, and the amplitude of the first voltage is greater than the first a magnitude of the second voltage, wherein the first voltage is output prior to the second voltage, and an output time of the second voltage is not less than an output time of the first voltage. The driving method of the scan driver according to claim 1, wherein the amplitude of the first voltage is twice the magnitude of the second voltage. The driving method of the scan driver according to claim 1, wherein an output time of the second voltage is equal to an output time of the first voltage. The driving method of the scan driver according to claim 1, wherein the time at which the scan lines of the adjacent scan lines load the scan drive signals has a partial overlap. The driving method of the scan driver according to claim 4, wherein the partial overlapping time is 1/3 of a time when any one of the scan lines of the adjacent position loads the scan driving signal. The driving method of the scan driver of claim 5, wherein the number of the at least one clock control signal is three, and is a first clock control signal, a second clock control signal and a third clock control signal, the second clock The control signal is delayed by a first time from the first clock control signal, and the third clock control signal is delayed by a first time from the second clock control signal. The driving method of the scan driver according to claim 6, wherein the first time is one third of each pulse period in the first clock control signal. A display panel driving method, the display panel includes a plurality of scan lines, a plurality of data lines vertically intersecting the scan lines, a data driver for providing data signals for the plurality of data lines, and a scan driver for providing scan signals for the plurality of scan lines a scan line of two adjacent positions and a data line of two adjacent positions define a pixel unit, the pixel unit includes at least one display element for displaying the data signal, and the driving method includes: providing at least one clock control signal to the The scan driver, the clock control signal is a pulse signal; corresponding to the clock control signal, a scan drive signal is provided for each scan line, and each scan drive signal includes two driving voltages, and the two driving voltages are the first voltage and the second voltage. a voltage, the voltage amplitude of the first voltage is greater than a voltage amplitude of the second voltage, wherein the first voltage is output before the second voltage, and an output time of the second voltage is not less than an output of the first voltage time. The driving method of the display panel according to claim 8, wherein the amplitude of the first voltage is twice the magnitude of the second voltage. The driving method of the display panel according to claim 9, wherein the output time of the second voltage is equal to the output time of the first voltage. The driving method of the display panel according to claim 8, wherein the time at which the scan lines of the scan lines of the adjacent positions are loaded is partially overlapped. The driving method of the display panel according to claim 11, wherein the partial overlapping time is 1/3 of a time when any one of the scanning lines of the adjacent scanning line loads the scanning driving signal. The driving method of the display panel of claim 12, wherein the number of the at least one clock control signal is three, and is a first clock control signal, a second clock control signal, and a third clock control signal, the second clock The control signal is delayed by a first time from the first clock control signal, and the third clock control signal is delayed by a first time from the second clock control signal, the first time being one third of each pulse period of the first clock control signal . The method of driving a display panel according to claim 12, wherein the display panel comprises an array substrate, and the plurality of scan lines, the plurality of data lines, and the at least one display element displaying the data signal are disposed on the array substrate. The scan driver is disposed in the non-display area of the array substrate.