TWI646648B - Fan-out semiconductor package - Google Patents

Abstract

The present invention provides a fan-out type semiconductor package, comprising: a first connecting member having a through hole; and a semiconductor wafer disposed in the through hole of the first connecting member and having an active surface and an inactive surface opposite to the active surface The active surface is provided with a connection pad; an encapsulation covering at least a portion of the first connection member and at least a portion of the semiconductor wafer; and a second connection member disposed on the first connection member and the semiconductor wafer. The first connecting member and the second connecting member respectively comprise a first redistribution layer and a second redistribution layer, and the first redistribution layer and the second redistribution layer are electrically connected to the connection pad and formed by one layer or a plurality of layers, At least one of the first redistribution layers is disposed between the plurality of insulating layers of the first connection member, and the second redistribution layer includes a sensor pattern that recognizes the fingerprint.

Description

Fan-out type semiconductor package

This application claims the priority of Korean Patent Application No. 10-2016-0106218 filed on the Korean Intellectual Property Office on August 22, 2016, and Korea filed on October 21, 2016 at the Korea Intellectual Property Office. The priority of the patent application No. 10-2016-0137663, the entire disclosure of each of which is incorporated herein by reference.

The present disclosure relates to a fan-out type semiconductor package, and more particularly to a fan-out type semiconductor package having a fingerprint recognition function.

Recently, an important trend in the development of semiconductor wafer related technology has been to reduce the size of semiconductor wafers. Therefore, in the field of packaging technology, with the rapid increase in demand for small-sized semiconductor wafers and the like, it has been required to realize a small-sized semiconductor package including a plurality of leads at the same time.

The fan-out package is a packaging technology that meets the needs of the above technology. Such a fan-out type package has a small size, and a plurality of pins can be realized by rewiring a connection terminal in a direction other than a region where a semiconductor wafer is disposed.

One aspect of the present disclosure provides an ultra-small, ultra-thin fan-out type semiconductor package having a fingerprint recognition function.

According to an aspect of the present disclosure, a fan-out type semiconductor package can be provided, wherein a first connection member is introduced, the first connection member has a through hole and a plurality of redistribution layers, and the through hole has a semiconductor wafer configuration, the plurality of The redistribution layer is formed in the first connection member, the second connection member is introduced to the semiconductor wafer and the first connection member, the second connection member includes a redistribution layer, and the redistribution layer includes a sensor pattern, the inductor The pattern implements high sensitivity fingerprint recognition.

According to an aspect of the disclosure, a fan-out type semiconductor package may include: a first connection member having a through hole; and a semiconductor wafer disposed in the through hole of the first connection member and having an active surface and opposite to the active surface The active surface is provided with a connection pad; an encapsulation body encapsulating at least a portion of the first connection member and at least a portion of the semiconductor wafer; and a second connection member disposed on the first connection member and the semiconductor wafer. The first connecting member and the second connecting member respectively include a first redistribution layer and a second redistribution layer electrically connected to the connection pad and formed of one or more layers, at least one of the first redistribution layers being disposed on Between the plurality of insulating layers constituting the first connecting member, and at least one of the second redistributing layers includes a sensor pattern for recognizing the fingerprint.

100‧‧‧Semiconductor package

100A, 100B, 100C, 100D, 100E, 100F‧‧‧ fan-out semiconductor packages

110‧‧‧First connecting member

110H‧‧‧through hole

111a‧‧‧First insulation

111b‧‧‧Second insulation

111c‧‧‧ third insulation

112a‧‧‧First redistribution layer

112b‧‧‧Second redistribution layer

112c‧‧‧ Third rewiline layer

112d‧‧‧fourth redistribution layer

113a‧‧‧First via

113b‧‧‧Second via

113c‧‧‧ third via

120‧‧‧Semiconductor wafer

121‧‧‧Ontology

122‧‧‧Connecting mat

123‧‧‧ Passivation layer

130‧‧‧Encapsulation

131‧‧‧ openings

140‧‧‧Second connection member

140a‧‧‧ Third connecting member

140b‧‧‧Second connection member

141, 141a, 141b‧‧‧ insulation

142, 142a, 142b‧‧‧ rewiring layer

143, 143a, 143b‧‧‧ vias

150‧‧‧ Passivation layer

160‧‧‧ under bump metal layer

170‧‧‧Connecting terminal

190‧‧‧ Passive components

1000‧‧‧Electronic devices

1010‧‧‧ motherboard

1020‧‧‧ wafer related components

1030‧‧‧Network related components

1040‧‧‧Other components

1050‧‧‧ camera module

1060‧‧‧Antenna

1070‧‧‧Display device

1080‧‧‧Battery

1090‧‧‧ signal line

1100‧‧‧Smart Phone

1101‧‧‧ Ontology

1110‧‧‧ motherboard

1120‧‧‧Electronic components

1130‧‧‧ camera module

2100‧‧‧Fan-out semiconductor package

2120‧‧‧Semiconductor wafer

2121‧‧‧ Ontology

2122‧‧‧Connecting mat

2130‧‧‧Encapsulation

2140‧‧‧Connecting members

2141‧‧‧Insulation

2142‧‧‧Rewiring layer

2143‧‧‧vias

2150‧‧‧ Passivation layer

2200‧‧‧Fan-in semiconductor package

2220‧‧‧Semiconductor wafer

2221‧‧‧ Ontology

2222‧‧‧Connecting mat

2223‧‧‧ Passivation layer

2240‧‧‧Connecting members

2241‧‧‧Insulation

2242‧‧‧Wiring pattern

2243, 2243h‧‧‧through holes

2250‧‧‧ Passivation layer

2251‧‧‧ openings

2270‧‧‧ solder balls

2280‧‧‧ underfill resin

2290‧‧‧Molded materials

2301, 2302‧‧‧Intermediate substrate

2500‧‧‧ motherboard

g‧‧‧Predetermined interval

I-I’‧‧‧ cut line

II-II’‧‧‧ Thread

M1, M2, M3, M4‧‧ layers

Rx‧‧‧ sensing pattern

Tx‧‧‧ induction pattern

Sr‧‧ interval

St‧‧ interval

Wr‧‧‧ line width

Wt‧‧‧ line width

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. The above and other aspects, features and advantages will be more apparent and understood. In the drawings: FIG. 1 is a block diagram illustrating an embodiment of an electronic device system; FIG. 2 is an illustration of an embodiment of an electronic device. 3A and 3B are schematic cross-sectional views illustrating a state of a fan-in type semiconductor package before and after packaging; FIG. 4 is a cross-sectional view showing a packaging process of a fan-in type semiconductor package; FIG. 6 is a cross-sectional view showing a state in which a semiconductor package is mounted on an interposer and finally mounted on a main board of an electronic device; FIG. 6 is a cross-sectional view showing a state in which a fan-in type semiconductor package is embedded in an interposer and finally mounted on a main board of an electronic device. FIG. 7 is a cross-sectional view showing a fan-out type semiconductor package; FIG. 8 is a cross-sectional view showing a fan-out type semiconductor package mounted on a main board of an electronic device; FIG. 9 is a view showing a fan-out type semiconductor package; 1 is a schematic cross-sectional view taken along line I-I' of the fan-out type semiconductor package of FIG. 9; FIG. 11 is a schematic view of the fan-out type half of FIG. FIG. 12 is a schematic view showing another embodiment of M1 and M2 of the fan-out type semiconductor package of FIG. 9; FIG. 13 is a modified embodiment of the fan-out type semiconductor package of FIG. FIG. 14 is a cross-sectional view showing another modified embodiment of the fan-out type semiconductor package of FIG. 9; FIG. Figure 15 is a cross-sectional view showing another embodiment of the fan-out type semiconductor package; Figure 16 is a plan view taken along line II-II' of the fan-out type semiconductor package of Figure 15; Figure 17 is a fan-out of Figure 15 A schematic cross-sectional view of a modified embodiment of a semiconductor package; and FIG. 18 is a cross-sectional view of another modified embodiment of the fan-out semiconductor package of FIG.

Hereinafter, each exemplary embodiment of the present invention will be described with reference to the drawings. In the drawings, the shapes, dimensions, and the like of the various components may be exaggerated or reduced for clarity.

The term "exemplary embodiment", as used herein, is not intended to refer to the same exemplary embodiments, but rather to the particular features or characteristics that are different from the specific features or characteristics of another exemplary embodiment. However, the exemplary embodiments provided herein are considered to be capable of being implemented in combination, in whole or in part, with each other. For example, an element that is illustrated in a particular exemplary embodiment is not illustrated in another exemplary embodiment, unless the opposite or contradictory description is provided in another exemplary embodiment. It can also be understood as a description related to another exemplary embodiment.

The meaning of "connected" to another component in the specification includes the indirect connection via the third component and the direct connection between the two components. In addition, "electrical connection" means the concept of physical connection and physical disconnection. It should be understood that when When "a" or "second" refers to an element, the element is not limited thereby. The use of "first" and "second" may be used only for the purpose of distinguishing the elements from the other elements and may not limit the order or importance of the elements. In some cases, a first element could be termed a second element without departing from the scope of the invention as set forth herein. Similarly, the second element may also be referred to as a first element.

Herein, the upper portion, the lower portion, the upper side, the lower side, the upper surface, the lower surface, and the like are illustrated in the drawings. For example, the first connecting member is disposed at a level higher than that of the redistribution layer. However, the scope of the patent application is not limited thereto. In addition, the vertical direction refers to the upward direction and the downward direction, and the horizontal direction refers to a direction perpendicular to the upward direction and the downward direction. In this case, the vertical cross section means a case taken along a plane in the vertical direction, and an example of the vertical cross section may be a cross-sectional view shown in the drawing. Further, the horizontal section refers to a case of taking a plane in the horizontal direction, and an example of the horizontal section may be a plan view shown in the drawing.

The terms used herein are for illustrative purposes only and are not limiting of the invention. In this case, the singular forms include the plural forms unless otherwise indicated in the context.

Electronic device

1 is a block diagram showing an embodiment of an electronic device system.

Referring to FIG. 1 , a motherboard 1010 can be housed in the electronic device 1000 . The motherboard 1010 can include a wafer related component 1020, a network related component 1030, and other components 1040, etc. that are physically or electrically connected thereto. These components can be connected to the following Other components to form various signal lines 1090.

The wafer related component 1020 may include: a memory chip such as a volatile memory (such as a dynamic random access memory (DRAM)), and a non-volatile memory (such as a read only memory (read only memory). ROM)), flash memory, etc.; application processor chips, such as a central processing unit (eg, a central processing unit (CPU)), a graphics processor (eg, a graphics processing unit (GPU)) ), digital signal processor, cryptographic processor, microprocessor, microcontroller, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (application-specific integrated circuit, ASIC) and the like. However, wafer related component 1020 is not limited thereto, but may include other types of wafer related components. Additionally, wafer related components 1020 can be combined with each other.

Network related components 1030 may include, for example, the following protocols: wireless fidelity (Wi-Fi) (Institute of Electrical And Electronics Engineers (IEEE) 802.11 family, etc.), global interoperability microwave access (worldwide) Interoperability for microwave access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, long term evolution (LTE), evolution data only (Ev-DO), high speed packet access + (high speed Packet access +, HSPA+), high speed downlink packet access + (HSDPA+), high speed uplink packet access + (HSUPA+), Enhanced data GSM environment (EDGE), global system for mobile communications (GSM), global positioning system (GPS), general packet radio service (GPRS) ), code division multiple access (CDMA), time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, 3G protocol, 4G Agreement, 5G Agreement and any other wireless and wireline agreements specified after the above agreement. However, network related component 1030 is not limited thereto, but may include a variety of other wireless standards or protocols or wired standards or protocols. Additionally, network related components 1030 can be combined with one another as described above with wafer related components 1020.

Other components 1040 can include a high frequency inductor, a ferrite inductor, a power inductor, a ferrite bead, a low temperature co-fired ceramic; LTCC), electromagnetic interference (EMI) filter, multilayer ceramic capacitor (MLCC), or a combination thereof. However, other components 1040 are not limited thereto, and may include passive components and the like for various other purposes. Additionally, other components 1040 can be combined with one another as described above with wafer related component 1020 or network related component 1030.

Depending on the type of electronic device 1000, the electronic device 1000 may include other components that may be physically or electrically connected to the motherboard 1010, or other components that may not be physically connected or electrically connected to the motherboard 1010. These other components may include, for example, photos Camera module 1050, antenna 1060, display device 1070, battery 1080, audio codec (not shown), video codec (not shown), power amplifier (not shown), compass (not shown), Accelerometer (not shown), gyroscope (not shown), speaker (not shown), large-capacity storage unit (such as hard disk drive) (not shown), compact disk (CD) drive ( Not shown), digital versatile disk (DVD) driver (not shown), etc. However, these other components are not limited thereto, but may include other components for various purposes depending on the type of the electronic device 1000 and the like.

The electronic device 1000 can be a smart phone, a personal digital assistant (PDA), a digital camera, a digital still camera, a network system, a computer, a monitor, a tablet PC, and a notebook. Personal computer, portable Internet PC (netbook PC), TV, video game machine, smart watch or car components. However, the electronic device 1000 is not limited thereto, and may be any other electronic device that processes data.

2 is a perspective view illustrating an embodiment of an electronic device.

Referring to FIG. 2, a semiconductor package can be used for various purposes in the electronic device 1000 described above. For example, the main board 1110 can be received in the body 1101 of the smart phone 1100, and the various electronic components 1120 can be physically connected or electrically connected to the main board 1110. In addition, other components (eg, camera module 1130) that may be physically connected or electrically connected to the motherboard 1110 or that may not be physically connected or electrically connected to the motherboard 1110 may be housed in the body 1101. In the electronic component 1120 Some of the electronic components may be wafer related components, and the semiconductor package 100 may be, for example, an application processor between the wafer related components, but not limited thereto. The electronic device is not necessarily limited to the smart phone 1100, but may be other electronic devices as described above.

Semiconductor package

In general, many sophisticated circuits are integrated into a semiconductor wafer. However, the semiconductor wafer itself cannot function as a completed semiconductor product and may be damaged by external physical or chemical influences. Therefore, the semiconductor wafer cannot be used alone, but it can be packaged in an electronic device or the like and used in a package state in an electronic device or the like.

Here, in terms of electrical connection, a semiconductor package is required due to a difference in circuit width between the semiconductor wafer and the main board of the electronic device. In detail, the size of the connection pads of the semiconductor wafer and the spacing between the connection pads of the semiconductor wafer are extremely precise, but the size of the component mounting pads of the main board used in the electronic device and the interval between the component mounting pads of the main board are remarkably Greater than the size and spacing of the connection pads of the semiconductor wafer. Therefore, it may be difficult to mount the semiconductor wafer directly on the main board, and a packaging technique for buffering a circuit width difference between the semiconductor wafer and the main board is required.

Depending on the structure and purpose of the semiconductor package, the semiconductor package fabricated by the package technology can be classified into a fan-in type semiconductor package or a fan-out type semiconductor package.

The fan-in type semiconductor package and the fan-out type semiconductor package will be described in more detail below with reference to the drawings.

Fan-in semiconductor package

3A and 3B are cross-sectional views illustrating a state of a fan-in type semiconductor package before and after packaging.

4 is a cross-sectional view showing a packaging process of a fan-in type semiconductor package.

Referring to the drawings, the semiconductor wafer 2220 may be, for example, an integrated circuit (IC) in a bare state, and the semiconductor wafer 2220 includes: a body 2221 including germanium (Si), germanium (Ge), gallium arsenide (GaAs). And a connection pad 2222 formed on one surface of the body 2221 and including a conductive material such as aluminum (Al); and a passivation layer 2223, such as an oxide film or a nitride film, etc., and formed on one surface of the body 2221 And covering at least a portion of the connection pad 2222. In this case, since the connection pad 2222 is remarkably small in size, it is difficult to mount the integrated circuit (IC) on a printed circuit board (PCB) and a motherboard or the like of the electronic device.

Accordingly, the connection member 2240 can be formed on the semiconductor wafer 2220 depending on the size of the semiconductor wafer 2220 to rewire the connection pads 2222. The connecting member 2240 can be formed by forming an insulating layer 2241 on the semiconductor wafer 2220 using an insulating material such as a photosensitive dielectric (PID) resin; forming a via hole 2243h exposing the connection pad 2222; and then A wiring pattern 2242 and a via hole 2243 are formed. Next, a passivation layer 2250 that protects the connection member 2240 may be formed, an opening 2251 may be formed, and an under bump metal layer 2260 or the like may be formed. That is, the fan-in type semiconductor package 2200 including, for example, the semiconductor wafer 2220, the connection member 2240, the passivation layer 2250, and the under bump metal layer 2260 can be manufactured by a series of processes.

As described above, the fan-in type semiconductor package may have all of the connection pads in which the fan-in type semiconductor package may have, for example, an input/output (I/O) terminal of the semiconductor wafer, The package form in the semiconductor wafer, and can have excellent electrical characteristics and can be produced at low cost. Therefore, many components mounted in a smart phone have been manufactured in a fan-in type semiconductor package. In detail, many components installed in smart phones have been developed which can perform fast signal transmission when having a relatively small size.

However, since all of the input/output terminals need to be disposed inside the semiconductor wafer in the fan-in type semiconductor package, the fan-in type semiconductor package has a large space limitation. Therefore, it is difficult to apply this structure to a semiconductor wafer having a large number of input/output terminals or a semiconductor wafer having a small size. In addition, due to the above disadvantages, the fan-in type semiconductor package cannot be directly mounted and used on the main board of the electronic device. Here, even if the size of the input/output terminal of the semiconductor wafer and the interval between the input/output terminals of the semiconductor wafer are increased by the rewiring process, the size and semiconductor of the input/output terminal of the semiconductor wafer in this case The spacing between the input/output terminals of the wafer may still be insufficient to mount the fan-in type semiconductor package directly on the motherboard of the electronic device.

FIG. 5 is a cross-sectional view showing a state in which a fan-in type semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic device.

6 is a cross-sectional view showing a state in which a fan-in type semiconductor package is embedded in an interposer and finally mounted on a main board of an electronic device.

Referring to the drawings, in a fan-in type semiconductor package 2200, a semiconductor wafer The connection pad 2222 of the 2220 (that is, the input/output terminal) can be re-routed via the interposer substrate 2301, and the fan-in type semiconductor package 2200 can be finally mounted on the main board 2500 of the electronic device in a state where it is mounted on the interposer substrate 2301. . In this case, the solder ball 2270 or the like may be fixed by the underfill resin 2280 or the like, and the outer surface of the semiconductor wafer 2220 may be covered with the molding material 2290 or the like. The fan-in type semiconductor package 2200 can be embedded in a separate interposer substrate 2302, and the connection pads 2222 (ie, input/output terminals) of the semiconductor wafer 2220 can be interposed in a state in which the fan-in type semiconductor package 2200 is embedded in the interposer substrate 2302. The substrate 2302 is re-routed, and the fan-in type semiconductor package 2200 is finally mountable on the main board 2500 of the electronic device.

As described above, it may be difficult to directly mount and use a fan-in type semiconductor package on the main board of the electronic device. Therefore, the fan-in type semiconductor package can be mounted on a separate interposer substrate and then mounted on the main board of the electronic device by a packaging process; or the fan-in type semiconductor package can be embedded in the interposer substrate in the fan-in type semiconductor package. Install and use on the motherboard of the electronic device.

Fan-out type semiconductor package

FIG. 7 is a cross-sectional view illustrating a fan-out type semiconductor package.

Referring to the drawings, in the fan-out type semiconductor package 2100, for example, the outer surface of the semiconductor wafer 2120 is protected by the encapsulation 2130, and the connection pads 2122 of the semiconductor wafer 2120 can be directed toward the semiconductor wafer 2120 by the connection member 2140. Reroute outside. In this case, the passivation layer 2150 may be further formed on the connection member 2140, and the under bump metal layer may be further formed in the opening of the passivation layer 2150. 2160. Solder balls 2170 may be further formed on the under bump metal layer 2160. The semiconductor wafer 2120 can be an integrated circuit including a body 2121, a connection pad 2122, a passivation layer (not shown), and the like. The connecting member 2140 may include an insulating layer 2141, a redistribution layer 2142 formed on the insulating layer 2141, and a via hole 2143 electrically connecting the connection pad 2122 and the redistribution layer 2142 to each other.

As described above, the fan-out type semiconductor package may have a form in which an input/output terminal of a semiconductor wafer is rerouted and configured toward a semiconductor wafer via a connection member formed on the semiconductor wafer. As described above, in the fan-in type semiconductor package, all of the input/output terminals of the semiconductor wafer need to be disposed in the semiconductor wafer. Therefore, when the size of the semiconductor wafer is reduced, it is necessary to reduce the size and pitch of the balls, thereby making it impossible to use a standardized ball layout in the fan-in type semiconductor package. On the other hand, as described above, the fan-out type semiconductor package has a form in which an input/output terminal of a semiconductor wafer is rewired and arranged outside the semiconductor wafer by a connection member formed on the semiconductor wafer. Therefore, even in the case where the size of the semiconductor wafer is reduced, the standardized ball layout can be used in the fan-out type semiconductor package as well, so that the fan-out type semiconductor package can be mounted on the main board of the electronic device without using a separate interposer. , as described below.

FIG. 8 is a cross-sectional view showing a state in which a fan-out type semiconductor package is mounted on a main board of an electronic device.

Referring to the drawings, the fan-out type semiconductor package 2100 may be mounted on the main board 2500 of the electronic device via solder balls 2170 or the like. That is, as described above, the fan-out type semiconductor The package 2100 includes a connection member 2140 formed on the semiconductor wafer 2120 and capable of rewiring the connection pad 2122 to a fan-out area outside the area of the semiconductor wafer 2120, thereby enabling practical use in the fan-out type semiconductor package 2100 Standardized ball layout. Therefore, the fan-out type semiconductor package 2100 can be mounted on the main board 2500 of the electronic device without using a separate interposer or the like.

As described above, since the fan-out type semiconductor package can be mounted on the main board of the electronic device without using a separate interposer, the fan-out type semiconductor package can be thinner than the thickness of the fan-in type semiconductor package using the interposer substrate. Implemented in the case. Therefore, the fan-out type semiconductor package can be miniaturized and thinned. In addition, the fan-out type semiconductor package has excellent thermal and electrical characteristics, which makes the fan-out type semiconductor package particularly suitable for use in mobile products. Therefore, the fan-out type semiconductor package can be implemented in a smaller form than a general package-on-package (POP) type using a printed circuit board (PCB), and the fan-out type semiconductor package can solve the cause The problem of bending.

Meanwhile, the fan-out type semiconductor package means a packaging technique as described above for mounting a semiconductor wafer on a main board or the like of an electronic device and protecting the semiconductor wafer from external influence, and with a printed circuit board such as an interposer substrate ( The PCB is different in concept, and the printed circuit board has a different specification and purpose from the fan-out type semiconductor package and has a fan-in type semiconductor package embedded therein.

An ultra-small, ultra-thin fan-out type semiconductor package having a fingerprint recognition function will be described below with reference to the drawings.

Figure 9 is a cross-sectional view showing an embodiment of a fan-out type semiconductor package.

Fig. 10 is a plan view schematically taken along line I-I' of the fan-out type semiconductor package of Fig. 9.

FIG. 11 is a schematic view showing an embodiment of M1 and M2 of the fan-out type semiconductor package of FIG. 9.

FIG. 12 is a schematic view showing another embodiment of M1 and M2 of the fan-out type semiconductor package of FIG. 9.

Referring to the drawings, a fan-out type semiconductor package 100A according to an exemplary embodiment of the present disclosure may include a first connection member 110, a semiconductor wafer 120, an encapsulant 130, and a second connection member 140. The first connection member 110 has a through hole 110H. The semiconductor wafer 120 is disposed in the through hole 110H of the first connecting member 110 and has an active surface and an inactive surface opposite to the active surface. The active surface is provided with a connection pad 122. The encapsulant 130 encloses at least a portion of the first connection member 110 and at least a portion of the semiconductor wafer 120. The second connection member 140 is disposed on the active surfaces of the first connection member 110 and the semiconductor wafer 120. The first connection member 110 may be connected to the semiconductor wafer 120 via the second connection member 140. The first connection member 110 may include a plurality of redistribution layers 112a, a redistribution layer 112b, and a redistribution layer 112c electrically connected to the connection pads 122. The second connection member 140 may include a plurality of redistribution layers 142 that are electrically connected to the connection pads 122. The one of the plurality of redistribution layers 112a, the redistribution layer 112b, and the redistribution layer 112c of the first connection member 110 may be disposed on the plurality of insulation layers 111a and the insulation layers 111b forming the first connection member 110. between. Among the plurality of redistribution layers 142 of the second connection member 140, the redistribution layer M1 and the redistribution layer M2 are disposed outside the second connection member 140, and the redistribution layer M1 and The redistribution layer M2 may include a sensor pattern Tx and a sensor pattern Rx that can recognize a fingerprint by accurately detecting a change in capacitance.

The fingerprint identification sensor structure according to the related art is generally a four-layer cored-type general ball grid array (BGA) based on a copper clad laminate (CCL). Substrate structure. For example, a semiconductor wafer surface is mounted on a lower surface of a ball grid array substrate using a connection member having a pattern formation having a fingerprint recognition sensor function on a lower surface thereof. Solder balls or the like are formed at the same level to mount the ball grid array substrate on which the semiconductor wafer is mounted on the lower surface on the main board of the electronic device. In this substrate structure, it is difficult to form fine wiring on the Tx layer and the Rx layer and to make the Tx layer and the Rx layer ultra-thin (this is important in improving the sensitivity of transmission and reception of the inductor), and it is technically difficult to ensure the outermost The complete flatness of the contact layer. In addition, ferroelectric insulating materials are required to improve the touch sensing efficiency including the Tx layer and the Rx layer, but it is difficult to use materials other than the existing substrate materials. In addition, since the semiconductor wafer and the passive component are mounted on the lower end portion of the substrate, the thickness of the semiconductor wafer and the thickness of the passive component are limited, and the height of the solder ball needs to be high. In addition, recent customers have increased the demand for the overall thickness of the fingerprint sensor to be easily changed from ultra-thin to thick without changing the wiring layer, so that the fingerprint sensor is suitable for various applications. Therefore, there has been a high demand for the development of new structures that make fingerprint identification sensors suitable for various applications.

In the fan-out type semiconductor package 100A according to the exemplary embodiment, the sense is included The redistribution layer 142 of the second connection member 140 of the heater pattern Tx and the inductor pattern Rx can be fabricated by a semiconductor method, so that the insulating layer can be ultra-fine patterned and thinned, thereby improving the transmission and reception sensitivity of the inductor. Further, in the case where the thickness of the semiconductor wafer 120 can be easily changed depending on the required specifications, the overall thickness of the fan-out type semiconductor package 100A can be easily adjusted by adjusting the first connection member 110. In addition, the semiconductor wafer 120 may be disposed in the through hole 110H of the first connection member 110 such that the height of the connection terminal 170 for the fan-out type semiconductor package to be connected to the main board of the electronic device may be reduced. In addition, the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c may be formed in the first connection member 110 to further reduce the thickness and improve the performance of the fan-out type semiconductor package 100A. In particular, the redistribution layer 112b may be formed between the insulating layer 111a constituting the first connection member 110 and the insulating layer 111b to remarkably enhance this effect.

Meanwhile, the sensor pattern Tx and the sensor pattern Rx may include a Tx (Transfer Transistor) pattern and an Rx (Reset Transistor) pattern, and the Tx pattern and the Rx pattern are in different layers M1 and layers. Formed on M2. In this case, the Tx pattern and the Rx pattern may be arranged in a mesh form with respect to the transparent surface. In addition, when a precision circuit technique is applied in pattern formation, an Rx pattern can be formed such that the line width Wr of the Rx pattern is narrow and the interval Sr between the Rx patterns is wide, and the Tx pattern can be formed such that the line width Wt is wide And the interval St between the Tx patterns is narrow. Here, the line width Wt of the Tx pattern is larger than the line width Wr of the Rx pattern, and the interval St between the Tx patterns is smaller than the interval Sr between the Rx patterns. Therefore, the Tx pattern can easily transmit the recognized signal to the Rx pattern through a wide area. And the transmitted signal can be transmitted to the other layers M3 and M4 via the via holes.

Alternatively, the sensor pattern Tx and the sensor pattern Rx may include a Tx pattern and an Rx pattern formed on the same layer M1. In this case, an M2 layer can be omitted, which is different from the case shown in the drawing. That is, the sensor pattern Tx and the inductor pattern Rx can be formed on the same layer M1 using a fine spacing technique. In this case, the Tx pattern and the Rx pattern may be arranged in a diamond shape with a predetermined interval g between the patterns to significantly enhance the sensing sensitivity. The individual pads of the Tx pattern can be connected to each other again via the via holes on the layer M3 below the layer M1 to improve the sensing sensitivity. The pads of the Rx pattern can be connected to each other via the precision circuit on the outermost layer M1. The Tx pattern and the Rx pattern may be arranged in a diamond shape with a predetermined interval g between the Tx pattern and the Rx pattern. The specific form of the Tx pattern and the Rx pattern is not particularly limited. For example, the corners of the individual patterns may be round, as shown in the figures.

At the same time, the passivation layer 150 may be further disposed on the second connection member 140. In this case, the dielectric constant of the passivation layer 150 may be greater than the dielectric constant of the insulating layer 141 constituting the second connection member 140. That is, an insulating material having a high dielectric constant (for example, a ferroelectric insulating material) can be used in the passivation layer 150, and the passivation layer 150 has a sensor pattern Tx and a sensor pattern Rx configuration. In this case, the sensitivity of the induction can be more effectively improved.

Meanwhile, at least one layer M3 of the redistribution layer 142 of the second connection member 140 may include an electromagnetic wave blocking pattern. The electromagnetic wave blocking pattern may be, for example, a plate shape. The electromagnetic wave blocking pattern can block the semiconductor wafer 120 and have a routing pattern in the redistribution layer 142. Electromagnetic waves generated by layers M4 and the like. Depending on the configuration, the electromagnetic wave blocking pattern can also block electromagnetic waves generated by other components.

The individual components included in the fan-out type semiconductor package 100A according to an exemplary embodiment will be described in more detail below.

The first connection member 110 maintains the rigidity of the fan-out type semiconductor package 100A depending on a specific material, and the first connection member 110 can be used to ensure uniformity of the thickness of the envelope body 130. The semiconductor wafer 120 and the second connecting member 120 can be electrically connected to the main board of the electronic device via the first connecting member 110 via the connection terminal 170 or the like. The first connection member 110 may include the plurality of redistribution layers 112a, the redistribution layer 112b, and the redistribution layer 112c to effectively rewire the connection pads 122 of the semiconductor wafer 120, and the first connection member 110 may provide a width A wide wiring design region to significantly suppress the formation of the redistribution layer in other regions. The semiconductor wafer 120 may be disposed in the through hole 110H to be separated from the first connection member 110 by a predetermined distance. The side surface of the semiconductor wafer 120 may be surrounded by the first connection member 110. Individual passive components 190 (eg, capacitors or inductors) may be further disposed in the through holes 110H, and the passive components 190 may be electrically connected to the semiconductor wafers 120. However, this is only an example.

The first connection member 110 may include a first insulating layer 111a, a first red wiring layer 112a, a second red wiring layer 112b, a second insulating layer 111b, and a third redistribution layer 112c. The first redistribution layer 112a contacts the second connection member 140 and is embedded in the first insulating layer 111a. The second redistribution layer 112b is disposed on the other surface of the first insulating layer 111a with respect to the surface of the first insulating layer 111a in which the first redistribution layer 112a is embedded. On the surface. The second insulating layer 111b is disposed on the first insulating layer 111a and covers the second redistribution layer 112b. The third redistribution layer 112c is disposed on the second insulating layer 111b. The first redistribution layer 112a, the second redistribution layer 112b, and the third redistribution layer and 112c may be electrically connected to the connection pads 122. The first redistribution layer 112a and the second redistribution layer 112b, the second redistribution layer 112b, and the third redistribution layer 112c may pass through the first via holes 113a and the first through the first insulating layer 111a and the second insulating layer 111b, respectively. The two via holes 113b are electrically connected to each other.

Since the first redistribution layer 112a is embedded in the first insulating layer 111a, the insulating distance of the insulating layer 141 of the second connecting member 140 may be substantially fixed. Since the first connection member 110 may include a large number of the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c, the second connection member 140 may be further simplified. Therefore, the yield reduction of the defects occurring in the process of forming the second connecting member 140 can be suppressed, and the second connecting member 140 can be thinned. The first redistribution layer 112a may be recessed into the first insulating layer 111a such that there is a step between the lower surface of the first insulating layer 111a and the lower surface of the first redistribution layer 112a. Therefore, when the encapsulant 130 is formed, the material of the encapsulant 130 can be prevented from infiltrating the phenomenon of contaminating the first redistribution layer 112a.

The lower surface of the first redistribution layer 112a of the first connection member 110 may be disposed higher than the level of the lower surface of the connection pad 122 of the semiconductor wafer 120. In addition, the distance between the redistribution layer 142 of the second connection member 140 and the first redistribution layer 112a of the first connection member 110 may be greater than the connection pad of the redistribution layer 142 of the second connection member 140 and the first semiconductor wafer 120. The distance between 122. Here, the first redistribution layer 112a may be recessed in the first insulating layer 111a. The first connecting member 110 The level of the double wiring layer 112b may be disposed between the active surface and the inactive surface of the semiconductor wafer 120. The first connection member 110 may be formed to have a thickness corresponding to the semiconductor wafer 120. Therefore, the level of the second redistribution layer 112b formed in the first connection member 110 may be disposed between the active surface and the inactive surface of the semiconductor wafer 120.

The thickness of the first redistribution layer 112a of the first connection member 110, the thickness of the second redistribution layer 112b, and the thickness of the third redistribution layer 112c may be greater than the thickness of the redistribution layer 142 of the second connection member 140. Since the thickness of the first connection member 110 may be equal to or larger than the thickness of the semiconductor wafer 120, the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c may be formed in a large size depending on the specifications of the first connection member 110. On the other hand, the redistribution layer 142 of the second connection member 140 is formed through a precision circuit process (for example, a semiconductor process), and the redistribution layer 142 of the second connection member 140 can be formed to a relatively small thickness.

For example, a material including an inorganic filler and an insulating resin can be used as the material of the insulating layer 111a and the insulating layer 111b. For example, a thermosetting resin such as an epoxy resin or the like; a thermoplastic resin such as a polyimide resin; or a reinforcing such as an inorganic filler (for example, silica, alumina, etc.) may be used. Resin of the material, in more detail, Ajinomoto Build up Film (ABF), FR-4, bismaleimide triazine (BT), photographic imaging dielectric (PID) resin Wait. Alternatively, a resin in which an inorganic filler or a core material (for example, glass fiber (or glass cloth, glass fabric)) is injected into a thermosetting resin or a thermoplastic resin, such as a prepreg or the like, may also be used.

The redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c may be conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), Lead (Pb), titanium (Ti) or alloys thereof. The redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c perform various functions depending on the design of their corresponding layers. For example, the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. Here, the signal pattern may include various signals other than a ground pattern, a power supply pattern, and the like, such as a data signal. In addition, the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c may include a pad pattern for via holes, a pad pattern for connecting terminals, and the like.

The material of each of the via hole 113a and the via hole 113b may be a conductive material. Each of the via hole 113a and the via hole 113b may be completely filled with a conductive material, or a conductive material may be formed along a wall surface of each via hole. When the holes for the via holes 113a and the via holes 113b are formed, some pad patterns of the first redistribution layer 112a and the second redistribution layer 112b may serve as a barrier layer, and thus are advantageous for the via holes 113a and the via holes 113b. Each has a tapered process with an upper surface width greater than the lower surface width. In this case, the via hole 113a and the via hole 113b may be integrated with portions of the second redistribution layer 112b and the third redistribution layer 112c, respectively.

The semiconductor wafer 120 may be an integrated circuit (IC) provided by integrating hundreds to millions of elements or more in a single wafer. The integrated circuit may be, for example, an application-specific integrated circuit (ASIC) capable of performing fingerprint recognition sensing processing. Semiconductor wafer 120 It can be formed on the basis of active wafers. In this case, the base material of the body 121 may be bismuth (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Various circuits can be formed on the body 121. The connection pads 122 can electrically connect the semiconductor wafer 120 to other components. The material of each of the connection pads 122 may be a conductive material such as aluminum (Al) or the like. A passivation layer 123 exposing the connection pads 122 may be formed on the body 121, and the passivation layer 123 may be an oxide film, a nitride film, or the like, or a double layer composed of an oxide layer and a nitride layer. The lower surface of the connection pad 122 may have a step relative to the lower surface of the encapsulant 130 through the passivation layer 123. Therefore, the phenomenon that the encapsulation body 130 penetrates into the lower surface of the connection pad 122 can be prevented to some extent. The insulating layer (not shown) or the like can be further configured in other required positions.

The encapsulant 130 can protect the semiconductor wafer 120. The encapsulation form of the encapsulation 130 is not particularly limited and may be in the form of at least a portion of the encapsulation 130 surrounding the semiconductor wafer 120. For example, the encapsulation 130 may cover at least a portion of the first connection member 110 and at least a portion of the inactive surface of the semiconductor wafer 120, and the encapsulation body 130 may fill the wall surface of the through hole 110H and the side surface of the semiconductor wafer 120. The space between. In addition, the encapsulant 130 may also be filled in at least a portion of the space between the passivation layer 123 of the semiconductor wafer 120 and the second connection member 140. The specific material of the envelope body 130 is not particularly limited. For example, an insulating material can be used as the specific material of the encapsulant 130. In this case, the insulating material may be: a thermosetting resin such as an epoxy resin or the like; a thermoplastic resin such as a polyimide resin; a resin having a reinforcing material such as an inorganic material injected into a thermosetting resin and a thermoplastic resin. Filler), such as Ajinomoto to form a film, FR-4, BT, Photographic Imaging (PID) resin Wait. Further, a known molding material such as an epoxy molding compound (EMC) or the like can also be used. Alternatively, a resin in which an inorganic filler or a core material (for example, glass fiber (or glass cloth, glass fabric)) is injected into a thermosetting resin or a thermoplastic resin may be used as the insulating material.

The second connection member 140 may rewire the connection pads 122 of the semiconductor wafer 120, and the second connection member 140 may include a redistribution layer 142 that may implement a highly sensitive fingerprint recognition function. The tens to hundreds of connection pads 122 having various functions may be re-routed by the second connection member 140, and the connection pads 122 may be physically connected or electrically connected to an external source via the connection terminal 170. In addition, a fingerprint recognition function for implementing a high-inspired fingerprint recognition function can be implemented. The second connection member 140 may include an insulating layer 141, a redistribution layer 142, and a via hole 143. The redistribution layer 142 is disposed on the insulating layer 141, and the via hole 143 penetrates the insulating layer 141 and is connected to the redistribution layer 142.

For example, an insulating material may be used as the material of the insulating layer 141. In this case, the insulating material may be: a thermosetting resin such as an epoxy resin or the like; a thermoplastic resin such as a polyimide resin; a resin having a reinforcing material such as an inorganic material injected into a thermosetting resin and a thermoplastic resin. Filler), such as ABF, FR-4, BT, Photosensitive Dielectric (PID) resin, and the like. A photosensitive insulating material (for example, a photosensitive dielectric resin) is used as a material of the insulating layer to facilitate formation of a precise pattern. When necessary, when the insulating layer 141 is a plurality of layers, the materials of the insulating layers 141 may be identical to each other, and may be different from each other. When the insulating layer 141 is a plurality of layers, the insulating layers 141 can be integrated with each other according to a process, thereby making the layers between the insulating layers The boundaries can also be unobvious.

The redistribution layer 142 may include a layer M1, a layer M2, a layer M3, and a layer M4. The layers M1 and M2 are capable of performing a fingerprint recognition function, the layer M3 is capable of performing a shield function, and the layer M4 is capable of performing a rewiring function. The material of each of the redistribution layers 142 may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb). , titanium (Ti) or its alloys, and the like. The redistribution layer 142 performs various functions depending on the design of its corresponding layer. For example, layer M1 may include an Rx pattern and a Tx pattern, or layer M1 and layer M2 may include an Rx pattern and a Tx pattern. Layer M3 may include an electromagnetic wave blocking pattern. Layer M4 may include a ground (GND) pattern, a power supply (PWR) pattern, a signal (S) pattern, and the like. Here, the signal pattern may include various signals other than a ground pattern, a power supply pattern, and the like, such as a data signal. Additionally, these layers M1, M2, M3, and M4 may include various pad patterns.

The via hole 143 can electrically connect the connection pad 122, the redistribution layer 142, and the like formed on the different layers to each other, thereby generating an electrical path in the fan-out type semiconductor package 100A. The material of each of the via holes 143 may be, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti). Or a conductive material such as an alloy thereof. The conductive material may completely fill each of the via holes 143, or the conductive material may be formed along the wall surface of each of the via holes. In addition, each of the via holes 143 may have all shapes known in the related art, such as a taper, a cylinder, or the like.

The passivation layer 150 can protect the second connection member 140 from external physical or chemical Learn to damage. The passivation layer 150 can be the outermost layer of the fingerprint contact. The material of the passivation layer 150 is not particularly limited, but may be a known insulating material. However, ferroelectric insulating materials can be used as a material for the passivation layer to improve the efficiency of touch sensing. For example, the dielectric constant of the passivation layer 150 may be greater than the dielectric constant of the insulating layer 141 of the second connection member 140.

The under bump metal layer 160 may additionally be used to improve the connection reliability of the connection terminal 170 and improve the board level reliability of the fan-out type semiconductor package 100A. The under bump metal layer 160 may be connected to the third redistribution layer 112c of the first connection member 110 exposed through the opening 131 of the encapsulation 130. The under bump metal layer 160 may be formed in the opening 131 of the passivation layer 130 by a known metallization method using a known conductive material (eg, metal), but not limited thereto.

The connection terminal 170 may additionally be used to physically or electrically connect the fan-out type semiconductor package 100A. For example, the fan-out type semiconductor package 100A can be mounted on the main board of the electronic device via the connection terminal 170. Each of the connection terminals 170 may be formed of a conductive material such as solder or the like. However, this is merely an example, and the material of each of the connection terminals 170 is not limited thereto. Each of the connection terminals 170 may be a land, a ball, a pin, or the like. The connection terminal 170 may be formed in a multilayer structure or a single layer structure. When the connection terminal 170 is formed in a multilayer structure, the connection terminal 170 may include a copper (Cu) pillar and solder. When the connection terminal 170 is formed in a single layer structure, the connection terminal 170 may include tin-silver solder or copper. However, this is merely an example, and the connection terminal 170 is not limited thereto.

The number, interval, or configuration of the connection terminals 170 are not particularly limited, and It can be substantially modified by those of ordinary skill in the art, depending on the design details. For example, according to the number of the connection pads 122 of the semiconductor wafer 120, the connection terminals 170 can be set in the number of tens to thousands, but not limited thereto, and can also be set to tens to thousands or more. Quantity or number of tens to thousands or less. When the connection terminal 170 is a solder ball, the connection terminal 170 may cover a side surface of the under bump metal layer 160 that extends to the lower surface of the passivation layer 130, and the connection reliability may be more excellent.

At least one of the connection terminals 170 may be disposed in the fan-out area. The fan-out area is an area other than the area in which the semiconductor wafer 120 is disposed. That is, the fan-out type semiconductor package 100A according to the exemplary embodiment may be a fan-out type package. Compared to fan-in packages, fan-out packages offer excellent reliability, fan-out packages can implement multiple input/output (I/O) terminals, and fan-out packages can facilitate three-dimensional ( 3D) Internal connection. In addition, compared to a ball grid array (BGA) package, a land grid array (LGA) package, etc., the fan-out package can be mounted on an electronic device without a separate board. . Therefore, the fan-out type package can be made to have a relatively small thickness, and the fan-out type package can be price competitive.

Meanwhile, although not shown in the drawings, the metal layer may be further disposed on the wall surface of the through hole 110H as necessary. A metal layer can be used to effectively dissipate the heat generated by the semiconductor wafer 120. In addition, the metal layer can also be used to block electromagnetic waves. In addition, the number of the through holes 110H may be plural, and the semiconductor wafer 120 or the passive component may be disposed in the through holes 110H, respectively. In addition to the above structure, a known structure in the related art can be applied.

Figure 13 is a cross-sectional view showing a modified embodiment of the fan-out type semiconductor package of Figure 9.

Referring to the drawings, in the fan-out type semiconductor package 100B according to the modified embodiment, the redistribution layer 142 of the second connection member 140 may include a layer M1, a layer M2, and a layer M3, and the layers M1 and M2 can perform fingerprint recognition functions. Layer M3 is capable of rewiring functions. A layer capable of performing a shielding function can be omitted. In this case, the thickness of the insulating layer closest to the semiconductor wafer 120 in the insulating layer 141 of the second connecting member 140 may be greater than the thickness of the other insulating layers. The shielding function can be performed via a difference in thickness such that the second connecting member can be further thinned. Meanwhile, the layer M1 and the layer M2 may also function as one layer depending on the design of the sensor pattern Tx and the sensor pattern Rx. The architectural description repeated as described above will be omitted below.

Figure 14 is a cross-sectional view showing a modified embodiment of the fan-out type semiconductor package of Figure 9.

Referring to the drawings, in the fan-out type semiconductor package 100C according to another modified embodiment, the semiconductor wafer 120 may be disposed in a downwardly facing form in the drawing. In this case, the second connection member 140b may be disposed on the inactive surface of the semiconductor wafer 120, the second connection member 140b includes the redistribution layer 142b, and the redistribution layer 142b includes a plurality of layers M1, M2 for performing the above functions, and The layer M3, and the third connecting member 140a can be disposed on the active surface of the semiconductor wafer 120, the third connecting member 140a includes the redistribution layer 142a, and the main purpose of the redistribution layer 142a is to rewire the connection pads 122 of the semiconductor wafer 120. . The second connection member 140b and the third connection member 140a may be connected to each other via the first connection member 110. Second connecting member 140b The insulating layer 141b may be formed of an insulating material (for example, Photographic Imaging Dielectric (PID) resin), and the redistribution layer 142b and the via hole 143b of the second connection member 140b may be formed of a known conductive material such as copper (Cu) or the like. The insulating layer 141a of the third connection member 140a may be formed of an insulating material (for example, Photographic Imaging Dielectric (PID) resin), and the redistribution layer 142a and the via hole 143a of the third connection member 140a may be made of a known conductive material (for example: Copper) is formed. The layer M1, the layer M2 and the layer M3 of the second connecting member 140b are visually designed and modified as described above. The architectural description repeated as described above will be omitted below.

Figure 15 is a cross-sectional view showing another embodiment of a fan-out type semiconductor package.

Figure 16 is a plan view schematically taken along line II-II' of the fan-out type semiconductor package of Figure 15 .

Referring to the drawings, according to the fan-out type semiconductor package 100D of another exemplary embodiment of the present disclosure, the first connection member 110 may include: a first insulating layer 111a, a first redistribution layer 112a, a second redistribution layer 112b, and a first The second insulating layer 111b, the third redistribution layer 112c, the third insulating layer 111c, and the fourth redistribution layer 112d. The first redistribution layer 112a and the second redistribution layer 112b are respectively disposed on surfaces facing the first insulating layer 111a. The second insulating layer 111b is disposed on the first insulating layer 111a and covers the first redistribution layer 112a. The third redistribution layer 112c is disposed on the second insulating layer 111b. The third insulating layer 111c is disposed on the first insulating layer 111a and covers the second redistribution layer 112b. The fourth redistribution layer 112d is disposed on the third insulating layer 111c. First redistribution layer 112a, second redistribution layer 112b, third redistribution layer 112c, and fourth redistribution The layer 112d can be electrically connected to the connection pad 122. Since the first connection member 110 may include a larger number of the redistribution layer 112a, the redistribution layer 112b, the redistribution layer 112c, and the redistribution layer 112d, the second connection member 140 may be further simplified. The first redistribution layer 112a and the second redistribution via the first via hole 113a, the second via hole 113b, and the third via hole 113c penetrating through the first insulating layer 111a, the second insulating layer 111b, and the third insulating layer 111c, respectively The layer 112b, the third redistribution layer 112c, and the fourth redistribution layer 112d may be electrically connected to each other.

The thickness of the first insulating layer 111a may be greater than the thickness of the second insulating layer 111b and the thickness of the third insulating layer 111c. Basically, the first insulating layer 111a may be relatively thick to maintain rigidity, and the second insulating layer 111b and the third insulating layer 111c may be introduced to form a larger number of the redistribution layer 112c and the redistribution layer 112d. The insulating material included in the first insulating layer 111a may be different from the insulating material included in the second insulating layer 111b and the third insulating layer 111c. For example, the first insulating layer 111a may be formed, for example, as a prepreg including a core material, an inorganic filler, and an insulating resin, and the second insulating layer 111b and the third insulating layer 111c may be an Ajinomorphic film (ABF) or A photosensitive insulating film including an inorganic filler and an insulating resin is formed. However, the materials of the first insulating layer 111a, the second insulating layer 111b, and the third insulating layer 111c are not limited thereto. Similarly, the diameter of the first via hole 113a may be larger than the diameter of the second via hole 113b and the diameter of the third via hole 113c.

The lower surface of the third redistribution layer 112c of the first connection member 110 may be disposed at a lower level than the lower surface of the connection pad 122 of the semiconductor wafer 120. In addition, the redistribution layer 142 of the second connection member 140 and the third weight of the first connection member 110 The distance between the wiring layers 112c may be smaller than the distance between the redistribution layer 142 of the second connection member 140 and the connection pads 122 of the first semiconductor wafer 120a. Here, the third redistribution layer 112c may be disposed on the second insulating layer 111b in a protruding form to contact the second connection member 140. The first red wiring layer 112a and the second red wiring layer 112b of the first connection member 110 may be disposed at a level between the active surface and the inactive surface of the semiconductor wafer 120. The first connection member 110 may be formed to have a thickness corresponding to the thickness of the semiconductor wafer 120. Therefore, the first red wiring layer 112a and the second red wiring layer 112b formed in the first connection member 110 may be disposed at a level between the active surface and the inactive surface of the semiconductor wafer 120.

The thickness of the first redistribution layer 112a, the second redistribution layer 112b, the third redistribution layer 112c, and the fourth redistribution layer 112d of the first connection member 110 may be greater than the thickness of the redistribution layer 142 of the second connection member 140. Since the thickness of the first connection member 110 may be equal to or larger than the thickness of the semiconductor wafer 120, the redistribution layer 112a, the redistribution layer 112b, the redistribution layer 112c, and the redistribution layer 112d may also be formed to have a large size. On the other hand, the redistribution layer 142 of the second connection member 140 may be formed to a relatively small thickness. The architectural description repeated as described above will be omitted below.

Figure 17 is a cross-sectional view showing a modified embodiment of the fan-out type semiconductor package of Figure 15.

Referring to the drawings, in the fan-out type semiconductor package 100E according to the modified embodiment, the redistribution layer 142 of the second connection member 140 may include a layer M1, a layer M2, and a layer M3, and the layers M1 and M2 can perform fingerprint recognition functions. And layer M3 can perform the rewiring function. A layer capable of performing a shielding function can be omitted. In this case Next, the thickness of the insulating layer in the insulating layer 141 of the second connecting member 140 that is closest to the semiconductor wafer 120 may be greater than the thickness of the other insulating layers. The shielding function can be performed via a difference in thickness such that the second connecting member can be further thinned. Meanwhile, the layer M1 and the layer M2 may also function as one layer depending on the design of the sensor pattern Tx and the sensor pattern Rx. The architectural description repeated as described above will be omitted below.

Figure 18 is a cross-sectional view showing a modified embodiment of the fan-out type semiconductor package of Figure 15.

Referring to the drawings, in the 100F of the fan-out type semiconductor package according to another modified embodiment, the semiconductor wafer 120 may be disposed in a downward-facing form in the drawing. In this case, the second connection member 140b may be disposed on the inactive surface of the semiconductor wafer 120, the second connection member 140b includes the redistribution layer 142b, and the redistribution layer 142b includes a plurality of layers M1, M2 for performing the above functions, and The layer M3, and the third connecting member 140a can be disposed on the active surface of the semiconductor wafer 120, the third connecting member 140a includes the redistribution layer 142a, and the main purpose of the redistribution layer 142a is to rewire the connection pad 122 of the semiconductor wafer 120. . The second connection member 140b and the third connection member 140a may be connected to each other via the first connection member 110. The insulating layer 141b of the second connection member 140b may be formed of an insulating material (for example, Photographic Imaging Dielectric (PID) resin), and the redistribution layer 142b and the via hole 143b of the second connection member 140b may be formed of a known conductive material, for example, for example Copper and so on. The insulating layer 141a of the third connecting member 140a may be formed of an insulating material such as a photosensitive imaging dielectric (PID) resin, and the redistribution layer 142a and the via hole 143a of the third connecting member 140a may be formed of a known conductive material such as copper. Layer M1, layer M2 of the second connecting member 140b and Layer M3 is visually designed and modified as described above. The architectural description repeated as described above will be omitted below.

As described above, according to an exemplary embodiment of the present disclosure, an ultra-small, ultra-thin fan-out type semiconductor package having a fingerprint recognition function can be provided.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and it is intended to be a part of the invention, and may be modified and modified without departing from the spirit and scope of the invention.

Claims (19)

A fan-out type semiconductor package includes: a first connecting member having a through hole; a semiconductor wafer disposed in the through hole of the first connecting member, and having an active surface and a non-active surface opposite to the active surface a contact pad disposed on the active surface; an encapsulation covering at least a portion of the first connection member and at least a portion of the semiconductor wafer; and a second connection member disposed on the first connection member and The semiconductor wafer, wherein the first connecting member and the second connecting member respectively comprise a first redistribution layer and a second redistribution layer, and the first redistribution layer and the second redistribution layer are electrically Connected to the connection pad and formed of one or more layers, at least one of the first redistribution layers being disposed between the plurality of insulation layers of the first connection member, and the second At least one of the redistribution layers includes a sensor pattern that recognizes a fingerprint; and a passive component is disposed in the through hole, wherein the passive component is electrically connected to the connection pad. The fan-out type semiconductor package according to claim 1, wherein the inductor pattern includes a Tx pattern and an Rx pattern formed on different layers, and the Tx pattern and the Rx pattern are configured in a mesh form. . The fan-out type semiconductor package of claim 2, wherein a line width of the Tx pattern is larger than a line width of the Rx pattern, and an interval between the Tx patterns is smaller than between the Rx patterns interval. The fan-out type semiconductor package of claim 1, wherein the inductor pattern comprises a Tx pattern and an Rx pattern formed on the same layer, and the Tx pattern and the Rx pattern are arranged in a diamond shape. The fan-out type semiconductor package of claim 1, further comprising a passivation layer disposed on the second connection member; wherein the passivation layer has a dielectric constant greater than the second connection The dielectric constant of the insulating layer of the member. The fan-out type semiconductor package of claim 1, wherein at least one of the second redistribution layers comprises an electromagnetic wave blocking pattern. The fan-out type semiconductor package of claim 1, wherein the second connecting member comprises a plurality of insulating layers, and the plurality of insulating layers of the second connecting member are the most The thickness of the adjacent insulating layer is greater than the thickness of the other insulating layers of the second connecting member. The fan-out type semiconductor package of claim 1, wherein the second connection member is disposed on the active surface of the semiconductor wafer, and the first connection member is connected by the second connection A member is coupled to the semiconductor wafer. The fan-out type semiconductor package of claim 1, further comprising a third connecting member, the third connecting member including a third redistribution layer, the third redistribution layer being electrically connected to the connection The pad is formed by one or more layers, wherein the second connecting member is disposed on the inactive surface of the semiconductor wafer, and the third connecting member is disposed on the active surface of the semiconductor wafer And the second connecting member and the third connecting member are connected to each other by the first connecting member. The fan-out type semiconductor package of claim 1, wherein the first connecting member comprises: a first insulating layer; a 1-1st redistribution layer embedded in the first insulating layer; a second wiring layer disposed on the other surface of the first insulating layer opposite to a surface in which the 1-1st redistribution layer is embedded; a second insulating layer disposed on the first insulating layer And covering the 1-2th rewiring layer; and the 1-3th rewiring layer, disposed on the second insulating layer. The fan-out type semiconductor package according to claim 10, wherein the lower surface of the 1-1st rewiring layer has a step with respect to a lower surface of the first insulating layer. The fan-out type semiconductor package according to claim 1, wherein the first connecting member comprises: a first insulating layer; a 1-1st rewiring layer and a 1-2th rewiring layer, respectively disposed in the On the opposite surface of the first insulating layer; the second insulating layer, And disposed on the first insulating layer and covering the 1-1st redistribution layer; and the 1-3th redistribution layer disposed on the second insulating layer. The fan-out type semiconductor package according to claim 12, wherein the first connecting member further includes a third insulating layer and a 1-4th rewiring layer, and the third insulating layer is disposed in the first The 1-2th redistribution layer is covered on the insulating layer, and the 1-4th redistribution layer is disposed on the third insulating layer. The fan-out type semiconductor package of claim 12, wherein the thickness of the first insulating layer is greater than the thickness of the second insulating layer. A fan-out type semiconductor package includes: a first connecting member having a through hole and a first redistribution layer; and a semiconductor wafer disposed in the through hole of the first connecting member and having an active surface and the active a non-active surface opposite to each other, wherein the active surface is provided with a connection pad; an encapsulation body encapsulating at least a portion of the first connection member and at least a portion of the semiconductor wafer; and a second connection member disposed in the a first connecting member and a first side of the semiconductor wafer, and including a second redistribution layer; a connection terminal disposed on the first connection member and a second of the semiconductor wafer opposite to the first side On the side, and including one or more connection terminals disposed in a region not overlapping the semiconductor wafer in a direction from the first side to the second side, wherein the connection terminal Electrically connected to the connection of the semiconductor wafer a pad, and an outermost redistribution layer of the second redistribution layer of the second connection member includes a sensor pattern for recognizing a fingerprint; and a passive component disposed in the through hole, wherein the The passive component is electrically connected to the connection pad. The fan-out type semiconductor package of claim 15, wherein no semiconductor wafer is disposed at a level of the connection terminal. The fan-out type semiconductor package of claim 15, wherein the connection terminal is at least via the first redistribution layer of the first connection member and the second weight of the second connection member One or more of the wiring layers are electrically connected to the connection pads of the semiconductor wafer. The fan-out type semiconductor package of claim 15, wherein the connection pad of the semiconductor wafer faces the second connection member. The fan-out type semiconductor package of claim 15, further comprising a third connecting member, the third connecting member comprising a third redistribution layer interposed between the semiconductor wafer and the connection terminal, Wherein the connection terminal is electrically connected to the connection pad of the semiconductor wafer via at least the third redistribution layer of the third connection member, and the connection pad of the semiconductor wafer faces the first Three connecting members.