TWI646415B - Voltage domain communication - Google Patents

Abstract

The integrated circuit 6 including the first voltage domain 4 incorporates a real-time clock circuit 12 that communicates with a processing circuit 16 contained in the second voltage domain via a communication circuit 18. The communication circuit 18 includes a first parallel-serial conversion circuit 24 located in the first voltage domain 4, a level transfer circuit 32 for transmitting serial signals between the voltage domains, and a second parallel-serial serial located in the second voltage domain Conversion circuit 26.

Description

Communication between voltage domains

The present invention relates to the field of integrated circuits. More specifically, the present invention relates to communication between different voltage domains in an integrated circuit.

It is known to provide integrated circuits that operate in multiple voltage domains. For example, a voltage domain may be designed for low-power operation, such as an immediate clock. This domain can use unregulated power and thick gate oxide transistors. The goal of other voltage domains in the other integrated circuit may be low dynamic power, and therefore use a lower regulation voltage to support the processor core. As the voltage difference increases and the need for lower power consumption also increases, it becomes difficult to communicate signals between these voltage domains.

As can be seen from one aspect, the present invention provides an integrated circuit including: a first processing circuit located in a first voltage domain and configured to operate at a first voltage; a second A processing circuit, the second processing circuit is located in a second voltage domain and is configured to operate at a second voltage, the second voltage being different from the first A voltage; and a communication circuit that is coupled to the first processing circuit and to the second processing circuit, and is configured to communicate one or more between the first processing circuit and the second processing circuit A plurality of multi-bit signals; wherein the communication circuit includes: a first parallel-serial conversion circuit configured to convert the one between a parallel form and a serial form processed by the first processing circuit Or more multi-bit signals for transferring between the first voltage domain and the second voltage domain; a level transfer circuit, the level transfer circuit is configured to connect the first voltage and the second voltage Changing the voltage level of the one or more multi-bit signals in the tandem form between voltages; and a second parallel-to-serial conversion circuit, the second parallel-to-serial conversion circuit is configured to be used by the second processing circuit The one or more multi-bit signals are converted between the processed parallel form and the tandem form for transfer between the first voltage domain and the second voltage domain.

The technology recognizes that when communicating between the first voltage domain and the second voltage domain, by using parallel-to-serial conversion circuits on each side of the level transfer circuit, the need to transfer between the domains having the level transfer circuit is reduced The number of signals that can be obtained outweighs the compensation for the additional burden associated with the parallel-serial conversion circuit.

Although it should be understood that the first processing circuit may take many different forms, the present technology is particularly useful when the first processing circuit includes an instant clock circuit configured to generate an instant clock value. These real-time clocks need to work continuously, and therefore these real-time clocks are designed to have low power. This technology makes it possible to Lu Zhi's special low-power voltage domain communication is more effective.

It should be understood that the multi-bit signals transferred between the two voltage domains can take many different forms. In the case where the first processing circuit includes a real-time clock circuit, these multi-bit signals may include one or more of the following: a time signal that indicates a real-time value, which is to be passed from the real-time clock circuit to the second Processing circuit; time setting signal indicating the instant value, the instant clock circuit is to be set to the instant value, and the time setting signal is passed from the second processing circuit to the instant clock circuit; alarm setting signal, the alarm setting The signal indicates an alarm value, at which the immediate circuit triggers an alarm operation, and transmits the alarm setting signal from the second processing circuit to the immediate clock circuit; and an alarm signal, the alarm signal indicates that the alarm time is reached, and the alarm signal It is transferred from the real-time clock circuit to the second processing circuit.

The second processing circuit can take many different forms. In the context of use with real-time clock circuits, in some embodiments, the second processing circuit has one or more inactive sleep modes, and the real-time clock circuit is configured to trigger the second processing when a predetermined instant value is reached The wake-up reaction in the circuit to convert the second processing circuit from the inactive mode to the active mode.

In order to reduce the signal flow across the voltage domain, in some embodiments, the second processing circuit includes a shadow time register, and the shadow time value from the real-time clock circuit is written into the shadow time register. The second processing circuit can then read this shadow time value instead of having to read the time value from the immediate clock circuit itself, thereby avoiding the need to pass the signal across the voltage domain boundary.

In some embodiments, the shadow register may obtain a snapshot of the real-time clock value that is updated periodically, so that the shadow time value tracks the real-time value. When the second place When the management circuit is in the inactive mode, the update signal and tracking operation will not be performed.

The real-time clock circuit can serve other circuits of a plurality of different processing circuits, each of these processing circuits can be formed in their own domain, or each of these processing circuits can be shared with the first processing circuit Voltage domain. In this case, each of the other processing circuits may have an associated communication circuit for performing the parallel-to-serial conversion and level transfer discussed previously. Therefore, multiple ports using the interface of the present technology can be provided in one circuit of the real-time clock circuit.

In some embodiments, the multi-bit signal passing through the interface between the voltage domains may undergo a conversion between the first code used on one side of the domain boundary and the second code used on the other side of the other domain boundary . For example, Gray coding can be advantageously used in the domain with low static power and high dynamic power to reduce the amount of signal switching, however, on the other side of the voltage domain boundary, conventional binary coding can be used because The code is more directly accessible and easy to operate with standard processing techniques.

In some embodiments, the first voltage domain may be an unregulated voltage, because for very low power operation, the voltage regulation is usually power inefficient. In some embodiments, the first voltage may originate from a charge storage device (such as a battery or supercapacitor) or may be obtained by energy harvesting, and the first processing circuit may use thick gate oxide transistors because of these Transistors are very suitable for low power applications.

The second voltage domain may be a regulated voltage because this permits the use of techniques such as dynamic voltage and frequency scaling in the second voltage domain. The second voltage is usually lower than the first voltage.

As can be seen from another aspect, the present invention provides an integrated circuit including: a first processing means for performing a first processing, and the first processing means is located in a first voltage domain And is set to operate at a first voltage; a second processing means for performing the second processing, and the second processing means is located in the second voltage domain and is configured to operate at the second voltage, the The second voltage is different from the first voltage; and communication means for communicating one or more multi-bit signals between the first processing circuit and the second processing circuit; wherein the communication means includes: First parallel-to-serial conversion means for converting the one or more multi-bit signals between the parallel form and the serial form processed by the first processing circuit for use in the first Transferring between a voltage domain and the second voltage domain; level shifting means for changing the one or more of the tandem form between the first voltage and the second voltage Voltage levels of multiple multi-bit signals; and second parallel-serial conversion means for converting the one or more between the parallel form and the serial form processed by the second processing circuit Multiple multi-bit signals for transferring between the first voltage domain and the second voltage domain.

It can be seen from another aspect that the present invention provides a method of operating an integrated circuit, which includes the following steps: Perform the first process with a first processing circuit located in the first voltage domain and configured to operate at the first voltage; perform with a second processing circuit located in the second voltage domain and configured to operate at the second voltage Second processing, the second voltage is different from the first voltage; and one or more multi-bit signals are communicated between the first processing circuit and the second processing circuit; wherein the step of communicating includes: Converting the one or more multi-bit signals between the parallel form and the tandem form processed by the first processing circuit for transferring between the first voltage domain and the second voltage domain; Changing the voltage level of the one or more multi-bit signals in the serial form between the voltage and the second voltage; and converting the parallel form and the serial form processed by the second processing circuit One or more multi-bit signals are used to transfer between the first voltage domain and the second voltage domain.

The above description and other objects, features, and advantages of the present invention will be apparent from the following detailed description of illustrative embodiments read in conjunction with the accompanying drawings.

2‧‧‧Integrated circuit

4‧‧‧ First voltage domain

6‧‧‧ Second voltage domain

8‧‧‧The third voltage domain

10‧‧‧Wake control circuit

12‧‧‧Real-time clock circuit

14‧‧‧ Gray counter

16‧‧‧Processing circuit

18‧‧‧Communication circuit

20‧‧‧ processing circuit

22‧‧‧Communication circuit

24‧‧‧ Shadow time register/first parallel-serial conversion circuit

26‧‧‧Second parallel-to-serial conversion circuit

28‧‧‧ Binary code Gray code converter/code converter

30‧‧‧ Gray code binary code converter/code converter

32‧‧‧ Level transfer circuit

34‧‧‧Step

36‧‧‧Step

38‧‧‧Step

40‧‧‧Step

42‧‧‧Step

44‧‧‧Step

46‧‧‧Step

48‧‧‧Step

50‧‧‧Step

52‧‧‧Step

Fig. 1 schematically illustrates an integrated circuit including a plurality of voltage domains; Fig. 2 schematically illustrates a communication circuit for transmitting multi-bit signals between a plurality of voltage domains; Fig. 3 is A flowchart that schematically illustrates the process of sending a multi-bit signal from the first domain to the second domain; and FIG. 4 is a flowchart schematically illustrating the process of transmitting a multi-bit signal from the second domain to the first domain.

FIG. 1 schematically illustrates an integrated circuit 2 including a first voltage domain 4, a second voltage domain 6, and a third voltage domain 8. The first voltage domain 4 operates in the case of an unregulated power source originating from a charge storage device (such as a battery or supercapacitor) or by energy harvesting, and the first voltage domain 4 uses thick gate oxide transistors For low power operation. The first voltage domain has a design for achieving low current leakage to allow continuous energization of the first voltage domain, but the first voltage domain suffers from relatively high unfavorable dynamic power consumption. The second voltage domain 6 suffers from relatively high current leakage, but has relatively low dynamic power consumption. Regulated power is supplied to the second voltage domain, which can be gated by power to reduce power consumption. The power gating of the power supply in the second voltage domain allows the circuits in the second voltage domain to be put into the sleep mode, and the wake-up signal generated by the wake-up controller 10 in the first voltage domain can wake the circuit from the sleep mode .

The first voltage domain 4 includes an instant clock circuit 12 formed with a thick gate oxide transistor. The real-time clock circuit 12 includes a gray counter 14 for storing and updating the gray-coded real-time value. The real-time clock circuit 12 includes a memory for storing the number of Gray-coded alarms, which is compared with the current real-time value in the Gray counter 14 and triggers an alarm or wake-up event when a match occurs. The stored number of alarms is set using a multi-bit time setting signal sent from the processing circuit 16 located in the second voltage domain to the real-time clock circuit 12.

Provide a communication circuit in the real-time clock circuit 12 and the processing circuit 16 18. The communication circuit 18 bridges between different operating voltages used in the first domain 4 and the second domain 6. The operating voltage of the first domain 4 is higher than the operating voltage of the second domain 6. Therefore, the communication circuit 18 includes a level transfer circuit which will be described later.

A third voltage domain 8 containing other processing circuits 20 is also provided in the integrated circuit 2. The further processing circuit 20 may have its own associated communication circuit 22 through which the further processing circuit 20 communicates with the real-time clock circuit 12. Therefore, the real-time clock circuit 12 can communicate with different processing circuits 16, 20 via multiple ports. The communication circuit 22 may have a form similar to that of the communication circuit 18.

The processing circuit 16 located in the second domain 6 includes a shadow time register 24 into which the shadow time value of the multi-bit time value supplied from the real-time clock signal is written via the communication circuit 18. This multi-bit time signal is transmitted through the communication circuit 18. When the processing circuit 16 is active (for example, not in the sleep mode), the clock update signal supplied from the real-time clock circuit 12 can be used to update the shadow time value held in the shadow time register 24, so that the processing circuit 16 can switch from the shadow time The scratchpad 24 acquires the immediate value instead of requiring the instant clock circuit 12 itself to read the time value.

The wake-up control circuit 10 is triggered by an instant clock circuit 12 that reaches the wake-up time alarm value to generate a wake-up signal, and sends the wake-up signal to the processing circuit 16 via the communication circuit 18. This can be supplied to the processing circuit 16 as an interrupt, and trigger the processing circuit 16 to exit the sleep state of the processing circuit 16 and return to the active mode in which the processing circuit 16 performs processing.

The processing circuit 16 is responsible for programming the real-time clock circuit 12 via the communication circuit 18, and supplies the time setting signal (multi-bit) to the real-time clock circuit 12, Used for alarm settings and other parameters that may be necessary for both general alarms (multi-bit) and wake-up alarms (multi-bit). The real-time clock circuit 12 passes the real-time clock value (multi-bit) and the alarm signal and the shadow real-time value update trigger back to the processing circuit 16 across the communication circuit 18.

Figure 2 schematically illustrates the communication circuit 18 in more detail. The first parallel-to-serial conversion circuit 24 is provided in the first voltage domain. The second parallel-serial conversion circuit 26 is provided in the second voltage domain. The second parallel-to-serial conversion circuit 26 includes a binary code Gray code converter 28 for sending a binary value from the second voltage domain to the first voltage domain (using the Gray coding method). A Gray code binary code converter 30 is provided in the second parallel-serial conversion circuit 26 for receiving signals in the opposite direction, that is, receiving Gray coded signals, and converting these signals for use in the second voltage domain The second is the binary coded signal. It should be appreciated that such transcoders 28, 30 may be provided at another location within the communication circuit 18 (eg, within the first voltage domain). Binary code Gray code conversion can be performed in a variety of different ways, such as a bit-sequence way when necessary.

Figure 2 illustrates how a wide parallel signal including a multi-bit signal representing at least the wake-up time and time value converts their signals into narrow strings before being passed across the interface between the voltage domains by the level transfer circuit 32列信号。 Column signal. Reducing the number of signals that need to be transferred through this voltage domain interface reduces the additional burden associated with this level shift, and therefore increases the efficiency in a sense, which is surprisingly higher than performing parallel on either side of the interface Compensation required for conversion.

It should be understood that the parallel-to-serial conversion performed is used to produce narrower signals that are passed between multiple domains. The parallel signal does not have to be converted into a single bit stream, but it can simply make the parallel signal narrower. For example, a 32-bit parallel signal can be Reduced to a 2-bit signal, the 2-bit signal is then serially transmitted, for example, via 16 clock cycles, to represent the original 32-bit signal.

Figure 3 is a flow chart that schematically illustrates the transfer of multi-bit signals from the first domain to the second domain. At step 34, the process waits until there is information to send. Step 36 then performs parallel-to-serial conversion on this multi-bit data. Step 38 transfers the generated serial data from the first domain level to the second domain. Step 40 converts the serial data received in the second domain from the serial form to the parallel form. Step 42 converts the received parallel data from the Gray code of the parallel data to a binary code. It should be appreciated that in some embodiments, transcoding may be performed on the other side of the domain boundary.

Figure 4 is a flow chart that schematically illustrates the transfer of multi-bit signals from the second domain to the first domain. At step 44, the process waits until there is material to send. Step 46 converts the multi-bit data from binary encoding to Gray encoding. Step 48 converts the parallel multi-bit signal values into a tandem representation. Step 50 performs level transfer of serial data from the second voltage domain to the first voltage domain. Step 52 converts the serial data received in the first voltage domain from the serial form to the parallel form.

Although the illustrative embodiments of the present invention have been described with reference to the drawings, it should be understood that the present invention is not limited to their precise embodiments, and without departing from the scope and spirit of the invention as defined by the scope of the additional patent application, Those skilled in the art can implement various changes, additions and modifications in the present invention.

Claims (16)

An integrated circuit includes: a first processing circuit, the first processing circuit is located in a first voltage domain, and is configured to operate at a first voltage; a second processing circuit, the second processing The circuit is located in a second voltage domain and is configured to operate at a second voltage that is different from the first voltage; and a communication circuit that is coupled to the first processing circuit and coupled To the second processing circuit, and is configured to communicate one or more multi-bit signals between the first processing circuit and the second processing circuit; wherein the communication circuit includes: a first parallel-serial conversion circuit, the The first parallel-serial conversion circuit is configured to convert the one or more multi-bit signals between a parallel form and a serial form processed by the first processing circuit for transmission from the first voltage domain to The second voltage domain; a level transfer circuit configured to change one of the one or more multi-bit signals in the tandem form between the first voltage and the second voltage Voltage level; and a second parallel-serial conversion circuit configured to convert the one or more multiple bits between a parallel form processed by the second processing circuit and the serial form The meta signal is used to pass from the second voltage domain to the first voltage domain, wherein at least one of the first parallel-serial conversion circuit and the second parallel-serial conversion circuit is configured to be used by the first processing circuit The multi-bit signal is converted between a first code representing a value and a second code used by the second processing circuit to represent the value. The integrated circuit according to claim 1, wherein the first processing circuit includes an instant clock circuit configured to generate an instant clock value. The integrated circuit according to claim 2, wherein the one or more multi-bit signals include at least one of the following: a time signal indicating the transfer from the real-time clock circuit to the second processing circuit An instant value; a time setting signal indicating an instant value, the instant clock circuit is to be set to the instant value, and the time setting signal is passed from the second processing circuit to the instant clock circuit; an alarm Setting signal, the alarm setting signal indicates an alarm value, at which the instant clock circuit is to trigger an alarm operation, and the alarm setting signal is transmitted from the second processing circuit to the instant clock circuit; and an alarm signal, The alarm signal indicates that an alarm time has been reached, and the alarm signal is transmitted from the immediate clock circuit to the second processing circuit. The integrated circuit according to claim 2, wherein the second processing circuit has one or more inactive modes, and the real-time clock signal is set to trigger the second processing circuit when a predetermined instant value is reached A wake-up response to switch the second processing circuit from one of the one or more inactive modes to an active mode. The integrated circuit according to claim 2, wherein the second processing circuit includes a shadow time register, and a shadow time value from the real-time clock circuit is written into the shadow time register. The integrated circuit according to claim 5, wherein the real-time clock circuit is configured to send an update signal to the shadow time register to update the shadow time value to track the real-time value. The integrated circuit according to claim 6, wherein the update signal is not sent when the second processing circuit is in an inactive mode. The integrated circuit according to claim 2, wherein the integrated circuit includes a plurality of further processing circuits, the further processing circuit is coupled to the real-time clock circuit, and the further processing circuit is configured to be different from the first voltage One of the voltage domains and a voltage different from the first voltage. The integrated circuit according to claim 1, wherein the first code is a Gray code and the second code is a binary code. The integrated circuit according to claim 1, wherein the first voltage is an unregulated voltage. The integrated circuit of claim 10, wherein the first voltage comes from one of: directly from a charge storage device; and from energy harvesting. The integrated circuit according to claim 1, wherein the first processing circuit is formed using a thick gate oxide transistor. The integrated circuit according to claim 1, wherein the second voltage is a regulated voltage. The integrated circuit according to claim 1, wherein the second voltage is lower than the first voltage. An integrated circuit includes: a first processing means for performing a first processing, and the first processing means is located in a first voltage domain and is set to a first voltage The second processing means, the second processing means for performing the second processing, and the second processing means is located in a second voltage domain and is configured to operate at a second voltage, the second voltage is different The first voltage; and communication means for communicating one or more multi-bit signals between the first processing circuit and the second processing circuit; wherein the communication means includes: a first parallel-to-serial conversion Means, the first parallel-to-serial conversion means for converting the one or more multi-bit signals between a parallel form and a serial form processed by the first processing circuit, for switching from the first voltage domain Transferred to the second voltage domain; level shifting means for changing the one or more multi-bit signals in the tandem form between the first voltage and the second voltage A voltage level; and second parallel-serial conversion means for converting the one or more multiple bits between a parallel form and a serial form processed by the second processing circuit A meta-signal for transferring from the second voltage domain to the first voltage domain, wherein at least one of the first parallel-serial conversion means and the second parallel-serial conversion means is configured to be controlled by the first The processing means converts the multi-bit signal between a first code representing a value and a second code representing the value by the second processing means. A method of operating an integrated circuit, the method comprising the steps of: performing a first process with a first processing circuit located in a first voltage domain and arranged to operate at a first voltage; using a second processing circuit A second processing circuit in the domain and configured to operate at a second voltage performs second processing, the second voltage is different from the first voltage; and communication between the first processing circuit and the second processing circuit One or more multi-bit signals; wherein the step of communicating includes: converting the one or more multi-bit signals between a parallel form and a serial form processed by the first processing circuit for Passing from the first voltage domain to the second voltage domain; changing one of the voltage levels of the one or more multi-bit signals in the tandem form between the first voltage and the second voltage; Converting the one or more multi-bit signals between a parallel form and a serial form by the second processing circuit for transmission from the second voltage domain to the first voltage domain; The first processing circuit converts the multi-bit signal between a first code representing a value and a second code used by the second processing circuit to represent the value.