TWI643261B - Methods for plasma processing a wafer and plasma controlling, and a plasma reaction system - Google Patents

Abstract

Embodiments of the present invention provide a method of plasma processing a wafer, comprising disposing a wafer on a support member in a reaction chamber. A plasma is generated in the reaction chamber, and ions in the plasma are directed toward the wafer by a first bias voltage. A first ion concentration and a second ion concentration of the plasma are detected at a first position and a second position around the support member, respectively. The first ion concentration and the second ion concentration are compared. When the difference between the first ion concentration and the second ion concentration is greater than a critical value, a plurality of plasma displacement controllers are used to generate a second bias voltage in the reaction chamber to change the direction of travel of the ions in the plasma.

Description

Plasma processing wafer, plasma control method and plasma reaction system

Embodiments of the present invention are directed to a method of controlling a plasma, and more particularly to a method of applying a plasma to a wafer.

The semiconductor integrated circuit industry has experienced rapid growth, and advances in integrated circuit materials and design techniques have produced several generations of integrated circuits. Each generation of integrated circuits has smaller and more complex circuits than the previous generation. In the development of integrated circuits, the density of functions (ie, the number of devices connected per wafer area) typically increases, and the geometry size (ie, the smallest component or line that can be fabricated in the process) ) Zoom out. The downsizing process generally provides the advantage of increasing production efficiency and reducing costs. However, the reduction in size also increases the complexity of the integrated circuit process and manufacturing. In order to achieve these advances, similar developments in integrated circuit manufacturing and manufacturing are also required.

Plasma devices are commonly used in the semiconductor integrated circuit industry to perform a variety of semiconductor processes. For example, plasma devices have been used to clean up wafer surface contamination, deposited material layers, etching, ion cloth values, and plasma doping. The condition or problem of the plasma reaction system will affect the number of good crystal grains per wafer. If the plasma reaction system cannot be solved immediately or the process parameters are adjusted, there will be more wafer processing. The rate is affected.

In view of this, there is a need to find a method of plasma processing a wafer capable of solving the above problems.

Embodiments of the present invention provide a method of plasma processing a wafer, comprising disposing a wafer on a support member in a reaction chamber. A plasma is generated in the reaction chamber, and ions in the plasma are directed toward the wafer by a first bias voltage. A first ion concentration and a second ion concentration of the plasma are detected at a first position and a second position around the support member, respectively. The first ion concentration and the second ion concentration are compared. When the difference between the first ion concentration and the second ion concentration is greater than a critical value, a plurality of plasma displacement controllers are used to generate a second bias voltage in the reaction chamber to change the direction of travel of the ions in the plasma.

Embodiments of the present invention provide a plasma control method comprising providing a support in a reaction chamber, wherein a plurality of isolated segments are disposed around the support member, and each of the isolated segments has a conductive element. The ions of the plasma that are directed toward the wafer from the first direction are detected by each of the conductive elements to generate a plurality of corresponding currents. The ion concentration of each isolated segment is determined based on the corresponding current described above. A plurality of plasma displacement controllers are provided to determine the displacement of the plasma ions in the second direction based on the ion concentration of each of the isolated segments, wherein the first direction is different from the second direction.

Embodiments of the present invention provide a plasma reaction system including an upper electrode assembly located above a reaction chamber and coupled to a first RF power source. The utility model is disposed in the reaction chamber and coupled to the support of the second RF power source. A plurality of plasma displacement controllers disposed outside the reaction chamber surround the space between the support member and the upper electrode assembly in the reaction chamber.

100‧‧‧ Plasma Reaction System

102‧‧‧Reaction chamber

102a‧‧‧Reaction wall

102b‧‧‧ Reaction chamber bottom

103‧‧‧Upper electrode assembly

104‧‧‧Support

106, 106a-106h‧‧‧ Section

108‧‧‧ interval

110‧‧‧ wafer

110a‧‧‧First area

110b‧‧‧Second area

112, 112a-112d‧‧‧ Plasma Displacement Controller

114‧‧‧Conductive components

116‧‧‧Magnetic components

118‧‧‧Detecting current

120, 120a-120h‧‧‧ integrator

122‧‧‧ Controller

124‧‧‧First RF power supply

126‧‧‧ impedance matching circuit

128‧‧‧RF coil set

130‧‧‧ gas inlet

132‧‧‧ Space

134a‧‧‧plate electrode

134b‧‧‧ ring electrode

136‧‧‧second RF power supply

190‧‧‧ openings

200‧‧‧ plasma

300‧‧‧ method

302-310‧‧‧ operation

400A‧‧‧First District

400B‧‧‧Second District

402‧‧‧Base

404‧‧‧Fins

406‧‧‧ dielectric layer

408‧‧ ‧ gate layer

410‧‧‧Isolated area

412‧‧‧ spacer layer

414‧‧‧hard mask layer

416‧‧‧ Plasma

418‧‧‧Lightly doped bungee zone

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic cross-sectional view showing a plasma reaction system in accordance with some embodiments of the present invention.

Figure 2 is a top plan view of a plasma reaction system in accordance with some embodiments of the present invention.

Fig. 3 is a schematic cross-sectional view showing a line tangent to A'-A' of the plasma reaction system shown in Fig. 2 in a part of the embodiment of the present invention.

Figure 4 is a schematic diagram showing the circuit connection of a plasma reaction system according to some embodiments of the present invention.

Figure 5 is a schematic illustration of a plasma reaction system in accordance with some embodiments of the present invention.

Fig. 6 is a schematic view showing the displacement of the plasma after the operation of the plasma controller shown in Fig. 1 in some embodiments of the present invention.

7A-7C are top views of a pattern of plasma ion implanted wafers in accordance with some embodiments of the present invention.

Figure 8 is a flow chart of an exemplary method of some embodiments of the present invention.

Figure 9 is a cross-sectional view showing a semiconductor device according to some embodiments of the present invention.

10A-10E are schematic views of various stages of performing a lightly doped drain process in a semiconductor device in accordance with some embodiments of the present invention.

The following disclosure provides many different embodiments or examples to implement various features of the embodiments of the invention. The disclosure of the present specification is a specific example of the various components and their arrangement in order to simplify the description of the invention. Of course, these specific examples are not intended to limit the embodiments of the invention. For example, if the disclosure of the present specification describes the formation of a first feature in a Above or above the second feature, that is, the embodiment includes the embodiment in which the first feature formed is in direct contact with the second feature, and the additional feature is formed on the first feature and the first An embodiment in which the first feature described above may not be in direct contact with the second feature described above. In addition, different examples in the description of the embodiments of the present invention may use repeated reference symbols and/or words. These repeated symbols or words are used for the purpose of simplification and clarity and are not intended to limit the relationship between the various embodiments and/or the appearance.

Furthermore, for convenience of describing the relationship of one element or feature in the figure to another (plural) element or (complex) feature, space-related terms such as "below" and "below" may be used. , "lower", "above", "upper" and similar terms. It will be understood that the spatially relative terms encompass different orientations of the device in use or operation, in addition to the orientation depicted in the drawings. The device may also be additionally positioned (eg, rotated 90 degrees or at other orientations) and the description of the spatially relevant terms used may be interpreted accordingly. It will be appreciated that additional operational steps may be provided before, during, and after the method, and in some method embodiments, some of the operational steps may be replaced or omitted.

The embodiments discussed below may discuss specific aspects, such as a plasma device that can be applied to implant a dopant between wafers. Those skilled in the art can readily appreciate that other applications may be considered in other embodiments. For example, the method of plasma processing a wafer may be applied to any process having an ion cloth value, and is not limited to the above process.

It should be noted that the embodiments discussed herein may not necessarily describe every component or feature that may be present within the structure. For example, one or more components may be omitted from the drawings, such as when the discussion of the components may be sufficient It is possible to omit various aspects of the embodiment from the drawings. Furthermore, the method embodiments discussed herein may be discussed in a particular order, but in other method embodiments, the order may be performed in any reasonable order.

Before describing embodiments, certain advantageous features and aspects of embodiments of the invention are briefly described. In summary, embodiments of the present invention provide a method for processing a wafer by using a plasma. In the process of implanting a plasma into a wafer, a plasma displacement controller is used to shift the plasma, and the plasma doping can be adjusted. The uniformity of the wafer doping in the step, thus ensuring the performance of the semiconductor device.

1 is a schematic cross-sectional view of a plasma reaction system 100 in accordance with some embodiments of the present invention. The plasma reaction system 100 can be coupled to a process system platform and includes a multi-purpose reaction chamber that can perform a particular process such as an ion implantation process, an etching process, and the like. Although the embodiments of the present invention are expressed in this particular architecture, it will be appreciated that the present invention is also applicable to a variety of other different architectures and designs. Even this plasma reaction system 100 is merely a simple graphical representation, and some portions of the plasma reaction system 100 are not shown. For example, actuators, valves, seal assemblies, and the like are not shown. Those skilled in the art will appreciate that these and other components of the plasma reaction system 100 can be included therein.

As shown in FIG. 1, the plasma reaction system 100 includes a reaction chamber 102, an upper electrode assembly 103, a support member 104, a plasma displacement controller 112, a controller 122, a first RF power source 124, an impedance matching circuit 126, and A second RF power source 136. The plasma reaction system 100 generally includes a reaction chamber 102 that defines at least a portion of the chamber for the process to be a chamber. The reaction chamber 102 includes a reaction chamber wall 102a and a reaction chamber bottom 102b. Reaction chamber wall 102a extends perpendicularly from the edge of the reaction chamber bottom 102b. In some embodiments, one of the slit shutters may be selectively sealed on the reaction chamber wall 102a to facilitate feeding and discharging of the wafer 110 into and out of the plasma reaction system 100. In some embodiments, the reaction chamber bottom 102b includes a suction port (not shown) for withdrawing gas from the reaction chamber 102. For example, an extraction system (including, for example, a throttle valve and a vacuum pump, etc.) can be coupled to the suction port of the reaction chamber bottom 102b. Once the slit shutter is sealed, the pumping system can be operated to draw and maintain a vacuum within the reaction chamber 102.

The upper electrode assembly 103 is located above the reaction chamber 102 and includes a plate electrode 134a at an upper end of the reaction chamber 102, a ring electrode 134b disposed between the plate electrode 134a and the reaction chamber wall 102a, and a radio frequency coil group 128. The ring-shaped electrode 134b is surrounded. In one embodiment, the plate electrode 134a is a showerhead in a gas distribution system. Under this architecture, plate electrode 134a can serve as a component for distributing gas into reaction chamber 102 and is coupled to a source of gas (not shown). This source of gas contains precursors or process gases used to treat the reaction chamber 102. The plate electrode 134a is connected to a DC power source (for example, a ground). In some embodiments, plate electrode 134a, reaction chamber wall 102a, and a reaction chamber bottom 102b are coupled together to ground.

The RF coil assembly 128 is coupled to the first RF power source 124 and generates and maintains the plasma 200 in the reaction chamber 102 by the RF power provided by the first RF power source 124. In one embodiment, the first RF power source 124 is a high frequency RF power source. The first RF power source 124 is coupled to the RF coil assembly 128 via an impedance matching circuit 126 for enhancing process gas dissociation and plasma density. For example, impedance matching circuit 126 can include one or more capacitors, inducers, and other circuit components. The first RF power source 124 has a frequency of approximately 2 MHz or more The rate RF power is supplied to the RF coil group 128, but is not limited thereto. In some embodiments, the first RF power source 124 has a bias voltage between about -30K and +30K volts, and a pulse width during operation of between about 5 and 300 microseconds, but is not limited thereto.

As shown in FIG. 1, the support member 104 is disposed on the reaction chamber bottom 102b of the reaction chamber 102 and is disposed to carry the wafer 110. In some embodiments, ring electrode 134b and RF coil assembly 128 act as the top electrode of plasma reaction system 100, while support member 104 acts as the lower electrode. The support 104 can be any configuration suitable for supporting a wafer, such as an electrostatic chuck or a vacuum chuck. The support member 104 includes a support plane as a support surface for the wafer 110, the shape of which generally conforms to the profile of the wafer 110 to be supported thereon. For example, the surface of the support 104 is generally circular to support a substantially circular wafer 110. In one embodiment, the surface of the support member 104 is coupled to a wafer temperature control system (not shown), such as a resistive heating coil and/or a fluid passageway that connects a heating or cooling fluid system. Support 104 may comprise any of the materials used in plasma reaction system 100. For example, the material of the support 104 comprises steel, other electrically conductive metals or alloys. In some embodiments, the support 104 includes a vacuum system for holding the wafer 110 in place.

In some embodiments, the second RF power source 136 is coupled to the support 104. The second RF power source 136 is a low frequency RF power source that delivers the RF power supply support 104 at a frequency of approximately 0.5 to 10 KHz, but is not limited thereto. In some embodiments, the bias voltage of the second RF power source 136 is between about -0.2 and 10 kilovolts, and the pulse width during operation is between about 20 and 100 microseconds, but is not limited thereto. In an embodiment, by the top electrode (ring electrode 134b and A first bias E1 between the RF coil assembly 128) and the lower electrode (support 104). The ions guiding the plasma 200 impinge on the surface of the wafer 110 in a first direction (for example, in the Y-axis direction). In some embodiments, the second RF power source 136 can also be a DC bias source.

In addition, according to some embodiments, the support member 104 includes a plurality of segments 106, a controller 122, and a plurality of plasma displacement controllers located outside the reaction chamber 102 (eg, the plasma displacement controller 112a and the plasma displacement controller 112b). ). Section 106 is disposed on support 104 and is configured to detect ion concentration. When segment 106 detects the ion concentration of plasma 200, this ion concentration information is passed to controller 122. In some embodiments, the controller 122 determines the output voltages of the plasma displacement controller 112a and the plasma displacement controller 112b based on the information of the ion concentration provided by the segment 106, the plasma displacement controller 112a and the plasma displacement controller. The output voltage difference of both 112b will generate a bias voltage in the reaction chamber 102, and the ions of the plasma 200 change the direction of travel by the bias. The detailed operation mechanism will be described in detail in the relevant paragraph of Fig. 6.

Referring to Figure 2, a second top view is a top view of a plasma reaction system 100 in accordance with some embodiments. As shown in FIG. 2, the support member 104 includes a trench-like opening (not shown) that surrounds the outside of the wafer 110. Each trench-like opening contains a section for detecting ion concentration, such as 106a-106h. It should be noted that the description of section 106a in embodiments of the present invention may be applied to any other section, and each section 106a-106h may be physically isolated by insulating wall 108. Each of the segments 106a-106h can also be electrically insulated from each other by an insulating material or a high dielectric constant material disposed between the segments. The total number and arrangement of segments 106a-106h are not limited to the pattern of the drawings. For example, segments 106a-106h are located on the circumference of support 104 The perimeter, for example, located outside the edge of the wafer 110, can be arranged in any shape or configuration. The segments 106a-106h can be arranged as close as possible to the edge of the wafer 110. In some embodiments, the distance between each segment and its nearest neighboring two segments is the same for each segment in segments 106a-106h.

During the plasma processing of the wafer, ions of the plasma 200 bombard the entire surface of the wafer 110, and portions of the ions will penetrate each of the trench openings and impact each of the segments 106a-106h. The dopant ion concentration for a given region of wafer 110 can be determined when the total charge of ions impinging on segments 106a-106h is measured. For example, if the total number of ions striking the segments 106a-106h increases, the ion concentration implanted into the wafer 110 increases.

Since each segment 106a-106h of the plasma reaction system 100 is physically isolated from each other, the distribution of the plasma ion concentration can be determined when the total charge number of the ions of the impact segments 106a-106h is detected, that is, the crystal can be determined. The distribution of the doping ion concentration for a given area in circle 110. For example, the ion concentration measured by segment 106a is associated with the ion concentration of the A portion of the nearest wafer 110, and the ion concentration measured for segment 106b is the ion of the B portion of the nearest wafer 110. The concentration is related, and so on, the ion concentration of the CH portion of the wafer 110 can be obtained. Since the ion concentration of each of the segments 106a-106h can be separately measured, the uniformity of the ion concentration distribution across the wafer surface in the plasma process can be monitored.

Additionally, in some embodiments, the plasma reaction system 100 includes a plurality of plasma displacement controllers 112a-112d located outside of the reaction chamber 102 and surrounding the reaction chamber 102. The controller 122 can determine the output voltage of each of the plasma displacement controllers 112a-112d according to the ion concentration detected by each of the segments 106a-106h during the plasma processing of the wafer 110, thereby reacting a bias in the cavity 102 The pressure is such that the plasma produces a different displacement than the first direction (i.e., the Y direction), thereby adjusting the ion concentration of the A-H portion of the wafer 110.

In some embodiments, as shown in FIG. 2, the plasma reaction system 100 has a plurality of plasma displacement controllers 112a-112d, and the pair of plasma displacement controllers 112a-112d are respectively located in the reaction chamber 102. On both sides. For example, the plasma displacement controller 112a and the plasma displacement controller 112b are located on a line (e.g., line B'-B') that traverses the center of the reaction chamber 102. In some embodiments, the plasma displacement controllers 112a-112d include coils. The material of the coil may be copper, iron, nickel, titanium, other conductive metals or the above alloys. It is worth noting that the total number and arrangement of the plasma displacement controllers are not limited to the pattern of the drawings. For example, the plasma displacement controller is located around the reaction chamber 102 and can be arranged in any shape or configuration. In some embodiments, the plasma displacement controllers can be located on opposite sides of the reaction chamber 102 that are not horizontal. In some embodiments, the plasma displacement controllers may not be located on opposite sides of the reaction chamber 102, and the plasma displacement controller may be disposed in an asymmetric arrangement around the reaction chamber 102.

Referring to Fig. 3, Fig. 3 is a cross-sectional view, taken along line A'-A' of the plasma reaction system 100 shown in Fig. 2, in part of the embodiment of the present invention. As shown in FIG. 3, the edge of the wafer 110 can be seen above the support member 104. In some embodiments, the section 106a is located at the grooved opening 190 of the support 104. In some embodiments, section 106a has a conductive element 114 within opening 190.

As shown in FIG. 3, ions of the plasma 200 pass through the opening 190 and impinge on the conductive elements 114 in the section 106a. Conductive element 114 can be any metallic material capable of conducting electrical current, such as copper, aluminum, stainless steel, carbon, graphite, other electrically conductive metals or alloys. The conductive element 114 can be a Faraday cup, the shape thereof Shaped like a cup, when the ions of the plasma 200 impinge on the conductive element 114 at various angles, the charge carried by the plasma ions neutralizes to generate an escaped charge, and the inner side wall of the conductive element 114 captures the above-mentioned escaped Charge. The inner side wall of the conductive element 114 may be a right angle or a non-right angle.

The conductive element 114 can act as an element in the circuit, and when the ions of the plasma 200 impinge on the conductive element 114, the conductive element 114 produces a current 118. The magnitude of current 118 is related to the number of ions and ionic charge impinging on conductive element 114 in section 106a. In one embodiment, the magnitude of current 118 is positively correlated with the number of ions and ionic charge impinging on conductive element 114 in section 106a. In some embodiments, the magnitude of current 118 is inversely related to the number of ions and ionic charge impinging on conductive element 114 in section 106a. Moreover, in some embodiments, segment 106a also has a magnetic element 116 that generates a magnetic field that prevents secondary electrons from escaping away from conductive element 114.

In some embodiments, the gap between the conductive element 114 and the support 104 can be filled with an insulating material to hold the conductive element 114 in place. For example, the above insulating material may be a polymer or an epoxy resin. Moreover, in addition to the contiguous point between the conductive element 114 and the support member 104, the gap between the conductive element 114 and the support member 104 can also be an open space.

The foregoing components for detecting plasma ions (for example, the conductive member 114) can be applied to any semiconductor process using plasma, such as ion implantation, plasma etching, plasma enhanced chemical vapor deposition. Deposition, PECVD, plasma enhanced atomic layer deposition (PEALD) and epitaxial growth processes, but are not limited thereto.

Referring to Fig. 4, Fig. 4 is a schematic diagram showing the circuit connection of the plasma reaction system 100 in some embodiments of the present invention. As shown in FIG. 4, each of the sections 106a-106h of the plasma reaction system 100 for detecting the ion concentration of the plasma 200 is coupled to the integrators 120a-120h, respectively. Each integrator 120a-120h can include a plurality of various active or passive components for detecting the current generated by the accumulated charge in the corresponding segment. For example, each integrator 120a-120h can include an ammeter or ammeter. Each integrator 120a-120h generates information (i.e., ion concentration information) of the ion concentration of the plasma received by each of the conductive elements 114 in the segments 106a-106h based on the received current.

Referring to Figure 5, Figure 5 is a schematic illustration of a plasma reaction system 100 in accordance with some embodiments of the present invention. It should be noted that, for the sake of brevity, FIG. 5 only illustrates three sections 106, however, the number of sections 106, integrators 120 and plasma displacement controllers 112 are not limited to those shown in FIG. quantity.

In some embodiments, the plasma reaction system 100 includes a controller 122. The controller 122 is configured to receive ion concentration information from the integrator 120, and determine an output voltage of the plasma displacement controller 112 according to the ion concentration information provided by each integrator 120 to adjust the ion concentration of the plasma 200. Uniformity. In some embodiments, a plurality of segments 106 are arranged around the edge of the wafer 110 and detect ions from the plasma 200 to generate a current (eg, current 118), and the integrator 120 derives each based on the magnitude of the current. The controller 122 receives the ion concentration information from the integrator 120 and determines whether to adjust the output voltage of the plasma displacement controller 112. When the controller 122 adjusts the output voltage of the one or more plasma displacement controllers 112, the pressure difference between the plurality of plasma displacement controllers 112 will generate a bias voltage in the reaction chamber 102, and the bias voltage will be changed. The direction of travel of the ions in the plasma 200 is compensated for by the detection of uneven ion concentration distribution. In some embodiments, controller 122 includes a plurality of processing systems and/or logic for receiving ion concentration information from integrator 120 and comparing the ion concentration of each corresponding segment 106 to thereby determine plasma displacement The output voltage of the controller 112.

After the controller 122 compares the ion concentrations of each corresponding segment 106, the uniformity of the ion concentration distribution is obtained. When the difference between the ion concentrations is greater than a given threshold, the controller 122 can adjust the output voltage of the plasma displacement controller 112. For example, referring to FIGS. 2 and 5, if the region of the highest ion concentration measured by the integrator 120 is twice the region of the lowest ion concentration in the segments 106a-106h, the controller 122 can be powered. During the pulping process, the output voltage of each of the plasma displacement controllers 112a-112d is determined, thereby generating a bias voltage within the reaction chamber 102 to adjust the uniformity of the distribution of ion concentrations. For example, when the ion concentration detected by the segment 106a of FIG. 2 is low, the amount of ion implantation of the A portion representing the wafer 110 by the plasma is small. At this time, the controller 122 adjusts the plasma displacement controllers 112a-112d to generate a bias in the reaction chamber 102 to change the traveling direction of the ions of the plasma 200. Thus, in the next process, more ions of the plasma 200 impinge on the A portion of the wafer 110.

Referring to Fig. 6, Fig. 6 is a cross-sectional view showing a line tangent to B'-B' of the plasma reaction system 100 shown in Fig. 2, which is a partial embodiment of the present invention. In addition, FIG. 6 illustrates that when the plasma displacement controller (eg, the plasma displacement controller 112a and the plasma displacement controller 112b) of the plasma reaction system 100 of FIG. 1 operates, the ions of the plasma 200 are displaced. schematic diagram. In some embodiments, when the plasma reaction system 100 is to adjust the ion concentration doped on the wafer 110, the plasma displacement controller 112a And the plasma displacement controller 112b separately provides different output voltages to generate a second bias E2 in the second direction (for example, the X direction) in the reaction chamber 102, and the second bias E2 guides the ion edge of the plasma 200. The second direction produces a displacement. In some embodiments, the output voltages of the plasma displacement controller 112a and the plasma displacement controller 112b may vary with time, such that the direction and magnitude of the second bias voltage E2 are a function of time, thereby causing the plasma 200 The ions collectively impact an area of the wafer 110. As shown in FIG. 6, if the ion concentration measured by the segment 106 on the right side of the wafer 110 is low, the second bias voltage E2 generated by the plasma displacement controller 112a and the plasma displacement controller 112b, The ions of the plasma 200 can be displaced to the right and concentrated on the right edge of the wafer 110.

In some embodiments, as shown in FIG. 6, the plasma displacement controllers 112a-112b are located outside of the reaction chamber 102 and surround a space 132 between the reaction chamber wall 102a and the support member 104. When the controller 122 determines the output voltage and frequency of each of the plasma displacement controllers, the ions of the plasma 200 can be impacted onto the surface of the wafer 110 in any pattern.

Referring to Figures 7A-7C, Figures 7A-7C are top views of a pattern of plasma implanted wafers 110, in accordance with some embodiments. As shown in FIGS. 7A-7C, the region defining the ion implantation wafer 110 of the plasma 200 is the first region 110a, and the region where the ions of the plasma 200 are not implanted into the wafer 110 is the second region 110b. In some embodiments, the second bias E2 generated by the plasma displacement controller 112 causes the ions of the plasma 200 to be implanted only in the first region 110a of the wafer 110, while the ions of the plasma 200 are not implanted in the wafer. The second region 110b of 110. The pattern of the first region 110a may be a square, a triangle, a sector, or the like. It should be noted that the pattern of the first region 110a is not limited to the pattern shown in FIGS. 7A-7C, and may be other patterns of irregular shapes.

Referring to Figure 8, Figure 8 is a flow diagram of a method 300 of plasma processing a wafer in accordance with some embodiments. Method 300 can be performed by plasma reaction system 100 as shown in Figures 1, 2, 3, and 6. It is to be noted that other steps not shown may be performed without departing from the embodiments of the embodiments of the invention.

The method 300 begins at operation 302, in which a wafer is placed on a support within a reaction chamber. For example, as shown in FIG. 1, wafer 110 is placed on support 104 located within reaction chamber 102.

Next, in operation 304, a plasma is generated in the reaction chamber, and ions in the plasma are directed toward the wafer by a first bias voltage. For example, the first RF power source 124, which is a high frequency RF power source, supplies RF power to the RF coil assembly 128 to generate and maintain the plasma 200 in the reaction chamber 102, and serves as a second RF power source for a low frequency RF power source. 136 delivers an RF power supply support 104. As a result, a first bias E1 between the top electrode (the ring electrode 134b and the RF coil group 128) and the lower electrode (the support member 104) is formed in the reaction chamber 102 in the first direction (for example, the Y direction). The electric field directs ions in the plasma 200 to impinge on the surface of the wafer 110 in a first direction. The plasma 200 can be generated via one or more gases and ionized via radio frequency power provided by the first RF power source 124. The plasma parameters can be influenced by adjusting the frequency and amplitude of the RF power. In addition, the plasma parameters can be adjusted by adjusting the gas flow rate. The plasma parameter is, for example, the energy of the plasma ion.

Next, in operation 306, the first ion concentration and the second ion concentration of the plasma are detected at the first position and the second position around the support. For example, the segment 106a shown in FIG. 2 and the region opposite thereto The segment 106e detects the total charge of the plasma ions measured by the corresponding conductive element 114, and then receives the current generated by the conductive element 114 via the corresponding integrators 120a and 120e, resulting in an impact to the segment 106a and the segment. The ion concentration of the 106e plasma (eg ion concentration information).

Next, in operation 308, the first ion concentration and the second ion concentration are compared. For example, the controller 122 accepts the plasma ion concentration (ion concentration information) of the segments 106a and 106e and compares the differences to determine the uniformity of ions impinging on the surface of the wafer 110.

Next, in operation 310, when the difference between the first ion concentration and the second ion concentration is greater than a threshold, a plurality of plasma displacement controllers are used to generate a second bias voltage in the reaction chamber to change the traveling direction of the plasma. For example, when the difference in ion concentration between the segments 106a and 106e is greater than a given threshold, the output voltage of each of the plasma displacement controllers 112a-112d is determined by the controller 122, thereby generating a different The second bias voltage E2 in one of the directions in the second direction causes the ions of the plasma 200 to be displaced in the second direction (for example, the X direction). When the ion concentration detected by the segment 106a is greater than the ion concentration detected by the segment 106e, and the difference in ion concentration is greater than the critical value, the ion of the plasma 200 may be caused by the segment 106a toward the region by the second bias voltage E2. The direction of the segment 106e is displaced, thereby improving the uniformity of the ion concentration of the plasma process. In some embodiments, the second bias voltage E2 is an alternating current or direct current voltage. In some embodiments, the plasma displacement controller further includes a magnet, and the second bias E2 is slightly modified at the edge of the space 132 by the magnet to improve the uniformity of the ion concentration of the plasma process. In some embodiments, the plasma displacement controller can provide an output voltage and frequency in a bipolar pulse mode to adjust the displacement of ions of the plasma 200.

It should be noted that the above method 300 succinctly describes the flow of the plasma processing wafer, and only describes the ion concentration of the two segments 106a and 106e, but actually can detect the ion concentration of more segments to determine Uniformity of ion concentration.

In a plurality of process steps of fabricating a semiconductor device, a plasma process can be performed by the plasma reaction system 100 described above. Some illustrative steps for forming a semiconductor device are shown in Figures 9 and 10A-10E. In some embodiments, a lightly doped drain (LDD) process is performed using the plasma reaction system 100. Additionally, in some embodiments, the semiconductor device is a fin field effect transistor device. It should be noted that the semiconductor device illustrated in FIG. 9 and FIGS. 10A-10E is only an example of such a device, and some components of the device are omitted for clarity of the lightly doped drain process. That is, the semiconductor device may include other material layers, and the method of forming the semiconductor device may also include other processes.

Figure 9 is a cross-sectional view of the semiconductor device along the X-Y plane, in accordance with some embodiments. 10A-10E are cross-sectional views along the Y-Z plane of a fin 404 in Fig. 9, in accordance with some embodiments. As shown in FIG. 9, the semiconductor device includes a substrate 402. Substrate 402 can be a semiconductor substrate, such as a germanium substrate. In addition, the above semiconductor substrate may also be an elemental semiconductor, including germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide (indium phosphide) ), indium arsenide and/or indium antimonide; alloy semiconductors including bismuth alloy (SiGe), phosphorus arsenide alloy (GaAsP), arsenic aluminum indium alloy (AlInAs), arsenic aluminum gallium Alloy (AlGaAs), arsenic gallium alloy (GaInAs), indium gallium alloy (GaInP) and/or phosphorus indium gallium alloy (GaInAsP) or a group of the above materials Hehe. In addition, the substrate 402 may also be a semiconductor-on-insulator (SOI) substrate.

The semiconductor device includes fins 404 that may be formed on the substrate 402 using a deposition process, a lithography process, an etch process, a chemical mechanical polishing (CMP) process, a cleaning process, or a combination thereof.

As shown in FIG. 9, the semiconductor device also includes a dielectric layer 406 formed on the fins 404. The dielectric layer 406 can be hafnium oxide, tantalum nitride, hafnium oxynitride, a high-k dielectric material, or any other suitable dielectric material, or a combination thereof. The material of the high-k dielectric material may be a metal oxide, a metal nitride, a metal halide, a transition metal oxide, a transition metal nitride, a transition metal telluride, a metal oxynitride, Metal aluminate, zirconium silicate, zirconium aluminate. For example, the high-k dielectric material may be LaO, AlO, ZrO, TiO, Ta ₂ O ₅ , Y ₂ O ₃ , SrTiO ₃ (STO), BaTiO ₃ (BTO), BaZrO, HfO. ₂ , HfO ₃ , HfZrO, HfLaO, HfSiO, HfSiON, LaSiO, AlSiO, HfTaO, HfTiO, HfTaTiO, HfAlON, (Ba, Sr)TiO ₃ (BST), Al ₂ O ₃ , other high dielectric constants of other suitable materials Dielectric material, or a combination of the above. The dielectric layer 406 can be formed by chemical vapor deposition (CVD) or spin coating. The chemical vapor deposition method can be, for example, low pressure chemical vapor deposition (LPCVD) or low temperature chemical gas. Low temperature chemical vapor deposition (LTCVD), rapid thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer Atomic layer deposition (ALD) by chemical vapor deposition or other commonly used methods.

The semiconductor device also includes a gate layer 408 formed over the dielectric layer 406. The material of the gate layer 408 comprises amorphous germanium, polycrystalline germanium, one or more metals, metal nitrides, conductive metal oxides, or combinations thereof. The above metal may comprise molybdenum, tungsten, titanium, tantalum, platinum or hafnium. The metal nitride may include molybdenum nitride, tungsten nitride, titanium nitride, and tantalum nitride or other materials. The above conductive metal oxide may include ruthenium oxide and indium tin oxide. The gate layer 408 can be formed by chemical vapor deposition, sputtering, resistance heating evaporation, electron beam evaporation, or any other suitable deposition method.

Referring to Figures 10A-10E, Figures 10A-10E are schematic illustrations of various stages of performing a lightly doped gate process in a semiconductor device, in accordance with some embodiments. As shown in FIG. 10A, the semiconductor device also includes an isolation region 410 buried in the fin 404 and formed between the adjacent two gate layers 408. The isolation region 410 can comprise hafnium oxide, tantalum nitride, hafnium oxynitride, other suitable materials, and combinations thereof. Further, the semiconductor device has a first region 400A and a second region 400B. In some embodiments, the first region 400A is a region where an N-type metal oxide semiconductor is to be formed, and the second region 400B is a region where a P-type metal oxide semiconductor is to be formed.

Next, as shown in FIG. 10B, a spacer layer 412 is formed on the fin 404 and the gate layer 408. The spacers 412 may comprise tantalum nitride, hafnium oxide, hafnium oxynitride or other dielectric materials, and may be formed by chemical vapor deposition or other deposition methods.

Next, as shown in FIG. 10C, after the spacer layer 412 is formed, a dielectric material layer is deposited on the spacer layer 412, and the dielectric material layer is patterned by an etching process to form a hard mask layer 414. On the second zone 400B. At this time, the hard mask layer 414 does not cover the spacer layer 412 on the first region 400A. The hard mask layer 414 can comprise hafnium oxide, tantalum nitride, hafnium oxynitride or other materials that can act as a hard mask. The patterning process includes a lithography process and an etching process. The lithography process includes photoresist coating (eg, spin coating), soft baking, reticle alignment, exposure, post-exposure bake, development of photoresist, rinsing, drying (eg, hard bake), other suitable processes, or the foregoing. combination. Alternatively, the lithography process can be performed or replaced by other suitable methods, such as maskless lithography, electron-beam writing, and ion-beam writing. The etching process includes dry etching, wet etching, or other etching methods.

Next, as shown in Fig. 10D, the plasma 416 is implanted into the first region 400A of the semiconductor device by a plasma process. Arsenic-containing gas plasma 416 may be, for example, AsH _3, thereby providing an N-type dopant in the first region 400A. In other embodiments, when the first region 400A is a region where a P-type metal oxide semiconductor is to be formed, and the second region 400B is a region where an N-type metal oxide semiconductor is to be formed, the plasma 416 is a boron-containing gas such as B _{2 .} H ₆ , thereby providing P-type dopants in the first region 400A. Further, the plasma 416 is usually mixed with an inert gas such as helium or argon. In some embodiments, the plasma process described above is performed using the plasma reaction system 100 of the present invention. The plasma reaction system 100 of the embodiments of the present invention can control the ion concentration of implants located in different regions of the wafer surface. For example, using the plasma reaction system 100 of the embodiment of the present invention will result in the edge of the wafer. The difference in ion concentration between the first region 400A and the first region 400A at the center of the wafer is reduced.

Finally, as shown in FIG. 10E, the hard mask layer 414 is removed using an etching process. At this time, dopants are implanted on the surface of the fins 404 on both sides of the gate layer 418 of the first region 400A of the semiconductor device to form a lightly doped drain region 418. In this doping step, the uniformity of the ion concentration distribution of the lightly doped drain region 418 may affect the difference in performance between the semiconductor devices, and the uniformity of the ion concentration distribution of the plasma doping process may be as described in some embodiments above. The plasma reaction system 100 is executed.

The plasma reaction system described in the embodiments of the present invention can be used in any plasma process, and is not limited to the above-described process of forming a lightly doped drain region. During these plasma processing steps, the traveling direction of the plasma can be adjusted by a plurality of plasma displacement controllers, and the uniformity of the ion concentration can be adjusted in real time during the process, and the semiconductor device can be improved. Yield. In addition, the plasma reaction system of the embodiment of the present invention can directly detect and adjust the uniformity of the surface ion concentration and the distribution of the wafer which can finally become a product, thereby reducing the waste of the control wafer. In addition, since the plasma displacement controller can automatically adjust the ion concentration during the process, the time for manually adjusting the plasma parameters between the two batches of the machine is reduced, and the idle time of the machine is lost. Therefore, it is reduced, so that more batch processes can be executed per unit time, and the cycle time for forming a semiconductor device is reduced.

In accordance with some embodiments, a method of plasma processing a wafer is provided. The method of plasma processing a wafer includes disposing a wafer on a support in a reaction chamber. A plasma is generated in the reaction chamber, and ions in the plasma are directed toward the wafer by a first bias voltage. A first ion concentration and a second ion concentration of the plasma are detected at a first position and a second position around the support member, respectively. Comparing the first ion concentration and Second ion concentration. When the difference between the first ion concentration and the second ion concentration is greater than a critical value, a plurality of plasma displacement controllers are used to generate a second bias voltage in the reaction chamber to change the direction of travel of the ions in the plasma.

In accordance with some embodiments, a method of plasma processing a wafer is provided. A method of plasma treating a wafer includes providing a support in a reaction chamber, wherein a plurality of isolated segments are disposed around the support and each of the isolated segments has a conductive element. The ions of the plasma that are directed toward the wafer from the first direction are detected by each of the conductive elements to generate a plurality of corresponding currents. The ion concentration of each isolated segment is determined based on the corresponding current described above. A plurality of plasma displacement controllers are provided to determine the displacement of the plasma ions in the second direction based on the ion concentration of each of the isolated segments, wherein the first direction is different from the second direction.

According to some embodiments, a plasma reaction system is provided. The plasma reaction system includes an upper electrode assembly positioned above the reaction chamber and coupled to the first RF power source. The utility model is disposed in the reaction chamber and coupled to the support of the second RF power source. A plurality of plasma displacement controllers disposed outside the reaction chamber surround the space between the support member and the upper electrode assembly in the reaction chamber.

The above is a brief description of the features of the embodiments of the present invention, and the detailed description of the embodiments of the present invention will be more readily understood by those of ordinary skill in the art. It will be appreciated by those of ordinary skill in the art that the present disclosure may be readily utilized as a variation or design basis for other structures or processes to achieve the same objectives and/or advantages of the embodiments of the invention. It is to be understood by those of ordinary skill in the art that the invention may be made without departing from the spirit and scope of the embodiments of the invention. Make more Movement, substitution and retouching.

Claims (9)

A method for plasma processing a wafer, comprising: disposing a wafer on a support member in a reaction chamber; generating a plasma in the reaction chamber, and causing the plasma in the first bias The ions are directed toward the wafer; a first ion concentration and a second ion concentration of the plasma are detected at a first position and a second position around the support member; and the first ion concentration is compared And the second ion concentration; and when the difference between the first ion concentration and the second ion concentration is greater than a threshold, a plurality of plasma displacement controllers are used to generate a second bias voltage in the reaction chamber to change the a direction of travel of ions in the plasma, wherein ions in the plasma are implanted into a first region of the wafer by the second bias, but not implanted in the wafer different from the first region Two areas. The method of processing a wafer by the plasma according to claim 1, wherein when the ion concentration of the first position is less than the ion concentration of the second position, ions in the plasma are supported by the second bias Displacement toward the direction from the second position toward the first position. The method of processing a wafer by the plasma according to claim 1, wherein the ions in the plasma are directed toward the wafer by the first bias in a first direction, and the ions in the plasma A displacement of a second direction different from the first direction is generated by the second bias. The method for processing a wafer by the plasma according to claim 1, wherein the plasma displacement controller comprises a first plasma displacement controller disposed outside the reaction chamber and surrounding the reaction chamber, and a Second plasma displacement controller, And generating the second biasing force: generating a first output voltage by using the first plasma displacement controller; generating a second output voltage by using the second plasma displacement controller; and using the first output The voltage and the second output voltage generate the second bias voltage. A plasma control method includes: providing a support member in a reaction chamber, wherein the support member is provided with a plurality of isolated segments around the support member, and each of the isolated segments has a conductive member; Each of the conductive elements detects ions of a plasma that is directed toward the support by a first direction to generate a plurality of corresponding currents; and determining an ion concentration of each of the isolated segments according to the corresponding currents And providing a first plasma displacement controller and a second plasma displacement controller, using the first plasma displacement controller to generate a first output voltage according to an ion concentration of each of the isolated segments The second plasma displacement controller generates a second output voltage, and determines a displacement of the plasma ions in a second direction by generating a bias voltage between the first output voltage and the second output voltage, wherein The first direction is different from the second direction. The plasma control method of claim 5, wherein the first direction is perpendicular to the second direction. A plasma reaction system comprising: an upper electrode assembly located above a reaction chamber and coupled to a first RF power source; a support member disposed in the reaction chamber and coupled to a second RF power And a plurality of plasma displacement controllers disposed outside the reaction chamber and surrounding a space between the support member and the upper electrode assembly. The plasma reaction system of claim 7, wherein each of the plasma displacement controllers comprises a coil. The plasma reaction system of claim 7, wherein the plasma displacement controller comprises a first plasma displacement controller and a second plasma displacement controller, the first plasma displacement controller And the second plasma displacement controller is disposed on opposite sides of the reaction cavity.