CN108987227B

CN108987227B - Method for processing wafer by plasma, plasma control method and reaction system

Info

Publication number: CN108987227B
Application number: CN201710407467.1A
Authority: CN
Inventors: 陈嘉任; 顾文昱; 吴奇颖; 林燕飞; 陈冠中; 陈嘉直
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2017-06-02
Filing date: 2017-06-02
Publication date: 2022-02-18
Anticipated expiration: 2037-06-02
Also published as: CN108987227A

Abstract

Embodiments of the present disclosure provide a method of plasma processing a wafer, including disposing the wafer on a support within a reaction chamber. A plasma is generated in the reaction chamber, and ions in the plasma are ejected to the wafer by a first bias voltage. A first ion concentration and a second ion concentration of the plasma are detected at a first position and a second position around the support, respectively. The first ion concentration and the second ion concentration are compared. When the difference between the first ion concentration and the second ion concentration is larger than the critical value, a plurality of plasma displacement controllers are used for generating a second bias voltage in the reaction cavity so as to change the traveling direction of ions in the plasma.

Description

Method for processing wafer by plasma, plasma control method and reaction system

Technical Field

Embodiments of the present disclosure relate to a method of controlling plasma, and more particularly, to a method of applying plasma to a process wafer.

Background

The semiconductor integrated circuit industry has experienced rapid growth, and advances in integrated circuit materials and design techniques have resulted in several generations of integrated circuits, each generation having smaller and more complex circuits than the previous generation. In the development of integrated circuits, the density of functions (i.e., the number of devices connected per chip area) is generally increased and the geometric dimensions (i.e., the smallest component or line that can be fabricated in a process) are reduced. The down-sizing process generally provides the advantages of increased production efficiency and reduced cost. However, the shrinking dimensions also increase the complexity of the integrated circuit fabrication and manufacturing processes. To achieve these advances, similar developments in integrated circuit processing and fabrication are needed.

Plasma devices are commonly used in the semiconductor integrated circuit industry to perform a variety of semiconductor processes. For example, plasma devices have been used to clean the wafer surface of contaminants, deposit material layers, etch, ion implantation, and plasma doping. The condition or problem of the plasma reaction system affects the good wafer count of each wafer, and if the problem of the plasma reaction system cannot be solved or the process parameters cannot be adjusted in real time, the process yield of more wafers is affected.

In view of the above, there is a need for a method of plasma processing a wafer that addresses the above-mentioned problems.

Disclosure of Invention

An embodiment of the present disclosure provides a method for plasma control, including providing a support within a reaction chamber, wherein a plurality of isolated segments are disposed around the support, and each isolated segment has a conductive element thereon. Ions of the plasma directed toward the wafer from the first direction are detected by each of the conductive elements to produce a plurality of corresponding currents. And determining the ion concentration of each isolated section according to the corresponding current. Providing a plurality of plasma displacement controllers for determining the displacement of the ions of the plasma in a second direction according to the ion concentration of each isolated section, wherein the first direction is different from the second direction.

An embodiment of the present disclosure provides a plasma reaction system, which includes an upper electrode assembly disposed above a reaction chamber and coupled to a first rf power source. And a support member disposed in the reaction chamber and coupled to the second RF power source. And the plasma displacement controllers are arranged outside the reaction cavity and surround the space between the support piece and the upper electrode assembly in the reaction cavity.

Drawings

Fig. 1 is a schematic cross-sectional view of a plasma reaction system according to some embodiments of the present disclosure.

Fig. 2 is a top view of a plasma reaction system according to some embodiments of the present disclosure.

FIG. 3 is a schematic cross-sectional view taken along line A '-A' of the plasma reaction system shown in FIG. 2 according to some embodiments of the present disclosure.

Fig. 4 is a schematic circuit diagram of a plasma reaction system according to some embodiments of the present disclosure.

Fig. 5 is a schematic diagram of a plasma reaction system in accordance with some embodiments of the present disclosure.

Fig. 6 is a schematic diagram illustrating a plasma displacement generated after the plasma controller shown in fig. 1 operates according to some embodiments of the present disclosure.

Fig. 7A-7C are top views of patterns of an ion implanted wafer of a plasma according to some embodiments of the present disclosure.

FIG. 8 is a flow chart of an exemplary method of some embodiments of the present disclosure.

Fig. 9 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

Fig. 10A-10E are schematic diagrams illustrating stages in performing a lightly doped drain process in a semiconductor device according to some embodiments of the present disclosure.

Description of reference numerals:

100 plasma reaction system

102 reaction cavity

102a reaction chamber wall

102b reaction chamber bottom

103 upper electrode assembly

104 support piece

106. 106a-106h section

108 interval of

110 wafer

110a first area

110b second region

112. 112a-112d plasma displacement controller

114 conductive element

116 magnetic element

118 sense current

120. 120a-120h integrator

122 controller

124 first radio frequency power supply

126 impedance matching circuit

128 radio frequency coil assembly

130 gas inlet

132 space

134a plate electrode

134b ring electrode

136 second rf power supply

190 opening

200 plasma

300 method

302-310 operations

400A first region

400B second region

402 substrate

404 fin

406 dielectric layer

408 gate layer

410 isolation region

412 spacer layer

414 hard mask layer

416 plasma

418 lightly doped drain region

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of embodiments of the disclosure. Rather, the following disclosure of the present invention describes specific examples of components and arrangements thereof in order to simplify the present disclosure. Of course, these specific examples are not intended to limit the embodiments of the present disclosure. For example, the following disclosure describes forming a first feature over or on a second feature, including embodiments in which the first feature and the second feature are formed in direct contact, and also includes embodiments in which additional features may be formed between the first feature and the second feature, such that the first feature and the second feature may not be in direct contact. In addition, repeated reference characters and/or usage of words may be used in various instances in describing embodiments of the disclosure. These repeated symbols or words are provided for simplicity and clarity and are not intended to limit the relationship between the various embodiments and/or the illustrated appearance structures.

Furthermore, spatially relative terms, such as "under", "below", "lower", "over", "upper" and the like, may be used herein for convenience in describing the relationship of an element or feature to another element(s) or feature(s) in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. It will be appreciated that additional operational steps may be provided before, during and after the method, and that in certain method embodiments, certain operational steps may be substituted or omitted.

The embodiments discussed below may be discussed in particular context, for example, a plasma device may be applied to a wafer for implanting dopants between isolation structures. One skilled in the art will readily appreciate from the disclosure that other applications are contemplated in other embodiments, such as the method of plasma processing a wafer may be applied to any process having an ion implantation value, and is not limited to the above-described process.

It is worthy to note that the embodiments discussed herein may not necessarily recite every component or feature that may be present in the structure. For example, one or more elements may be omitted from a drawing, e.g., while a discussion of components may be sufficient to convey various aspects of an embodiment. Further, the method embodiments discussed herein may be discussed in a particular order of performance, while in other method embodiments, they may be performed in any reasonable order.

Before explaining the embodiments in detail, certain advantageous features and aspects of the embodiments of the present disclosure are briefly described. In summary, embodiments of the present disclosure provide a method for processing a wafer by using a plasma, in which a plasma displacement controller is used to displace the plasma during the plasma implantation into the wafer, so as to adjust the uniformity of the wafer doping in the plasma doping step, thereby ensuring the performance of the semiconductor device.

Fig. 1 is a schematic cross-sectional view of a plasma reaction system 100 according to some embodiments of the present disclosure. The plasma processing system 100 may be coupled to a processing system platform and may include a multi-purpose reaction chamber configured to perform a particular process, such as an ion implantation process, an etching process, and the like. While the disclosed embodiments are expressed in this particular architecture, it is to be understood that the disclosure may have application in various other architectures and designs. Even more, the plasma reaction system 100 is a simple representation of the drawings, and some parts of the plasma reaction system 100 are not shown. For example, actuators, valves, seal assemblies and the like are not shown. One skilled in the art will appreciate that these and other components making up the plasma reaction system 100 may be included therein.

As shown in fig. 1, the plasma reaction system 100 comprises a reaction chamber 102, an upper electrode assembly 103, a support 104, a plasma displacement controller 112, a controller 122, a first rf power source 124, an impedance match circuit 126, and a second rf power source 136. The plasma reaction system 100 generally includes a reaction chamber 102, wherein the reaction chamber 102 defines at least a portion of a region for performing a process as a chamber. The reaction chamber 102 includes a reaction chamber wall 102a and a reaction chamber bottom 102 b. The reaction chamber wall 102a extends vertically from the edge of the reaction chamber bottom 102 b. In some embodiments, a slit valve may be provided in the chamber wall 102a for selective sealing to facilitate the transfer of the wafer 110 into and out of the plasma reaction system 100. In some embodiments, the reaction chamber bottom 102b includes a pumping port (not shown) for pumping gas from the reaction chamber 102. For example, a pumping system (including, for example, a throttle valve, a vacuum pump, etc.) may be connected to the pumping port of the reaction chamber bottom 102 b. Once the slit valve is sealed, the pumping system may be operated to draw and maintain a vacuum within the reaction chamber 102.

The upper electrode assembly 103 is disposed above the reaction chamber 102, and includes a plate electrode 134a disposed at the upper end of the reaction chamber 102, a ring electrode 134b disposed between the plate electrode 134a and the reaction chamber wall 102a, and an RF coil assembly 128 surrounding the ring electrode 134 b. In one embodiment, the plate electrode 134a is a showerhead in a gas distribution system. In this configuration, the plate electrode 134a may serve as a component for distributing gases into the reaction chamber 102 and may be coupled to a gas source (not shown). The gas source contains the precursor or process gases used to process the reaction chamber 102. The plate electrode 134a is connected to a direct current power source (e.g., ground). In some embodiments, the plate electrode 134a, the chamber wall 102a, and a chamber bottom 102b are all connected to ground.

The rf coil assembly 128 is coupled to the first rf power source 124 and generates and sustains the plasma 200 in the reaction chamber 102 by the rf power provided by the first rf power source 124. In one embodiment, the first RF power source 124 is a high frequency RF power source. The first RF power source 124 is coupled to an RF coil assembly 128 via an impedance match circuit 126 to enhance dissociation of the process gas and plasma density. For example, the impedance matching circuit 126 may include one or more capacitors, inductors, and other circuit components. The first rf power supply 124 delivers rf power at a frequency of about 2MHz or greater to the rf coil assembly 128, but is not so limited. In some embodiments, the bias voltage of the first RF power source 124 is between about-30K and about +30K volts, and the pulse width (pulse width) of the first RF power source is between about 5 microseconds and about 300 microseconds.

As shown in fig. 1, the support 104 is disposed on the reaction chamber bottom 102b of the reaction chamber 102 and configured to support the wafer 110. In some embodiments, the ring electrode 134b and the RF coil assembly 128 serve as the top electrode of the plasma reaction system 100, while the support 104 serves as the bottom electrode. The support 104 may be any configuration suitable for supporting a wafer, such as an electrostatic chuck or a vacuum chuck. The support 104 includes a support surface that serves as a support surface for the wafer 110 and is generally contoured to conform to the shape of the wafer 110 to be supported thereon. For example, the surface of the support 104 is generally circular and is configured to support a generally circular wafer 110. In one embodiment, the surface of the support 104 is connected to a wafer temperature control system (not shown), such as resistive heating coils and/or fluid channels connected to a heating or cooling fluid system. The support 104 may comprise any material used in the plasma reaction system 100. For example, the material of the support 104 may comprise steel, other conductive metals, or alloys. In some embodiments, the support 104 includes a vacuum system for holding the wafer 110 in place.

In some embodiments, a second rf power source 136 is coupled to the support 104. The second RF power source 136 is a low frequency RF power source that delivers RF power at a frequency of about 0.5 to 10KHz to the support member 104, but is not limited thereto. In some embodiments, the bias voltage of the second RF source 136 is between about-0.2 and 10 kilovolts, and the pulse width (pulse width) of the second RF source is between about 20 and 100 microseconds, but is not limited thereto. In one embodiment, a first bias voltage E1 is applied between the top electrode (ring electrode 134b and RF coil assembly 128) and the bottom electrode (support 104). Ions of the plasma 200 are directed to impinge on the surface of the wafer 110 in a first direction (e.g., the Y-axis direction). In some embodiments, the second RF power source 136 may also be a DC bias source.

In addition, according to some embodiments, the support 104 includes a plurality of sections 106, a controller 122, and a plurality of plasma displacement controllers (e.g., plasma displacement controller 112a and plasma displacement controller 112b) located outside the reaction chamber 102. The section 106 is disposed on the support 104 and configured to detect an ion concentration. When the section 106 detects the ion concentration of the plasma 200, the information of the ion concentration is transmitted to the controller 122. In some embodiments, the controller 122 determines the output voltages of the plasma displacement controller 112a and the plasma displacement controller 112b according to the information of the ion concentration provided by the section 106, and the voltage difference between the outputs of the plasma displacement controller 112a and the plasma displacement controller 112b generates a bias voltage in the reaction chamber 102, by which the ions of the plasma 200 change their traveling direction, and the detailed operation mechanism is described in detail in the related paragraph of fig. 6.

Referring to fig. 2, fig. 2 is a top view of a plasma reaction system 100 according to some embodiments. As shown in fig. 2, the support 104 includes a trench-like opening (not shown) around the outside of the wafer 110. Each of the trench-like openings includes a section, e.g., 106a-106h, for detecting the ion concentration. It is noted that the description of the section 106a in the embodiments of the present disclosure may be applicable to any other section, and each section 106a-106h may be physically separated by an insulating wall 108. Each of the segments 106a-106h may also be electrically isolated from each other by insulating materials or high dielectric constant materials disposed between the segments. The total number and arrangement of the segments 106a-106h is not limited to the pattern of the figures. For example, the segments 106a-106h may be arranged in any shape or configuration around the support 104, such as outside the edge of the wafer 110. The segments 106a-106h may be arranged as close as possible to the edge of the wafer 110. In some embodiments, the distance between each segment and its nearest neighbor two of the segments 106a-106h is the same for each segment.

During the process of plasma treating the wafer, ions of plasma 200 bombard the entire surface of wafer 110, a portion of which penetrates each trench-like opening and strikes each segment 106a-106 h. The total charge of the ions impinging on the segments 106a-106h is measured to determine the dopant ion concentration for a given region of the wafer 110. For example, if the total number of ions impinging on segments 106a-106h increases, the ion concentration implanted into wafer 110 increases.

Since each of the sections 106a-106h of the plasma reaction system 100 are physically isolated from each other, the distribution of plasma ion concentration, i.e., the distribution of dopant ion concentration in a given region of the wafer 110, can be determined by detecting the total charge of the ions striking the sections 106a-106 h. For example, the ion concentration measured in segment 106a is related to the ion concentration of portion A of the nearest neighboring wafer 110, the ion concentration measured in segment 106B is related to the ion concentration of portion B of the nearest neighboring wafer 110, and so on to obtain the ion concentrations of portions C-H of the wafer 110. Since the ion concentration of each segment 106a-106h can be measured individually, the uniformity of the ion concentration distribution across the wafer surface during the plasma process can be monitored.

In addition, in some embodiments, the plasma reaction system 100 includes a plurality of plasma displacement controllers 112a-112d located outside the reaction chamber 102 and surrounding the reaction chamber 102. The controller 122 determines the output voltage of each of the plasma displacement controllers 112a-112d based on the ion concentration detected by each of the segments 106a-106H during plasma processing of the wafer 110 to generate a bias voltage within the chamber 102 that causes the plasma to displace in a direction different from the first direction (i.e., the Y direction) to adjust the ion concentration of the portions a-H of the wafer 110.

In some embodiments, as shown in FIG. 2, the plasma reaction system 100 has a plurality of plasma displacement controllers 112a-112d, and the pairs of plasma displacement controllers 112a-112d are respectively located at two opposite sides of the reaction chamber 102. For example, the plasma displacement controller 112a and the plasma displacement controller 112B are located on a straight line (e.g., line B '-B') passing through the center of the reaction chamber 102. In some embodiments, the plasma displacement controllers 112a-112d comprise coils. The material of the coil can be copper, iron, nickel, titanium, other conductive metals or alloys of the above. It should be noted that the total number and arrangement of the plasma displacement controllers are not limited to the patterns shown in the drawings. For example, the plasma displacement controllers may be disposed around the reaction chamber 102 in any shape or configuration. In some embodiments, the plasma displacement controllers may be located on non-horizontal opposing sides of the reaction chamber 102. In some embodiments, the plasma displacement controllers may not be located on opposite sides of the reaction chamber 102, and the plasma displacement controllers may be disposed around the reaction chamber 102 in an asymmetric arrangement.

Referring to fig. 3, fig. 3 is a schematic cross-sectional view taken along a line a '-a' of the plasma reaction system 100 shown in fig. 2 according to some embodiments of the present disclosure. As shown in fig. 3, the edge of the wafer 110 may be seen above the support 104. In some embodiments, the section 106a is located at the trench-like opening 190 of the support 104. In some embodiments, the segment 106a has a conductive element 114 within the opening 190.

As shown in fig. 3, ions of plasma 200 pass through opening 190 and impact conductive element 114 in segment 106 a. The conductive element 114 may be any metallic material capable of conducting electrical current, such as copper, aluminum, stainless steel, carbon, graphite, other electrically conductive metals or alloys. The conductive element 114 may be a faraday cup shaped like a cup, and when ions of the plasma 200 impact the conductive element 114 at various angles, the charges of the plasma ions neutralize and generate dissipated charges, and the inner sidewall of the conductive element 114 may capture the dissipated charges. The inner sidewall of the conductive element 114 may be at a right angle or at a non-right angle.

Conductive element 114 may be implemented as a component in an electrical circuit, wherein when ions of plasma 200 impact conductive element 114, conductive element 114 generates a current 118. The magnitude of the current 118 is related to the number of ions and the ionic charge impinging on the conductive element 114 in the segment 106 a. In one embodiment, the magnitude of the current 118 is positively correlated to the number of ions and the ion charge impinging on the conductive element 114 in the segment 106 a. In some embodiments, the magnitude of the current 118 is inversely related to the number of ions and the ionic charge impacting the conductive element 114 in the segment 106 a. In addition, in some embodiments, the segment 106a also has a magnetic element 116, and the magnetic field generated by the magnetic element 116 prevents secondary electrons from escaping away from the conductive element 114.

In some embodiments, the gap between the conductive element 114 and the support 104 may be filled with an insulating material to hold the conductive element 114 in place. For example, the insulating material may be a polymer or an epoxy resin. In addition, besides the connection point between the conductive element 114 and the support 104, the gap between the conductive element 114 and the support 104 may also be an open space.

The aforementioned components for detecting plasma ions (e.g., the conductive component 114) can be applied to any of various semiconductor processes using plasma, such as, but not limited to, ion implantation, plasma etching, Plasma Enhanced Chemical Vapor Deposition (PECVD), Plasma Enhanced Atomic Layer Deposition (PEALD), and epitaxial growth processes.

Referring to fig. 4, fig. 4 is a schematic circuit diagram of a plasma reaction system 100 according to some embodiments of the present disclosure. As shown in FIG. 4, each of the sections 106a-106h of the plasma reaction system 100 for detecting the ion concentration of the plasma 200 is coupled to an integrator 120a-120h, respectively. Each integrator 120a-120h may include a plurality of various active or passive elements for detecting the current generated by the charge accumulated in the corresponding segment. For example, each integrator 120a-120h may include an ammeter or current meter. Each integrator 120a-120h generates information corresponding to the ion concentration (i.e., ion concentration information) of the plasma received by each conductive element 114 in the segments 106a-106h based on the received current.

Referring to fig. 5, fig. 5 is a schematic diagram of a plasma reaction system 100 according to some embodiments of the present disclosure. It is noted that, for the sake of simplicity, fig. 5 only shows 3 segments 106 for illustration, however, the number of segments 106, integrators 120, and plasma displacement controllers 112 is not limited to the number shown in fig. 5.

In some embodiments, the plasma reaction system 100 includes a controller 122. The controller 122 is configured to receive the ion concentration information from the integrators 120 and determine the output voltage of the plasma displacement controller 112 according to the ion concentration information provided by each integrator 120 to adjust the uniformity of the ion concentration of the plasma 200. In some embodiments, the plurality of segments 106 are arranged around the edge of the wafer 110 and detect ions from the plasma 200 to generate a current (e.g., current 118), the integrator 120 derives ion concentration information received by each segment 106 based on the magnitude of the current, and the controller 122 receives the ion concentration information from the integrator 120 and determines whether to adjust the output voltage of the plasma displacement controller 112. When the controller 122 adjusts the output voltage of one or more of the plurality of plasma displacement controllers 112, the pressure difference between the plurality of plasma displacement controllers 112 generates a bias voltage within the reaction chamber 102, which changes the traveling direction of the ions in the plasma 200 to compensate for the detection result of the non-uniform ion concentration distribution. In some embodiments, the controller 122 includes a plurality of processing systems and/or logic configured to receive ion concentration information from the integrator 120 and compare the ion concentration of each corresponding segment 106, thereby determining the output voltage of the plasma displacement controller 112.

The controller 122 compares the ion concentration of each corresponding segment 106 to obtain the uniformity of the ion concentration distribution. When the difference between the ion concentrations is greater than a given threshold, the controller 122 may adjust the output voltage of the plasma displacement controller 112. For example, referring to fig. 2 and 5, if the region of highest ion concentration measured by the integrator 120 is twice the region of lowest ion concentration in the segments 106a-106h, the controller 122 may determine the output voltage of each of the plasma displacement controllers 112a-112d during the plasma process, thereby generating a bias voltage within the chamber 102 to adjust the uniformity of the distribution of ion concentration. For example, when the detected ion concentration is lower in the section 106a of fig. 2, it means that the portion a of the wafer 110 is implanted with fewer ions by the plasma. At this time, the controller 122 adjusts the plasma displacement controllers 112a-112d to generate a bias voltage within the reaction chamber 102 to change the direction of travel of the ions of the plasma 200. Thus, more ions of plasma 200 impact portion A of wafer 110 in subsequent processes.

Referring to fig. 6, fig. 6 is a schematic cross-sectional view taken along line B '-B' of the plasma reaction system 100 shown in fig. 2 according to some embodiments of the present disclosure. In addition, fig. 6 is a schematic diagram illustrating ion generation displacement of the plasma 200 after the plasma displacement controllers (e.g., the plasma displacement controller 112a and the plasma displacement controller 112b) of the plasma reaction system 100 of fig. 1 are operated. In some embodiments, when the plasma reaction system 100 is to adjust the concentration of ions doped on the wafer 110, the plasma displacement controller 112a and the plasma displacement controller 112b respectively provide different output voltages to generate a second bias voltage E2 in a second direction (e.g., the X direction) in the reaction chamber 102, and the second bias voltage E2 guides the ions of the plasma 200 to displace along the second direction. In some embodiments, the output voltages of the plasma displacement controller 112a and the plasma displacement controller 112b may be varied over time such that the direction and magnitude of the second bias voltage E2 is a function of time, thereby causing ions of the plasma 200 to impact a region of the wafer 110 in a concentrated manner. As shown in fig. 6, if the ion concentration measured in the right section 106 of the wafer 110 is low, the second bias voltage E2 generated by the plasma displacement controller 112a and the plasma displacement controller 112b can displace the ions of the plasma 200 to the right, so as to be implanted into the right edge of the wafer 110.

In some embodiments, as shown in FIG. 6, the plasma displacement controllers 112a-112b are located outside the reaction chamber 102 and surround a space 132 between the reaction chamber wall 102a and the support 104. After the controller 122 determines the output voltage and frequency of each plasma displacement controller, ions from the plasma 200 may impact the surface of the wafer 110 in any pattern.

Referring to fig. 7A-7C, fig. 7A-7C are top views of patterns of a plasma implanted wafer 110, according to some embodiments. As shown in fig. 7A to 7C, a region of the wafer 110 where ions of the plasma 200 are implanted is defined as a first region 110a, and a region of the wafer 110 where ions of the plasma 200 are not implanted is defined as a second region 110 b. In some embodiments, the second bias voltage E2 generated by the plasma displacement controller 112 causes ions of the plasma 200 to be implanted only in the first region 110a of the wafer 110 while ions of the plasma 200 are not implanted in the second region 110b of the wafer 110. The pattern of the first region 110a may be square, triangular, fan-shaped, etc. It should be noted that the pattern of the first region 110a is not limited to the pattern shown in fig. 7A-7C, and may be other irregular patterns.

Referring to fig. 8, fig. 8 is a flow chart of a method 300 of plasma processing a wafer according to some embodiments. The method 300 may be performed by the plasma reaction system 100 as shown in fig. 1, 2, 3, and 6. It is to be noted that other steps not shown may be performed without departing from the scope of the embodiments described in the embodiments of the present disclosure.

The method 300 begins at operation 302 where a wafer is disposed on a support within a reaction chamber. For example, as shown in FIG. 1, a wafer 110 is placed on a support 104 within a reaction chamber 102.

Next, in operation 304, a plasma is generated in the reaction chamber, and ions in the plasma are ejected toward the wafer by a first bias voltage. For example, a first RF power source 124, which is a high frequency RF power source, delivers RF power to the RF coil assembly 128 to generate and sustain a plasma 200 in the reaction chamber 102, and a second RF power source 136, which is a low frequency RF power source, delivers RF power to the support 104. In this manner, a first bias voltage E1 between the top electrode (ring electrode 134b and RF coil assembly 128) and the bottom electrode (support 104) creates an electric field in the reaction chamber 102 along a first direction (e.g., Y direction) that directs ions in the plasma 200 to impact the surface of the wafer 110 in the first direction. The plasma 200 may be generated by one or more gas flows ionized by the rf power provided by the first rf power source 124. Plasma parameters can be influenced by adjusting the frequency and amplitude of the rf power, and plasma parameters can also be adjusted by adjusting the gas flow rate. The plasma parameter is, for example, the energy of the plasma ions.

Next, in operation 306, a first ion concentration and a second ion concentration of the plasma are detected at a first location and a second location, respectively, around the support. For example, the total charge of the plasma ions detected by the corresponding conductive element 114 can be detected in the section 106a and the section 106e opposite to the section 106a shown in fig. 2, and the current generated by the conductive element 114 is received by the corresponding

integrators

120a and 120e, so as to obtain the ion concentration (e.g., ion concentration information) of the plasma impacting the

sections

106a and 106 e.

Next, in operation 308, the first ion concentration and the second ion concentration are compared. For example, the controller 122 receives ion concentrations (ion concentration information) of the plasmas of the

sections

106a and 106e and compares the difference to determine uniformity of ions impinging on the surface of the wafer 110.

Next, in operation 310, when the difference between the first ion concentration and the second ion concentration is greater than a threshold value, a second bias voltage is generated in the reaction chamber by using a plurality of plasma displacement controllers to change the proceeding direction of the plasma. For example, when the difference between the ion concentrations in the sections 106a and 106E is greater than a given threshold, the controller 122 determines the output voltage of each of the plasma displacement controllers 112a-112d, thereby generating a second bias voltage E2 in a second direction different from the first direction to displace the ions of the plasma 200 in the second direction (e.g., the X direction). When the ion concentration detected by the section 106a is greater than the ion concentration detected by the section 106E, and the difference between the ion concentrations is greater than the threshold value, the second bias E2 is used to shift the ions of the plasma 200 from the section 106a toward the section 106E, thereby improving the uniformity of the ion concentration of the plasma process. In some embodiments, the second bias voltage E2 is an alternating voltage. In some embodiments, the plasma displacement controller further comprises a magnet, which may be used to slightly modify the second bias E2 at the edge of the space 132 to improve the uniformity of the ion concentration in the plasma process. In some embodiments, the plasma displacement controller may provide the output voltage and frequency in a bipolar pulse mode to adjust the displacement of the plasma 200.

It is noted that the method 300 is described for simplicity in describing the process of plasma processing a wafer, and only two

segments

106a and 106e are described for detecting ion concentration, but more segments may be detected to determine the uniformity of ion concentration.

In various process steps of fabricating a semiconductor device, a plasma process may be performed by the plasma reaction system 100 described above. Some illustrative steps for forming a semiconductor device are shown in fig. 9 and 10A-10E. In some embodiments, a Lightly Doped Drain (LDD) process is performed using the plasma reaction system 100. In addition, in some embodiments, the semiconductor device is a finfet device. It is noted that the semiconductor devices illustrated in fig. 9 and 10A-10E are merely examples of such devices, and some elements of the devices are omitted for clarity of the lightly doped drain process. That is, the semiconductor device may include other material layers, and the method of forming the semiconductor device may also include other processes.

Fig. 9 is a cross-sectional view of a semiconductor device along an X-Y plane, according to some embodiments. Fig. 10A-10E are cross-sectional views along the Y-Z plane of one fin 404 of fig. 9 according to some embodiments. As shown in fig. 9, the semiconductor device includes a substrate 402. The substrate 402 may be a semiconductor substrate, such as a silicon substrate. In addition, the semiconductor substrate may be an elemental semiconductor including germanium (germanium); compound semiconductors including silicon carbide (silicon carbide), gallium arsenide (gallium arsenide), gallium phosphide (gallium phosphide), indium phosphide (indium phosphide), indium arsenide (indium arsenide), and/or indium antimonide (indium antimonide); the alloy semiconductor comprises silicon germanium alloy (SiGe), phosphorus arsenic gallium alloy (GaAsP), arsenic aluminum indium alloy (AlInAs), arsenic aluminum gallium alloy (AlGaAs), arsenic indium gallium alloy (GaInAs), phosphorus indium gallium alloy (GaInP) and/or phosphorus arsenic indium gallium alloy (GaInAsP) or the combination of the materials. In addition, the substrate 402 may also be a Semiconductor On Insulator (SOI) substrate.

The semiconductor device includes a fin 404. the fin 404 may be formed on the substrate 402 using a deposition process, a photolithography process, an etching process, a Chemical Mechanical Polishing (CMP) process, a cleaning process, or a combination thereof.

As shown in fig. 9, the semiconductor device also includes a dielectric layer 406 formed over the fin 404. The dielectric layer 406 may be silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material, or any other suitable dielectric material, or combinations thereof. The high-k dielectric material may be metal oxide, metal nitride, metal silicide, or transition metalOxides, transition metal nitrides, transition metal silicides, metal oxynitrides, metal aluminates, zirconium silicates, zirconium aluminates. For example, the high-k dielectric material can be LaO, AlO, ZrO, TiO, Ta₂O₅、Y₂O₃、SrTiO₃(STO)、BaTiO₃(BTO)、BaZrO、HfO₂、HfO₃、HfZrO、HfLaO、HfSiO、HfSiON、LaSiO、AlSiO、HfTaO、HfTiO、HfTaTiO、HfAlON、(Ba,Sr)TiO₃(BST)、Al₂O₃Other high dielectric constant dielectric materials of other suitable materials, or combinations thereof. The dielectric layer 406 may be formed by Chemical Vapor Deposition (CVD) or spin-on coating, such as Low Pressure Chemical Vapor Deposition (LPCVD), Low Temperature Chemical Vapor Deposition (LTCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Atomic Layer Deposition (ALD), or other conventional methods.

The semiconductor device also includes a gate layer 408 formed over the dielectric layer 406. The material of the gate layer 408 comprises amorphous silicon, polysilicon, one or more metals, metal nitrides, conductive metal oxides, or combinations thereof. The metal may comprise molybdenum (molybdenum), tungsten (tungsten), titanium (titanium), tantalum (tantalum), platinum (platinum) or hafnium (hafnium). The metal nitride may include molybdenum nitride (molybdenum nitride), tungsten nitride (tungsten nitride), titanium nitride (titanium nitride), and tantalum nitride (tantalum nitride), or other materials. The conductive metal oxide may include ruthenium metal oxide (ruthenium oxide) and indium tin oxide (indium tin oxide). The gate layer 408 can be formed by chemical vapor deposition, sputtering, resistive heating evaporation, e-beam evaporation, or any other suitable deposition method.

Referring to fig. 10A-10E, fig. 10A-10E are schematic diagrams illustrating stages in performing a lightly doped drain process in a semiconductor device, according to some embodiments. As shown in fig. 10A, the semiconductor device also includes an isolation region 410 embedded in the fin 404 and formed between two adjacent gate layers 408. The isolation region 410 may comprise silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, and combinations thereof. In addition, the semiconductor device has a first region 400A and a second region 400B. In some embodiments, the first region 400A is a region to be formed with an nmos and the second region 400B is a region to be formed with a pmos.

Next, as shown in fig. 10B, a spacer layer 412 is formed on fin 404 and gate layer 408. The spacers 412 may comprise silicon nitride, silicon oxide, silicon oxynitride, or other dielectric material, and may be formed by chemical vapor deposition or other deposition methods.

Next, as shown in fig. 10C, after the spacer layer 412 is formed, a dielectric material layer is deposited on the spacer layer 412 and patterned by an etching process to form a hard mask layer 414 on the second region 400B. At this time, the hard mask layer 414 does not cover the spacer layer 412 on the first region 400A. The hard mask layer 414 may comprise silicon dioxide, silicon nitride, silicon oxynitride, or other materials capable of acting as a hard mask. The patterning process includes a photolithography process and an etching process. The photolithography process includes photoresist coating (e.g., spin coating), soft baking, photomask alignment, exposure, post exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), other suitable processes, or a combination of the foregoing. In addition, the photolithography process may be performed or replaced by other suitable methods, such as maskless lithography, electron-beam writing (electron-beam writing), and ion-beam writing (ion-beam writing). The etching process includes dry etching, wet etching or other etching methods.

Next, as shown in fig. 10D, a plasma 416 is implanted into the first region 400A of the semiconductor device using a plasma process. The plasma 416 may be an arsenic-containing gas, such as AsH₃Thereby providing N-type doping in the first region 400A. In other embodiments, when the first region 400A is a region to be formed with PMOS and the second region 400B is a region to be formed with NMOSIn the region(s), the plasma 416 is a boron-containing gas, such as B₂H₆Thereby providing P-type doping in the first region 400A. In addition, the plasma 416 is typically mixed with an inert gas, such as helium or argon. In some embodiments, the plasma process described above is performed using the plasma reaction system 100 described in embodiments of the present disclosure. The plasma reaction system 100 according to the embodiments of the present disclosure can control the concentration of the implanted ions at different regions of the wafer surface, for example, the difference between the concentration of the implanted ions in the first region 400A at the edge of the wafer and the concentration of the implanted ions in the first region 400A at the center of the wafer can be reduced by using the plasma reaction system 100 according to the embodiments of the present disclosure.

Finally, as shown in fig. 10E, the hard mask layer 414 is removed using an etching process. At this time, dopants are implanted into the surface of the fin 404 on both sides of the gate layer 418 in the first region 400A of the semiconductor device to form a lightly doped drain region 418. The uniformity of the ion concentration profile of the lightly doped drain region 418 during this doping step may affect the performance variation between semiconductor devices, and the uniformity of the ion concentration profile of the plasma doping process may be performed by the plasma reaction system 100 as described in some embodiments above.

The plasma reaction system according to the embodiments of the present disclosure may be used in any plasma process, and is not limited to the process of forming the lightly doped drain region. During these plasma processing steps, the direction of plasma travel can be adjusted by a plurality of plasma displacement controllers, and the uniformity of ion concentration can be adjusted in real time during the process, thereby improving the yield of semiconductor devices. In addition, the plasma reaction system of the embodiment of the present disclosure can directly detect and adjust the surface ion concentration of the wafer which can finally become a product and the uniformity of the distribution thereof, so that the waste of the control wafer can be reduced. In addition, since the plasma displacement controller can automatically adjust the ion concentration during the process, the time for artificially adjusting the plasma parameters between two batches (run) of the tool is reduced, and the idle time (lost time) of the tool is also reduced, so that more batches of processes can be performed per unit time, and the cycle time (cycle time) for forming the semiconductor device is reduced.

According to some embodiments, a method of plasma processing a wafer is provided. A method of plasma processing a wafer includes disposing the wafer on a support within a reaction chamber. A plasma is generated in the reaction chamber, and ions in the plasma are ejected to the wafer by a first bias voltage. A first ion concentration and a second ion concentration of the plasma are detected at a first position and a second position around the support, respectively. The first ion concentration and the second ion concentration are compared. When the difference between the first ion concentration and the second ion concentration is larger than the critical value, a plurality of plasma displacement controllers are used for generating a second bias voltage in the reaction cavity so as to change the traveling direction of ions in the plasma.

According to some embodiments, a method of plasma processing a wafer is provided. The method for plasma processing a wafer includes providing a support within a reaction chamber, wherein a plurality of isolated segments are disposed about the support, and each isolated segment has a conductive element thereon. Ions of the plasma directed toward the wafer from the first direction are detected by each of the conductive elements to produce a plurality of corresponding currents. And determining the ion concentration of each isolated section according to the corresponding current. Providing a plurality of plasma displacement controllers for determining the displacement of the ions of the plasma in a second direction according to the ion concentration of each isolated section, wherein the first direction is different from the second direction.

According to some embodiments, a plasma reaction system is provided. The plasma reaction system includes an upper electrode assembly disposed above the reaction chamber and coupled to a first RF power source. And a support member disposed in the reaction chamber and coupled to the second RF power source. And the plasma displacement controllers are arranged outside the reaction cavity and surround the space between the support piece and the upper electrode assembly in the reaction cavity.

The foregoing has outlined rather broadly the features of several embodiments of the present disclosure so that those skilled in the art may better understand the detailed description of the embodiments that follow. It should be appreciated by those skilled in the art that the present disclosure may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes and/or achieving the same advantages of the embodiments of the present disclosure. It will be further understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments of the disclosure as defined by the appended claims.

Claims

1. A method of plasma processing a wafer, comprising:

arranging a wafer on a supporting member in a reaction chamber;

generating a plasma in the reaction chamber, and ejecting ions in the plasma to the wafer through a first bias voltage;

detecting a first ion concentration and a second ion concentration of the plasma at a first position and a second position around the support, respectively;

comparing the first ion concentration and the second ion concentration; and

when the difference between the first ion concentration and the second ion concentration is larger than a critical value, a plurality of plasma displacement controllers are used for generating a second bias voltage in the reaction cavity so as to change the advancing direction of ions in the plasma; wherein ions in the plasma are implanted into a first region of the wafer through the second bias voltage, but not into a second region of the wafer different from the first region, wherein the plurality of plasma displacement controllers are positioned on a straight line passing through a center of the reaction chamber, wherein output voltages of the plurality of plasma displacement controllers vary with time, and the plurality of plasma displacement controllers provide the output voltages and the output frequencies in a bipolar pulse mode.

2. The method of claim 1, wherein when the ion concentration at the first location is less than the ion concentration at the second location, ions in the plasma are displaced by the second bias toward the first location from the second location.

3. The method of claim 1, wherein ions in the plasma are directed toward the wafer in a first direction by the first bias voltage and are displaced in a second direction different from the first direction by the second bias voltage.

4. The method of claim 1, wherein the plurality of plasma displacement controllers comprises a first plasma displacement controller and a second plasma displacement controller disposed outside and surrounding the reaction chamber, and the step of generating the second bias voltage comprises:

generating a first output voltage by using the first plasma displacement controller;

generating a second output voltage by using the second plasma displacement controller; and

the second bias voltage is generated by the first output voltage and the second output voltage.

5. A plasma control method, comprising:

providing a support member in a reaction chamber, wherein a plurality of isolated sections are arranged around the support member, and each isolated section is provided with a conductive element;

detecting ions of a plasma directed toward the support from a first direction by each of the conductive elements to generate a plurality of corresponding currents;

determining an ion concentration of each of the isolated segments according to the plurality of corresponding currents; and

providing a first plasma displacement controller and a second plasma displacement controller, generating a first output voltage and a second output voltage by using the first plasma displacement controller and the second plasma displacement controller according to the ion concentration of each isolated section, and generating a bias voltage through the first output voltage and the second output voltage to determine the displacement of the ions of the plasma in a second direction, wherein the first direction is different from the second direction, the first plasma displacement controller and the second plasma displacement controller are positioned on a straight line passing through a circle center of the reaction cavity, the first output voltage of the first plasma displacement controller and the second output voltage of the second plasma displacement controller change along with time, and the first plasma displacement controller and the second plasma displacement controller provide output voltage and output voltage in a bipolar pulse mode Frequency.

6. The method of claim 5, wherein the first direction is perpendicular to the second direction.

7. A plasma reaction system, comprising:

an upper electrode assembly located above a reaction chamber and coupled to a first RF power source;

a supporting member disposed in the reaction chamber and coupled to a second RF power source; and

a plurality of plasma displacement controllers disposed outside the reaction chamber and surrounding a space in the reaction chamber between the support member and the upper electrode assembly, wherein at least one of the plurality of plasma displacement controllers and the first rf power source are coupled to the upper electrode assembly through an impedance matching circuit, wherein output voltages of the plurality of plasma displacement controllers vary with time, and the plurality of plasma displacement controllers provide output voltages and frequencies in a bipolar pulse mode.

8. The plasma reaction system of claim 7, wherein the plurality of plasma displacement controllers comprises a first plasma displacement controller and a second plasma displacement controller disposed on opposite sides of the reaction chamber.