TWI640992B - Word line decoder circuit - Google Patents

Abstract

A word line decoder circuit is provided in a memory storage device. The memory storage device includes a memory cell array. The word line decoder circuit includes a word line decoder and a power supply circuit. The word line decoder is coupled to the plurality of word lines of the memory storage device. The power supply circuit is coupled to the word line decoder. The power supply circuit is operative to provide a first power supply to the word line decoder in a read mode and a second power supply to the word line decoder in a standby mode. The voltage value of the first power source is greater than or less than the voltage value of the second power source

Description

Word line decoder circuit

This invention relates to a decoder circuit and, more particularly, to a word line decoder circuit.

In general, memory storage devices typically have three modes of operation, including a read mode, a standby mode, and a deep power down mode. The memory storage device requires an instruction to wake up its dynamic operation in the deep power saving mode. Therefore, in the deep power saving mode, the current consumed by the memory storage device is very low. Although the memory storage device in the deep power saving mode has this advantage, it takes a considerable amount of time to use the command to wake up the memory storage device.

In addition, in the prior art, the memory storage device in the standby mode usually has a high voltage (HV), and the presence of the high voltage will cause the leakage current of the memory storage device to become larger, thereby increasing the current consumption thereof. .

The present invention provides a word line decoder circuit that can reduce current consumption in a standby mode.

The word line decoder circuit of the present invention is disposed in a memory storage device and the memory storage device includes a memory cell array. The word line decoder circuit includes a word line decoder and a power supply circuit. The word line decoder is coupled to the plurality of word lines of the memory storage device. The power supply circuit is coupled to the word line decoder. The power supply circuit is operative to provide a first power supply to the word line decoder in a read mode and a second power supply to the word line decoder in a standby mode. The voltage value of the first power source is greater or smaller than the voltage value of the second power source.

In an embodiment of the invention, the power supply circuit is further configured to provide a third power supply to the word line decoder in the read mode. The voltage value of the third power source is greater than or less than the voltage value of the second power source.

In an embodiment of the invention, the voltage value of the first power source is equal to the voltage value of the third power source.

In an embodiment of the invention, the read mode includes a first read period and a second read period. The word line decoder receives the first power source during the first reading. The word line decoder receives the third power supply during the second reading.

In an embodiment of the invention, during the first reading, a first bank of the memory cell array is read. The second block in the memory cell array is read during the second read.

In an embodiment of the invention, the first block and the second block are the same blocks in the memory cell array.

In an embodiment of the invention, the first block and the second block are different blocks in the memory cell array.

In an embodiment of the invention, the word line decoder includes a plurality of sub-decoders. Each sub-decoder is coupled to a corresponding plurality of word lines among the word lines.

In an embodiment of the invention, the power supply circuit includes a plurality of power supplies. Each power supply is coupled to one of a corresponding one of the sub-decoders. Each power supply is configured to provide a first power source or a third power source to which the sub-decoder is coupled in a read mode, and to provide a second power source to the coupled sub-decoder in a standby mode.

In an embodiment of the invention, the power supply circuit is coupled to a first charge pump circuit. The first charge pump circuit is configured to provide a first power source and increase a voltage value of the first power source when the first power source is lower than the first reference voltage.

In an embodiment of the invention, the power supply circuit is coupled to the second charge pump circuit. The second charge pump circuit is configured to provide a third power source, and to increase the voltage value of the third power source when the third power source is lower than the second reference voltage.

In an embodiment of the invention, the word line decoder circuit further includes a pre-decoder. The predecoder is coupled to the power supply circuit. The predecoder is configured to select a block in the memory cell array in the read mode for a read operation.

In an embodiment of the invention, the second power source is one selected from the group consisting of a first voltage, a second voltage, and a third voltage.

In an embodiment of the invention, the first voltage is greater than the second voltage. The second voltage is greater than the third voltage.

Based on the above, in an exemplary embodiment of the invention, the power supply circuit provides a first power supply to the word line decoder in a read mode and a second power supply to a word line decoder in a standby mode. Therefore, the consumption current of the word line decoder circuit in the standby mode can be lowered.

The above described features and advantages of the invention will be apparent from the following description.

The invention is illustrated by the following examples, but the invention is not limited to the illustrated embodiments. Further combinations are also allowed between the embodiments. The term "coupled" as used throughout the specification (including the scope of the patent application) may be used in any direct or indirect connection. For example, if the first device is described as being coupled to the second device, it should be construed that the first device can be directly connected to the second device, or the first device can be connected through other devices or some kind of connection means. Connected to the second device indirectly. In addition, the term "signal" may refer to at least one current, voltage, charge, temperature, data, electromagnetic wave or any other one or more signals.

FIG. 1 is a schematic diagram of a memory storage device according to an embodiment of the invention. 2 is a schematic diagram showing the memory cell array circuit of the embodiment of FIG. 1. Referring to FIG. 1 to FIG. 2 , the memory storage device 100 of the embodiment includes a memory control circuit 110 and a memory cell array 120 . In this embodiment, the memory control circuit 110 is configured to control the memory storage device 100 to operate in one of a plurality of operating modes. The operation modes of this embodiment include, for example, a read mode and a standby mode. In the present embodiment, the voltage generator circuit 130 provides the first power source P1, the second power source P2, or the third power source P3 to the memory storage device 100 in different operation modes. The memory cell array 120 is electrically coupled to the memory control circuit 110. The memory cell array 120 is used to store data. In the present embodiment, the memory cell array 120 includes, for example, four memory banks 122_1 to 122_4, the number of which is for illustrative purposes only, and the present invention is not limited thereto. Each memory block has a corresponding bit line decoder circuit 142, a word line decoder circuit 144, and a sense amplifier circuit 146 to cooperate with the memory control circuit 110 to perform data access operations.

In this embodiment, the circuit architectures of the various circuit functional blocks among the memory control circuit 110, the memory cell array 120, and the voltage generator circuit 130 can be implemented by any suitable circuit in the technical field, respectively. The present invention is not limited thereto, and detailed steps and embodiments thereof may be sufficiently taught, suggested, and implemented by the ordinary knowledge in the art, and thus will not be described again.

3 is a schematic diagram of a word line decoder circuit according to an embodiment of the present invention. Referring to FIG. 3, the word line decoder circuit 300 of the present embodiment includes a power supply circuit 320 and a word line decoder 344. The input end of the power supply circuit 320 is coupled to the pre-decoder 310, and the output is coupled to the word line decoder 344. The input end of the word line decoder 344 is coupled to the power supply circuit 320, and the output end is coupled to a plurality of word lines (not shown) of the memory storage device 100.

Specifically, in the present embodiment, the predecoder 310 receives the block address signal and decodes it to output the block address BK[0] to the block address BK[n-1] to the power supply. Circuit 320, where n is a positive integer greater than two. During reading, one or more target blocks in the memory cell array 120 are selected and read. In the present embodiment, the power supply circuit 320 includes a plurality of power supplies 320_0 to 320_(n-1), and the word line decoder 344 includes a plurality of sub-decoders 344_0 to 344_(n-1). In this embodiment, the word lines of the memory storage device 100 are divided into a group, for example, every k, and each word line group is coupled to a corresponding one of the sub-decoders 344_0 to 344_(n-1). A decoder, where k is a positive integer greater than one. Therefore, in the present embodiment, the word line address WL[0:k-1] output by the sub-decoder 344_0 is, for example, an address corresponding to the first to kth word lines, and the sub-decoder 344_(n -1) The output word line address WL[(n-2)*k:(n-1)*(k-1)] is, for example, corresponding to the (n-2)*kth to the (n-1)th ) *(k-1) The address of the word line, where "*" is a multiplication sign.

In the present embodiment, the power supply circuit 320 provides the first power supply HV1 or the third power supply HV2 to the word line decoder 344 in the read mode, and provides the second power supply to the word line decoder 344 in the standby mode. . For example, in the present embodiment, the target block corresponding to the block address BK[0] is read, for example, and therefore, in the read mode, the first power source HV1 or the third power source received by the power supply 320_0 HV2 is supplied to sub-decoder 344_0 via transistor switch Q1 or Q2. In this example, during reading, the voltage of the node HV[0] is equal to the first power source HV1 or the third power source HV2. In the present embodiment, in the standby mode, the transistor switches Q1 and Q2 are not turned on, and the transistor switch Q3 is turned on, so that the second power source supplied to the sub-decoder 344_0 via the transistor switch Q3 has a voltage value of, for example, VCC- Vt, where VCC is the voltage value of the bias voltage VCC, and Vt is the threshold voltage value of the transistor switch Q3. In this embodiment, the voltage values of the first power source HV1 and the third power source HV2 may be equal or unequal. In the present embodiment, the voltage value of the first power source HV1 is smaller than the voltage value VCC-Vt of the second power source, and the voltage value of the third power source HV2 is smaller than the voltage value VCC-Vt of the second power source.

In addition, the operation method of other power supplies in the power supply circuit 320 can refer to the power supply 320_0, and details are not described herein again. Therefore, in this embodiment, each power supply is configured to provide a first power supply or a third power supply to the sub-decoder coupled thereto in the read mode, and provide a second power supply to the coupled sub-decoder in the standby mode. . In the present embodiment, the power supply circuit 320 provides one of the two power sources to the word line decoder 344 in the read mode as an illustration, but the invention is not limited thereto. In an embodiment, only one power source (for example, the first power source or the third power source) may be provided to the word line decoder in the read mode, or from more than two power sources in the read mode. The selection of one is provided to the word line decoder, which is not limited in the present invention.

4 is a schematic diagram showing the signal waveform of the embodiment of FIG. 3. Referring to FIG. 3 and FIG. 4, in the embodiment, the read mode includes a first read period T1 and a second read period T2. During the first read period T1, the memory block corresponding to the block address BK[m] is read, and during the second read period T2, the memory block corresponding to the block address BK[m] is Read, where m is an integer greater than or equal to zero. That is, in the read mode of the present embodiment, the same block in the memory cell array is read. For example, referring to FIG. 3, assuming that m=0, the block address BK[m] is BK[0], indicating that in the read mode of the embodiment, during the first read period T1 and the second read In the period T2, the memory block corresponding to the block address BK[0] is read.

In this embodiment, during the first read period T1, the first selection signal S1 is at a high level, and the control signal BK[0]*S1 passes through the level shifter LS1 to conduct the crystal switch Q1. At this time, the second selection signal S2 is at a low level, and the transistor switch Q2 is not turned on. Therefore, during the first read period T1, the first power source HV1 is delivered to the node HV[0] and supplied to the sub-decoder 344_0. In the first reading period T1, the voltage level of the first power source HV1 is the target voltage HVt required for the read operation. In this embodiment, during the second read period T2, the second selection signal S2 is at a high level, and the control signal BK[0]*S2 passes through the level shifter LS2 to conduct the crystal switch Q2. At this time, the first selection signal S1 is at a low level, and the transistor switch Q1 is not turned on. Therefore, in the second read period T2, the third power source HV2 is delivered to the node HV[0] and supplied to the sub-decoder 344_0. In the second reading period T2, the voltage level of the third power source HV2 is the target voltage HVt required for the read operation.

FIG. 5 is a schematic diagram showing signal waveforms according to another embodiment of the present invention. Referring to FIG. 4 and FIG. 5, the read operation of this embodiment is similar to the embodiment of FIG. 4, but the main difference between the two is, for example, that in the read mode of the embodiment, the memory cell array is different. The block is read. Specifically, in the present embodiment, in the first read period T1, the memory block corresponding to the block address BK[m] is read, and in the second read period T2, the corresponding block address The memory block of BK[m+h] is read, where h is a positive integer greater than zero. In addition, the power supply circuit 320 of the present embodiment provides a method for operating the power supply to the word line decoder 344 in the read mode. The detailed steps and implementation manners of the embodiment can be sufficiently taught, suggested, and implemented by the embodiment of FIG. Therefore, I will not repeat them.

6 is a schematic diagram showing the voltage generator circuit of the embodiment of FIG. 1. Referring to FIG. 1 , FIG. 3 and FIG. 6 , the voltage generator circuit 130 of the embodiment includes a first charge pump circuit 610 and a second charge pump circuit 620 . The first charge pump circuit 610 is configured to supply the first power source P1 to the memory cell array 120, and boost the voltage value of the first power source P1 when the first power source P1 is lower than the reference voltage Vref (first reference voltage). The second charge pump circuit 620 is configured to provide the third power source P3 to the memory cell array 120, and to increase the voltage value of the third power source P3 when the third power source P3 is lower than the reference voltage Vref (second reference voltage). In the present embodiment, the reference voltage Vref received by the first charge pump circuit 610 and the second charge pump circuit 620 may be the same or different, and the invention is not limited thereto.

Specifically, in the present embodiment, the first charge pump circuit 610 includes an oscillator 612, a charge pump 614, and a comparator 616. The charge pump 614 is configured to generate the first power source HV1 and output the first power source HV1 to the word line decoder 320 and the comparator 616. When the voltage value of the first power source HV1 is lower than the reference voltage Vref, the comparator 616 outputs the enable signal EN1 and returns it to the oscillator 612 to enable the oscillator 612 to generate an oscillation signal, so that the charge pump 614 boosts the third power source accordingly. P3 to the preset voltage value. In addition, the detailed steps and implementations of the method for operating the second charge pump circuit 620 of the present embodiment can be sufficiently taught, suggested, and implemented by the disclosure of the first charge pump circuit 610, and thus will not be described again.

In this embodiment, the circuit architectures of various circuit functional blocks (such as an oscillator, a charge pump, and a comparator) among the first charge pump circuit 610 and the second charge pump circuit 620 can be respectively adapted by any one of the technical fields. The present invention is not limited thereto, and detailed steps and implementations thereof may be sufficiently taught, suggested, and implemented by the ordinary knowledge in the art, and thus will not be described again.

In the embodiment of FIG. 3, in the standby mode, the power supply circuit 320 provides, for example, a second power supply having a voltage value of VCC-Vt (second voltage) to the word line decoder 344, but the invention is not limited thereto. this. In other embodiments, in the standby mode, the power supply circuit, for example, provides a second power supply having a voltage value VCC (first voltage) to a word line decoder, such as FIG. 10, or is provided with a voltage value VSS ( The second power source of the third voltage is supplied to the word line decoder, such as FIG. In other words, in an exemplary embodiment of the present invention, the second power source is one selected from the group consisting of the first voltage VCC, the second voltage VCC-Vt, and the third voltage VSS. The first voltage VCC is greater than the second voltage VCC-Vt, and the second voltage VCC-Vt is greater than the third voltage VSS.

FIG. 7 is a schematic diagram of a word line decoder circuit according to another embodiment of the present invention. Referring to FIG. 3 and FIG. 7, the word line decoder circuit 400 of the present embodiment is similar to the word line decoder circuit 300 of the embodiment of FIG. 3, but the main difference between the two is, for example, the power supply circuit 420. A second power supply having a voltage value VSS (third voltage) is supplied to the word line decoder 444.

Specifically, taking the power supply 420_0 as an example, the node HV[0] is coupled to one end of the transistor switch Q4. The other end of the transistor switch Q4 is coupled to the third voltage VSS, and the control end of the transistor switch Q4 is controlled by the control signal. . Where the control signal An inverted signal representing the delayed block address BK[0]. In standby mode, the control signal The control transistor switch Q4 is turned on, and the control signals BK[0]*S1, BK[0]*S2 respectively control the transistor switches Q1 and Q2 to be non-conducting. Therefore, the third voltage VSS is supplied to the sub-decoder 444_0 via the transistor switch Q4. . In this embodiment, in the standby mode, the operation mode of the other power supply providing the third voltage VSS to the corresponding sub-decoder may refer to the power supply 420_0, and so on, and details are not described herein again. In the present embodiment, the voltage value of the first power source HV1 is greater than the voltage value VSS of the second power source, and the voltage value of the third power source HV2 is greater than the voltage value VSS of the second power source.

FIG. 8 is a schematic diagram showing the control signal generating circuit of the embodiment of FIG. 7. FIG. 9 is a schematic diagram showing the waveform of the control signal of the embodiment of FIG. 8. Referring to FIG. 7 to FIG. 9, the control signal generating circuit 800 of the present embodiment includes a delay element 810 and an OR gate 820. Delay element 810 receives block address BK[0] and delays it by a delay time TD. Then, OR gate 820 generates output signal BK[0]D according to block address BK[0] and delayed block address BK[0]. Thereafter, the output signal BK[0]D is output to the next stage circuit of the control signal generating circuit 800 for inversion to generate a control signal. . Other control signals, such as control signals The way of generating can be deduced by analogy, and will not be described here. In the exemplary embodiment of the present invention, there are many ways to generate control signals. The figures shown in FIG. 8 and FIG. 9 are for illustrative purposes only, and the present invention is not limited thereto.

FIG. 10 is a schematic diagram of a word line decoder circuit according to another embodiment of the present invention. Referring to FIG. 3 and FIG. 10, the word line decoder circuit 500 of the present embodiment is similar to the word line decoder circuit 300 of the embodiment of FIG. 3, but the main difference between the two is, for example, the power supply circuit 520. A second power supply having a voltage value VCC (first voltage) is provided to the word line decoder 544.

Specifically, taking the power supply 520_0 as an example, the node HV[0] is coupled to one end of the transistor switch Q5. The other end of the transistor switch Q5 is coupled to the first voltage VCC, and the control end of the transistor switch Q5 is controlled by the control signal. H. Where the control signal H represents the high level signal of the inverted signal of the delayed block address BK[0]. In standby mode, the control signal H controls the transistor switch Q5 to be turned on, and the control signals BK[0]*S1, BK[0]*S2 respectively control the transistor switches Q1, Q2 to be non-conducting, therefore, the first voltage VCC is supplied to the sub-decoder via the transistor switch Q5. 544_0. In this embodiment, in the standby mode, the operation mode of the other power supply providing the first voltage VCC to the corresponding sub-decoder may refer to the power supply 520_0, and so on, and details are not described herein again. In the present embodiment, the voltage value of the first power source HV1 is smaller than the voltage value VCC of the second power source, and the voltage value of the third power source HV2 is smaller than the voltage value VCC of the second power source.

In summary, in the exemplary embodiment of the present invention, in the standby mode, the power supply of the word line decoder is not a high voltage (HV) provided by the charge pump to reduce the transistor subcritical region current. (sub-threshold current), thereby reducing the standby current. The power source of the word line decoder is, for example, a first voltage, a second voltage, or a third voltage in the standby mode. In an exemplary embodiment of the invention, in the read mode, for example, two power sources are designed, namely a first power source and a third power source. Upon receiving a read command, the two power supplies are alternately provided to the word line decoder. In an exemplary embodiment of the invention, in the same read mode, the plurality of blocks that are read may be the same block or different blocks in the memory cell array. Therefore, in an exemplary embodiment of the present invention, the consumption current of the word line decoder in the standby mode can be lowered.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧ memory storage device
110‧‧‧ memory control circuit and
120‧‧‧Memory cell array
130‧‧‧Voltage generator circuit
122_1, 122_2, 122_3, 122_4‧‧‧ memory blocks
142‧‧‧ bit line decoder circuit
144‧‧‧ character line decoder circuit
146‧‧‧Sense Amplifier Circuit
300, 400, 500‧‧‧ character line decoder circuit
310, 410, 510‧‧‧ predecoder
320, 420, 520‧‧‧ power supply circuit
320_0, 320_(n-1), 420_0, 420_(n-1), 520_0, 520_(n-1)‧‧‧ power supply
344, 444, 544‧‧ ‧ character line decoder
344_0, 344_(n-1), 444_0, 444_(n-1), 544_0, 544_(n-1)‧‧‧ sub-decoder
610‧‧‧First charge pump circuit
612‧‧‧Oscillator
614‧‧‧Charge pump
616‧‧‧ comparator
620‧‧‧Second charge pump circuit
800‧‧‧Control signal generation circuit
810‧‧‧ delay element
820‧‧‧ or gate
P1, HV1‧‧‧ first power supply
P2‧‧‧second power supply
P3, HV2‧‧‧ third power supply
HVt‧‧‧ target voltage
VCC‧‧‧ first voltage
VSS‧‧‧ third voltage
Q1, Q2, Q3, Q4, Q5‧‧‧ transistor switch
HV[0], HV[n-1]‧‧‧ nodes
BK[0]*S1, BK[0]*S2, BK[n-1]*S1, BK[n-1]*S2 , , H, H‧‧‧Control signal
BK[0]D‧‧‧ output signal
S1‧‧‧ first choice signal
S2‧‧‧ second choice signal
BK[0], BK[m], BK[m+h], BK[x]‧‧‧ block addresses
WL[0:k-1], WL[(n-2)*k:(n-1)*(k-1)]‧‧‧ character line address
T1‧‧‧First reading period
T2‧‧‧second reading period
LS1, LS2‧‧‧ position shifter
Vref‧‧‧reference voltage
EN1, EN2‧‧‧ enable signal

FIG. 1 is a schematic diagram of a memory storage device according to an embodiment of the invention. 2 is a schematic diagram showing the memory cell array circuit of the embodiment of FIG. 1. 3 is a schematic diagram of a word line decoder circuit according to an embodiment of the present invention. 4 is a schematic diagram showing the signal waveform of the embodiment of FIG. 3. FIG. 5 is a schematic diagram showing signal waveforms according to another embodiment of the present invention. 6 is a schematic diagram showing the voltage generator circuit of the embodiment of FIG. 1. FIG. 7 is a schematic diagram of a word line decoder circuit according to another embodiment of the present invention. FIG. 8 is a schematic diagram showing the control signal generating circuit of the embodiment of FIG. 7. FIG. 9 is a schematic diagram showing the waveform of the control signal of the embodiment of FIG. 8. FIG. 10 is a schematic diagram of a word line decoder circuit according to another embodiment of the present invention.

Claims (14)

A word line decoder circuit is disposed in a memory storage device and the memory storage device includes a memory cell array, the word line decoder circuit comprising: a word line decoder coupled to the memory a plurality of word lines of the body storage device; and a power supply circuit coupled to the word line decoder for providing a first power source to the word line decoder in a read mode, and The standby mode provides a second power supply to the word line decoder, wherein the voltage value of the first power source is greater than or less than a voltage value of the second power source. The word line decoder circuit of claim 1, wherein the power supply circuit is further configured to provide a third power source to the word line decoder in the read mode, wherein the third power source The voltage value is greater than or less than the voltage value of the second power source. The word line decoder circuit of claim 2, wherein the voltage value of the first power source is equal to the voltage value of the third power source. The word line decoder circuit of claim 2, wherein the read mode comprises a first read period and a second read period, the word line decoder during the first read period The first power source is received, and the word line decoder receives the third power source during the second reading. The word line decoder circuit of claim 4, wherein during the first reading, a first block of the memory cell array is read, and the second read A second block of the memory cell array is read during the period. The word line decoder circuit of claim 5, wherein the first block and the second block are the same block in the memory cell array. The word line decoder circuit of claim 5, wherein the first block and the second block are different blocks in the memory cell array. The character line decoder circuit of claim 2, wherein the word line decoder comprises: a plurality of sub-decoders, each of the sub-decoders being coupled to a corresponding one of the word lines Yuan line. The character line decoder circuit of claim 8, wherein the power supply circuit comprises: a plurality of power supplies, each of the power supplies being coupled to one of the sub-decoders Each of the power supplies is configured to provide the first power source or the third decoder to which the third power source is coupled in the read mode, and provide the second power source to the coupled sub-decoder in the standby mode. . The word line decoder circuit of claim 2, wherein the power supply circuit is coupled to a first charge pump circuit, the first charge pump circuit is configured to provide the first power source, and When the first power source is lower than a first reference voltage, the voltage value of the first power source is increased. The word line decoder circuit of claim 10, wherein the power supply circuit is coupled to a second charge pump circuit, the second charge pump circuit is configured to provide the third power source, and When the third power source is lower than a second reference voltage, the voltage value of the third power source is increased. The character line decoder circuit of claim 1, further comprising: a pre-decoder coupled to the power supply circuit for selecting the memory cell array in the read mode A block is used to perform a read operation. The word line decoder circuit of claim 1, wherein the second power source is one selected from the group consisting of a first voltage, a second voltage, and a third voltage. The word line decoder circuit of claim 13, wherein the first voltage is greater than the second voltage, and the second voltage is greater than the third voltage.