TWI638451B - Pixel array substrate - Google Patents

Abstract

A pixel array substrate includes a first pixel unit, a second pixel unit adjacent to the first pixel unit, a first thin film transistor connected to the first pixel unit, and a second thin film of the second pixel unit. Scan lines electrically connected to at least one of the transistors, and electrically connected to at least one of the first thin film transistor of the first pixel unit and at least one of the second thin film transistor of the second pixel unit and interlaced with the scan line Data line. The first color filter pattern of the first pixel unit and the second color filter pattern of the second pixel unit partially overlap on the data line to form a stacked region of the first color filter pattern and the second color filter pattern. The data line has a wide portion and a narrow portion. The width of the stacked area on the narrow portion of the data line is greater than the width of the stacked area on the wide portion of the data line.

Description

Pixel array substrate

The present invention relates to an array substrate, and more particularly, to a pixel array substrate.

The display panel includes a first substrate, an active device layer disposed on the first substrate, a second substrate disposed opposite the first substrate, and a display medium disposed between the first substrate and the second substrate. Generally, if the display medium is a non-self-luminous material (such as liquid crystal), the display panel further includes a color filter layer disposed on the second substrate, so that the display panel can display a color screen. In the manufacturing process of a display panel, a first substrate having an active device layer and a second substrate having a color filter layer are assembled, and when the assembly accuracy of the two is not good, the display quality may decrease. In view of this, the color filter layer can be directly fabricated on the first substrate having the pixel layer, and a color filter on array (COA) structure is formed to improve the above problems.

However, the element density of the active element layer is different in different regions. Therefore, when a plurality of color filter patterns of the color filter layer are formed in a region with a low element density, a sag region is easily formed between two adjacent color filter patterns. When the color filter layer with the sunken area is combined with the display medium and the second substrate to form a display panel, the display panel is prone to air bubbles caused by the sunken area, causing the display panel to be defective.

The invention provides a pixel array substrate. A display panel including the pixel array substrate has a low probability of air bubbles.

The pixel array substrate of the present invention includes a first pixel unit, a second pixel unit, a scan line, and a data line. The first pixel unit includes a first thin-film transistor, a first pixel electrode electrically connected to the first thin-film transistor, and a first color filter pattern disposed overlapping the first pixel electrode. The second pixel unit is adjacent to the first pixel unit. The second pixel unit includes a second thin-film transistor, a second pixel electrode electrically connected to the second thin-film transistor, and a second color filter pattern disposed overlapping the second pixel electrode. The scan line is electrically connected to at least one of the first thin film transistor and the second thin film transistor. The data lines and the scan lines are staggered and are electrically connected to at least one of the first thin film transistor and the second thin film transistor. The first thin film transistor and the second thin film transistor are located on opposite sides of the data line, respectively. The first color filter pattern and the second color filter pattern partially overlap on the data line to form a stacked area of the first color filter pattern and the second color filter pattern. The data line has a wide portion and a narrow portion, and the width of the stacked region on the narrow portion is greater than the width of the stacked region on the wide portion.

In an embodiment of the present invention, the first color filter pattern has a straight edge on a wide portion of the data line, and the first color filter pattern has a curved edge on a narrow portion of the data line.

In an embodiment of the present invention, the narrow portion of the data line is intersected with the scan line, and the narrow portion of the data line includes a first sub-portion and a second sub-portion. The first sub-section overlaps the scanning line. The second sub-section does not overlap the scanning line and is connected between the wide section of the data line and the first sub-section. The width of the stacked region on the second sub-portion is greater than the width of the stacked region on the first sub-portion.

In an embodiment of the present invention, the above-mentioned stacked region of the first color filter pattern and the second color filter pattern includes a first sub-region located on a narrow portion of the data line and a first sub-region located on a wide portion of the data line. Second child area. The width of the first sub-region of the stacked region is larger than the width of the second sub-region of the stacked region. The scan line has a notch. In the vertical projection direction, at least a part of the first sub-region is located in the gap of the scanning line.

In an embodiment of the present invention, the scanning line has a notch, the first color filter pattern has a first convex portion, and the first convex portion is convex toward a first direction crossing the extending direction of the data line, and is perpendicular to In the projection direction, a portion of the first convex portion of the first color filter pattern is located in a notch of the scanning line.

In an embodiment of the present invention, the first color filter pattern has a first convex portion, and the first convex portion is convex toward an extending direction of the scanning line. The narrow portion of the data line includes a first sub-portion and a second sub-portion. The first sub-section overlaps the scanning line. The second sub-section does not overlap the scanning line, and is connected between the wide section of the data line and the first sub-section. The width of the second sub-portion of the portion is reduced from the wide portion to the first sub-portion of the narrow portion, and the first convex portion is located on the first sub-portion and the second sub-portion of the portion.

In an embodiment of the present invention, the first color filter pattern has at least one first convex portion, and the at least one first convex portion overlaps with the second color filter pattern to form a stacked region on the narrow portion. .

According to an embodiment of the present invention, the first color filter pattern has a plurality of first convex portions. The plurality of first convex portions are respectively located on opposite sides of the scan line. The plurality of first convex portions are connected to define a notch of the first color filter pattern, and the notch overlaps the narrow portion of the scanning line and the data line.

In an embodiment of the present invention, the first color filter pattern and the second color filter pattern have a first convex portion and a second convex portion, respectively. The first convex portion protrudes in a first direction crossing the extending direction of the data line, the second convex portion protrudes in a second direction opposite to the first direction, and the first convex portion and the second convex portion partially overlap to form Stacked areas on narrow sections.

In an embodiment of the present invention, the above-mentioned first pixel electrode includes a plurality of first sub-pixel electrodes located on opposite sides of a scanning line, and the second pixel electrode includes a plurality of first pixel electrodes located on opposite sides of the scanning line. Multiple second sub-pixel electrodes.

Based on the foregoing, a pixel array substrate according to an embodiment of the present invention includes adjacent first pixel units and second pixel units, scan lines, and data lines. The first thin film transistor of the first pixel unit and the second thin film transistor of the second pixel unit are located on opposite sides of the data line, respectively. The first color filter pattern of the first pixel unit and the second color filter pattern of the second pixel unit partially overlap on the data line to form a stacked region of the first color filter pattern and the second color filter pattern. In particular, the data line has a wide portion and a narrow portion, and the width of the stacked region on the narrow portion is greater than the width of the stacked region on the wide portion. As a result, the probability of air bubbles in the display panel composed of the pixel array substrate and the opposite substrate can be reduced.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic top view of a pixel array substrate according to an embodiment of the present invention. FIG. 2 is an enlarged schematic view of a portion R1 of the pixel array substrate of FIG. 1. FIG. 3 is a schematic cross-sectional view of the pixel array substrate drawn according to the section line A-A 'of FIG. 2. FIG. 4 is a schematic cross-sectional view of the pixel array substrate drawn according to the section line B-B 'of FIG. 2.

Please refer to FIG. 1, FIG. 2, FIG. 3, and FIG. 4. The pixel array substrate 1000 includes a substrate 1 (illustrated in FIGS. 3 and 4), a plurality of first pixel units 100, a plurality of first pixel units 100 disposed on the substrate 1. Two pixel units 200, multiple scan lines SL and multiple data lines DL. The data lines DL and the scan lines SL are arranged alternately. Figure 1 depicts a first pixel unit 100, a second pixel unit 200, a scan line SL, and two data lines DL1, DL2 as examples. Those skilled in the art should be able to use The required pixel array substrate 1000 is realized.

Referring to FIG. 1, an extension direction y of the data lines DL1 and DL2 is interlaced with an extension direction x of the scan line SL. For example, in this embodiment, the extension direction y of the data lines DL1 and DL2 and the extension direction -x of the scan line SL may be substantially perpendicular, but the invention is not limited thereto. In this embodiment, the substrate 1 may be a light-transmitting substrate, and the material thereof is, for example, glass, quartz, organic polymer, or other applicable materials. However, the present invention is not limited to this. In other embodiments, the substrate 1 may also be an opaque / reflective substrate, and the material thereof is, for example, a conductive material, a wafer, a ceramic, or other applicable materials.

The first pixel unit 100 includes a first thin film transistor T1, a first pixel electrode 110, and a first color filter pattern 120. In this embodiment, the first thin film transistor T1 includes a gate G1, a semiconductor pattern SE1, a source S1, and a drain D1. An insulating layer 130 (labeled in FIGS. 3 and 4) is disposed between the gate electrode G1 and the semiconductor pattern SE1. In this embodiment, the first pixel unit 100 may further include thin film transistors T3 and T4. Similarly, the thin film transistor T3 includes a gate G3, a semiconductor pattern SE3, a source S3, and a drain D3. An insulating layer 130 (labeled in FIGS. 3 and 4) is disposed between the gate G3 and the semiconductor pattern SE3. S3 and drain D3 are respectively electrically connected to different two regions of the semiconductor pattern SE3; the thin film transistor T4 includes a gate G4, a semiconductor pattern SE4, a source S4 and a drain D4, and an insulating layer 130 (labeled in FIGS. 3 and 4). ) Is disposed between the gate G4 and the semiconductor pattern SE4, and the source S4 and the drain D4 are electrically connected to different two regions of the semiconductor pattern SE4, respectively. In this embodiment, the semiconductor pattern SE1 of the first thin film transistor T1 and the semiconductor pattern SE3 of the thin film transistor T3 may be directly connected, and the semiconductor pattern SE4 of the thin film transistor T4 and the semiconductor patterns SE1 and SE3 may be separated, but the present invention does not This is the limit.

In this embodiment, the first pixel electrode 110 may selectively include a plurality of first sub-pixel electrodes 112 and 114 respectively located on opposite sides of the scan line SL. In this embodiment, the pixel array substrate 1000 may optionally include a common line CL, and the first pixel unit 100 may further include an electrode 140. The common line CL is located on one side of the scan line SL. The electrode 140 and the common line CL overlap in the vertical projection direction z to form a shared capacitance Cst-1.

In this embodiment, the gate G1 of the first thin film transistor T1, the gate G3 of the thin film transistor T3, and the gate G4 of the thin film transistor T4 are electrically connected to the scanning line SL; the source of the first thin film transistor T1 The electrode S1 is electrically connected to the data line DL1, and the drain D1 of the first thin-film transistor T1 is electrically connected to the first sub-pixel electrode 112; the source S3 of the thin-film transistor T3 and the source of the first thin-film transistor T1 S1 is electrically connected; the drain D3 of the thin film transistor T3 is electrically connected to the electrode 140 of the sharing capacitor Cst-1; the source S4 of the thin film transistor T4 is electrically connected to the electrode 140 of the sharing capacitor Cst-1. In this embodiment, the first pixel unit 100 further includes a signal line TL1. The signal line TL1 and the first pixel electrode 110 overlap in the vertical projection direction z, and the drain electrode D4 of the thin film transistor T4 and the signal line TL1 are electrically connected. Sexual connection. However, the present invention is not limited to this. In other embodiments, the drain electrode D4 of the thin film transistor T4 can be selectively connected to the common line CL through the opening of the insulating layer 130 (illustrated in FIG. 3).

With the layout described in the previous paragraph, when the data signal is input to the data line DL1 and the scan signal is input to the scan line SL to enable the first thin film transistor T1, the thin film transistor T3, and the thin film transistor T4 to be turned on, the first sub pixel electrode 112 and the first sub-pixel electrode 114 may have different potentials, so that the two regions where the first sub-pixel electrode 112 and the first sub-pixel electrode 114 are located have different brightness, thereby improving the color washout problem. .

It should be noted that the structure of the above-mentioned first pixel unit 100 is only used to illustrate the present invention and is not intended to limit the present invention. According to other embodiments, the first pixel unit 100 may also have other appropriate structures.

The first color filter pattern 120 is disposed overlapping the first pixel electrode 110. For example, in this embodiment, the first color filter pattern 120 may overlap the first sub-pixel electrode 112 and the first sub-pixel electrode 114. In this embodiment, the first color filter pattern 120 may have a plurality of through-holes 122 and 124, and the first sub-pixel electrode 112 and the first sub-pixel electrode 114 may pass through the through-holes 122 and 124 and the first sub-pixel electrode respectively. The drain D1 of the thin film transistor T1 and the drain D3 of the thin film transistor T3 are electrically connected. However, the present invention is not limited to this. According to other embodiments, the first color filter pattern 120 may also take other appropriate forms.

The second pixel unit 200 is adjacent to the first pixel unit 100. In this embodiment, the structure of the second pixel unit 200 and the structure of the first pixel unit 100 may be selectively the same, but the present invention is not limited thereto. The structure of the second pixel unit 200 according to an embodiment of the present invention is exemplified below.

The second pixel unit 200 includes a second thin film transistor T2, a second pixel electrode 210, and a second color filter pattern 220. In this embodiment, the second thin film transistor T2 includes a gate G2, a semiconductor pattern SE2, a source S2, and a drain D2. An insulating layer 130 (labeled in FIGS. 3 and 4) is disposed between the gate electrode G2 and the semiconductor pattern SE2. In this embodiment, the second pixel unit 200 may optionally further include thin film transistors T5 and T6. Similarly, the thin film transistor T5 includes a gate G5, a semiconductor pattern SE5, a source S5, and a drain D5. An insulating layer 130 (labeled in FIGS. 3 and 4) is disposed between the gate G5 and the semiconductor pattern SE5. S5 and drain D5 are respectively electrically connected to different two regions of the semiconductor pattern SE5; the thin film transistor T6 includes a gate G6, a semiconductor pattern SE6, a source S6 and a drain D6, and an insulating layer 130 (labeled in FIGS. 3 and 4) ) Is disposed between the gate G6 and the semiconductor pattern SE6, and the source S6 and the drain D6 are electrically connected to different two regions of the semiconductor pattern SE6, respectively. In this embodiment, the semiconductor pattern SE2 of the second thin film transistor T2 and the semiconductor pattern SE5 of the thin film transistor T5 may be directly connected, and the semiconductor pattern SE6 of the thin film transistor T6 and the semiconductor patterns SE2 and SE5 may be separated, but the present invention does not This is the limit.

In this embodiment, the second pixel electrode 210 may selectively include a plurality of second sub-pixel electrodes 212 and 214 respectively located on opposite sides of the scan line SL. In this embodiment, the second pixel unit 200 may further include an electrode 240. The electrode 240 and the common line CL overlap in the direction z to constitute a shared capacitance Cst-2.

In this embodiment, the gate G2 of the second thin-film transistor T2, the gate G5 of the thin-film transistor T5, and the gate G6 of the thin-film transistor T6 are electrically connected to the scanning line SL; The source S2 is electrically connected to the data line DL2, and the drain D2 of the second thin-film transistor T2 is electrically connected to the second sub-pixel electrode 212; the source S5 of the thin-film transistor T5 and the source of the second thin-film transistor T2 The electrode S2 of the thin film transistor T5 is electrically connected to the electrode 240 of the sharing capacitor Cst-2; the source S6 of the thin film transistor T6 is electrically connected to the electrode 240 of the sharing capacitor Cst-2. In this embodiment, the second pixel unit 200 further includes a signal line TL2. The signal line TL2 and the second pixel electrode 210 overlap in the vertical projection direction z. The drain electrode D6 of the thin film transistor T6 and the signal line TL2 are electrically connected. Sexual connection. However, the present invention is not limited to this. In other embodiments, the drain electrode D6 of the thin film transistor T6 can be selectively connected to the common line CL through the opening of the insulating layer 130 (illustrated in FIG. 3).

Similarly, using the layout described in the previous paragraph, when a data signal is input to the data line DL2 and a scan signal is input to the scan line SL to enable the second thin film transistor T2, the thin film transistor T5, and the thin film transistor T6 to be turned on, the second sub The pixel electrode 212 and the second sub-pixel electrode 214 may have different potentials so that the two regions where the second sub-pixel electrode 212 and the second sub-pixel electrode 214 are located have different brightness, thereby improving the problem of color cast.

It should be noted that the structure of the second pixel unit 200 described above is only used to illustrate the present invention and not to limit the present invention. According to other embodiments, the second pixel unit 200 may also have other appropriate structures.

The second color filter pattern 220 is overlapped with the second pixel electrode 210. For example, in this embodiment, the second color filter pattern 220 may overlap the second sub-pixel electrode 212 and the second sub-pixel electrode 214. In this embodiment, the second color filter pattern 220 may selectively have a plurality of through holes 222 and 224, and the second sub-pixel electrode 212 and the second sub-pixel electrode 214 may respectively pass through the through holes 222 and 224, respectively. It is electrically connected to the drain electrode D2 of the second thin film transistor T2 and the drain electrode D5 of the thin film transistor T5. However, the present invention is not limited thereto, and according to other embodiments, the second color filter pattern 220 may also take other appropriate forms.

In this embodiment, the gate electrodes G1, G2, G3, G4, G5, G6, the scan lines SL, and the common line CL may belong to the first conductive layer, the data lines DL1, DL2, the sources S1, S2, S3, S4, S5, S6, drain electrodes D1, D2, D3, D4, D5, D6, and electrodes 140, 240 may belong to the second conductive layer, but the invention is not limited thereto. The first conductive layer and the second conductive layer are generally metal materials, but the present invention is not limited thereto. According to other embodiments, the first conductive layer and the second conductive layer may also be other conductive materials, such as alloys, A nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, or a stacked layer of a metal material and other conductive materials. In this embodiment, the first sub-pixel electrode 112, the first sub-pixel electrode 114, the second sub-pixel electrode 212, and the second sub-pixel electrode 214 may belong to the same third conductive layer, but the present invention is not limited to This is limited. In this embodiment, the third conductive layer is, for example, a transparent conductive layer. The material of the transparent conductive layer may be a metal oxide, such as: indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, or other suitable oxides, or at least the foregoing. Stacked layers of the two. However, the present invention is not limited thereto. According to other embodiments, the third conductive layer may also be a reflective conductive layer, or a combination of a reflective conductive layer and a transparent conductive layer.

Please refer to FIG. 1, FIG. 2, FIG. 3 and FIG. 4. The first thin film transistor T1 and the second thin film transistor T2 are located on opposite sides of the data line DL, respectively. The first color filter pattern 120 and the second color filter pattern 220 partially overlap on the data line DL to form a stacked region 10 of the first color filter pattern 120 and the second color filter pattern 220. The data line DL has a wide portion 262 and a narrow portion 264. The width W2 of the stacked region 10 on the narrow portion 264 is larger than the width W1 of the stacked region 10 on the wide portion 262. Furthermore, in this embodiment, the narrow portion 264 of the data line DL is interleaved with the scan line SL, and the narrow portion 264 of the data line DL includes a first sub-portion 264a and a second sub-portion 264b. The first sub-portion 264a overlaps the scanning line SL, and the second sub-portion 264b does not overlap the scanning line SL and is connected between the wide portion 262 of the data line DL and the first sub-portion 264a. The width W2 of the stack region 10 on the second sub-portion 264b is larger than the width W3 of the stack region 10 on the first sub-portion 264a. In this embodiment, the width W1 is substantially equal to the width W3, but the invention is not limited thereto. In addition, in this embodiment, the width K of the part of the second sub-portion 264b can be reduced from the wide portion 262 of the data line DL2 to the first sub-portion 264a, but the present invention is not limited thereto.

In this embodiment, the first color filter pattern 120 has a straight edge 120s1 on a wide portion 262 of the data line DL, and the first color filter pattern 120 has a curved edge 120s2 on a narrow portion 264 of the data line DL. Furthermore, in this embodiment, the second color filter pattern 220 also has a straight edge 220s1 on the wide portion 262 of the data line DL, and the second color filter pattern 210 is on the narrow portion 264 of the data line DL. Also has curved edges 220s2. The distance L1 in the direction x of the straight edge 120s1 of the first color filter pattern 120 and the straight edge 220s1 of the second color filter pattern 220 may be equal to the width W1 of the stacked region 10 on the wide portion 262 of the data line DL2. The maximum distance L2 in the direction x of the curved edge 120s2 of the first color filter pattern 120 and the curved edge 210b of the second color filter pattern 220 may be equal to the width W2 of the stacked region 10 on the narrow portion 264 of the data line DL.

The stacked region 10 of the first color filter pattern 120 and the second color filter pattern 220 includes a first sub-region 12 and a second sub-region 14. The first sub-region 12 is located on the narrow portion 264 of the data line DL. The second sub-region 14 is located on the wide portion 262 of the data line DL. The width W2 of the first sub-region 12 of the stacked region 10 is larger than the width W1 of the second sub-region 14 of the stacked region 10. In this embodiment, the scanning line SL has a notch U, and in the vertical projection direction z, at least part of the first sub-region 12 is located within the notch U of the scanning line SL.

In this embodiment, the first color filter pattern 120 has a first convex portion 126, and the first convex portion 126 is convex in a direction -x that intersects the extending direction y of the data line DL, and is in a vertical projection direction z. Part of the first convex portion 126 of the first color filter pattern 120 is located in the notch U of the scan line SL. Furthermore, in this embodiment, the first convex portion 126 of the first color filter pattern 120 may be located on the first sub-portion 264 a and the second sub-portion 264 b of the narrow portion 264 of the data line DL. In this embodiment, the second color filter pattern 220 has a second convex portion 226, and the second convex portion 226 is convex in a direction x opposite to the direction -x, and the first convex portion 126 of the first color filter pattern 120 The second convex portion 226 of the second color filter pattern 220 is partially overlapped to form a partial stack region 10 on the narrow portion 264 of the data line DL and having a width W2.

In short, at least one of the first color filter pattern 120 and the second color filter pattern 220 has at least one convex portion (also referred to as a repair portion) extending to an adjacent pixel unit. The convex portion can fill a gap g between the narrow portion 264 of the data line DL and a portion of the first conductive layer (for example, the scanning line SL), and the convex portion overlaps another color filter pattern. A stacked region 10 having a wider width W2 is formed. In the process of forming the color filter pattern, at least one convex portion of at least one of the first color filter pattern 120 and the second color filter pattern 220 can fill the narrow portion 264 of the data line DL and the first conductive layer. The gap g is relatively wide, so it is not easy to form a depression at the junction of the first color filter pattern 120 and the second color filter pattern 220. Therefore, the display panel composed of the pixel array substrate 1000 and the counter substrate is less prone to air bubbles.

FIG. 5 is a schematic top view of a pixel array substrate according to another embodiment of the present invention. FIG. 6 is an enlarged schematic view of a portion R2 of the pixel array substrate of FIG. 5. FIG. 7 is a schematic cross-sectional view of the pixel array substrate drawn according to the section line C-C 'of FIG. 6. FIG. 8 is a schematic cross-sectional view of the pixel array substrate drawn according to the section line D-D 'of FIG. 6.

Please refer to FIG. 5, FIG. 6, FIG. 7, and FIG. 8. The pixel array substrate 1000A is similar to the pixel array substrate 1000 described above. Therefore, the same or corresponding components are denoted by the same or corresponding reference numerals. Only the differences between the pixel array substrate 1000A and the pixel array substrate 1000 will be described below. For the same or corresponding parts, please refer to the foregoing description.

Please refer to FIGS. 5, 6, 7 and 8. The first color filter pattern 120A and the second color filter pattern 220A partially overlap on the data line DL1 to form the first color filter pattern 120A and the second color. The stacked region 10 of the filter pattern 220A. The data line DL1 has a wide portion 262 and a narrow portion 264. The width W2 of the stacked region 10 on the narrow portion 264 is larger than the width W1 of the stacked region 10 on the wide portion 262. The first color filter pattern 120A has at least one first convex portion 126A, and the at least one first convex portion 126A overlaps with the second color filter pattern 220A to form a stacked region 10 on the narrow portion 264.

Different from the pixel array substrate 1000, in this embodiment, the first color filter pattern 120A may have a plurality of first convex portions 126A and a plurality of first convex portions 126A respectively located on opposite sides of the scanning line SL. The notches 128 connected to define the first color filter pattern 120A, the notches 128 overlap the narrow portion 264 of the scan line SL and the data line DL1. In addition, in this embodiment, the edges 220c of the second color filter pattern 220A on the wide portion 262 and the narrow portion 264 of the data line DL1 may optionally be linear edges, but the invention is not limited thereto. The pixel array substrate 1000A has similar functions and advantages as the pixel array substrate 1000, and will not be repeated here.

In summary, a pixel array substrate according to an embodiment of the present invention includes adjacent first pixel units and second pixel units, scan lines and data lines. The first thin film transistor of the first pixel unit and the second thin film transistor of the second pixel unit are located on opposite sides of the data line, respectively. The first color filter pattern of the first pixel unit and the second color filter pattern of the second pixel unit partially overlap on the data line to form a stacked region of the first color filter pattern and the second color filter pattern. In particular, the data line has a wide portion and a narrow portion, and the width of the stacked region on the narrow portion is greater than the width of the stacked region on the wide portion. Therefore, the display panel composed of the pixel array substrate and the counter substrate is less prone to air bubbles.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

1‧‧‧ substrate
10‧‧‧stacking area
12‧‧‧ the first sub-region
14‧‧‧Second Subdivision
100‧‧‧ the first pixel unit
110‧‧‧first pixel electrode
112, 114‧‧‧ first sub-pixel electrode
120, 120A‧‧‧The first color filter pattern
120s1, 220s1‧‧‧Straight edge
120s2, 220s2‧‧‧curved edge
122, 124, 222, 224‧‧‧ through holes
126, 126A‧‧‧The first convex part
128‧‧‧ notch
130‧‧‧ Insulation
140, 240‧‧‧ electrodes
200‧‧‧ second pixel unit
210‧‧‧Second pixel electrode
212, 214‧‧‧‧second sub pixel electrode
220, 220A‧‧‧Second color filter pattern
220c‧‧‧Edge
226‧‧‧Second Convex
262‧‧‧wide
264‧‧‧Narrow section
264a‧‧‧First Division
264b‧‧‧Second Subpart
1000, 1000A‧‧‧ pixel array substrate
A-A ', B-B', C-C ', D-D'‧‧‧ hatch
CL‧‧‧ shared line
Cst-1, Cst-2‧‧‧ sharing capacitor
DL, DL1, DL2‧‧‧ data line
D1 ～ D6‧‧‧‧Source
G1 ～ G6‧‧‧Gate
g‧‧‧ clearance
L1, L2‧‧‧ distance
R1, R2‧‧‧partial
SL‧‧‧scan line
S1 ～ S6‧‧‧Source
SE1 ～ SE6‧‧‧Semiconductor pattern
T1 ～ T6‧‧‧Thin-film transistor
TL1, TL2 ‧‧‧ signal line
U‧‧‧ gap
W1, W2, W3, K‧‧‧Width
x, -x, y, z‧‧‧ directions

FIG. 1 is a schematic top view of a pixel array substrate according to an embodiment of the present invention. FIG. 2 is an enlarged schematic view of a portion R1 of the pixel array substrate of FIG. 1. FIG. 3 is a schematic cross-sectional view of the pixel array substrate drawn according to the section line A-A 'of FIG. 2. FIG. 4 is a schematic cross-sectional view of the pixel array substrate drawn according to the section line B-B 'of FIG. 2. FIG. 5 is a schematic top view of a pixel array substrate according to another embodiment of the present invention. FIG. 6 is an enlarged schematic view of a portion R2 of the pixel array substrate of FIG. 5. FIG. 7 is a schematic cross-sectional view of the pixel array substrate drawn according to the section line C-C 'of FIG. 6. FIG. 8 is a schematic cross-sectional view of the pixel array substrate drawn according to the section line D-D 'of FIG. 6.

Claims (11)

A pixel array substrate includes: a first pixel unit including: a first thin film transistor; a first pixel electrode electrically connected to the first thin film transistor; and a first color filter pattern A second pixel unit adjacent to the first pixel unit and including: a second thin film transistor; a second pixel electrode and the second thin film electrode The crystal is electrically connected; and a second color filter pattern is disposed overlapping the second pixel electrode; a scan line is electrically connected to at least one of the first thin film transistor and the second thin film transistor; And a data line arranged alternately with the scanning line and electrically connected to at least one of the first thin film transistor and the second thin film transistor, wherein the first thin film transistor and the second thin film transistor are respectively located at Opposite sides of the data line; the first color filter pattern and the second color filter pattern partially overlap on the data line to form a stack of the first color filter pattern and the second color filter pattern District; the information Having a wide portion and a narrow portion, the width of the stack region of the stack region is greater than the width of the wide portion in the narrow portion of the. The pixel array substrate according to item 1 of the patent application scope, wherein the first color filter pattern has a straight edge on the wide portion of the data line, and the first color filter pattern is on the data line. The narrow portion has a curved edge. The pixel array substrate according to item 1 of the scope of patent application, wherein the narrow portion of the data line is interleaved with the scan line, and the narrow portion of the data line includes: a first sub-portion overlapping the scan line And a second sub-portion that does not overlap the scan line and is connected between the wide portion and the first sub-portion of the data line, wherein the width of the stacking region on the second sub-portion is greater than that in the The width of the stacked region on the first sub-portion. The pixel array substrate according to item 1 of the scope of the patent application, wherein the stacked region of the first color filter pattern and the second color filter pattern includes: a first sub-region located in the narrow area of the data line Ministry. The pixel array substrate according to item 4 of the scope of patent application, wherein the stacked region of the first color filter pattern and the second color filter pattern further includes: a second sub-region, which is located on the data line. On the wide portion, the width of the first sub-region of the stacking region is greater than the width of the second sub-region of the stacking region; the scanning line has a gap; and in a vertical projection direction, at least part of the first The sub-area is located within the gap in the scan line. The pixel array substrate according to item 1 of the scope of patent application, wherein the scanning line has a gap, the first color filter pattern has a first convex portion, and the first convex portion faces the extending direction of the data line. A cross in a first direction is convex, and in a vertical projection direction, a portion of the first convex portion of the first color filter pattern is located in the notch of the scan line. The pixel array substrate according to item 1 of the scope of the patent application, wherein the first color filter pattern has a first convex portion, and the first convex portion is convex toward the extending direction of the scanning line. The narrow portion includes: a first sub-section that overlaps the scanning line; and a second sub-section that does not overlap the scanning line and is connected between the wide portion and the first sub-section of the data line, part of which The width of the second sub-portion is reduced from the wide portion to the first sub-portion of the narrow portion, and the first convex portion is located on the first sub-portion and the second sub-portion of the portion. The pixel array substrate according to item 1 of the scope of patent application, wherein the first color filter pattern has at least one first convex portion, and the at least one first convex portion overlaps the second color filter pattern, so that The stacked region is formed on the narrow portion. The pixel array substrate according to item 1 of the scope of patent application, wherein the first color filter pattern has a plurality of first convex portions, which are respectively located on opposite sides of the scanning line, and the first convex portions are connected to A notch defining the first color filter pattern is overlapped with the narrow portion of the scan line and the data line. The pixel array substrate according to item 1 of the scope of patent application, wherein the first color filter pattern and the second color filter pattern have a first convex portion and a second convex portion, respectively, and the first convex portion The first convex portion protrudes toward a first direction crossing the extending direction of the data line, the second convex portion protrudes toward a second direction opposite to the first direction, and the first convex portion partially overlaps the second convex portion. To form the stacked region on the narrow portion. The pixel array substrate according to item 1 of the patent application scope, wherein the first pixel electrode includes a plurality of first sub-pixel electrodes respectively located on opposite sides of the scan line, and the second pixel electrode includes A plurality of second sub-pixel electrodes located on opposite sides of the scan line.