TWI638358B - Memory device and operation method thereof - Google Patents

Abstract

A method of operating a memory device is provided. A memory array of the memory device includes a plurality of word lines and a plurality of bit lines. The method of operating the memory device includes: applying a write voltage to at least one selected word line of the word lines; and during a high level of the write voltage, according to the bit lines A plurality of selected bit lines of data 0 are written at individual locations of the word lines, and a plurality of different bit line voltages are applied to the selected bit lines to which data 0 is written.

Description

Memory device and method of operating same

The present invention relates to a memory device and method of operation thereof.

In a memory device, the resistance-capacitance delay time (RC delay time) of a word line is inevitable when transmitting an electronic signal. The longer the word line length, the more severe the resistance-capacitance delay time. When a word line voltage is applied, the word line voltage is applied to the beginning of the word line. Due to the resistance-capacitance delay time, the waveform of the word line voltage received at the end of the word line may be distorted. However, this may cause the writing speed between the memory cell at the beginning of the word line and the memory cell at the end of the word line to be inconsistent, so that the basic write threshold voltage distribution (dumb program Vth distribution) becomes wider. This will slow down the writing speed of the memory device. During the writing process, in order to pull the end of the word line high to a high voltage, a sufficient write pulse width will be required. However, an excessively long write pulse width will reduce the write speed of the memory cell. Therefore, the present invention provides a memory device and an operation method thereof, in order to solve the inconsistent writing speed between the memory cell and the memory cell at the end of the word line due to the resistance-capacitor delay time, so that the basic writing is performed. The threshold voltage distribution is narrowed to improve the program performance of the memory device.

According to an embodiment of the present invention, a method for operating a memory device is provided. A memory array of the memory device includes a plurality of word lines and a plurality of bit lines, and the method of operating the memory device includes: applying a write And a voltage is applied to at least one selected word line of the word lines; and during a high level of the write voltage, a plurality of selected bit lines are selected according to the plurality of written data 0 in the bit lines At a respective location of the word lines, a different plurality of bit line voltages are applied to the selected bit lines to which data 0 is written.

According to another embodiment of the present invention, a method for operating a memory device is provided. The memory array of the memory device includes a plurality of word lines and a plurality of bit lines, and the bit lines are based on the word lines. The plurality of individual locations are divided into a plurality of bit line groups, and the method of operating the memory device includes: applying a write voltage to the at least one selected word line of the word lines; and the write voltage During a high level period, different plurality of bit line voltages are applied to the bit line groups.

According to still another embodiment of the present invention, a memory device includes: a memory array including a plurality of word lines and a plurality of bit lines; a control circuit coupled to the memory array, and an operating voltage generation The circuit is coupled to the memory array and the control circuit, and the operating voltage generating circuit generates a write voltage to the word lines of the memory array. Under the control of the control circuit, in a high level period of the write voltage, a plurality of selected bit lines are selected from the plurality of bit lines according to the plurality of written data 0 in the bit lines. In an individual position, the operating voltage generating circuit applies a different plurality of bit line voltages to the selected bit lines to which data 0 is written.

In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

100‧‧‧ memory device

110‧‧‧Memory array

120‧‧‧Control circuit

130‧‧‧Operating voltage generating circuit

VPGM‧‧‧ write voltage

VPASS‧‧‧ turn-on voltage

VBL and VBL’‧‧‧ bit line voltage

VSSL‧‧‧ memory string selection voltage

T1‧‧‧ high standard period

GSL‧‧‧Ground selection signal line

SSL‧‧‧ memory string selection line

WL‧‧‧ character line

BL‧‧‧ bit line

BLG1, BLG2 and BLG3‧‧‧ bit line group

310, 320‧‧‧ basic write threshold voltage distribution

Fig. 1A is a functional block diagram showing a memory device in accordance with an embodiment of the present invention.

FIG. 1B shows a schematic diagram of a memory array in accordance with an embodiment of the present invention.

Fig. 2 shows a signal waveform diagram according to an embodiment of the present invention.

FIG. 3A is a schematic view showing the waveform of the tunneling oxide layer across the pressure according to the embodiment of the present invention.

Figure 3B shows the basic write threshold voltage distribution in accordance with embodiments of the present invention and prior art techniques.

Fig. 4 and Fig. 5 show signal waveform diagrams of the other two embodiments of the present invention.

The technical terms of the present specification refer to the idioms in the technical field, and some of the terms are explained or defined in the specification, and the explanation of the terms is based on the description or definition of the specification. Various embodiments of the present disclosure each have one or more of the technical features. Those skilled in the art can selectively implement some or all of the technical features of any embodiment, or selectively combine some or all of the technical features of these embodiments, where possible.

Please refer to FIG. 1A, which shows a functional block diagram of a memory device 100 in accordance with an embodiment of the present invention. The memory device 100 includes a memory array 110, a control circuit 120, and an operation voltage generating circuit 130. The memory array 110 includes a plurality of memory cells (not shown) arranged in an array. The control circuit 120 is coupled to the memory array 110 and the operating voltage generating circuit 130. Control circuit 120 controls various operations performed by memory array 110, such as, but not limited to, reading, writing, erasing, and the like. The control circuit 120 controls the output operating voltage generating circuit 130 to generate, for example, but not limited to, writing The voltage VPGM, the skip voltage VPASS, the bit line voltages VBL and VBL', and the memory string selection voltage VSSL are supplied to the memory array 110. The roles of the write voltage VPGM, the turn-on voltage VPASS, the bit line voltages VBL, VBL', and the memory string selection voltage VSSL will be described separately below.

Please refer to FIG. 1B, which shows a schematic diagram of a memory array 110 in accordance with an embodiment of the present invention. The memory array 110 includes a plurality of word lines WL and a plurality of bit lines BL. The memory cell is located at the intersection of the word line WL and the bit line BL.

In the embodiment of the present invention, the bit lines BL are divided into a plurality of bit line groups. For example, but not limited to, taking FIG. 1B as an example, according to the positions of the bit lines BL on the word line WL, the bit lines BL are divided into three bit line groups BLG1, BLG2 and BLG3. . Wherein, the bit line group BLG1 is located at the beginning of the word line WL, the bit line group BLG2 is located at the middle end of the word line WL, and the bit line group BLG3 is located at the end of the word line WL, where The voltage to the word line WL is received by the beginning of the word line WL, and is transferred to the middle end of the word line WL and the end of the word line WL. Therefore, the end of the word line WL is subjected to the most severe resistance-capacitance delay.

In addition, a switching element is disposed at each end of each of the bit lines BL to determine whether the block block is selected. For example, in the direction of FIG. 1B, one of the switching elements (for example, a MOS transistor) is located at the left end of the bit line BL, and the control end of the switching element (for example, the gate of the MOS transistor) is coupled to the ground selection. A ground selected line (GSL); and another switching element (for example, a MOS transistor) is located at the right end of the bit line BL, and the control end of the switching element is coupled to a string selected line SSL. That is to say, in the 1B picture, the word line WL and the bit The intersection of the line is the memory cell; the intersection of the ground selection signal line GSL and the bit line BL is a switching element (not a memory cell); the intersection of the memory string selection line SSL and the bit line BL is Switching element (not a memory cell).

Referring now to Figure 2, there is shown a signal waveform diagram in accordance with an embodiment of the present invention. In FIG. 2, the write voltage VPGM is applied to the selected word line WL, and the turn-on voltage VPASS is applied to the unselected word line WL, and the memory string selection voltage VSSL is applied to the memory string selection line SSL for pre-charging. The bit line voltage VBL is applied to the selected bit line to which the material 0 is written, and the bit line voltage VBL' is applied to the unselected bit line or to the selected bit line of the material 1.

In detail, when the write voltage VPGM transitions to a high level, the selected word line WL will be written. In the write operation, the level of the memory string selection voltage VSSL is changed from 0V to a high level for pre-charging, and then falls from the high level to the intermediate level (but not to 0V). The intermediate level of the memory string selection voltage VSSL satisfies: (1) allowing the voltage of 0V to be continuously supplied to the selected bit line BL of the write data 0 for writing; and (2) for the unselected bit line BL or the selected bit line to be written to the material 1 can cause the unselected bit line BL or the switching element of the selected bit line to be written to the material 1 to be turned off, so that the unselected bit line BL Or the gates of the plurality of transistors in the memory cells of the selected bit line of the data 1 are in a floating state, and when the skip voltage VPASS is pulled up, the memory strings may be Pulled up due to capacitive coupling effects.

The bit line voltage VBL is applied to the selected bit line BL to be written to the material 0. The bit line voltage VBL' is applied to the unselected bit line or the selected bit line BL to be written to the material 1. As shown in Figure 2, the bit line voltage VBL' will be pulled from the low level. The high to high level (for example, but not limited to, the voltage source VDD, whose value is, for example, 2.4V).

In the embodiment of the present invention, as shown in FIG. 2, in the high level period (T1) of the write voltage VPGM, different positions are applied depending on the position of the selected bit line BL to be written data 0 on the word line. The waveform of the bit line voltage VBL. In the T1 period, the closer to the bit line BL at the beginning of the word line WL, the bit line voltage VBL is pulled up to the high level earlier (the time when the bit line voltage VBL is turned to the high level is called "high level" State time"). Taking the grouping of FIG. 1B as an example, the bit line BL in the bit line group BLG1 is closest to the word line WL, so the bit line voltage of the selected bit line in the bit line group BLG1. VBL is first raised to the high level (please note that in the bit line group BLG1, some bit lines may be selected to write data 0, some bit lines may not be selected, and some bit lines may be selected as Write data 1); the bit line BL in the bit line group BLG2 is located at the middle end of the word line WL, so the bit line voltage VBL in the bit line group BLG2 is the second early high to high The bit line BL in the bit line group BLG3 is farthest from the beginning of the word line WL. Therefore, the bit line voltage VBL in the bit line group BLG3 is kept at a low level (0 V) in principle.

As is known, in a memory device, due to the resistance-capacitance delay effect of the word line, the memory cells near the beginning of the word line WL are applied with a high level of the write voltage VPGM (eg, but not limited The time at 20V) may be relatively long (for example but not limited to 10μs), so there is a faster writing speed. Conversely, the time at which the memory cells at the end of the word line WL are applied with the high level of the write voltage VPGM may be relatively short (eg, but not limited to 2-3 μs), so there is a slower write speed. . In a memory device, the greater the difference in writing speed between different memory cells, it may lead to basic writing. The wider the threshold voltage distribution, the worse the performance of the memory device.

Therefore, in the embodiment of the present invention, the individual high level of the individual bit line voltage VBL is adjusted according to the position of the bit line on the word line, so that the writing speed of the memory cell is uniform (that is, near the word line). The write memory speed of the memory cell at the end and the memory cell near the end of the word line are close to each other), and the basic write threshold voltage distribution can be narrowed to facilitate the performance of the memory device.

Since the writing speed of the memory cell is related to the tunneling oxide layer (Tunnel Oxide) across the voltage between the floating gate and the bit line voltage (the tunneling oxide layer voltage is equal to the floating gate voltage minus the bit line) Voltage). The greater the cross-pressure of the tunneling oxide layer, the faster the writing speed of the memory cell is, and vice versa.

Therefore, in the embodiment of the present invention, since the bit line of the memory cell near the beginning of the word line WL is pulled up to a high level earlier, the memory cell near the beginning of the word line WL can be lowered early. The tunneling oxide layer crosses the voltage, so that the writing speed of the memory cell near the beginning of the word line WL is lowered, so that the writing speeds of all the memory cells can be close to each other, and the influence of the RC delay is reduced.

FIG. 3A is a schematic view showing the waveform of the tunneling oxide layer across the pressure according to the embodiment of the present invention. As shown in FIG. 3A, in the embodiment of the present invention, since the bit line (that is, the bit line group BL1) of the memory cell near the beginning of the word line WL is pulled up to a high level earlier, The tunneling oxide layer crossing pressure of the memory cell near the beginning of the word line WL is lowered early, thereby slowing down the writing speed of the memory cell near the beginning of the word line WL. As is known, in the embodiment of the present invention, the writing speed has an integral area with respect to the tunneling oxide layer across the pressure versus time. Therefore, as can be seen from FIG. 3A, the bit line groups BLG1, BLG2 and The time-integrated area of the tunneling oxide layer of BLG3 is relatively close, that is, the writing speeds of the bit line groups BLG1, BLG2 and BLG3 are relatively close, and the basic write threshold voltage distribution can be narrowed to facilitate memory. The writing speed of the body device.

Figure 3B shows the basic write threshold voltage distribution in accordance with embodiments of the present invention and prior art techniques. As shown in FIG. 3B, the basic write threshold voltage distribution 310 of the embodiment of the present invention is narrower than the basic write threshold voltage distribution 320 of the prior art. Therefore, the performance of the memory device of the embodiment of the present invention can be improved.

In summary, in the above embodiment of the present invention, the bit line near the beginning of the word line WL is pulled up to the high level earlier, and the bit line located in the middle part of the word line WL is pulled up to the high level. And so on, and the bit line near the end of the word line WL is in principle kept at a low level (0V). The writing speeds of all the memory cells are made close to each other (that is, the writing speeds of the memory cells near the beginning of the word line and the memory cells near the end of the word line are close to each other), and the basic writing can be narrowed. The critical voltage distribution is entered to facilitate the performance of the memory device.

Referring now to Figure 4, there is shown a signal waveform diagram of another embodiment of the present invention. In FIG. 4, in the high level period of the write voltage VPGM, a different bit line voltage VBL is applied in accordance with the position of the selected bit line BL to which the material 0 is to be written. In the T1 period, the bit line BL closer to the beginning of the word line WL, the higher the bit level of the bit line voltage VBL is. Taking the grouping of FIG. 1B as an example, the bit line BL in the bit line group BLG1 is closest to the word line WL, so the high level of the bit line voltage VBL is the highest to slow the bit line group. The writing speed of the memory cell of BLG1 (the degree of mitigation is the greatest); the bit line BL in the bit line group BLG2 is located at the middle end of the word line WL, and the bit line voltage The high level of the VBL is the second highest to slow down the writing speed of the memory cell of the bit line group BLG2 (the second largest degree of mitigation); the bit line BL in the bit line group BLG3 is away from the word line The WL is the farthest from the beginning, so its bit line voltage VBL is kept at a low level (0V) in principle.

Therefore, in the embodiment of Fig. 4, the writing speed of the memory cell is made as uniform as possible (i.e., the memory cell near the beginning of the word line and the memory cell near the end of the word line). The input speeds are close to each other), and the basic write threshold voltage distribution can be narrowed to facilitate the performance of the memory device.

That is, in the embodiment of the present invention, the high level of the bit line of the memory cell near the beginning of the word line WL is the highest, so that the memory cell cell near the beginning of the word line WL can be reduced to the utmost extent. The tunnel oxide layer crosses the voltage (ie, reduces the charge that tunnels into the floating gate during the writing process), so that the writing speed of the memory cell near the beginning of the word line WL is lowered, so that all memory cells are written. The input speeds can be close to each other, reducing the effects of RC delay.

Similarly, with the waveform diagram of FIG. 4, the time integral area of the tunneling oxide layer crossing voltage of the bit line groups BLG1, BLG2 and BLG3 can be made relatively close, that is, the bit line groups BLG1, BLG2 Compared with the write speed of BLG3, the basic write threshold voltage distribution can be narrowed to facilitate the performance of the memory device.

In summary, in the embodiment of Fig. 4 of the present invention, the memory level of the middle portion of the word line WL is maximized by the highest level of the bit line of the memory cell near the beginning of the word line WL. The high level of the bit line of the cell is the second highest, and so on, so that the writing speed of all the memory cells is as uniform as possible (that is, the memory cell near the beginning of the word line and the end of the word line) The writing speed of the memory cells is close to each other), and the base can be narrowed This writes a critical voltage distribution to facilitate the performance of the memory device.

Referring now to Figure 5, there is shown a signal waveform diagram of another embodiment of the present invention. In Fig. 5, in the high level period of the write voltage VPGM, a waveform of a different bit line voltage VBL is applied in accordance with the position of the selected bit line BL to which the material 0 is to be written. During the T1 period, the bit line BL closer to the beginning of the word line WL has a higher high bit level of the bit line voltage VBL and is pulled to the high level at the earliest. Taking the grouping of FIG. 1B as an example, the bit line BL in the bit line group BLG1 is closest to the word line WL. Therefore, the bit line VLG has the highest bit level and the highest level. Pulled to a high level to slow down the write speed of the memory cell of the bit line group BLG1 (the degree of slowdown is the greatest); the bit line BL in the bit line group BLG2 is located at the middle end of the word line WL. Therefore, the high level of the bit line voltage VBL of the bit line group BLG2 is the second highest and the second time is pulled to the high level to slow down the writing speed of the memory cell of the bit line group BLG2 (slow down) The degree is the second largest; the bit line BL in the bit line group BLG3 is farthest from the beginning of the word line WL, so its bit line voltage VBL is kept at a low level (0 V) in principle.

Therefore, in the embodiment of Fig. 5, the writing speed of the memory cell is made as uniform as possible (i.e., the memory cell near the beginning of the word line and the memory cell near the end of the word line). The input speeds are close to each other), and the basic write threshold voltage distribution can be narrowed to facilitate the performance of the memory device.

That is, in the embodiment of Fig. 5 of the present invention, the highest level of the bit line near the beginning of the word line WL is the highest and the highest level is pulled to the highest level, so that the memory cell near the beginning of the word line WL can be reduced to the utmost extent. The tunneling oxide layer crosses the voltage, so that the writing speed of the memory cell near the beginning of the word line WL is lowered, so that all memory cells are written. Speeds can be close to each other, reducing the effects of RC delays.

Similarly, with the waveform diagram of FIG. 5, the time integral area of the tunneling oxide layer crossing voltage of the bit line groups BLG1, BLG2, and BLG3 can be relatively close, that is, the bit line groups BLG1, BLG2. Compared with the write speed of BLG3, the basic write threshold voltage distribution can be narrowed to facilitate the performance of the memory device.

In summary, in the embodiment of Fig. 5 of the present invention, the bit position of the bit line near the beginning of the word line WL is the highest and the first level is raised to the high level, and the bit located in the middle of the word line WL. The high level of the line is the second highest and the second is pulled high to the high level, and so on, so that the writing speed of all memory cells is uniform (that is, the memory cell near the beginning of the word line is close to The write speeds of the memory cells at the end of the word line are close to each other), and the basic write threshold voltage distribution can be narrowed to facilitate the performance of the memory device.

In addition, in other possible embodiments of the present invention, there may be multiple bit line grouping methods. For example, if the memory array includes 8k bit lines and divides the 8k bit lines into 4 groups, the grouping manner may be 2k-2k-2k-2k (each bit line group includes 2k bits) Line), or 4k-2k-1k-1k (the bit line group near the beginning of the word line includes 4k bit lines, ... the bit line group near the end of the word line includes 1k bit lines) 3k-1k-2k-2k (the bit line group near the beginning of the word line includes 3k bit lines, ... the bit line group near the end of the word line includes 2k bit lines) or other way . That is, each of the meta-line groups may include the same number of bit lines or include a different number of bit lines.

In addition, in other possible embodiments of the present invention, the number of bit line groups may be any number (even one bit line group may include one bit line), which is also within the spirit of the present case.

Additionally, the high level of bit line voltage VBL (applied to the selected bit line to which data 0 is to be written) can utilize any available existing bias source.

In addition, other possible embodiments of the present application can also be used for quick pass write (QPW). For example, for a selected bit line to which data 0 is to be written, the bit line voltage VBL can rise from Vqpw (eg, Vqpw = 0.2V to 1.2V) to VDD (when QPW is enabled).

In addition, the individual high levels of the bit line voltage VBL (applied to the selected bit line to be written to the data 0) of the bit line groups can be equally divided into VDD (that is, evenly distributed between VDD and 0V). (Assume that the highest level of the bit line voltage VBL is VDD). For example, assuming that VDD is 2.4V, the high level of the bit line voltage VBL of the bit line group BLG1 is 1.6V, and the high level of the bit line voltage VBL of the bit line group BLG2 is 1.6V/2= 0.8V, and the high level of the bit line voltage VBL of the bit line group BLG3 is 0V.

However, in another possible embodiment of the present invention, the individual high levels of the bit line voltage VBL (applied to the selected bit line to be written to the data 0) of the bit line groups may not be evenly divided by VDD (ie, Not evenly distributed between VDD and 0V) (assuming that the highest level of the bit line voltage VBL is VDD). For example, assuming that VDD is 2.4V, the high level of the bit line voltage VBL of the bit line group BLG1 is 1.6V, and the high level of the bit line voltage VBL of the bit line group BLG2 is 1.1V, and the bit is The high level of the bit line voltage VBL of the line group BLG3 is 0V.

In addition, the individual high levels of the bit line voltage VBL of the bit line groups may be between 0V and VDD, and may even be between 0.1V and 1.3V, or It is between 0V and the voltage that enables the memory string selection transistor (which is a MOS transistor) on the memory string selection line SSL to be completely transmitted into the cell string.

The above embodiments of the present invention can be applied to 2D (2D) NAND Flash Memory or 3D (3D) NAND flash memory. In addition, the foregoing embodiments of the present disclosure may apply a single level cell (SLC), a multi-level cell (MLC) memory, a triple-level cell (TLC), or a fourth-level cell (TLC). Layer storage unit (QLC, quad-level cell).

That is, in the above embodiments of the present invention, according to the position of the bit line in the byte group at the position of the word line, the high level and the transition state of the bit line voltage applied to the bit lines are adjusted to be high. The level of time is such that the writing speed of all memory cells is as uniform as possible (that is, the writing speeds of the memory cells near the beginning of the word line and the memory cells near the end of the word line are close to each other) . Therefore, the above three embodiments of the present invention can narrow the basic write threshold voltage distribution to facilitate the performance of the memory device.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

Claims (7)

A method of operating a memory device, the memory array of the memory device comprising a plurality of word lines and a plurality of bit lines, the method of operating the memory device comprising: applying a write voltage to the word lines At least one selected word line; and in a high level period of the write voltage, a plurality of selected bit lines in the bit lines are selected according to the bit lines in the bit lines Individual locations, applying different plurality of bit line voltages to the selected bit lines to be written to the material 0, wherein the first plurality of the selected bit lines of the data 0 are written Selecting a bit line and a second plurality of selected bit lines, wherein the first selected bit lines are closer to the end of the word lines than the second selected bit lines, and the write voltage During the high level period, a first bit line voltage and a second bit line voltage are respectively applied to the first and second selected bit lines, and the first bit line voltage is a high level is higher than a second high level of the second bit line voltage, and/or a first bit line voltage A high level transition time is earlier than a second high level transition time of the second bit line voltage. A method of operating a memory device, the memory array of the memory device comprising a plurality of word lines and a plurality of bit lines, the bit lines being divided into a plurality of individual positions according to the plurality of individual positions of the word lines a group of bit lines, the method of operating the memory device comprising: applying a write voltage to at least one selected word line of the word lines; Applying a different plurality of bit line voltages to the bit line groups during a high level period of the write voltage, wherein a first bit line group among the bit line groups Applying a first bit line voltage and a second bit line voltage to the second bit line group closer to the same end of the word lines, and during the high level period of the write voltage The first bit line group and the second bit line group, a first high level of the first bit line voltage is higher than a second highest level of the second bit line voltage, and/or a first high level transition time of the first bit line voltage is earlier than a second highest level transition time of the second bit line voltage. The method of operating a memory device according to claim 2, wherein each of the bit line groups includes the same number of bit lines. The method of operating a memory device according to claim 2, wherein each of the bit line groups includes a different number of bit lines. The method of operating a memory device according to claim 2, wherein the high level of the bit line voltages applied to the bit line groups during the high level period of the write voltage The quasi-uniform distribution is between a voltage source and a low level. The method of operating a memory device according to claim 2, wherein the high level of the bit line voltages applied to the bit line groups during the high level period of the write voltage The quasi-uniformity is not evenly distributed between a voltage source and a low level. A memory device includes: a memory array including a plurality of word lines and a plurality of bit lines; a control circuit coupled to the memory array; and an operating voltage generating circuit coupled to the memory An array and the control circuit, the operating voltage generating circuit generates a write voltage to the word lines of the memory array, wherein, under the control of the control circuit, during a high level of the write voltage, According to the plurality of selected bit lines of the bit lines in the bit lines being selected at a plurality of individual positions of the word lines, the operating voltage generating circuit applies different plurality of bit line voltages to be written Entering the selected bit lines of the material 0, wherein, for the one of the selected bit lines to which the material 0 is written, the first plurality of selected bit lines and the second plurality of selected bit lines, The first selected bit line is closer to the end of the word line than the second selected bit line, and during the high level of the write voltage, the operating voltage generating circuit respectively applies a First bit line voltage and a second bit line voltage The plurality of the plurality of first and second selected bit line, the first bit line of a first high level voltage higher than the second bit A second high level of the line voltage, and/or a first high level transition time of the first bit line voltage is earlier than a second highest level transition time of the second bit line voltage.