TWI637399B - Memory system and memory-control method with a programming status - Google Patents

Abstract

A memory system having a stylized state includes at least a first memory, at least a second memory, and a controller. Each of the at least one first memory has a plurality of memory regions to store data. Each of the at least one second memory has a plurality of memory regions for programming the material from the at least one first memory. The controller is coupled to the second memory for recording a stylized state of the data. When the at least one first memory or the at least one second memory is about to be used, checking whether the stylization is successful by querying the stylized state, and the at least one first memory stores the data until the stylization Checked as successful.

Description

Memory system and memory control method with stylized state

The present invention relates to a memory system and a memory control method including a stylized state, and more particularly to a stylized result of checking a memory system using a stylized state.

Memory devices and memory systems are widely used in various electronic devices. As far as the stylization of data is concerned, when staging data into a memory device, it is usually necessary to check the stylized results as soon as possible. However, checking the stylized results requires a long inspection time. Especially when performing a check of stylized results during the inspection, the controller or firmware of the electronic device may be occupied. The firmware or controller's functionality is then stopped or delayed until the stylized results are checked. Therefore, too much time is wasted and the performance of the electronic device is suddenly deteriorated.

Therefore, there is a need for an efficient and dynamically adjusted memory control method and to prevent sudden deterioration of the performance of an electronic device by using a stylized state.

An embodiment of the present invention provides a memory system having a stylized state, including at least a first memory, at least a second memory, and a controller. Each of the at least one first memory has a plurality of memory regions To store data. Each of the at least one second memory has a plurality of memory regions for programming the material from the at least one first memory. The controller is coupled to the second memory for recording a stylized state of the data. When the at least one first memory or the at least one second memory is about to be used, checking whether the stylization is successful by querying the stylized state, and the at least one first memory stores the data until the stylization Checked as successful.

An embodiment of the present invention provides a memory control method having a stylized state, including recording a stylized state of at least one first memory stylized to at least one second memory; when the at least one When the first memory or the at least one second memory is about to be used, checking whether the stylization is successful by querying the stylized state; and storing the data in the at least one first memory until the stylization is checked as successful .

10‧‧‧ memory system

100-10N‧‧‧ first memory

100A-10NA, 100B-10NB, 300A-30NA, 300B-30NB‧‧‧ memory area

200‧‧‧ controller

300-30N‧‧‧Second memory

1 is a schematic diagram showing a memory system according to an embodiment of the invention; FIGS. 2A and 2B are diagrams showing a stylization of a memory system according to an embodiment of the invention; FIG. 3A is a diagram showing A schematic diagram of the stylization of the sequential writing described in the foregoing; FIG. 3B is a schematic diagram showing the stylization of sequential writing according to an embodiment of the present invention; and FIG. 4A is a view showing the random writing described in the previous case. Schematic diagram of stylization; FIG. 4B is a schematic diagram showing stylization of random writing according to an embodiment of the invention; Figure 5 is a diagram showing a memory control method according to an embodiment of the present invention.

In order to make the objects, features and advantages of the present invention more comprehensible, the specific embodiments of the invention are set forth in the accompanying drawings. The intention is to illustrate the spirit of the invention and not to limit the scope of the invention, it being understood that the following embodiments can be implemented by software, hardware, firmware, or any combination of the above.

1 is a schematic diagram showing a memory system 10 in accordance with an embodiment of the present invention. The memory system 10 includes at least one first memory 100~10N, a controller 120, and at least one second memory 300~30N. For example, the first memory 100~10N is a random access memory (RAM), and the second memory 300~30N is a NAND memory. As shown in FIG. 1, each of the first memories 100 to 10N has a plurality of memory areas for storing data, and each of the memory areas may include a plurality of blocks. For example, the first memory 100 includes memory areas 100A and 100B for storing data, and the first memory 10N includes memory areas 10NA and 10NB for storing data. In addition, each of the at least one second memory 300~30N includes a plurality of memory regions, and the data from the first memory 100~10N is programmed, and each memory region includes a plurality of blocks. For example, the second memory 300 includes memory areas 300A and 300B to programmatic data, and the second memory 30N includes memory areas 30NA and 30NB to program the data. In another embodiment, the second memory 300~30N may be a different die of the memory device. Further, the controller 200 includes a firmware of the memory system 10. In another embodiment, the controller 200 can include A microcontroller and read-only memory (ROM) store the firmware code. The microcontroller can execute the firmware code to access or operate the second memory 300~30N. In detail, the controller 200 reads or writes the second memories 300 to 30N. It is noted that in some embodiments, the controller 200 further records, interrogates, and/or updates the stylized state of the second memory 300~30N.

As shown in FIG. 1, the controller 200 is coupled to the second memory 300~30N for recording the stylized state of the data. In detail, the data is stored in the first memory 100~10N and is programmed into the second memory 300~30N. It should be noted that when at least one first memory 100~10N or at least one second memory 300~30N is to be used, the stylized state is polled to check whether the stylization is successful. In other words, the stylized results are not checked immediately when the data is stylized into a memory device. The stylized result is checked just before the first memory 100~10N or the second memory 300~30N is used or accessed. Therefore, it is possible to prevent the lengthy inspection time caused by the stylized result from being immediately checked once the programmatic data is obtained, thereby obtaining better performance. In addition, the at least one first memory 100~10N stores data until the stylized result is successful. Therefore, when the stylization fails, the data stored in the first memory 100~10N can be a source of recovery or support stylization. For example, the data stored in the first memory 100~10N can be programmed again into the second memory 300~30N.

In one embodiment, the stylized state recorded by the controller 200 includes information about the data, information about the first memory 100~10N and the data being programmed from the memory area, and about the second memory 300~30N and the data. Information that is stylized into a memory area. Furthermore, the stylized state further includes information of at least one block of the second memory 300~30N of the data stylized destination. Again, when using The stylized state is updated when at least one first memory 100~10N or at least one second memory 300~30N or when the stylized state is polled. Once the data is programmed from the first memory 100~10N to the second memory 300~30N, the controller 200 records the stylized state. However, until at least one first memory 100~10N or at least one second memory 300~30N is used, the controller 200 checks the stylized result in a stylized state. Because at this stage, the controller 200 records the basic information about the stylization without checking or detecting, it takes only a short time to record the stylized state, and the memory system 10 can be prevented from being sacrificed.

2A and 2B are diagrams showing the stylization of the memory system 10 according to an embodiment of the present invention. On the one hand, as shown in FIG. 2A, the data DataW and MetaW are stored in the memory areas 100A and 100B of the first memory 100, and the data DataX and MetaX are stored in the memory areas 101A and 101B of the first memory 101, and the data DataY and MetaY are stored. The memory areas 102A and 102B are stored in the first memory 102, and the data DataZ and MetaZ are stored in the memory areas 103A and 103B of the first memory 103. On the other hand, the first memories 104, 105, 106, and 10N have no data to store. Then, the data DataW, ÐataX, DataY, and DataZ are respectively programmed into the memory areas 300A, 301A, 302A, and 30NA of the second memories 300, 301, 302, and 30N. At the same time, the memory areas 300B, 301B, 302B, and 30NB of the second memory 300, 301, 302, and 30N are still empty and are not stylized with any material. In detail, the memory areas 300A, 301A, 302A, and 30NA are buffer memories, and the memory areas 300B, 301B, 302B, and 30NB are cache memories. It should be noted that the data DataW, ÐataX, DataY and DataZ are respectively programmed into the second memory 300, 301, 302 and 30N, and the data DataW, ÐataX, DataY and DataZ is still stored in the first memory 100, 101, 102, and 103 until the stylization is checked as successful.

Then, as shown in FIG. 2B, the data DataA is stored in the memory area 104A and is programmed into the memory area 300A of the second memory 300, and the data DataB is stored in the memory area 105A and is programmed into the second memory 301. The memory area 301A, the data DataC is stored in the memory area 106A and is programmed into the memory area 302A of the second memory 302. The data DataD is stored in the memory area 10NA and is programmed into the memory area 30NA of the second memory 30N. . Further, the data DataW, ÐataX, DataY, and DataZ are transferred from the memory areas 300A, 301A, 302A, and 30NA to the memory areas 300B, 301B, 302B, and 30NB, respectively.

The details of the stylized state of the memory system 10 are shown in Table 1:

The stylized states shown in Table 1 correspond to the embodiments of Figs. 2A and 2B. According to the stylized state of Table 1, the memory areas 300A (buffer memory) and 300B (cache memory) of the second memory 300 store the data DataA and DataW stylized from the first memories 104 and 100. The memory areas 301A (buffer memory) and 301B (cache memory) of the second memory 301 store data DataB and DataX studded from the first memories 105 and 101. The memory areas 302A (buffer memory) and 302B (cache memory) of the second memory 302 store data DataC and DataY studded from the first memories 106 and 102. The memory area 30NA (buffer memory) and 30NB (cache memory) of the second memory 30N store data DataD and DataZ stylized from the first memories 10N and 103.

In one embodiment, when another data is about to be written to the at least one first memory 100~10N of the material stylized source, the stylized state is interrogated to check whether the stylization of the data is successful, and the other data is different from the data. . For example, another data DataT is different from the data DataW and is about to be written into the first memory 100. The controller 200 interrogates the stylized state to check if the stylization of the data is successful. If the stylization of the material is successful, another data DataT is written to the first memory 100, wherein the data DataW is previously programmed from the first memory 100. If the stylization of the material is unsuccessful, another data DataT will not be written to the first memory 100, and the first memory 100 continues to store the data DataW until the stylization of the data DataW is successful. It is important to note that the stylized state is updated as soon as the query is made.

However, the updated content of the stylized state of the memory system 10 is as shown in Table 2:

For example, since the data DataW is programmed to the memory area 300B (cache memory) is successful, Table 2 shows the updated stylized state. When the memory area 300B of the first memory 100 or the second memory 300 is about to be accessed or used, the controller 200 does not need to issue an instruction to check the state of the first memory 100 or the second memory 300. Therefore, the efficiency of the memory system 10 can be improved by instantly and dynamically updating the stylized state.

After recording and probing the stylized state, there are a number of ways to handle the stylized state based on the specifications and algorithms of the second memory 300~30N. In one embodiment, the stylized state of the cache memory (e.g., memory region 300B of second memory 300) is interrogated when the data is programmed into the cache memory. When the data is programmed into the buffer memory, the stylized state of the buffer memory (e.g., the memory area 300A of the second memory 300) is interrogated. In another embodiment shown in FIGS. 2A and 2B, the data DataW is programmed into the second memory 300, and then the data DataA is programmed into the second memory 300. When the latter data DataA is programmed to the same second memory 300 as the previous data DataW, the same In the block, you only need to query the stylized state of the cache. When the latter data is not programmed into the same second memory and the same block as the previous data, it is necessary to query the stylized state of both the cache memory and the buffer memory. In detail, both the cache memory and the buffer memory require more access time than just polling the cache. The memory control method of the present invention provides a dynamically adjustable seek method to handle stylized states, reduce access time, and improve efficiency. In another embodiment, when another piece of material is about to be written to the first memory that was not used, the stylized state will not be checked to save time.

In one embodiment, when the data is about to be read from at least one second memory 300~30N of the material stylized source, the stylized state is interrogated to check if the stylization of the data is successful. On the one hand, when the stylization of the data is successful, the data is stylized to at least one second memory 300~30N. On the other hand, when the stylization of the data is unsuccessful, the data of at least one second memory 300~30N to which the data is stylized is not read, and at least one first memory 100~10N of the data stylized source is still Save this information. Furthermore, since the data stored in the second memory 300 to 30N is about to be read, the buffered memory of the second memory 300 to 30N and the stylized state of the cache memory are interrogated.

Fig. 3A is a schematic diagram showing the stylization of the sequential writing described in the previous paragraph. As shown in FIG. 3A, the data DataW, ÐataX, DataY, and DataZ are sequentially written to the second memory (NAND) 300 to 303. After the firmware is sequentially written by the host transfer and NAND transfer data DataW, ÐataX, DataY and DataZ, it waits for a wait time T1, and once the write is completed or the program is completed, the stylized state is checked. To execute data DataA, ÐataB, DataC and DataD Write in order. Figure 3B is a diagram showing the stylization of sequential writing in accordance with an embodiment of the present invention. The firmware checks the stylized state before using the second memory 300~303, instead of checking the stylized state as soon as the write is completed or the program is completed. Therefore, the waiting time T2 shown in Fig. 3B is smaller than the waiting time T1 shown in Fig. 3A, and thus better performance is obtained.

Fig. 4A is a schematic diagram showing the stylization of random writing described in the foregoing, and Fig. 4B is a diagram showing the stylization of random writing according to an embodiment of the present invention. The data DataW, ÐataX, DataY and DataZ are randomly written into the second memory 300~303. As shown in Figures 4A and 4B, because the firmware checks the stylized state before using the second memory 300~303, instead of checking the stylized state immediately after the writing is completed or programmed, the 4B is checked. The waiting time T4 shown is smaller than the waiting time T3 shown in FIG. 4A.

Figure 5 is a diagram showing a memory control method according to an embodiment of the present invention. In step S500, the stylized state of the material stylized from the first memory to the second memory is recorded. Then, in step S502, when the first or second memory is about to be used, it is checked whether the stylization is successful by polling the stylized state. If the stylization is unsuccessful, step S504 is performed, and the first memory stores the data until the stylization is checked as successful. If the stylization is successful, step S506 is executed to update the stylized state. The detailed steps for recording, interrogating, and processing stylized states are as described above, so they are not described here.

The ordinal numbers in this specification and the scope of the patent application, such as "first", "second", "third", etc., have no sequential relationship with each other, and are only used to indicate that two are identical. Different components of the name. The term "coupled" as used in the specification of the present invention refers to various direct or indirect electrical connections. formula.

The present invention has been described above with reference to the preferred embodiments thereof, and is not intended to limit the scope of the present invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

Claims (18)

A memory system having a stylized state, comprising: a first memory for storing data; and a second memory different from the first memory for staging the first memory And a controller coupled to the second memory for recording the stylized state of the data from the first memory to the second memory, wherein the first memory or the first When the second memory is about to be used, it is checked whether the stylization is successful by interrogating the stylized state. A memory system having a stylized state as described in claim 1 wherein, when the stylization is unsuccessful, the first memory stores the data until the stylization is checked as successful. A memory system having a stylized state as described in claim 1 wherein the controller updates the stylized state when the stylization is successful. A memory system having a stylized state as described in claim 1, wherein the first memory includes a plurality of data regions, the second memory includes a plurality of data regions, and the stylized state includes Information about the data, information about the first memory and the data being stylized from the memory area, information about the second memory and the data being stylized into the memory area. A memory system having a stylized state as described in claim 1, wherein the second memory comprises a second buffer memory and a second cache memory. A memory system having a stylized state as described in claim 5 The controller uses a table to record the stylized state, and the table records the second buffer memory of the second memory and the data stored by the second cache. A memory system having a stylized state as described in claim 5, wherein the data is preferentially programmed into the second buffer memory and then programmed into the second cache memory. A memory system having a stylized state as described in claim 7 wherein the stylized state of the second cache memory is when the data is programmed to the second cache memory Being inquired. A memory system having a stylized state as described in claim 8 wherein the second cache memory and the second buffer memory are when the data is programmed into the second buffer memory. This stylized state will be queried. A memory control method having a stylized state, comprising: storing a data by a first memory; staging the data to a second memory different from the first memory, and recording from the first a memory stylized to a stylized state of the data of a second memory; and when the first memory or the second memory is about to be used, checking whether the stylization is by interrogating the stylized state success. A memory control method having a stylized state as described in claim 10, wherein when the stylization is unsuccessful, the data is stored by the first memory until the stylization is checked as successful. A memory having a stylized state as described in claim 10 A control method in which the stylized state is updated when the stylization is successful. A memory control method having a stylized state as described in claim 10, wherein the first memory includes a plurality of data regions, the second memory includes a plurality of data regions, and the stylized state includes Information about the data, information about the first memory and the data being stylized from the memory area, information about the second memory and the data being stylized into the memory area. A memory control method having a stylized state as described in claim 10, wherein the second memory comprises a second buffer memory and a second cache memory. The memory control method having a stylized state as described in claim 14 further includes: using a table to record the stylized state, and the form is to record the second buffer memory of the second memory. And the data stored by the second cache. A memory control method having a stylized state as described in claim 14 wherein the data is preferentially programmed into the second buffer memory and then programmed into the second cache memory. A memory control method having a stylized state as described in claim 16 wherein when the data is programmed into the second cache, the stylization of the second cache memory is interrogated. status. A memory control method having a stylized state as described in claim 17 wherein when the data is programmed into the second buffer memory, the second cache memory and the second buffer are interrogated. Stylization of memory status.