TWI636654B - Buck converter and control method thereof - Google Patents

Abstract

The invention discloses a buck converter and a control method thereof. The buck converter includes: a first power MOS field effect transistor and a second power MOS field effect transistor connected between the input voltage and ground; an output filter inductor and an output filter capacitor connected to the first power MOS field effect transistor Between the connection point of the crystal and the second power MOS field effect transistor and the ground; and a control device configured to sample the output voltage to generate an output voltage sampling signal, where the output voltage sampling signal is lower than the reference voltage and flows When the inductor current of the output filter inductor decreases to the lower limit threshold or is lower than the lower limit threshold, control the second power MOS field effect transistor from the on state to the off state and control the first power MOS field effect transistor from the off state Becomes the on state, and controls the first power MOS field effect transistor from the on state to the off state when the inductor current increases to the upper threshold, and controls the second power MOS field effect transistor from the off state to the on state status. The above-mentioned step-down converter has better stability, anti-interference ability and overload protection performance than the conventional step-down converter using a hysteresis mode.

Description

Buck converter and control method thereof

The present invention relates to the field of circuits, and more particularly, to a buck converter and a control method thereof.

In recent years, with the development of integrated circuits and information technology, battery-powered portable electronic products, such as mobile phones, cameras, and notebook computers, have become increasingly popular, which has increased the demand for high-performance power management chips. .

A DC-DC converter is one of the most widely used power management chips in portable electronic products. A buck converter is also called a buck converter. It is a DC-DC converter that converts a high input voltage to a low output voltage. It usually uses any one of two control modes, voltage mode and current mode, to realize the output voltage. control. In order to ensure the stability of the system, the buck converter needs to perform frequency compensation under these two control modes, which not only increases the design difficulty, but also increases the product cost. In addition, the buck converter's response to load current transient changes is relatively slow under these two control modes.

Hysteresis mode is the simplest control system suitable for a step-down converter and the fastest response to load current transient changes. It does not require frequency compensation and can respond to load current changes during the same switching cycle. . However, this control method is based on the pulse wave signal generated by comparing the sampled signal of the output voltage with the reference voltage to control the on-off of the power MOS (Metal-Oxide-Semiconductor) field-effect transistor in the buck converter. Off, making the anti-interference ability of the buck converter in this control mode very poor. For example, if the output voltage sampling signal or the reference voltage is subject to some kind of small noise interference, it will cause the power MOS field effect transistor in the buck converter to violently turn on and off, causing the output of the buck converter The voltage fluctuates sharply.

In addition, in a buck converter using a hysteresis mode, for high input voltage applications, it is often necessary to use a relatively large output filter inductor and output filter capacitor, which causes a serious lag in the phase of the output voltage of the buck converter. The phase lag will further make the system unstable; when an overload or short circuit occurs, the input voltage is relatively high and the output voltage is relatively low. The inductor current flowing through the output filter inductor rises much faster than its fall. Will make the current-limiting protection circuit ineffective, the inductor current will be out of control, which will cause damage to the output filter inductor and the entire chip.

In view of one or more of the problems described above, the present invention provides a novel buck converter and a control method thereof.

The step-down converter according to the embodiment of the present invention includes: a first power MOS field effect transistor and a second power MOS field effect transistor connected between an input voltage and a ground; an output filter inductor and an output filter capacitor connected to the first A connection point between a power MOS field effect transistor and a second power MOS field effect transistor and ground; and a control device configured to sample the output voltage to generate an output voltage sampling signal, which is low when the output voltage sampling signal is low When the reference voltage and the inductor current flowing through the output filter inductor decreases to a lower limit threshold value or is lower than the lower limit threshold value, the second power MOS field effect transistor is controlled from the on state to the off state and the first power MOS field effect is controlled The transistor changes from the off state to the on state, and controls the first power MOS field effect transistor from the on state to the off state and controls the second power MOS field effect transistor from when the inductor current increases to the upper threshold. The off state becomes the on state.

A control method for a step-down converter according to an embodiment of the present invention, wherein the step-down converter includes a first power MOS field effect transistor and a second power MOS field effect transistor connected between an input voltage and ground. And the output filter inductor and output filter capacitor connected between the connection point of the first power MOS field effect transistor and the second power MOS field effect transistor and ground, and the voltage between the two plates of the output filter capacitor is The control method of the output voltage of the step-down converter includes: sampling the output voltage to generate an output voltage sampling signal; and reducing the inductor current flowing through the output filter inductor when the output voltage sampling signal is lower than the reference voltage Control the second power MOS field effect transistor from the on state to the off state and control the first power MOS field effect transistor from the off state to the on state when the threshold is lower or lower than the lower threshold; and When it reaches the upper limit threshold, the first power MOS field effect transistor is controlled from the on state to the off state and the second power MOS field effect transistor is controlled from the off state to the on state.

The step-down converter and its control method according to the embodiments of the present invention have better stability and stronger anti-interference while maintaining the advantages of simple structure and fast response of the traditional step-down converter using hysteresis mode. Capacity, and more reliable overload protection.

L‧‧‧Output filter inductor

C‧‧‧output filter capacitor

R0‧‧‧Load resistance

R1, R2‧‧‧ output voltage divider network

Vo, V _OUT ‧‧‧ Output voltage

V _FB ‧‧‧ divided voltage

V _REF ‧‧‧ Reference Voltage

PWM‧‧‧Pulse Width Modulation

V _IN ‧‧‧ Input voltage

I _L ‧‧‧ inductor current

I _VALLEY ‧‧‧ Demagnetization current

t1‧‧‧Charging time

t2‧‧‧Discharge time

I _OUT ‧‧‧ Output current

I _PEAK ‧‧‧Peak current

S _H , S _L , P1, N1‧‧‧ Power MOS field effect transistor

Other features, objects, and advantages of the present invention will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features.

FIG. 1 shows a circuit topology of a conventional buck converter using a hysteresis mode; FIG. 2 shows a circuit topology of a buck converter according to an embodiment of the present invention; and FIG. 3 shows a circuit topology of FIG. Figure 4 shows the working waveform diagram of the buck converter under heavy load; Figure 4 shows the working waveform diagram of the buck converter shown in Figure 2 under light load; Figure 5 shows the second step Figure 6 shows the operating waveform of the buck converter under overload; Figure 6 shows the waveform of the inductor current in the buck converter shown in Figure 1; Figure 7 shows the second diagram A waveform diagram of the inductor current in the buck converter shown.

Features and exemplary embodiments of various aspects of the invention will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it is obvious to a person skilled in the art that the present invention can be implemented without the need for some of these specific details. The following description of the embodiments is merely for providing a better understanding of the present invention by showing examples of the present invention. The present invention is by no means limited to any specific configuration and algorithm proposed below, but rather without departing from the spirit of the present invention Any modifications, replacements, and improvements that cover elements, components, and algorithms are mentioned. In the drawings and the following description, well-known structures and techniques are not shown in order to avoid unnecessarily obscuring the present invention.

Figure 1 shows the circuit topology of a conventional buck converter using hysteresis. In the circuit topology shown in Figure 1, the power MOS field effect transistors _SH and _SL are implemented by power transistors; the output filter inductor L and the output filter capacitor C are the output filter inductor and output filter of the buck converter, respectively. Capacitor; R0 is the load resistance of the buck converter; R1 and R2 form the output divider network of the buck converter, which is used to set the output voltage Vo of the buck converter.

In the step-down converter shown in FIG. 1, the output voltage Vo is controlled by keeping the divided voltage V _FB of the output voltage Vo within a hysteresis window set by a reference voltage V _REF and a hysteresis comparator. Here, since the on and off of both the power MOS field effect transistors _SH and _SL are directly controlled based on the comparison result of the divided voltage V _FB and the reference voltage V _REF , the divided voltage V _FB and / or the reference voltage V _{REF is} affected by external noise to generate a small disturbance, which will cause the disturbance of both the power MOS field effect transistors _SH and _SL , resulting in jitter in the output voltage Vo of the buck converter. In addition, the phase shift produced by the output filter inductor L and the output filter capacitor C can also easily make the buck converter unstable.

In view of one or more problems of the conventional buck converter using hysteresis mode described in conjunction with FIG. 1, a novel buck converter is proposed. The buck converter according to the embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 2 shows a circuit topology of a buck converter according to an embodiment of the present invention. In the circuit topology shown in Figure 2, one end of the power MOS field effect transistor P1 is connected to the input voltage V _IN and the other end is connected to one end of the power MOS field effect transistor N1; One end is grounded; the connection point of the power MOS field effect transistor P1 and N1 is connected to one end of the output filter inductor L; the other end of the output filter inductor L is connected to one end of the output filter capacitor C; the other end of the output filter capacitor C is grounded; The voltage sampling network is used to sample the output voltage V _OUT of the buck converter. The output voltage sampling signal V _FB output by the output voltage sampling network can characterize the output voltage V _OUT of the buck converter. The signal V _FB is sent to the negative input of the comparator, and the reference voltage V _REF inside the buck converter is sent to the positive input of the comparator. The comparator generates a comparison result between the output voltage sampling signal V _FB and the reference voltage V _REF Characterization signal (for example, Pulse Width Modulation (PWM) signal); the upper tube sampling circuit is used to sample the current flowing through the power MOS field effect transistor P1, and the upper tube sampling circuit The sampled signal shown may be characterized by _L the size of the output filtering inductance L of inductor current I flows through the power MOS field effect transistor P1 is turned on; the current flowing through the power MOS field effect transistor N1 down tube sampling circuit for sampling, The down-sampling signal output by the down-sampling circuit can characterize the magnitude of the inductor current I _L flowing through the output filter inductor L when the power MOS field effect transistor N1 is on; the demagnetizing current control circuit is used for down-sampling based on the down-sampling circuit from the down-sampling circuit. Signal to control the end of the demagnetization process of the output filter inductor L; perform a logical AND operation on the demagnetization control signal output by the demagnetization current control circuit and the comparison result characterization signal output by the comparator to generate a first logic control signal; the first logic control signal Is sent to the S terminal of the RS trigger; the peak current control circuit is used to control the start of the demagnetization process of the output filter inductor L based on the up-sampling signal from the upper tube sampling circuit, and the peak control signal output by the peak current control circuit is sent Into the R terminal of the RS trigger; the RS trigger generates a second based on the first logic control signal and the peak control signal Control signal; logic circuit is used to generate the upper power MOS field effect transistor control signal and the lower power MOS field effect transistor for controlling the on and off of the power MOS field effect transistor P1 and N1 based on the second logic control signal Control signals; the upper tube driving circuit and the lower tube driving circuit drive the power MOS field effect transistors P1 and N1 on and off based on the upper power MOS field effect transistor control signal and the lower power MOS field effect transistor control signal, respectively. Here, immediately after the buck converter is powered on, the power MOS field effect transistor P1 is in an on state, and the power MOS field effect transistor N1 is in an off state.

Fig. 3 shows the operation waveform diagram of the buck converter shown in Fig. 2 under heavy load. As shown in FIG. 3, when the output voltage sampling signal V _{FB is} lower than the reference voltage V _REF and the demagnetizing current control circuit senses that the inductor current I _L flowing through the output filter inductor L is lower than the set demagnetizing current I _VALLEY , The logic circuit generates an upper power MOS field effect transistor control signal P1-ON that turns on the power MOS field effect transistor P1, and a lower power MOS field effect transistor control signal N1-OFF that turns off the power MOS field effect transistor N1. ; The upper tube driving circuit drives the power MOS field effect transistor P1 from the off state to the conductive state based on the upper power MOS field effect transistor control signal P1-ON; the lower tube driving circuit is based on the lower power MOS field effect transistor control signal N1 -OFF drives the power MOS field effect transistor N1 from the on state to the off state. Here, after the power MOS field effect transistor N1 changes from the on state to the off state and after a dead time delay, the power MOS field effect transistor P1 changes from the off state to the on state. At this time, the input voltage V _IN charges the output filter capacitor C via the output filter inductor L, the output voltage V _OUT gradually increases, the inductor current I _L flowing through the output filter inductor _L gradually increases, and the amount of increase in the inductor current I _L for:

Among them, t1 represents the charging time of the output filter capacitor C, that is, the on-time of the power MOS field effect transistor P1, and L represents the inductance of the output filter inductor L.

When the peak current control circuit senses that the inductor current I _L flowing through the output filter inductor L increases to a set peak current I _PEAK , the logic circuit generates an upper power MOS field effect power that turns off the power MOS field effect transistor P1. The crystal control signal P1-OFF and the lower power MOS field effect transistor control signal N1-ON that turns on the power MOS field effect transistor N1; the upper tube driving circuit drives power based on the upper power MOS field effect transistor control signal P1-OFF. The MOS field-effect transistor P1 changes from the on state to the off state; the down-tube driving circuit drives the power MOS field-effect transistor N1 from the off-state to the on-state based on the lower power MOS field-effect transistor control signal N1-ON. Here, after the power MOS field effect transistor P1 changes from the on state to the off state and after a dead time delay, the power MOS field effect transistor N1 changes from the off state to the on state. At this time, the output filter capacitor C is discharged through the output filter inductor L, the output voltage V _OUT gradually decreases, and the inductor current I _{L of the} flow filter inductor _L gradually decreases until the output voltage sampling signal V _{FB is} lower than the reference voltage V again. _{Up to REF} , the amount of decrease of the inductor current I _L is:

Among them, t2 represents the discharge time of the output filter capacitor C, that is, the power MOS field effect transistor N1 is the on-time, and L represents the inductance of the output filter inductor L.

In a balanced state, △ IL1 = △ IL2, and the average current of the inductor current I _L of the flow filter inductor L is equal to the output current I _OUT , that is, The switching frequency of the buck converter can be derived from the above relationship:

Fig. 4 shows the operation waveform diagram of the buck converter shown in Fig. 2 under the condition of light load. As shown in Figure 4, the buck converter operates in discontinuous mode due to the light load; when the output voltage sampling signal V _{FB is} lower than the reference voltage V _REF , the inductor current I _L flowing through the output filter inductor _L has dropped When it reaches zero and is lower than the set demagnetization current I _VALLEY , the logic circuit generates the upper power MOS field effect transistor control signal P1-ON that turns on the power MOS field effect transistor P1, and the power MOS field effect transistor N1 turns off Lower power MOS field effect transistor control signal N1-OFF; upper tube driving circuit drives power MOS field effect transistor P1 from off state to on state based on upper power MOS field effect transistor control signal P1-ON; lower tube drive The circuit drives the power MOS field effect transistor N1 from the on state to the off state based on the lower power MOS field effect transistor control signal N1-OFF. Here, after the power MOS field effect transistor N1 changes from the on state to the off state and after a dead time delay, the power MOS field effect transistor P1 changes from the off state to the on state. At this time, the input voltage V _IN charges the output filter capacitor C via the output filter inductor L, the output voltage V _OUT gradually increases, and the inductor current I _L flowing through the output filter inductor _L gradually increases.

When the peak current control circuit senses that the inductor current I _L flowing through the output filter inductor L increases to a set peak current I _PEAK , the logic circuit generates an upper power MOS field effect power that turns off the power MOS field effect transistor P1. The crystal control signal P1-OFF and the lower power MOS field effect transistor control signal N1-ON that turns on the power MOS field effect transistor N1; the upper tube driving circuit drives power based on the upper power MOS field effect transistor control signal P1-OFF. The MOS field-effect transistor P1 changes from the on state to the off state; the down-tube driving circuit drives the power MOS field-effect transistor N1 from the off-state to the on-state based on the lower power MOS field-effect transistor control signal N1-ON. Here, after the power MOS field effect transistor P1 changes from the on state to the off state and after a dead time delay, the power MOS field effect transistor N1 changes from the off state to the on state. At this time, the output filter capacitor C is discharged through the output filter inductor L, the output voltage V _OUT gradually decreases, and the inductor current IL of the flow filter inductor _L gradually decreases until it decreases to zero. When the output voltage sampling signal V _{FB is} lower than the reference voltage V _REF again, the above process is repeated.

From formula (1), the on-time of the power MOS field effect transistor P1 is:

From Equation (2), the on-time of the power MOS field effect transistor N1 is:

In the equilibrium state, the average current of the inductor current I _L of the flow filter inductor L is equal to the output current I _OUT , that is,

Among them, T represents the duty cycle of the buck converter.

From the above relationship, the switching frequency of the buck converter in discontinuous mode is:

FIG. 5 shows an operation waveform diagram of the buck converter shown in FIG. 2 under an overload condition. As shown in Figure 5, when the buck converter is overloaded, the output voltage sampling signal V _FB will always be lower than the reference voltage V _REF . The buck converter is only controlled by the peak current control circuit and the demagnetization current control circuit. At this time, whenever the inductor current _IL flowing through the output filter inductor L increases to the peak current I _PEAK , the logic circuit controls the power MOS field effect transistor P1 from the on-state to the off-state, and after a dead-band delay Control the power MOS field effect transistor N1 from the off state to the on state; whenever the inductor current I _L flowing through the output filter inductor _L decreases to the demagnetizing current I _VALLEY , the logic circuit controls the power MOS field effect transistor N1 from The on state becomes the off state, and the power MOS field effect transistor P1 is controlled to change from the off state to the on state after the dead time delay, and the above process is repeated. In this case, the inductor current _IL flowing through the output filter inductor L will always be between the peak current I _PEAK and the demagnetizing current I _VALLEY , the on time t1 of the power MOS field effect transistor P1, and the power MOS field effect power The on-times t2 of the crystal N1 are:

The switching frequency of the buck converter under overload is:

From the above analysis, it can be seen that the buck converter according to the embodiment of the present invention implements the hysteresis function by controlling the maximum and minimum values of the inductor current I _L flowing through the output filter inductor L, that is, in each switching cycle The inductor current I _L flowing through the output filter inductor L must be increased to a set upper threshold I _PEAK before the power MOS field effect transistor P1 is allowed to be turned off and the power MOS field effect transistor N1 is turned on, and the output filter inductor _L is allowed to flow. The inductor current I _{L of L} must be reduced to or less than the set lower limit threshold I _VALLEY , and the output voltage sampling signal V _FB must be lowered below the reference voltage V _REF before the power MOS field effect transistor P1 is allowed to turn on, and the above is repeated. process. In this way, the instantaneous dynamic interference signals of the output voltage and the reference voltage cannot affect the on and off of the power MOS field effect transistors P1 and N1. Therefore, the buck converter according to the embodiment of the present invention has a very strong anti-interference ability.

Generally, the rising slope of the inductor current I _L flowing through the output filter inductor L is proportional to the difference between the input voltage V _IN and the output voltage V _OUT , and the falling slope of the inductor current I _L flowing through the output filter inductor L is proportional to Output voltage V _OUT .

FIG. 6 shows a waveform diagram of an inductor current in the buck converter shown in FIG. 1. As shown in Figure 6, in the step-down converter shown in Figure 1, when overload or output short circuit occurs, the increase of the inductor current I _L flowing through the output filter inductor L in each duty cycle will be greater than the drop Amount, the inductor current will accumulate. Even if the current-limit protection function is implemented inside the buck converter shown in Figure 1, the current-limit protection function can no longer provide protection. The inductor current I _L flowing through the output filter inductor L is out of control. The output filter inductor L and the chip will be damaged soon.

FIG. 7 shows a waveform diagram of an inductor current in the buck converter shown in FIG. 2. The step-down converter according to the embodiment of the present invention can well solve the problem of inductor current accumulation during overload or output short circuit. As shown in Figure 7, even during the minimum on-time, the rising slope of the inductor current is too fast, so that the inductor current has increased above the upper threshold I _PEAK ; however, no matter how small the falling slope of the inductor current is, the demagnetizing current is controlled. The circuit will force the inductor current to decrease to the lower threshold I _VALLEY before the next cycle is allowed to start, so the amount of drop in the inductor current in each working cycle must be equal to the amount of increase, and there will be no accumulation phenomenon, making the entire buck conversion The device has more reliable overload protection capabilities.

In summary, the step-down converter according to the embodiment of the present invention introduces a peak current control circuit and a demagnetization current control circuit on the basis of a traditional step-down comparator using a hysteresis mode, and controls the power MOS field together with the hysteresis comparator. The conduction and closing of the effect transistor, while maintaining the advantages of simple structure and fast response of the traditional buck converter using hysteresis mode, it has better stability, stronger anti-interference ability, and more reliable Overload protection performance.

The present invention may be implemented in other specific forms without departing from the spirit and essential characteristics thereof. For example, the algorithms described in particular embodiments may be modified without the system architecture departing from the basic spirit of the invention. Therefore, the current embodiment is seen in all aspects The scope of the present invention is defined by the scope of the appended patent application rather than the above description, and all changes that fall within the meaning and scope of equivalents of the patent application scope are included in the scope of the present invention. Within the scope of the invention.

Claims (5)

A buck converter includes: a first power MOS field effect transistor and a second power MOS field effect transistor connected between an input voltage and ground; an output filter inductor and an output filter capacitor connected to the first power Between the connection point of the MOS field effect transistor and the second power MOS field effect transistor and ground, wherein the voltage between the two plates of the output filter capacitor is the output voltage of the buck converter And a control device configured to sample the output voltage to generate an output voltage sampling signal, where the output current sampling signal is lower than a reference voltage and an inductor current flowing through the output filter inductor is reduced to a lower limit When the threshold value is lower than the lower threshold value, controlling the second power MOS field effect transistor from an on state to an off state and controlling the first power MOS field effect transistor from an off state to an on state, When the inductor current increases to an upper threshold, control the first power MOS field effect transistor from an on state to an off state and control the second power MOS field effect transistor from an off state On state, and sampling the current flowing through the first power MOS field effect transistor or the second power MOS field effect transistor, where the first power MOS field effect transistor or The magnitude of the current of the second power MOS field effect transistor characterizes the magnitude of the inductor current; wherein the control device includes: an upper tube sampling circuit configured to convect a current flowing through the first power MOS field effect transistor. The current is sampled to generate a first sampling signal. The peak current control circuit is configured to determine whether the inductor current increases to the upper limit threshold based on the first sampling signal, and when the inductor current increases to the When the upper limit threshold value is controlled, the first power MOS field effect transistor is changed from an on state to an off state, and the second power MOS field effect transistor is controlled from an off state to an on state. The step-down converter according to item 1 of the scope of patent application, wherein the control device includes: a lower tube sampling circuit configured to sample a current flowing through the second power MOS field effect transistor to generate A second sampling signal; a demagnetizing current control circuit configured to determine, based on the second sampling signal, whether the inductor current is lower than or equal to the lower limit threshold, and when the output voltage sampling signal is lower than the reference voltage, And when the inductor current is lower than or equal to the lower limit threshold, controlling the second power MOS field effect transistor from the on state to the off state and controlling the first power MOS field effect transistor from the off state Is on. The step-down converter according to item 2 of the scope of patent application, wherein the control device further includes: an output voltage sampling network configured to sample the output voltage to generate the output voltage sampling signal; The comparator is configured to compare the output voltage sampling signal with the reference voltage, wherein the comparator determines that the output voltage sampling signal is lower than the reference voltage, and the demagnetization current control circuit determines When the inductor current is less than or equal to the lower limit threshold, the comparison result characterization signal output by the comparator and the demagnetization control signal output by the demagnetization current control signal jointly control the second power MOS field effect transistor to turn on. The state changes to the off state and controls the first power MOS field effect transistor from the off state to the on state. A control method for a step-down converter, wherein the step-down converter includes a first power MOS field effect transistor and a second power MOS field effect transistor connected between an input voltage and ground, and is connected to An output filter inductor and an output filter capacitor between a connection point of the first power MOS field effect transistor and the second power MOS field effect transistor and ground, and between two plates of the output filter capacitor The voltage is the output voltage of the step-down converter, and the control method includes the following steps: sampling the output voltage to generate an output voltage sampling signal; where the output voltage sampling signal is lower than a reference voltage and flows through When the inductor current of the output filter inductor decreases to a lower limit threshold value or is lower than the lower limit threshold value, controlling the second power MOS field effect transistor from an on state to an off state and controlling the first power MOS field effect The transistor is changed from the off state to the on state; when the inductor current increases to an upper threshold, controlling the first power MOS field effect transistor from the on state to the off state and controlling the The two power MOS field effect transistors change from an off state to an on state; a current flowing through the first power MOS field effect transistor or the second power MOS field effect transistor is sampled and flows through the first The magnitude of the current of the power MOS field effect transistor or the second power MOS field effect transistor characterizes the magnitude of the inductor current; the current flowing through the first power MOS field effect transistor is sampled to generate a first A sampling signal; determining whether the inductor current increases to the upper threshold value based on the first sampling signal; and controlling the first power MOS field effect transistor when the inductor current increases to the upper threshold value Changing from the on state to the off state and controlling the second power MOS field effect transistor from the off state to the on state. The control method according to item 4 of the scope of patent application, further comprising the steps of: sampling a current flowing through the second power MOS field effect transistor to generate a second sampling signal; and judging based on the second sampling signal Whether the inductor current is lower than or equal to the lower threshold; when the output voltage sampling signal is lower than the reference voltage and the inductor current is lower than or equal to the lower threshold, controlling the second power MOS The field effect transistor changes from an on state to an off state and controls the first power MOS field effect transistor from an off state to an on state.