TWI632644B - Intergrated circuit structure - Google Patents

Abstract

An integrated circuit structure includes an active area, a first top metal pattern, a second top metal pattern, a first metal pattern stack, a second metal pattern stack, a first transistor, and a second transistor. The active region is formed on a substrate. The first top metal pattern is electrically connected to the active area. The second top metal pattern is electrically connected to the active region, and is formed in the same metal layer as the first top metal pattern. The first metal pattern stack includes stacked K-layer first metal patterns. The second metal pattern stack includes stacked K-layer second metal patterns. A first transistor is formed on the substrate, and the first transistor is electrically connected to the first top metal pattern via the first metal pattern stack to electrically connect the active region via the first top gold pattern. A second transistor is adjacent to the first transistor, and the second transistor is electrically connected to the second top metal pattern through the second metal pattern stack to electrically connect the active region through the second top metal layer. .

Description

Integrated circuit structure

The invention relates to an integrated circuit structure.

As the size of integrated circuits shrinks, the impact of semiconductor manufacturing processes on the characteristics of electronic components becomes increasingly apparent.

For example, bandgap voltage is an important reference voltage source for integrated circuits. The bandgap voltage can be provided by a typical bandgap reference circuit, which usually includes an operational amplifier. However, the characteristics of the operational amplifier are often affected by the semiconductor process, which causes the output voltage of the operational amplifier to shift, which is quite unfavorable to the circuit designer.

Therefore, how to propose an integrated circuit structure to effectively reduce the influence of the semiconductor manufacturing process on the characteristics of circuit components is one of the topics that the industry is currently working on.

The invention relates to an integrated circuit structure. In the proposed integrated circuit structure, different transistors will be electrically connected to the active area through the same number of metal layers. By improving the spatial symmetry of the overall metal layout, The effects of process factors (such as metal etching) on different transistors can be uniformized, and the possibility of component mismatch is reduced.

According to an aspect of the present invention, an integrated circuit structure is provided, which includes an active area, a first top metal pattern, a second top metal pattern, a first metal pattern stack, a second metal pattern stack, a first transistor, and a second Transistor. The active region is formed on a substrate. The first top metal pattern is electrically connected to the active area. The second top metal pattern is electrically connected to the active region, and is formed in the same metal layer as the first top metal pattern. The first metal pattern stack includes stacked K-layer first metal patterns. The second metal pattern stack includes stacked K-layer second metal patterns. A first transistor is formed on the substrate, and the first transistor is electrically connected to the first top metal pattern via the first metal pattern stack to electrically connect the active region via the first top gold pattern. A second transistor is adjacent to the first transistor, and the second transistor is electrically connected to the second top metal pattern through the second metal pattern stack to electrically connect the active region through the second top metal layer. .

In order to have a better understanding of the above and other aspects of the present invention, preferred embodiments are described below in detail with the accompanying drawings, as follows:

100‧‧‧Integrated Circuit Structure

OD‧‧‧active zone

Ptop1‧‧‧First Top Metal Pattern

Ptop2‧‧‧Second Top Metal Pattern

STA1‧‧‧The first metal pattern stack

STA2‧‧‧Second metal pattern stacking

T1‧‧‧First transistor

T2‧‧‧Second transistor

M1‧‧‧First metal layer

M2‧‧‧Second metal layer

M3‧‧‧ Third metal layer

M4‧‧‧ Fourth metal layer

P11, P21, P31‧‧‧First metal pattern

P12, P22, P32‧‧‧Second metal pattern

CP‧‧‧ connection point

402‧‧‧ Operation Amplifier

404‧‧‧Band Gap Reference Circuit

in1, in2‧‧‧ input voltage

ref‧‧‧ Bandgap Reference Voltage

FIG. 1 is a schematic cross-sectional view of a integrated circuit structure according to an embodiment of the present invention.

FIG. 2 is a schematic top view of the integrated circuit structure according to an embodiment of the present invention.

3a to 3e are schematic diagrams showing various configurations of the first transistor T1 and the second transistor T2 on the substrate.

FIG. 4 is a schematic diagram of an operational amplifier to which the integrated circuit structure of the embodiment of the present invention is applied.

FIG. 5A shows an output voltage distribution diagram of a conventional circuit element.

FIG. 5B shows an output voltage distribution diagram of a circuit element implemented according to the integrated circuit structure of the present invention.

Herein, some embodiments of the present disclosure are described in detail with reference to the attached drawings, but not all embodiments are shown in the drawings. In fact, these inventions can use many different variations and are not limited to the embodiments herein. In contrast, this disclosure provides these embodiments to meet the legal requirements of the application. The same reference symbols are used in the drawings to identify the same or similar elements.

FIG. 1 is a schematic cross-sectional view of an integrated circuit structure 100 according to an embodiment of the present invention.

The integrated circuit structure 100 includes an active region OD, a first top metal pattern Ptop1, a second top metal pattern Ptop2, a first metal pattern stack STA1, a second metal pattern stack STA2, a first transistor T1, and a second transistor T2. The first transistor T1 and the second transistor T2 are, for example, metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET).

It should be noted that although the first transistor T1 and the second transistor T2 in FIG. 1 are represented by NMOS, the present invention does not limit the transistor types of the first transistor T1 and the second transistor T2. Depending on the implementation circuit, the first transistor T1 and the second transistor T2 can be both N-type transistors (such as NMOS), or both P-type transistors (such as PMOS), or both can be N-type transistors The other is a P-type transistor.

The active region OD is formed on a substrate (not shown). The active region OD includes, for example, one or more active elements formed on a substrate, and the first and second transistors T1 and T2 control signals and / or power signals can be provided through a metal conductive path. The first and second transistors T1 and T2 may be electrically connected to two separate areas in the active area OD, respectively, or may be electrically connected to the same area in the active area OD, depending on the actual circuit layout design.

The first top metal pattern Ptop1 is electrically connected to the active region OD. For example, the first top metal pattern Ptop1 may be connected down to the active region OD on the substrate through one or more electrically connected metal patterns (not shown). In the example of FIG. 1, the first top metal pattern Ptop1 is located on the fourth metal layer M4.

The second top metal pattern Ptop2 is electrically connected to the active region OD, and is formed in the same metal layer as the first top metal pattern Ptop1, such as a fourth metal layer M4. Similarly, the second top metal pattern Ptop2 can be connected down to the active region OD on the substrate through one or more layers of electrically connected metal patterns (not shown).

The first metal pattern stack STA1 includes stacked K (K is a positive integer) layers of the first metal pattern. K can be any positive integer, depending on the actual circuit layout. In the example in Figure 1, K is equal to 3, which is the first metal pattern stack STA1. The first metal pattern P11 is located in the first metal layer M1, the first metal pattern P21 is located in the second metal layer M2, and the first metal pattern P31 is located in the third metal layer M3.

Similarly, the second metal pattern stack STA2 includes stacked K-layer second metal patterns. As shown in FIG. 1, the second metal pattern stack STA2 includes a second metal pattern P12 located on the first metal layer M1, a second metal pattern P22 located on the second metal layer M2, and a second metal pattern P22 located on the third metal layer M3. Second metal pattern P32.

The first transistor T1 is formed on a substrate. The first transistor T1 may be electrically connected to the first top metal pattern Ptop1 via the first metal pattern stack STA1, so as to be electrically connected to the active region OD via the first top gold pattern Ptop1. As shown in Figure 1, the first metal pattern stack STA1 is electrically connected between the first top metal pattern Ptop1 and the gate of the first transistor T1, and the first metal patterns P11 ~ P31 of different layers are connected through the connection point. The CPs are electrically connected to form a metal conduction path from the gate of the first transistor T1 to the first top metal pattern Ptop1, thereby electrically connecting the gate of the first transistor T1 to the active region OD.

Except through the first top metal pattern Ptop1, each of the first metal patterns P11 ~ P31 in the first metal pattern stack STA1 cannot be electrically connected to the active area OD through other paths. Therefore, the gate of the first transistor T1 can be electrically connected to the active region OD only after a metal conductive path connected to the first top metal pattern Ptop1 is established.

The second transistor T2 is adjacent to the first transistor T1, and the second transistor T2 is electrically connected to the second top metal pattern through the second metal pattern stack STA2. Ptop2 is electrically connected to the active region OD through the second top metal layer Ptop2. As shown in Figure 2, the second metal pattern stack STA2 is electrically connected between the second top metal pattern Ptop2 and the gate of the second transistor T2, and the second metal patterns P12 ~ P32 of different layers pass through the connection point CP. Electrically connected to form a metal conduction path from the gate of the second transistor T2 to the second top metal layer Ptop2, thereby electrically connecting the gate of the second transistor T2 to the active region OD.

Similarly, except for the second top metal pattern Ptop2, each of the second metal patterns P12 ~ P32 in the second metal pattern stack STA2 cannot be electrically connected to the active area OD through other paths. Therefore, the gate of the second transistor T1 can be electrically connected to the active region OD only after a metal conductive path connected to the second top metal pattern Ptop2 is established.

In the above manner, the first transistor T1 and the second transistor T2 are forcibly configured to be electrically connected to the active region OD in the same metal layer (such as M4). For example, if the gate electrode of the first transistor T1 can be electrically connected to the active region OD through other metal patterns of the second metal layer M2, the second transistor T2 cannot be charged until the fourth metal layer M4. To the active region OD, the gate of the first transistor T1 must be prevented from being electrically connected to the active region OD in the second metal layer M2, and the first transistor T1 must first pass through the first metal pattern. The metal conduction path established by the stacked STA1 can be electrically connected to the active region OD only after being electrically connected to the fourth metal layer M4.

The study found that the above configuration can effectively avoid the occurrence of component mismatch. Further, in the semiconductor process, the metal pattern of each metal layer may be It needs to be achieved by plasma etching. However, etching a metal layer with plasma often affects the transistor that is electrically connected to the metal layer, and changes the characteristics of the transistor's components (such as threshold voltage (Vt)). Offset), so for different transistors, if the metal conductive path electrically connected to their gates has a similar metal pattern configuration, it means that the degree of influence of the etching process on these transistors is closer. The element characteristics of the transistor change due to the etching process, but because the amount of change in the element characteristics between different transistors is almost the same, the overall is still matched. Taking the first transistor T1 and the second transistor T2 respectively coupled to a negative input terminal and a positive input terminal of an operational amplifier as an example, if the first transistor T1 and the second transistor T2 are matched, the positive transistor T1 and the second transistor T2 can be avoided. The input offset voltage is generated between the negative input terminals, and this characteristic is quite advantageous for the band gap reference circuit using the operational amplifier.

FIG. 2 is a schematic top view of the integrated circuit structure 100 according to an embodiment of the present invention. In the example of FIG. 2, the first metal pattern stack STA1 and the second metal pattern stack STA2 are symmetrically arranged with the central axis CL between the first transistor T1 and the second transistor T2 as a symmetry axis. That is, the first metal pattern in the first metal pattern stack STA1 at the i (= 1, 2, 3) metal layer and the second metal pattern stack STA2 in the i (= 1, 2) at the same layer. 3) The second metal pattern of the metal layer is symmetrically arranged with the central axis CL between the first transistor T1 and the second transistor T2 as a symmetry axis.

As shown in FIG. 2, the first metal pattern P11 on the first metal layer M1 and the second metal pattern P12 on the same metal layer have substantially the same shape and configuration; the first metal pattern P12 on the second metal layer M2 A metal pattern P21 is in phase The second metal pattern P22 of the same metal layer has substantially the same shape and configuration; and the first metal pattern P31 of the third metal layer M3 and the second metal pattern P32 of the same metal layer have substantially the same shape. With configuration.

In one embodiment, the metal patterns in the first and second metal pattern stacks STA1 and STA2 may be required to have substantially the same area and / or shape.

For example, if the first metal pattern in the i-th metal layer in the first metal pattern stack STA1 has a first area, and the second metal pattern in the i-th metal layer in the second metal pattern stack STA2 has a first area Two areas can be designed so that the first area and the second area are substantially the same, that is, the difference between the two areas is less than a limit. This limit can be based on different actual circuit design requirements.

On the one hand, if the first metal pattern in the i-th metal layer in the first metal pattern stack STA1 has a first shape (such as a rectangle), and the second metal pattern in the i-th metal layer in the second metal pattern stack STA2 has A second shape can be designed so that the first shape is substantially the same as the second shape to further improve the spatial symmetry of the metal layout.

It can be understood that the circuit structure shown in Figs. 1 and 2 is only used to explain the technical features of the present invention, and not intended to limit the present invention. Such as the number of metal layers, the shape, size, and configuration of metal patterns, etc., can vary depending on the actual circuit design. It is within the spirit of the present invention that the gates of two adjacent transistors are configured to be electrically connected to the active region in the same metal layer.

Figures 3a to 3e show the first transistor T1 and the second transistor T2 Schematic diagram of various configurations on the substrate. In these examples, the first transistor T1 and the second transistor T2 are arranged symmetrically on the substrate in a common centroid. At this time, the first metal pattern stack STA1 and the second metal pattern stack STA2 corresponding to the first transistor T1 and the second transistor T2 may also be arranged in a symmetry manner with a common centroid, for example.

FIG. 4 is a schematic diagram of an operational amplifier 402 to which the integrated circuit structure of the embodiment of the present invention is applied. The integrated circuit structure includes a first transistor T1 and a second transistor T2, which are respectively coupled to a negative input terminal and a positive input terminal of the operational amplifier 402. The operational amplifier 402 can be used as a voltage output stage in the bandgap reference circuit 404, for example, and can output a stable bandgap reference voltage ref in response to the input voltages in1 and in2. The input voltage in1 is, for example, a voltage having a positive temperature coefficient (or a negative temperature coefficient), and the input voltage in2 is, for example, a voltage having a negative temperature coefficient (or a positive temperature coefficient), so as to obtain a band gap reference voltage ref near a zero temperature coefficient.

Because the first transistor T1 and the second transistor T2 are electrically connected to the active region OD in the same metal layer (such as the fourth metal layer M4), and the metal conduction path connected to the top metal pattern includes a substantially similar The metal pattern is configured, so the difference between the effect of the metal etching process on the first transistor T1 and the second transistor T2 is not large, so that the device characteristics of the first transistor T1 and the second transistor T2 can still be matched. In this way, the input offset voltage generated between the two input terminals of the operational amplifier 402 can be effectively avoided / reduced, thereby providing a more stable and accurate band gap reference voltage ref.

FIG. 5A shows an output voltage distribution diagram of a conventional circuit element. The circuit element described herein refers to, for example, a band gap reference circuit, which includes a first transistor and a second transistor which are electrically connected to the active region in different metal layers, respectively, which are respectively coupled to the operation at the voltage output stage. Two inputs of the amplifier. It can be seen from Figure 5A that the output voltages of the same circuit components implemented on the same wafer may still have considerable differences. Although the output voltages of most circuit components are concentrated between 2.65V to 2.75V, they are still The output voltage of a considerable proportion of circuit elements falls between 2.8V and 3.1V.

FIG. 5B shows an output voltage distribution diagram of a circuit element implemented according to the integrated circuit structure of the present invention. The circuit element described herein refers to, for example, a bandgap reference circuit, which includes a first transistor and a second transistor electrically connected to the active region in the same metal layer, which are respectively coupled to an operational amplifier at a voltage output stage. Two inputs. It can be seen from FIG. 5B that the output voltages of the same circuit elements implemented on the same wafer exhibit a concentrated Gaussian distribution, and the output voltage shift is only about ± 0.06V.

In summary, according to the integrated circuit structure proposed by the present invention, different transistors will be connected to the same metal layer first, and then electrically connected to the active area. By improving the spatial symmetry of the overall metal layout, the effects of process factors (such as metal etching) on different transistors can be effectively uniformed, thereby reducing the possibility of component mismatch.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims (6)

An integrated circuit structure includes: an active region formed on a substrate; a first top metal pattern electrically connected to the active region; a second top metal pattern electrically connected to the active region and connected to the first The top metal pattern is formed on the same metal layer; a first metal pattern stack is formed by the first metal pattern of K layers stacked and electrically connected; a second metal pattern is stacked by the K layer second and electrically connected Consisting of a metal pattern; a first transistor formed on the substrate, the first transistor being electrically connected to the first top metal pattern via the first metal pattern stack, and only allowing the first metal pattern to be stacked and An electrical path formed by the first top metal pattern is electrically connected to the active region; and a second transistor is adjacent to the first transistor, and the second transistor is electrically connected to the second transistor via the second metal pattern stack. The second top metal pattern is only allowed to be electrically connected to the active area via an electrical path formed by the second metal pattern stack and the second top metal pattern. According to the integrated circuit structure described in item 1 of the scope of patent application, wherein the first metal pattern in the i-th metal layer in the first metal pattern stack has a first area, and the first metal pattern in the second metal pattern stack has a first area. The second metal pattern of the i metal layer has a second area, and the difference between the first area and the second area is less than a limit. According to the integrated circuit structure described in item 1 of the patent application scope, wherein the first metal pattern in the i-th metal layer in the first metal pattern stack has a first shape, and the first metal pattern in the second metal pattern stack The second metal pattern of the i metal layer has a second shape, and the first shape is the same as the second shape. The integrated circuit structure described in item 1 of the scope of patent application, wherein the first metal pattern located in the i-th metal layer in the first metal pattern stack and the first metal pattern located in the i-th metal layer in the second metal pattern stack The two metal patterns are symmetrically arranged with the central axis between the first transistor and the second transistor as a symmetry axis. According to the integrated circuit structure described in item 1 of the patent application scope, wherein the first transistor and the second transistor are respectively coupled to a negative input terminal and a positive input terminal of an operational amplifier. The integrated circuit structure described in item 5 of the scope of the patent application, wherein the operational amplifier is configured as a voltage output stage of a band gap reference circuit.