TWI629690B - Method for accessing flash memory module and associated flash memory controller and memory device - Google Patents

Abstract

The invention discloses a method for accessing a flash memory module, wherein the flash memory module is a stereo flash memory module including a plurality of flash memory chips, each flash memory The body wafer includes a plurality of blocks, each of the blocks includes a plurality of data pages; and the method includes: planning the plurality of flash memory chips such that the plurality of flash memory chips have at least a first a super block and at least one second super block; and assigning the at least one second super block to store a plurality of sets of temporary codes encoded in a process of writing data to the at least one first super block Sex check code.

Description

Method for accessing flash memory module and related flash memory controller and memory device

The present invention relates to flash memory, and more particularly to a method of accessing a flash memory module and related flash memory controllers and memory devices.

In order to make the flash memory have higher density and larger capacity, the flash memory process is also moving toward stereoscopic development, and several different stereo NAND type flash memories (3D NAND-type) are produced. Flash). In the stereo NAND type flash memory, due to the difference in the overall structure and the change of the position of the floating gate, there are some problems in the writing and reading of the data compared with the conventional planar NAND type flash memory. . For example, in some stereo NAND type flash memories, a plurality of word lines are defined as a word line group, and the word line groups have a part of a control circuit together, and further Resulting in the failure of the floating gate transistor when the data is written to one of the character line groups of the character line group (write failure), which will cause the data of the floating gate crystal on the other character lines of the character line group. An error occurs; in addition, if a character line in the character line group is disconnected or short-circuited, the data of the floating gate crystal that affects other character lines of the character line group may be incorrect. Therefore, how to make a mistake correction method for the above problems, in order to maintain the correctness of the data as much as possible, without wasting memory space to save costs, is an important issue.

Accordingly, one of the objects of the present invention is to provide a method of accessing a flash memory module and associated flash memory controller and memory device using a similar Redundant Array of Independent Disks (Redundant Array of Independent Disks). RAID) error correction method, but it does not waste a lot of flash memory space, and only requires a small amount of buffer memory space during the processing of the flash memory controller to solve the problems in the prior art. .

In one embodiment of the present invention, a method for accessing a flash memory module is disclosed, wherein the flash memory module is a stereo flash memory module, and the flash memory module is A plurality of flash memory chips are included, each of the flash memory chips includes a plurality of multi-layer storage blocks and a plurality of single-layer storage blocks, each of which contains a plurality of data pages; each of the areas The block includes a plurality of floating gate transistors controlled by a plurality of word lines and bit lines respectively in a plurality of different planes, and the floating gate crystals on each of the word lines constitute at least one of the plurality of data pages a data page; and the method includes: encoding a data to generate at least one set of check codes, wherein the data is to be written to a first super block of the plurality of flash memory chips, wherein The first super block includes a multi-layer storage block of each of the plurality of flash memory chips; writing the data to the first super block; and the at least one Group check code is written to a second super Block, wherein the second super block comprises the plurality of flash memory chips in a single-level storage blocks each flash memory chip.

In another embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, and the flash memory module is a stereo flash memory module, the flash memory module includes a plurality of flash memory chips, each of the flash memory chips includes a plurality of multi-layer storage blocks and a plurality of single-layer storage areas Block, each block includes a plurality of data pages; each block includes a plurality of floating gate transistors controlled by a plurality of word lines and bit lines respectively in a plurality of different planes, and each of the characters The floating gate transistor on the line constitutes at least one data page of the plurality of material pages; and the flash memory controller comprises: a memory, a microprocessor and a codec. The memory is used to store a code; the microprocessor is configured to execute the code to control access to the flash memory module; and in the operation of the embodiment, the codec performs a data Encoding to generate at least one set of check codes, wherein the data is to be written into a first super block of the plurality of flash memory chips, wherein the first super block includes the plurality of flash memories a multi-layer storage block of each flash memory chip in the body wafer; and the microprocessor writing the data to the first super block, and writing the at least one set of check codes to the first In the second super block, the second super block includes a single-layer storage block of each of the plurality of flash memory chips.

In another embodiment of the present invention, a memory device includes a flash memory module and a flash memory controller, wherein the flash memory module is a stereo flash memory. The module, the flash memory module comprises a plurality of flash memory chips, each of the flash memory chips comprises a plurality of multi-layer storage blocks and a plurality of single-layer storage blocks, each block A plurality of data pages are included; each of the blocks includes a plurality of floating gate transistors respectively controlled by a plurality of word lines and bit lines in a plurality of different planes, and the floating gate crystals on each of the word lines Forming at least one of the plurality of material pages; and the flash memory controller when receiving a write command from a host to request a data to be written into the flash memory module Encoding the data to generate at least one set of check codes, and writing the data to a first super block of the plurality of flash memory chips, wherein the first super block includes the plurality of Every flash in the flash memory chip Rewriting a multi-layer storage block of the body wafer; and writing the at least one set of check codes to a second super block, wherein the second super block includes each of the plurality of flash memory chips A single-layer storage block of a flash memory chip.

In another embodiment of the present invention, a method for accessing a flash memory module is disclosed, wherein the flash memory module is a stereo flash memory module, and the flash memory model is The group contains a plurality of flash memory chips, each of which contains a plurality of blocks, each of which contains a plurality of data pages; each of the blocks contains a plurality of different planes a plurality of floating gate transistors controlled by the word line and the bit line, and the floating gate transistors on each of the word lines constitute at least one of the plurality of material pages; and the method comprises: planning The plurality of flash memory chips such that the plurality of flash memory chips have at least one first super block and at least one second super block; and assigning the at least one second super block to And configured to store a plurality of sets of temporary check codes encoded in a process of writing data to the at least one first super block.

In another embodiment of the present invention, a flash memory controller is disclosed. The flash memory controller is used to access a flash memory module, wherein the flash memory module is A stereo flash memory module, the flash memory module includes a plurality of flash memory chips, each of the flash memory chips includes a plurality of blocks, each of which includes a plurality of data pages Each block includes a plurality of floating gate transistors controlled by a plurality of word lines and bit lines respectively located in a plurality of different planes, and the floating gate transistors on each of the word lines constitute the plurality of data At least one data page in the page; and the flash memory controller includes a memory, a microprocessor, and a codec. The memory is used to store a code; the microprocessor is configured to execute the code to control access to the flash memory module; and in operation of the embodiment, the microprocessor plans the plurality of Flashing the memory chips such that the plurality of flash memory chips have at least one first super block and at least one second super block; and assigning the at least one second super block for storing in a data write A plurality of sets of temporary check codes encoded in the process of entering the at least one first super block.

In another embodiment of the invention, a memory device is disclosed that includes a flash memory module and a flash memory controller. The flash memory module is a stereo flash memory module, and the flash memory module comprises a plurality of flash memory chips, each flash memory chip comprises a plurality of blocks, each A block contains a plurality of data pages; each block includes a plurality of floating gate transistors controlled by a plurality of word lines and bit lines respectively in a plurality of different planes, and floating on each of the word lines The gate transistor forms at least one of the plurality of material pages; and the flash memory controller plans the plurality of flash memory chips such that the plurality of flash memory chips have at least one first super a block and at least one second super block, and assigning the at least one second super block to store a plurality of sets of transients encoded in a process of writing data to the at least one first super block Check code.

Please refer to FIG. 1 . FIG. 1 is a schematic diagram of a memory device 100 according to an embodiment of the present invention. The memory device 100 of the present embodiment is specifically a portable memory device (eg, conforming to SD/MMC, CF, MS, XD standard memory card). The memory device 100 includes a flash memory module 120 and a flash memory controller 110, and the flash memory controller 110 is used to access the flash memory module 120. According to the embodiment, the flash memory controller 110 includes a microprocessor 112, a read only memory (ROM) 112M, a control logic 114, a buffer memory 116, and an interface logic 118. The read-only memory system is used to store a code 112C, and the microprocessor 112 is used to execute the code 112C to control access to the flash memory module 120.

In a typical situation, the flash memory module 120 includes a plurality of flash memory chips, and each of the flash memory chips includes a plurality of blocks (eg, through a microprocessor). The flash memory controller 110 executing the code 112C performs copying, erasing, and merging data on the flash memory module 120, and copies, erases, and merges the data in units of blocks. In addition, a block can record a specific number of pages, wherein the controller (eg, the memory controller 110 executing the code 112C through the microprocessor 112) writes to the flash memory module 120. The operation of the data is written in units of data pages.

In practice, the flash memory controller 110 executing the code 112C through the microprocessor 112 can perform various control operations by using its own internal components, for example, using the control logic 114 to control the flash memory module 120. The access operation (especially for at least one block or at least one data page), the buffer memory 116 for the required buffering, and the interface logic 118 for communication with a host device.

On the other hand, in the present embodiment, the control logic 114 includes a first codec 132 and a second codec 134, wherein the first codec 132 is used to write to the flash. The data in one of the blocks of the memory module 120 is encoded to generate a corresponding error correction code, wherein the error correction code generated by the first codec 132 is only based on writing to a data page. The content of the middle sector is generated, and the generated error correction code is written to the data page along with the data content of the section. In addition, the second codec 134 is a fault-tolerant disk array (RAID) codec for encoding data written into a plurality of flash memory chips to generate a corresponding check code. The operation will be detailed in the following.

In this embodiment, the flash memory module 120 is a stereo NAND type flash memory (3D NAND-type flash) module. Please refer to FIG. 2, which is a stereo NAND flash memory. As shown in FIG. 2, the stereo NAND type flash memory includes a plurality of floating gate transistors 202, which pass through a plurality of bit lines (only shown as BL1 to BL3) and a plurality of characters. Lines (for example, WL0~WL2, WL4~WL6 shown) form a stereo NAND type flash memory architecture. In Fig. 2, taking the uppermost one plane as an example, all the floating gate transistors on the word line WL0 constitute at least one data page, and all the floating gate transistors on the word line WL1 constitute at least one other data. The page, while all the floating gate transistors of the word line WL2 constitute another at least one data page... such a heap. In addition, depending on the way the flash memory is written, the definition between the word line WL0 and the data page (logical data page) will be different. In detail, when using single-level storage (Single-Level Cell) , SLC) mode, all floating gate transistors on word line WL0 only correspond to a single logical data page; when writing using Multi-Level Cell (MLC), word line All floating gate transistors on WL0 correspond to two, three or four logical data pages, wherein the case where all floating gate transistors on word line WL0 correspond to three logical data pages may be referred to as three layers. The Triple-Level Cell (TLC) architecture, and the case where all of the floating gate transistors on the word line WL0 correspond to four logical data pages may be referred to as a Quad-Level Cell (QLC) architecture. Since the person having ordinary knowledge in the art should be able to understand the structure of the stereo NAND type flash memory and the relationship between the word line and the data page, the related details will not be described herein. In addition, in the operation of the flash memory controller 110, the "data page" is a minimum write unit, and the "block" is a minimum erase unit.

Please refer to FIG. 3, which is a conceptual diagram of the structure of the floating gate transistor 202. As shown in FIG. 3, the gate and the floating gate of each floating gate transistor are surrounded around the source and the drain (gate all around ) to enhance channel sensing capability.

It should be noted that the figures shown in FIGS. 2 and 3 are only examples of the stereo NAND type flash memory and the floating gate transistor 202, and are not intended to be limitations of the present invention, and those having ordinary knowledge in the art should be able to There are other types of stereo NAND flash memory, for example, some of the word lines can be connected to each other. And so on, and the design of the floating gate transistor 202 can be slightly changed.

As described in the prior art, in some stereo NAND type flash memories, a plurality of word lines are defined as a word line group, and the word line groups collectively have partial control circuits, thereby causing When the floating gate transistor of the data written to one of the character line groups fails (write failure), the data of the floating gate crystal on the other character lines of the character line group is caused to occur. error. In an embodiment, the word lines on the same plane are set to a character line group. Referring to FIG. 2, the word lines WL0 WL WL2 are attributed to the first word line group, and the word lines are WL4~WL6 will be attributed to the second character line group... and so on. Please refer to FIG. 4, which is a schematic diagram of multiple word line groups in a block. In FIG. 4, it is assumed that the block contains all floating gate transistors on 192 word lines, and one word line. The group contains 4 word lines, so the block in Figure 4 contains 48 word line groups WL_G0~WL_G47; in addition, in the figure, the block is a three-layer storage (TLC) area. The block, that is, the floating gate transistor on each word line, can be used to store data of three data pages. As shown in FIG. 4, the character line group WL_G0 is taken as an example, and the floating line on the character line WL0 is included. The gate transistor can be used to store the low data page P0L, the intermediate data page P0M and the high data page P0U. The floating gate transistor on the word line WL1 can be used to store the low data page P1L, the intermediate data page P1M and the high data page P1U, the word The floating gate transistor on the WL2 line can be used to store the low data page P2L, the intermediate data page P2M and the high data page P2U, and the floating gate transistor on the word line WL3 can be used to store the low data page P3L and the intermediate data page P3M. And high data page P3U. When the data is written into the data page of the word line group WL_G0 in the controller, the data is sequentially written to the floating gate transistors in the word lines WL0, WL1, WL2, WL3, and the word line WL0 is assumed. The data on WL1 is successfully written. However, when a write error occurs when the data is written to the word line WL2, an error occurs in the data originally written successfully on the word lines WL0 and WL1.

In addition, in some cases, even if the data has been successfully written, in the subsequent reading, there may be cases where unreadable or read errors may occur, such as the case where the word line is open. In the case where the data cannot be read, in addition, as described above, as long as one word line breaks in one character line group, the data of the entire character line group will be wrong. On the other hand, if a short circuit occurs in two word lines in different word line groups, for example, a short circuit occurs between the word line WL3 and the word line WL4 in FIG. 4, two word line groups are caused. The data on WL_G0 and WL_G1 cannot be read successfully.

As described above, since the flash memory encounters the above-mentioned write failure, word line disconnection, and word line short circuit in the writing of data and subsequent reading, the data of the entire character line group is incorrect. Therefore, the present invention proposes a method of accessing the flash memory module 120 that can solve the above problems in the following embodiments, and requires only a small amount of resources (ie, a small amount of memory space). can be completed. The details are as follows.

Referring first to FIG. 5, FIG. 5 is a schematic diagram of the flash memory controller 110 writing data to the flash memory module 120. As shown in FIG. 5, the flash memory module 120 includes a plurality of channels (in the present embodiment, two channels 510, 520 are taken as an example), and each channel is in the flash memory controller 110. There are respective sequencers and each includes a plurality of flash memory chips. In the present embodiment, the channel 510 includes flash memory chips 512, 514, and the channel 520 includes flash memory. Wafers 522, 524. In addition, one of each of the flash memory chips 512, 514, 522, 524 is configured as a super block, and the flash memory controller 110 will use the data as a super block. Write for the unit. In this embodiment, the super block 530 includes one of the three flash memory blocks 512, 514, 522, 524, and the super block 540 includes each of the flash memory chips. A single-layer storage block of 512, 514, 522, 524. It should be noted that in other embodiments of the present invention, the super block 530 may also be a four-layer storage block of each of the flash memory chips 512, 514, 522, 524.

Please refer to FIG. 5 and FIG. 6 at the same time. FIG. 6 is a schematic diagram of the flash memory controller 110 writing data to the super block 530 according to a first embodiment of the present invention, wherein in the following description, each A data is written to a data page of the flash memory chips 512, 514, 522, 524, that is, the first data is written into each of the flash memory chips 512, 514, 522, 524. The first data page P0, the second data will be written to the second data page P1, ... of each of the flash memory chips 512, 514, 522, 524, the Nth data will be written to The Nth data page P(N-1) of each of the flash memory chips 512, 514, 522, 524. Referring to FIG. 6, when the flash memory controller 110 needs to write the first data into the super block 530, first, the first codec 132 encodes the first data to generate a corresponding error. Correcting the code and writing the first data together with the error correction code generated by the first codec 132 to the first data page P0 of each of the flash memory chips 512, 514, 522, 524 In detail, the first codec 132 encodes the first part of the first data to generate an error correction code, and writes the first part of the data and its error correction code to the first of the flash memory chip 512. Data page P0; the first codec 132 encodes the second portion of the first data to generate an error correction code, and writes the second portion of the data and its error correction code to the first of the flash memory chip 514 Data page P0; the first codec 132 encodes the third part of the first data to generate an error correction code, and writes the third part of the data and its error correction code to the flash memory chip 522 a data page P0; and first The decoder 132 encodes the fourth portion of the first data (the last portion of the data) to generate an error correction code, and writes the fourth portion of the data and its error correction code to the first data of the flash memory chip 524. Page P0. It should be noted that the operation of the first codec 132 may be performed in units of sectors, wherein each data page is composed of a plurality of sectors. Before the first data and the error correction code generated by the first codec 132 are written to the super block 530, the second codec 134 in the flash memory controller 110 will target the first data and its The error correction code is encoded to generate a first set of check codes S0. In an embodiment, the second codec 134 may use a Reed Solomon (RS) encoding method or an exclusive-OR (XOR) operation to write to each flash memory. The data of the first material page P0 of the wafers 512, 514, 522, 524 is encoded to produce a first set of error correction codes S0. For example, but not as a limitation of the present invention, the second codec 134 may interact with each other of the first bit of the first data page P0 of the flash memory chips 512, 514, 522, 524 Repetitive OR operation to obtain the first bit of the first group of check codes S0, and the second bit of the first data page P0 of the flash memory chips 512, 514, 522, 524 are mutually The OR operation is used to obtain the second bit of the first group of check codes S0... and so on.

The first set of check codes S0 generated by the second codec 134 is used to generate data on the first data page P0 of one of the flash memory chips 512, 514, 522 or 524. In the case of an error, an error correction is performed. For example, it is assumed that when the data of the first data page P0 in the flash memory chip 512 fails to be corrected by using its own data (that is, the first codec cannot be utilized) When the error correction code generated by 132 is corrected, the second codec 134 can read the data of all the first data pages P0 of the flash memory chips 514, 522, and 524, plus the first group of schools. The code S0 is used to perform error correction to determine the data of the first material page P0 in the flash memory chip 512.

In addition, the first group of check codes S0 generated by the second codec 134 is temporarily stored in the buffer memory 116 of the flash memory controller 110.

In addition, during the writing of the first data, the flash memory controller 110 performs a read check operation on the written data to determine whether the data is successfully written. When the data is written incorrectly, the second codec 134 can directly correct the read data by using the first group of check codes S0 stored in the buffer memory 116, and the flash memory module 120 is used. It is not possible to directly correct the written data, and the corrected data (the first data after correction) can wait for the subsequent suitable time to be written together with other materials in the super block 530 to another super block. . After the flash memory controller 110 determines that the first data has been successfully written to the first data page P0 of the flash memory chips 512, 514, 522, 524, the flash memory controller 110 will The first group of check codes S0 is moved from the buffer memory 116 to the super block 540.

Next, when the flash memory controller 110 needs to write the second data into the super block 530, first, the first codec 132 respectively encodes the second data to generate a corresponding error correction code. The second data is written to the second material page P1 of each of the flash memory chips 512, 514, 522, 524 together with the error correction code generated by the first codec 132. Before the second data and the error correction code generated by the first codec 132 are written to the super block 530, the second codec 134 in the flash memory controller 110 will target the second data and its The error correction code is encoded to generate a second set of check codes S1. In one embodiment, the second codec 134 may use a Reed-Solomon encoding or a mutually exclusive OR operation to write to the second of each of the flash memory chips 512, 514, 522, 524. The data of the data page P1 is encoded to generate a second set of error correction codes S1.

In addition, the second group of check codes S1 generated by the second codec 134 is temporarily stored in the buffer memory 116 of the flash memory controller 110.

Similarly, during the writing of the second data, the flash memory controller 110 also performs a read check operation on the written data to determine whether the data is successfully written. When the data is written incorrectly, the second codec 134 can directly correct the read data using the second group of check codes S1 stored in the buffer memory 116, and the corrected data (corrected) The second data) can wait for the next suitable time to be written to another super block along with other data in the super block 530. After the flash memory controller 110 determines that the second data has been successfully written to the second data page P1 of the flash memory chips 512, 514, 522, 524, the flash memory controller 110 will The second set of check codes S1 is moved from the buffer memory 116 to the super block 540.

It should be noted that when a write error occurs in the process of writing the second data, since the data pages P1 and P0 belong to the same word line group WL_G0, the flash memory chip 512, The data page P0 in 514, 522, and 524 may also be damaged. For example, assuming that the material page P1 of the flash memory chip 514 has an error during the data writing, the data page P0 of the flash memory chip 514 that has been successfully written previously also has an error. At this time, since the buffer memory 116 itself does not store the first group check code S0, the flash memory controller 110 reads the first group check code S0 from the super block 540 to The first data read by block 530 is corrected.

Based on the same operation, the flash memory controller 110 continues to write the third data into the third material page P2 of the flash memory chips 512, 514, 522, 524, and generates the corresponding third. Group check code S2; and writing the fourth data into the fourth data page P3 of the flash memory chips 512, 514, 522, 524, and generating a corresponding fourth group check code S3, To complete the data write operation on the word line group WL_G0.

Then, similar to the above steps, the flash memory controller 110 writes the next 5~184th data into the flash memory chips 512, 514, 522, 524, and the second codec 134 is 5th. The ~184 data is encoded to generate the 5th to 183th check codes S4 to S183, respectively, and the 5th to 183th check codes S4 to S183 are stored in the super block 540.

For the 185th data, the flash memory controller 110 only writes the 185th data together with the error correction code generated by the first codec 132 to the data in the flash memory chips 512, 514, 522. Page P184 does not write data to the material page P184 in the flash memory chip 524. Before the 185th data is written to the super block 530, the second codec 134 encodes the 185th data and its error correction code to generate the 185th set of check code S184. Next, the flash memory controller 110 reads the first set of check codes S0, S8, S16, ..., S176 of each of the word line groups WL_G0 WL WL_45 from the super block 540, and the second codec pair The check codes S0, S8, S16, ..., S176 and the check code S184 are mutually exclusive or operated together to obtain a first set of final check codes SF0. Next, the flash memory controller 110 writes the 185th data to the data page P184 in the flash memory chips 512, 514, 522, and writes the first set of final check code SF0 to the flash memory. Data page P184 in wafer 524. In an embodiment, the second codec 134 performs a mutually exclusive operation on the first bit of the check codes S0, S8, S16, ..., S184 to generate the first bit of the final check code SF0. The second bit in the check codes S0, S8, S16, ..., S184 is mutually exclusive ORed to generate the second bit of the final check code SF0... and so on until the final school is completed. The last bit of the code SF0 is verified. Additionally, the check code S184 can be stored in the super block 540.

For the 186th data, the flash memory controller 110 only writes the 186th data together with the error correction code generated by the first codec 132 to the data in the flash memory chips 512, 514, 522. Page P185 does not write data to the material page P185 in the flash memory chip 524. Before the 186th data is written to the super block 530, the second codec 134 encodes the 186th data and its error correction code to generate the 186th set of check code S185. Next, the flash memory controller 110 reads the second set of check codes S1, S9, S17, ..., S177 of each of the word line groups WL_G0 WL WL_45 from the super block 540, and the second codec pair The check codes S1, S9, S17, ..., S177 and the check code S185 are mutually exclusive or operated together to obtain a second set of final check codes SF1. Next, the flash memory controller 110 writes the 186th data to the data page P185 in the flash memory chips 512, 514, 522, and writes the second set of final check code SF1 to the flash memory. Data page P185 in wafer 524. In an embodiment, the second codec 134 performs a mutually exclusive operation on the first bit of the check codes S1, S9, S17, ..., S185 to generate the first bit of the final check code SF1. The second bit in the check codes S1, S9, S17, ..., S185 is mutually exclusive ORed to generate the second bit of the final check code SF1... and so on until the final school is completed. The last bit of the code SF1. Further, the check code S185 can be stored in the super block 540.

Based on the similar operation, for the 187th to 192th data, the flash memory controller 110 writes the 187th to 192th data together with the error correction code generated by the first codec 132 to the flash memory chip 512. Data pages P186~P191 in 514, 522; and the second codec 134 also generates third to eighth sets of final check codes SF2~SF7 according to the similar operations described above, and the third to eighth sets of final checksums The codes SF2 to SF7 are written to the material pages P186 to P191 in the flash memory chip 524, respectively.

For the concept of generating the eight sets of final check codes SF0 to SF7 based on the first to 192th sets of check codes S0 to S191, reference may be made to the contents shown in FIG.

In this embodiment, the check code stored in the super block 540 is only a temporary check code, that is, the plurality of check codes S0~S191 stored in the super block 540 are only written in the data. This is only used when an error occurs during the super block 530. Therefore, after the final check codes SF0~SF7 are written to the super block 530, the plurality of sets of check codes S0~S191 stored in the super block 540 need not be used again, and therefore, in the subsequent super block 530. In the event that the data stored in the data is still valid, the flash memory controller 110 can erase or mark the contents of the super block 540 as invalid.

It should be noted that since the above final check codes SF0~SF7 are generated by the check codes S0~S191, the final check codes SF0~SF7 have substantially the previous set of check codes S0~. S191 information. That is, in the subsequent read operation, each set of check codes S0~S191 can be obtained in addition to the corresponding data page content (for example, reading the flash memory chips 512, 514, 522, 524). The data page P1 obtains the check code S1), and if an error occurs, it can be corrected by the corresponding final check code SF0~SF7. For example, if one of the word line groups WL_G0 is disconnected, for example, the word line corresponding to the data page P0 of the flash memory chip 514 is broken, the flash memory controller 110 can read The data in the other character line group regenerates the check codes S8, S16, ..., S184 and the final check code SF0 to regenerate the check code S0, and then uses the check code S0 and the self-flash memory. The content read by the material page P0 of the body wafers 512, 522, 524 regenerates the data of the data page P0 of the flash memory chip 514; the flash memory controller 110 reads the data in other character line groups. The check codes S9, S17, ..., S185 and the final check code SF1 are regenerated to regenerate the check code S1, and then the check code S1 and the data from the flash memory chips 512, 522, 524 are used. The content read by page P1 regenerates the data of the data page P1 of the flash memory chip 514; and the data of the data pages P2, P3 of the flash memory chip 514 are regenerated according to the similar operations described above. As described above, through the above operation, as long as the plurality of data lines are not broken in the super block 530, the data correction can be smoothly restored without occurrence of the fact that the data cannot be repaired.

In addition, if two data lines are short-circuited between the word line groups WL_G0 and WL_G1, for example, the word line corresponding to the data pages P3 and P4 of the flash memory chip 514 is short-circuited, and the previous paragraph can also be used. The method mentioned is used to correct the data in the word line groups WL_G0 and WL_G1, without the situation that the data cannot be repaired.

It should be noted that each of P0~P191 depicted in FIG. 6 represents not limited to three data pages, but may be two or four data pages.

Further, in the embodiment shown in FIGS. 6 to 7, the final check codes SF0 to SF7 are generated by reading the check code previously stored in the super block 540, however, the present invention does not This is limited. In another embodiment, the check code stored in the super block 540 can also be encoded together with the check code of the previous word line group in the process of generation, for example, the second codec. 134 may encode the ninth data (the ninth data page P8 written to each of the flash memory chips 512, 514, 522, 524) and the first group of check codes S0 to generate the ninth group. The check code S8, the 17th data (written to the 17th data page P16 of each of the flash memory chips 512, 514, 522, 524) and the 9th set of check code S8 are encoded together to generate The 17th group check code S16, ..., the 185th data (written to the 185th data page P184 of each of the flash memory chips 512, 514, 522, 524) and the 177th group check code S176 Coding is performed together to generate a 185th set of check codes S184. In this way, since the 185th group check code S184 itself has the information of the previous check codes S0, S8, S16, ..., S176, the 185th group check code S184 can be directly used as the first group final school. The code SF0 is stored and stored in the data block P184 of the super block 530 corresponding to the flash memory chip 524. Similarly, the final check codes SF1 SF SF7 can also be generated in the above manner, and stored in the data blocks P185 to P191 of the super block 530 corresponding to the flash memory chip 524, respectively.

In addition, in FIG. 5, the super block 530 includes only one of the three flash memory blocks 512, 514, 522, 524. However, in other embodiments, for example, flashing In the case where the memory module 120 is configured as two block planes, the super block 530 may include two three-layer storage areas of each of the flash memory chips 512, 514, 522, 524. Blocks, and two of the three flash memory blocks of each of the flash memory chips 512, 514, 522, 524 are controlled by different chip enable signals. Similarly, super block 540 can also include two single-layer storage blocks in each of flash memory chips 512, 514, 522, 524.

Please refer to FIG. 8 , which is a flowchart of a method for accessing a flash memory module according to an embodiment of the invention. Referring to the above disclosure, the process is as follows:

Step 800: The process begins.

Step 802: Plan a plurality of flash memory chips such that the plurality of flash memory chips have at least one first super block and at least one second super block.

Step 804: Write a data into the at least one super block.

Step 806: Encode the data to generate a plurality of sets of temporary check codes, and store the plurality of sets of temporary check codes to the at least one second super block.

Step 808: Generate a final check code according to the plurality of sets of temporary check codes.

Step 810: Write a final check code to the at least one first super block.

Step 812: Erasing or marking the at least one second super block as invalid.

Step 814: The process ends.

Briefly summarized in the present invention, in an embodiment of the method for accessing a flash memory module of the present invention, the second codec sequentially encodes multiple pieces of data written to the multi-stored super block. And storing the generated temporary check code to the super-block stored in the single-layer storage, and then reading the temporary check code stored in the super-block stored in the single-layer storage to generate a low amount of data. The final check code is stored and the final check code is stored in the multi-stored super block. Through the above access method, in addition to correcting data reading errors caused by data writing errors, word line disconnection, and word line short circuit, the buffer memory in the flash memory controller can be greatly reduced. Capacity requirements, and the flash memory module does not need to waste too much space to store the check code, so the cost of the flash memory controller and the use efficiency of the flash memory module can be greatly reduced. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100‧‧‧ memory device
110‧‧‧Flash Memory Controller
112‧‧‧Microprocessor
112C‧‧‧ Code
112M‧‧‧Reading memory
114‧‧‧Control logic
116‧‧‧Buffered memory
118‧‧‧Interface logic
120‧‧‧Flash Memory Module
132‧‧‧first codec
134‧‧‧Second codec
202‧‧‧Floating transistor
510, 520‧‧‧ channels
512, 514, 516, 518‧‧‧ flash memory chips
530, 540‧‧‧Super Block
800~814‧‧‧Steps
B1~B3‧‧‧ bit line
WL0~WL47‧‧‧ character line
WL_G0~WL_G47‧‧‧ character line group

1 is a schematic diagram of a memory device in accordance with an embodiment of the present invention. Figure 2 is a schematic diagram of an example of a stereo NAND type flash memory. Figure 3 is a conceptual diagram of the structure of a floating gate transistor. Figure 4 is a schematic diagram of multiple word line groups in a block. Figure 5 is a schematic diagram of the flash memory controller writing data to the flash memory module and the super block. Figure 6 is a diagram showing the flash memory controller writing data to the super block in accordance with a first embodiment of the present invention. FIG. 7 is a schematic diagram of generating eight sets of final check codes SF0 to SF7 according to the first to 192th check codes S0 to S191. 8 is a flow chart of a method of accessing a flash memory module in accordance with an embodiment of the present invention.

Claims (24)

A method for accessing a flash memory module, wherein the flash memory module is a 3D NAND-type flash module, and the flash memory module includes a plurality of A flash memory chip, each of which is a stereo flash memory chip and includes a plurality of blocks, each of which contains a plurality of data pages; each of the blocks includes a plurality of data blocks respectively a plurality of word lines of different planes and a plurality of floating gate transistors controlled by the bit lines, and the floating gate transistors on each of the word lines constitute at least one of the plurality of material pages; and the The method includes: planning the plurality of flash memory chips such that the plurality of flash memory chips have at least one first super block and at least one second super block, wherein the first super area Each of the block and the second super block includes a plurality of blocks respectively located in the plurality of flash memory chips; and assigning the at least one second super block for storing in a data write Into the process of the at least one first super block Code generating many temporary check code group. The method of claim 1, wherein the at least one second super block is exclusively used to store a temporary school generated by any data written into the encoding process of the at least one first super block. Code verification. The method of claim 1, wherein the at least one first super block comprises a multi-layer storage block of each of the plurality of flash memory chips, and the at least one A second super block includes a single layer storage block of each of the plurality of flash memory chips. The method of claim 3, wherein the multi-layer storage block is a Triple-Level Cell (TLC) block or a Quad-Level Cell (QLC) block. . The method of claim 1, further comprising: in the process of writing the data to the at least one first super block: reading the data from the first super block has been written Reading a portion of the content of the at least one first super block; and reading at least a portion of the temporary school from the second super block when an uncorrectable error occurs during reading of a portion of the content of the material The code is verified and the read data is error corrected using the read temporary check code. The method of claim 1, further comprising: reading the plurality of sets of temporary check codes from the at least one second super block; encoding the plurality of sets of temporary check codes Generating a set of final check codes; and writing the set of final check codes to the at least one first super block. The method of claim 6, further comprising: storing the data stored in the at least one first super block after the final verification code is written to the first super block If still valid, the content of the at least one second superblock is erased or marked as invalid. The method of claim 6, further comprising: after the final verification code of the group is written into the at least one first super block: Reading a portion of the material from the first super block; and reading an uncorrectable error in the process of reading a portion of the content, reading the group from the at least one first super block Check the code and use the set of final check codes read to correct the data read. A flash memory controller for accessing a flash memory module, wherein the flash memory module is a stereo flash memory (3D NAND-type flash) a module, the flash memory module includes a plurality of flash memory chips, each flash memory chip is a stereo flash memory chip, and includes a plurality of blocks, each block includes a plurality of data pages; each of the blocks includes a plurality of floating gate transistors controlled by a plurality of word lines and bit lines respectively in a plurality of different planes, and the floating gate transistors on each of the word lines constitute a floating gate transistor At least one of the plurality of data pages; and the flash memory controller includes: a memory for storing a code; a microprocessor for executing the code to control the An access to the flash memory module; and a codec; wherein the microprocessor plans the plurality of flash memory chips such that the plurality of flash memory chips have at least one first super block (super Block) and at least one second super block, wherein the Each of the super block and the second super block includes a plurality of blocks respectively located in the plurality of flash memory chips; and the at least one second super block is assigned for storage in a The plurality of sets of temporary check codes encoded in the process of writing the data to the at least one first super block. The flash memory controller of claim 9, wherein the at least one second super block is exclusively used to store any data written to the code of the at least one first super block. The temporary check code generated in the process. The flash memory controller of claim 9, wherein the at least one first super block comprises a multi-layer storage area of each of the plurality of flash memory chips. And the at least one second super block includes a single layer storage block of each of the plurality of flash memory chips. The flash memory controller of claim 11, wherein the multi-layer storage block is a triple-level cell (TLC) block or a four-layer storage (Quad-Level Cell). , QLC) block. The flash memory controller of claim 9, wherein in the process of writing the data to the at least one first super block: the microprocessor reads from the first super block The data has been written to a portion of the at least one first superblock; and when an uncorrectable error occurs during reading of a portion of the content, at least one of the second superblock is read A temporary check code, and the codec uses the read temporary check code to correct the read data. The flash memory controller of claim 9, wherein the microprocessor reads the plurality of sets of temporary check codes from the at least one second super block, the codec A plurality of sets of temporary check codes are encoded to generate a set of final check codes, and the microprocessor writes the set of final check codes into the at least one first super block. A flash memory controller as described in claim 14, wherein the group is the most After the final check code is written to the first super block, the microprocessor stores the at least one second super block if the data stored in the at least one first super block is still valid. The content is erased or marked as invalid. The flash memory controller of claim 14, wherein after the set of final check codes is written into the at least one first super block: the microprocessor is from the first super block Reading a portion of the content of the material; and when an uncorrectable error occurs during reading of a portion of the content, the microprocessor reads the final verification code from the at least one first super block And the codec uses the set of final check codes read to correct the read data. A memory device includes: a flash memory module, wherein the flash memory module is a 3D NAND-type flash module, and the flash memory module includes a plurality of flash memory chips, each of which is a stereo flash memory chip and includes a plurality of blocks, each of which contains a plurality of data pages; each of the blocks includes a plurality of floating gate transistors controlled by a plurality of word lines and bit lines respectively in a plurality of different planes, and the floating gate crystals on each of the word lines constitute at least one of the plurality of material pages And a flash memory controller for accessing the flash memory module; wherein the flash memory controller plans the plurality of flash memory chips such that the plurality of flash memory chips have At least one first super block and at least one second super block, and assigning the at least one second super block to store a process of writing data to the at least one first super block Multiple sets of temporary check codes generated by the encoding among them Each of the first super block and the second super block includes a plurality of blocks respectively located in the plurality of flash memory chips. The memory device of claim 17, wherein the at least one second super block is exclusively used to store temporary data generated by any data written into the encoding process of the at least one first super block. Check code. The memory device of claim 17, wherein the at least one first super block comprises a multi-layer storage block of each of the plurality of flash memory chips, and the The at least one second super block includes a single layer storage block of each of the plurality of flash memory chips. The memory device of claim 19, wherein the multi-layer storage block is a Triple-Level Cell (TLC) block or a Quad-Level Cell (QLC) region. Piece. The memory device of claim 17, wherein the flash memory controller reads the data from the first super block during the writing of the data to the at least one first super block The data has been written to a portion of the at least one first superblock; and when an uncorrectable error occurs during reading of a portion of the content, at least a portion of the second superblock is read The temporary check code, and the read temporary data is used to correct the error of the read data. The memory device of claim 17, wherein the flash memory controller Reading the plurality of sets of temporary check codes from the at least one second super block, and encoding the plurality of sets of temporary check codes to generate a set of final check codes, and finalizing the group The code is written into the at least one first super block. The memory device of claim 22, wherein after the final verification code is written to the first super block, the data stored in the at least one first super block is still In an effective case, the flash memory controller erases or marks the content of the at least one second super block as invalid. The memory device of claim 22, wherein after the set of final check codes is written into the at least one first super block: the flash memory controller is from the first super block Reading a portion of the material; and when an uncorrectable error occurs during reading of a portion of the material, the flash memory controller reads the final group from the at least one first super block The code is verified and the corrected data is read to correct the data read.