TWI588843B - Methods for accessing a storage unit of a flash memory and apparatuses using the same - Google Patents

Description

Method for accessing storage unit in flash memory and device using the same

The present invention relates to a flash memory device, and more particularly to a method of accessing a memory unit in a flash memory and a device using the same.

Memory cells in flash memory may fail after multiple accesses. In addition, it is also possible that in the production process, a whole column of data in the storage unit cannot be correctly accessed due to dust or mask problems. Accordingly, the present invention is directed to a method of accessing a flash memory unit and apparatus for using the same to protect data stored in a flash memory.

Embodiments of the present invention provide a method of accessing a storage unit in a flash memory, executed by a processing unit, including the following steps. After receiving the read command and the read address sent by the electronic device through the processing unit access interface, it is determined whether the value associated with the read address has not been stably stored in the storage unit. If so, the memory access controller is instructed to read the requested value from the random access memory and reply to the electronic device through the processing unit access interface.

An embodiment of the present invention provides an apparatus for accessing a storage unit in a flash memory, including at least a storage unit access interface and a processing unit access medium. Surface and processing unit. The processing unit is coupled to the storage unit access interface and the processing unit access interface. After receiving the read command and the read address sent by the electronic device through the processing unit access interface, the processing unit determines whether the value associated with the read address has not been stably stored in the storage unit; and, if so, indicates the memory The body access controller reads the requested value from the dynamic random access memory and replies to the electronic device through the processing unit access interface.

10‧‧‧ storage unit

110‧‧‧Memory cell array

120‧‧‧ line decoding unit

130‧‧‧ column coding unit

140‧‧‧ address unit

150‧‧‧ data buffer

20‧‧‧System Architecture of Flash Memory

200‧‧‧ controller

210‧‧‧Control unit

230‧‧‧storage unit access interface

250‧‧‧Processing unit access interface

300‧‧‧Flash storage device

10[ 0 ][ 0 ]~10[ j ][ i ]‧‧‧ storage unit

310[ 0 ][ 0 ]~310[ j ][ i ]‧‧‧Electronic signal

230[ 0 ]~230[ j ]‧‧‧storage unit access interface

410[ 0 ][ 0 ][ 0 ]~410[ j ][ i ][ k ]‧‧‧ Section data

510‧‧‧Information

530‧‧‧ horizontal error correction code

510[ 0 ][ 0 ][ 0 ]~510[ j ][ i ][ 0 ]‧‧‧Message

530[ 0 ][ 0 ][ 0 ]~530[ j ][ i ][ 0 ]‧‧‧Horizontal Error Correction Code

610‧‧‧Processing unit

620‧‧‧ Dynamic Random Access Memory

621, 623‧‧‧ Direct Memory Access Controller

630‧‧‧Disk array coding unit

640‧‧‧Multiplexer

650‧‧‧ Cache

660‧‧‧ Arbitration Unit

S711~S751‧‧‧ method steps

S811~S831‧‧‧ method steps

910‧‧‧Processing unit

930‧‧‧Disk array decoding unit

950‧‧‧ Cache

960‧‧‧section decoding unit

S1010~S1070‧‧‧ method steps

S1110~S1170‧‧‧ method steps

1210‧‧‧Processing unit

1220, 1230‧‧‧ Direct Memory Access Controller

1240‧‧‧ Dynamic Random Access Memory

1250‧‧‧ Cache

1300‧‧‧Three-tier unit block

PG0~PG191‧‧‧ page

WL0~WL63‧‧‧ character line

S1410~S1470‧‧‧ method steps

S1510~S1550‧‧‧ method steps

LSB‧‧‧ Lowest Bit

CSB‧‧‧Intermediate bit

MSB‧‧‧ highest bit

10[ 0 ][ 0 ]~10[ 3 ][ 3 ]‧‧‧ Storage unit

CH0~CH3‧‧‧ channel

CE0~CE3‧‧‧ connected to a specific channel storage unit

S2011~S2087‧‧‧ method steps

2100‧‧‧ character line write order lookup table

1 is a schematic diagram of a storage unit in a flash memory according to an embodiment of the present invention.

2 is a schematic diagram of a system architecture of a flash memory according to an embodiment of the present invention.

Figure 3 is a schematic diagram of an access interface of a flash memory in accordance with an embodiment of the present invention.

Figure 4 is a schematic diagram of logical data storage in accordance with an embodiment of the present invention.

Figure 5A is a schematic diagram of data storage applied to each segment in accordance with an embodiment of the present invention.

Figure 5B is a schematic diagram of a two-dimensional error correction code in accordance with an embodiment of the present invention.

Figure 6 is a block diagram of a system for performing a write job in accordance with an embodiment of the present invention.

7A and 7B are flowcharts of a method of writing data in a processing unit according to an embodiment of the present invention.

Figure 8 is a flow chart of a method for writing data in a storage unit access interface in accordance with an embodiment of the present invention.

Figure 9 is a block diagram of a system for performing a read job in accordance with an embodiment of the present invention.

Figure 10 is a flow chart of a method of reading data in a segment decoding unit in accordance with an embodiment of the present invention.

Figure 11 is a flow chart of a method of reading data in a processing unit in accordance with an embodiment of the present invention.

Figure 12 is a block diagram of a system for performing a write job in accordance with an embodiment of the present invention.

Figure 13 is a schematic illustration of a three-layer cell block in a storage unit in accordance with an embodiment of the present invention.

Figure 14 is a flow diagram of a method of writing performed in a processing unit in accordance with an embodiment of the present invention.

Figure 15 is a flow chart of a method of writing executed in a processing unit in accordance with an embodiment of the present invention.

Figure 16A is a schematic diagram showing the threshold voltage distribution of a plurality of single-layer cells in accordance with an embodiment of the present invention.

Figure 16B is a schematic diagram of the threshold voltage distribution of a plurality of multi-layer cells in accordance with an embodiment of the present invention.

Figure 16C is a schematic diagram showing the threshold voltage distribution of a plurality of three-layer cells in accordance with an embodiment of the present invention.

17A to 17C are diagrams showing threshold voltage distributions of a plurality of three-layer cells on one word line after three write operations in accordance with an embodiment of the present invention.

Figure 18A illustrates the use of RS (48, 45) vertical errors in accordance with an embodiment of the present invention. A schematic diagram of the data placement of the independent disk redundant array group of the correction code.

Figure 18B is a diagram showing the arrangement of data of a redundant array of independent disks using an RS (96, 93) vertical error correction code according to an embodiment of the present invention.

19A to 19B are diagrams of data writing timings according to an embodiment of the present invention.

20A to 20D are flowcharts of a method of writing data executed in a processing unit according to an embodiment of the present invention.

Figure 21 is a diagram showing the sequence of writing of word lines in accordance with an embodiment of the present invention.

Embodiments of the present invention provide a method for accessing a storage unit in a flash memory and a device using the same for encoding data to be stored to a storage unit and decoding data read from the storage unit. 1 is a schematic diagram of a storage unit in a flash memory according to an embodiment of the present invention. The storage unit 10 includes an array 110 composed of MxN memory cells, and each memory unit stores information of at least one bit. The flash memory can be a NOR flash memory, a NAND flash memory, or other types of flash memory. In order to correctly access the information, the row decoding unit 120 is configured to select a row specified in the memory cell array 110, and the column encoding unit 130 is configured to select a data of a certain number of bytes in the specified row as an output. Address unit 140 provides row information to row decoder 120 in which those rows in select memory cell array 110 are defined. Similarly, column decoder 130 selects a certain number of columns in a specified row of memory cell array 110 for read or write operations based on the column information provided by address unit 140. A row can be called a wordline, and a column can be called a bitline. The data buffer 150 can store data read from the memory cell array 110 or data to be written into the memory cell array 110. The memory unit can be single-level cells (SLCs), multi-level cells (MLCs), or triple-level cells (TLCs).

A single-level cell can represent two states, one of which is a state in which there is a zero charge in the floating gate and a state that has not been written after erasing (usually defined as "1"). And the other is a state in which there is some amount of negative charge in the floating gate (usually defined as a state of "0"). A gate with a negative charge causes the threshold voltage of the transistor in the cell to increase, that is, when the voltage is applied to the control gate of the transistor, the transistor can be turned on. One possible way to read the storage bit is to check the threshold voltage in this cell. If the threshold voltage is in a higher state, the bit value is "0". If the threshold voltage is in a lower state, the bit value is "1". Figure 16A is a schematic diagram showing the threshold voltage distribution of a plurality of single-layer cells in accordance with an embodiment of the present invention. Because the characteristics and operation results between the memory cells in the flash memory are not completely consistent (for example, due to small variations in impurity concentration or defects in the structure), although the same write operation is used to all the memories. Units, but not all memory cells have a completely consistent threshold voltage. Therefore, the distribution of the threshold voltage is as shown in Fig. 16A. A single-layer cell of state "1" typically has a negative threshold voltage such that most of the cells have a center voltage close to the left peak, while a small number of cells have a threshold voltage that is higher or lower than the center voltage of the left peak. Similarly, a single-level cell of state "0" typically has a positive threshold voltage such that most of the cells have a center voltage close to the right peak, while a small number of cells have a higher or lower critical value of the right peak center voltage. Electricity Pressure.

Although a multi-level cell is literally represented as having more than two voltage levels, that is, each cell can represent more than one bit of information, but currently most multi-level cells represent only two bits. Information to provide examples as shown below. A single multi-level cell uses one of four different states to store information for two bits, one of which is called the Least Significant Bit (LSB) and the other is called the highest bit. Most Significant Bit (MSB). Since the state of a memory cell is represented by a threshold voltage, the threshold voltage of the multi-layer cell has four different effective intervals. Figure 16B is a schematic diagram of the threshold voltage distribution of a plurality of multi-layer cells in accordance with an embodiment of the present invention. The expected distribution has four peaks, each corresponding to a state. Similarly, a single three-tier cell uses one of eight different states to store three bits of information, one of which is called the lowest bit and the other is called the middle bit (Center Significant) Bit, CSB), and the last bit is called the highest bit. The threshold voltage of a three-layer unit has eight different effective intervals. Figure 16C is a schematic diagram showing the threshold voltage distribution of a plurality of three-layer cells in accordance with an embodiment of the present invention. The expected distribution has eight peaks, each corresponding to a state. It should be noted that the present invention is also applicable to a flash memory device in which each memory unit supports more than three bits.

2 is a schematic diagram of a system architecture of a flash memory according to an embodiment of the present invention. The system architecture 20 of the flash memory includes a controller 200 for writing data to a specified address in the storage unit 10 and reading data from a specified address in the storage unit 10. In detail, the control unit 210 writes data to the specified address in the storage unit 10 through the storage unit access interface 230, and from the storage. The specified address in the memory unit 10 reads the data. The system architecture 20 uses a plurality of electronic signals to coordinate data and command transfer between the controller 200 and the storage unit 10, including a data line, a clock signal, and a control signal. The data line can be used to transfer commands, addresses, read and write data; the control signal line can be used to transmit chip enable (CE), address latch enable (ALE), command extraction Control signals such as command latch enable (CLE) and write enable (WE). The storage unit access interface 230 can communicate with the storage unit 10 by using a double data rate (DDR) protocol, for example, an open NAND flash interface (ONFI) and a double data rate switch (DDR toggle). ) or other interface. The control unit 210 can also use the processing unit access interface 250 to communicate with other electronic devices through a specified communication protocol, for example, a universal serial bus (USB), an advanced technology attachment (ATA), and an advanced sequence. Serial advanced technology attachment (SATA), peripheral component interconnect express (PCI-E) or other interface.

A flash storage device can include a plurality of storage units 10, each of which is implemented on a die having separate interfaces to communicate with the storage unit access interface 230. When accessing a large amount of data, the operations of these access storage units (for example, read or write operations) can be pipelined to improve access efficiency. Figure 3 is a schematic diagram of an access interface of a flash memory in accordance with an embodiment of the present invention. The flash storage device 300 can include j + 1 channels, each channel containing i + 1 storage units. In other words, i + 1 storage units share the same channel. For example, when the flash storage device 300 includes 8 channels ( j = 7 ) and each channel contains 8 storage units ( i = 7 ), the flash storage device 300 has a total of 64 storage units 10 [ 0 .. j ][ 0 .. i ]. The control unit may use flash memory storage device 300, an electronic flash signal is provided 310 [0 .. j] [0 .. i] by one of the data storage unit to the designated storage, and / or from The specified storage unit reads the data. Each storage unit has a separate wafer enable (CE) control signal. In other words, when data access is to be performed on a designated storage unit to which a specified storage unit access interface (also referred to as a channel) is connected, the corresponding wafer enable control signal needs to be enabled. Those skilled in the art can use any number of channels in the flash storage device 300, and each channel can include any number of storage units, and the invention is not so limited.

In order to ensure the correctness of the stored message, it can be protected by storing a two-dimensional error correction code (ECC). Figure 4 is a schematic diagram of logical data storage in accordance with an embodiment of the present invention. (J + 1) x (i + 1) th storage units may be included for storing the l-th error correction code (e.g., l = 1, 2, or 3) a storage unit, a code stored therein may be called Vertical error correction code (vertical ECC). Each vertical error correction code is generated based on the values of the corresponding addresses in the other ( j + 1) x (i + 1) - 1 storage units. The vertical error correction code may be a single parity correction (SPC), an RS code (Reed-Solomon code) or other code that provides a correction error function. For example, when i = 7 , j = 7 and l = 1 , the storage unit 10[ 7 ][ 7 ] can store the error correction code of the SPC (64, 63). When i = 7 , j = 7 and l = 2 , the memory cells 10[ 7 ][ 6 ] and 10[ 7 ][ 7 ] can store the error correction code of RS(64,62). When i = 7 , j = 7 and l = 3 , the memory cells 10[ 7 ][ 5 ], 10[ 7 ][ 6 ] and 10[ 7 ][ 7 ] can store the error correction of RS (64,61) code. The vertical error correction code is used to provide protection of the storage unit level, that is, when one of the storage units fails, the vertical error correction code and the correct value stored in other storage units can be restored and stored in the failed storage unit. All the values. In other storage units that do not store the vertical error correction code, in addition to storing the message, a horizontal error correction code (horizontal ECC) is stored. Each word line in each storage unit can store k + 1 (eg, k = 31 ) sectors of data. The k + 1 segments described above can be collectively referred to as a page. For example, for a specified word line, the storage unit 10[ 0 ][ 0 ] can store data of the section 410[ 0 ][ 0 ][ 0 ] to the section 410[ 0 ][ 0 ][ k ], the storage unit 10[ 0 ][ i ] can store data of section 410[ 0 ][ i ][ 0 ] to section 410[ 0 ][ i ][ k ], storage unit 10[ j ][ i ] can store section 410[ j ][ i ][ 0 ] to the data of the section 410[ j ][ i ][ k ]. Section 410[ 0 ][ 0 ][ 0 ] to section 410[ 0 ][ 0 ][ k ], section 410[ 0 ][ i ][ 0 ] to section 410[ 0 ][ i ][ k ] or 410[ j ][ i ][ 0 ] to the section 410[ j ][ i ][ k ] may also be referred to as a CE sector. Figure 5A is a schematic diagram of data storage applied to each segment in accordance with an embodiment of the present invention. Section 410 [0 .. j] [0 .. i] [0 .. k] according to any one of the posts 510 may comprise a horizontal ECC 530. The length of the message is fixed, such as 1K bytes. The horizontal error correction code 530 is generated based on the value in the message 510. The horizontal error correction code can be a single parity correction code, an RS code, or other code that provides a correction error function. The horizontal error correction code provides segment level protection, that is, when there are errors in the number of allowable values in the message, the horizontal error correction code and other correct message values stored in the same segment can be used to restore these errors. Value. Figure 5B is a schematic diagram of a two-dimensional error correction code in accordance with an embodiment of the present invention. Each segment contains a message and a horizontal error correction code. For example, the segment 410[ 0 ][ 0 ][ 0 ] contains the message 510[ 0 ][ 0 ][ 0 ] and is used to correct the message. The wrong level of error correction code 530[ 0 ][ 0 ][ 0 ]. Assuming l =1, that is, only one storage unit is used to store the vertical error correction code. Block 510[ j ][ i ][ 0 ] stores a vertical correction code for correcting the error bit in the message 510[ 0 ][ 0 ][ 0 ] to the message 510[ j - 1 ][ i ][ 0 ] And block 530[ j ][ i ][ 0 ] is stored to correct horizontal error correction code 530[ 0 ][ 0 ][ 0 ] to horizontal error correction code 530[ j - 1 ][ i ][ 0 ] The vertical error correction code of the error bit. When there are too many error bits in a block or a hardware error occurs in the storage unit and the horizontal error correction code cannot restore the message in this block, the vertical error correction code can be used plus the correct one in other blocks. Message to try to restore the message in this block. The above-mentioned block plus a vertical error correction code for protecting the value in the block may be referred to as a Redundant Array of Independent Disk (RAID group).

Figure 6 is a block diagram of a system for performing a write job in accordance with an embodiment of the present invention. Processing unit 610 can be implemented in a variety of manners, such as with dedicated hardware circuitry or general purpose hardware (eg, a single processor, multiple processors with parallel processing capabilities, graphics processors, or other computing capable processors), and When the code or software is executed, the functions described later are provided. The information to be written from the other electronic device to the specified storage unit is stored by the processing unit access interface 250 through the direct memory access (DMA) controller 623 to the dynamic random access memory 620. . The storage unit 10 [0] [0] to 10 [j] [i] to any of a single layer may comprise a plurality of units. The multiplexer 640 can be preset to be coupled to the dynamic random access memory 620 and the buffer 650. When the processing unit 610 detects that the DRAM-Dynamic Random Access Memory 620 has stored a certain length of information, for example, a 32K byte indicates that the direct memory access controller 621 will dynamically store the random random access memory. The message stored in the memory 620 is stored in the buffer 650 via the multiplexer 640 and simultaneously stored in a buffer (not shown) in the disk array encoding unit 630. The disk array encoding unit 630 can generate a vertical error correction code based on the current stored result and the newly received message using a conventional error correction code encoding method, such as SPC (64, 63), RS (64, 62), RS. (64,61) error correction code. The processing unit 610 can include two counters, one is a message counter for counting the number of times the message has been output, and the other is an error correction code counter for counting the number of vertical error correction codes that have been output. When the number of message counters in the processing unit 610 counts to the threshold value of the outputted message, the control multiplexer 640 is configured to couple the disk array encoding unit 630 to the buffer 650 and indicate the disk array encoding unit. 630 outputs the encoded vertical error correction code to the buffer 650 in one or more batches. When the number of error correction code counters in the processing unit 610 is counted to reach a threshold, the control multiplexer 640 is configured to couple the dynamic random access memory 620 to the buffer 650 for continuing subsequent steps. Message storage job. For example, when the error correction code of RS (64, 61) is used, the processing unit 610 controls the multiplexer 640 to couple the disk array coding unit 630 when the number of times the message counter has outputted the message reaches 61 times. The buffer 650 is connected, and the message counter is reset to 0. Then, the processing unit 610 controls the multiplexer 640 to dynamically randomize when the error correction code counter counts the number of times the error correction code has been outputted to 3 times. The access memory 620 is coupled to the buffer 650 and resets the error correction code counter to zero. After each time controlling the data output of the DRAM 620 or the disk array encoding unit 630, the processing unit 610 controls the arbitration unit 660 to read the value of the sector or vertical error correction code in the buffer 650 and pass the appropriate The storage unit access interface (eg, one of the storage unit access interfaces 230[ 0 ] to 230[ j ]) writes the read value to the corresponding storage unit (eg, storage unit 10[ 0 ][ 0 ] To one of 10[ j ][ i ]). The arbitration unit 660 can activate the chip enable signal of the corresponding storage unit in the appropriate storage unit access interface, and transmit the read value and the write address to the corresponding data line in the storage unit access interface. Storage unit. Each storage unit access interface (eg, storage unit access interfaces 230[ 0 ] to 230[ j ]) further includes a horizontal error correction code circuit for reading the data in the buffer 650 in batches (probably A message or a vertical error correction code) and a horizontal error correction code is generated accordingly. In detail, the horizontal error correction code 530 is generated according to the read message 510 after the storage unit access interface reads a message of a specified length from the buffer 650 each time, for example, a 1K byte. The storage unit access interface then writes the message 510 and the generated horizontal error correction code 530 to the designated address in the designated storage unit.

7A and 7B are flowcharts of a method of writing data in a processing unit according to an embodiment of the present invention. In a write operation of a redundant array of independent disks, the processing unit 610 first sets the message counter and the error correction code counter to 0 (step S711), and controls the multiplexer 640 to couple the dynamic random access memory. The body 620 is to the buffer 650 (step S713). Then, a loop including steps S721 to S731 is repeatedly executed until the messages in a separate disk redundancy array group are written into the specified storage unit, for example, the storage unit 10[ 0 ][ 0 ] to 10[ j ][ i - l ]. In detail, the processing unit 610 detects that the dynamic random access memory 620 has stored a new message of a specified length, for example, a 32K byte (step S721), indicating that the direct memory access controller 621 will be dynamically random. The message stored in the access memory 620 is stored in the buffer 650 via the multiplexer 640 and simultaneously stored in a buffer (not shown) in the disk array encoding unit 630 (step S723). Next, the processing unit 610 controls the arbitration unit 660 to read the value in the buffer 650 and write it through an appropriate storage unit access interface (eg, one of the storage unit access interfaces 230[ 0 ] to 230[ j ]). The read value is to a corresponding storage unit (for example, one of the storage units 10[ 0 ][ 0 ] to 10[ j ][ i ]) (step S725). After the post processing unit 610 increments a counter (step S727), the message is determined whether the counter value exceeds a threshold, e.g., (j + 1) x ( i + 1) - l - 1 ( step S731). If yes, proceed to steps S733 to S751 to write the vertical error correction code in the independent disk redundancy array group; otherwise, return to step S721 to write to the independent disk redundancy array group. Completed message.

To write the vertical error correction code in the independent disk redundancy array group, the processing unit 610 controls the multiplexer 640 to couple the disk array encoding unit 630 to the buffer 650 (step S733). Then, a loop including steps S741 to S751 is repeatedly executed until the vertical error correction code in the independent disk redundancy array group is written into the specified storage unit, for example, the storage unit 10[ j ][ i - l + 1 ] to 10[ j ][ i ]. In detail, the processing unit 610 instructs the disk array encoding unit 630 to output a vertical error correction code of a specified length (for example, 32K bytes) to the buffer 650 via the multiplexer 640 (step S741). Next, the processing unit 610 controls the arbitration unit 660 to read the value in the buffer 650 and write the read value to the corresponding storage unit through an appropriate storage unit access interface (eg, the storage unit access interface 230[ j ]). The specified address in (for example, one of the storage units 10[ j ][ i - l + 1 ] to 10[ j ][ i ]) (step S743). Post-processing unit 610 to an error correction code counter is incremented (step S745), the error correction code is determined whether the value of the counter exceeds a threshold, e.g., l - 1 (step S751). If yes, go back to step S711 to continue the write operation of the next independent disk redundancy array group; otherwise, return to step S741 to write the unfinished vertical error correction code in the independent disk redundancy array group. .

Figure 8 is a flow chart of a method for writing data in a storage unit access interface in accordance with an embodiment of the present invention. This method can be applied to one of the storage unit access interfaces 230[ 0 ] to 230[ j ]. After the storage unit access interface receives the instruction to write a message of a specific length (for example, a message of 32K bytes) into the storage unit by the arbitration unit 660 (step S811), a data write including steps S821 to S831 is repeatedly executed. Enter the loop until all writes are completed. In detail, for each round of write operation, the storage unit access interface acquires a message of a specified length (for example, a 1K byte message) from the arbitration unit 660 (step S821), and generates a horizontal error correction based on the obtained message. The code (step S823), and writing the message and the generated horizontal error correction code to the address of the next sector of the designated word line in the designated storage unit (step S825). It should be noted that, in step S825, if it is the first round of the write job, the read message and the generated horizontal error correction code are written into the address of the first segment of the specified word line. . Next, the storage unit access interface determines whether or not all of the write jobs are completed (step S831). If so, the entire process is ended; otherwise, the process returns to step S821 for the next round of writing. Fig. 19A is a timing chart of data writing according to an embodiment of the present invention. The storage unit access interfaces 230[0] to 230[3] are represented by channels CH0 to CH3, respectively, and the storage units connected to each storage unit access interface are denoted by CE0 to CE3, respectively. Figure 19A is the first data in all storage units 10[ 0 ][ 0 ] to 10[ 3 ][ 3 ] written to a page PG0 (including message and horizontal error correction code, or vertical error correction code). An example of a word line WL0. The arbitration unit 660 sequentially transfers the data of the page PG0 to the buffer (not shown) in the first storage unit CE0 connected to each channel through the channels CH0 to CH3, and then sends a write command to all connected storage units. CE0, used to start the actual write job. When any of the storage units CE0 receives the write command, it then enters a busy state to write the data of the page PG0 in the buffer to the single-level cell in the word line WL0. When all the storage units CE0 start the actual data writing operation, the channels CH0 to CH3 are in an available state, so that the arbitration unit 660 can sequentially transmit the data of the page PG0 to the second connected to each channel by using the channels CH0 to CH3. A buffer (not shown) in the storage unit CE1. Those skilled in the art can observe that the channels CH0 to CH3 have less idle time due to the use of the above-described independent disk redundant array group data arrangement, and are effectively utilized to transfer data to the storage unit.

Figure 9 is a block diagram of a system for performing a read job in accordance with an embodiment of the present invention. Processing unit 910 can be implemented in a variety of manners, such as with dedicated hardware circuitry or general purpose hardware (eg, a single processor, multiple processors with parallel processing capabilities, graphics processors, or other computing capable processors), and When the code or software is executed, the functions described later are provided. The storage unit 10 [0] [0] to 10 [j] [i] to any of a single layer may comprise a plurality of units. After the storage unit access interface (one of 230 [ 0 ] to 230 [ j ]) reads the value of one of the corresponding storage units, the read content is passed to the section decoding unit 960. The section decoding unit 960 first checks whether the message therein has an error using the horizontal error correction code therein, and if so, attempts to correct using the horizontal error correction code therein. After the content of the message is correct or has been successfully modified, the segment decoding unit 960 discards the horizontal error correction code and stores the message content in the buffer 950 so that other electronic devices can read the decoded message via the processing unit access interface 250. When the segment decoding unit 960 has not used the horizontal error correction code therein to correct the error in the message, the message processing unit 910 is sent to the message including the segment address and other information that the error occurred but cannot be restored. Next, processing unit 910 initiates a vertical correction procedure. In the vertical correction procedure, the processing unit 910 first obtains the information of the independent disk redundancy array group to which the segment address belongs, and finds all other segment addresses that can be used to recover the information in the error segment address (including The sector address where the vertical error correction code is stored). For example, please refer to FIG. 5B, assuming section 410 [0] [0] [0] 510 in the post [0] [0] [0] contains the error correction code even if the level of 530 [0] [0] [ 0 ] When the error cannot be corrected, the other sections that can be used to try to correct are 410[ 0 ][ 1 ][ 0 ] to 410[ j ][ i ][ 0 ]. Next, the processing unit 910 instructs the segment decoding unit 960 that the vertical correction procedure has been initiated, determines other segments corresponding to the segments that cannot be corrected, and instructs the storage unit access interfaces 230[ 0 ] to 230[ j ] to read the specified The value of the other sections. When the vertical correction program is started, the segment decoding unit 960 sequentially obtains the value of the specified segment through the storage unit access interfaces 230[ 0 ] to 230[ j ], and transmits the value to the disk array decoding unit 930 after the decoding is completed. . The disk array decoding unit 930 can use all the required segments of the data (including the original message and the vertical error correction code) to recover the previously uncorrectable error and transmit the restored result to the buffer 950 so that other electronic devices can be The processing unit access interface 250 reads the corrected message. It should be noted that the processing unit 910 of FIG. 9 and the processing unit 610 of FIG. 6 may be the same processing unit, and the present invention is not limited thereby.

Figure 10 is a flow chart of a method of reading data in a segment decoding unit in accordance with an embodiment of the present invention. The section decoding unit 960 obtains the value of one section from one of the storage unit access interfaces 230[ 0 ] to 230[ j ] (step S1010), and checks whether the message is correct using the horizontal error correction code therein ( Step S1020). If it is correct ("YES" path in step S1020), the original message is stored in the buffer 950 (step S1070); otherwise (the path "NO" in step S1020), an attempt is made to correct the horizontal error correction code therein. There is an error in the message (step S1030). Next, the section decoding unit 960 decides whether or not the correction is successful (step S1040). If successful (the path of "Yes" in step S1040), the corrected message is stored in the buffer 950 (step S1070); otherwise (the path of "NO" in step S1040), the message is sent to the processing unit 910. The error notifying this section cannot be replied using the horizontal error correction code (step S1050).

Figure 11 is a flow chart of a method of reading data in a processing unit in accordance with an embodiment of the present invention. The processing unit 910, after receiving the notification that the specified segment cannot be replied with the horizontal error correction code from the segment decoding unit (step S1110), decides to belong to other segment addresses in the same independent disk redundancy array group (step S1120). For example, referring to FIG. 5B, when the segment 410[ 0 ][ 0 ][ 0 ] cannot be recovered using the horizontal error correction code 510[ 0 ][ 0 ][ 0 ], the processing unit 910 decides to belong to the same independent magnetic. The other segments in the disk redundancy array group are 410[ 0 ][ 1 ][ 0 ] to 410[ j ][ i ][ 0 ]. The segmentation decoding unit 960 and the disk array decoding unit 930 have been activated by the vertical correction program (step S1130). When the segment decoding unit 960 receives the indication, the specified value read by one of the storage unit access interfaces 230[ 0 ] to 230[ j ] is decoded and output to the disk array decoding unit 930. Instead of being stored in the buffer 950. Next, the processing unit 910 repeatedly performs a loop of the section content reading to instruct the storage unit access interfaces 230[ 0 ] to 230[ j ] to read the content of the specified section. In the loop, the processing unit 910 instructs the designated storage unit access interface to read the contents of the next section (step S1140). The indicated storage unit access interface transmits the read result to the section decoding unit 960. The segment decoding unit 960 decodes the message therein and transmits it to the disk array decoding unit 930, and the disk array decoding unit 930 generates a new decoding result based on the previous decoding result and the newly received message. When the processing unit 910 receives the notification of completion of reading from the indicated storage unit access interface or segment decoding unit 960 (step S1150), it is determined whether to complete all other segments belonging to the same independent disk redundancy array group. The message reading job (step S1160). If yes (the path of YES in step S1160), the loop is ended; otherwise (the path of "NO" in step S1160), the specified storage unit access interface continues to read the contents of the next section (step S1140) . When the loop ends, the processing unit 910 instructs the extent decoding unit 960 and the disk array decoding unit 930 that the vertical correction procedure has ended (step S1170). When the section decoding unit 960 receives the indication that the vertical correction procedure has ended, the value that is subsequently decoded is stored in the buffer 950 instead of being output to the disk array decoding unit 930. On the other hand, when the disk array decoding unit 930 receives the indication, the current decoding result is stored in the buffer 950 as a vertical reply result of the designated segment.

Figure 12 is a block diagram of a system for performing a write job in accordance with an embodiment of the present invention. Processing unit 1210 can be implemented in a variety of manners, such as with dedicated hardware circuitry or general purpose hardware (eg, a single processor, multiple processors with parallel processing capabilities, graphics processors, or other computing capable processors), and When the code or software is executed, the functions described later are provided. Any of the storage units 10[ 0 ][ 0 ] to 10[ j ][ i ] may include a plurality of memory units, and each of the memory units may be implemented in a three-layer unit. The processing unit 1210 can control the storage unit access interface 230 to write the value stored in the buffer 1250 to one of the storage units 10[ 0 ][ 0 ] to 10[ j ][ i ]. For each storage unit, processing unit 1210 can write values word-by-word lines, where a number of pages can be stored on one word line. Although the following is an example in which one word line contains three pages, those skilled in the art can also modify the value of writing more or fewer pages on one word line, and the present invention is not limited thereto. A page can contain 8K, 16K, 32K or 64K Bytes. Since the three-layer cell is affected by the write operation of the adjacent word line, the original stored charge leaks, or more charges are drawn, causing the threshold voltage to change. Therefore, it is necessary to repeat the writing operation several times to avoid The problem caused the stored value represented in the unit to change. The technical solution described below can also be referred to as a F&F (foggy and fine) writing method. 17A to 17C are diagrams showing threshold voltage distributions of a plurality of three-layer cells on one word line after three write operations in accordance with an embodiment of the present invention. After the first write operation, the critical voltage distribution is shown by the solid line in Fig. 17A. It can be observed from Fig. 17A that after the first rough write operation, the critical voltage distribution cannot produce eight distinct states. Then, when a neighboring word line performs a write operation, it will affect the charge originally stored by the three-layer cell on the word line, making the threshold voltage distribution worse. The critical voltage distribution after the influence is shown by the broken line in Fig. 17A. In order to make the number of charges actually stored in the three-layer unit closer to the ideal value, the second write operation is performed, and the threshold voltage distribution after the second write operation is as shown by the solid line in FIG. 17B. It can be observed from Fig. 17B that after the second write operation, the critical voltage distribution can produce eight distinct states. However, when affected by subsequent write operations of adjacent word lines, a slight overlap occurs between the eight states in this threshold voltage distribution. The critical voltage distribution after the influence is shown by the broken line in Fig. 17B. In order to re-adjust the affected results, the word line will perform a third write operation, allowing for a wider gap between the eight states in the threshold voltage distribution. Please refer to Figure 17C for the threshold voltage distribution after the third write operation.

Referring back to FIG. 12, in this architecture, it is assumed that the capacity of the buffer 1250 can store values of three pages. Therefore, the dynamic random access memory 1240 needs to be temporarily stored in the electronic device through the processing unit access interface 250. The value of the nine pages. The processing unit 1210 can instruct the direct memory access (DMA controller) 1220 to store the value on the processing unit access interface 250 to the specified address in the dynamic random access memory 1240, and receive the new address. The value of a page overwrites the value of the oldest stored page. It should be noted that the value of the page written by the overlay has been stably stored in the specified storage unit after three times of writing. The DRAM 1240 can be integrated into a system on chip (SOC) comprising components 230 [ 0 .. j ], 250, 1210, 1220, 1230, and 1250, or implemented in a separate wafer. In the actual write operation, the processing unit 1210 may instruct the direct memory access controller 1230 to read the values of the three pages from the dynamic random access memory 1240 and store them in the buffer 1250, and then access through the storage unit. One of the interfaces 230[0] through 230[j] writes the value in the buffer 1250 to the three-level cell on the specified word line in the specified storage unit. Figure 13 is a schematic diagram of a three-layer cell block (TLC block) in a memory cell in accordance with an embodiment of the present invention. The three-level cell block 1300 may contain a total of 192 pages of values, with page numbers PG0 through PG191. The value of three pages can be stored on each character line, and the word line labels are WL0 to WL63. Referring to Figure 16C, the lowest bits indicated in all three-level cells on each character line are grouped together to become a page value. Similarly, the middle bits and the highest bits indicated in all three-tier units are grouped together to become the values of the other two pages. In order to stabilize the stored values, the processing unit 1210 needs to use two batches in addition to writing the values of the three most recently received pages in the DRAM 1240 to the three-level cell block 1300. The DRAM 1240 reads the values of the six pages that have been previously written to the buffer 250, and uses the specified storage unit access interface to write to the three-layered line on the specified word line in the specified storage unit. unit. For example, after writing the three-level cells on the pages PG6 to PG8 to the word line WL2, the processing unit 1210 instructs the direct memory access controller 1230 to read the values of the pages PG0 to PG2 from the dynamic random access memory 1240. And storing in the buffer 250, and using the storage unit access interface 230 to write the value in the buffer 250 to the memory unit on the word line WL0, and then instructing the direct memory access controller 1230 from the dynamic random access. The memory 1240 reads the values of the pages PG3 through PG5 and stores them in the buffer 250, and uses the storage unit access interface 230 to write the values in the buffer 250 to the memory cells on the word line WL1. Figure 21 is a diagram showing the sequence of writing of word lines in accordance with an embodiment of the present invention. This write order for a single storage unit can be recorded in a lookup table 2100 for the processing unit 1210 to determine the word line or page to be written each time. The lookup table contains three columns that record the order of each of the word lines WL0 to WL63 between the first, second, and third writes. Since the value in the three-layer unit needs to be repeated for several times, the processing unit 1210 needs to first determine the storage unit when receiving the data reading command from other electronic devices through the processing unit access interface 250. Whether the stored value has stabilized. If yes, the one of the specified storage unit access interfaces 230[ 0 ] to 230[ j ] reads the value of the specified address in the specified storage unit and replies to the requested electronic device; if not, then The DRAM 1240 reads the value of the specified address to be stored in the specified storage unit and replies to the requested electronic device. It should be noted that information about the address stored in the storage unit for the value temporarily stored in the DRAM 1240 can be stored in the DRAM 1240 or the register (register, Not shown, and the processing unit 1210 can use this information to determine whether the value to be read by other electronic devices has been stably stored in the specified storage unit. In detail, if the information stored in the DRAM 1240 or the scratchpad indicates that the temporarily stored value of the DRAM 1240 is stored in the read address, it means that it is to be read. The value taken has not been stored stably in the storage unit.

Figure 14 is a flow diagram of a method of writing performed in a processing unit in accordance with an embodiment of the present invention. After the processing unit 1210 receives the write command and the write address issued by the other electronic device through the processing unit access interface 250 (step S1410), the direct memory access controller 1220 instructs the value to be written by the processing unit. The access interface 250 is moved to the dynamic random access memory 1240 (step S1420). Determining whether the value of the specified number of pages has been received (step S1430), for example, the value of the nth to n + 2 pages, and if so, performing the actual write operation (step S1440 to step S1470); otherwise, continuing to pass through the processing unit The access interface 250 receives the value that has not been transmitted (step S1410 to step S1420). In the actual write operation, the processing unit 1210 instructs the direct memory access controller 1230 to store the value of the specified number of pages temporarily stored in the DRAM 1240 to the buffer 1250 (step S1440), indicating The storage unit access interface 230 writes the value in the buffer 1250 to the three-layer unit on the specified word line in the specified storage unit (step S1450). Next, in order to avoid the previously written value from being affected by the write operation, the processing unit 1210 further uses two batches to indicate that the direct memory access controller 1230 will be temporarily stored in the dynamic random access memory 1240. The values of the six pages that have been recently written to the storage unit are again stored in the buffer 1250. In detail, the processing unit 1210 instructs the direct memory access controller 1230 to store the values of the third to first pages before being temporarily stored in the DRAM 1240 to the buffer 1250, for example, the n - 3 a value to n - 1 page, and instructing the specified storage unit access interface to rewrite the value in the buffer 1250 to the three-layer unit on the specified word line in the specified storage unit (step S1460), and the processing unit 1210 instructs the direct memory access controller 1230 to store the values of the sixth to fourth pages temporarily stored in the DRAM 1240 to the buffer 1250, for example, the values of the n - 6th to n - 4th pages. And instructing the specified storage unit access interface to rewrite the value in the buffer 1250 to the three-layer unit on the designated word line in the specified storage unit (step S1470).

Figure 15 is a flow chart of a method of writing executed in a processing unit in accordance with an embodiment of the present invention. After the processing unit 1210 receives the read command and the read address issued by the other electronic device through the processing unit access interface 250 (step S1510), it is determined whether the value of the address to be read has not been stably stored in the storage unit ( Step S1520). If so, the direct memory access controller 1220 is instructed to read the requested value from the dynamic random access memory 1240 and reply to the requested electronic device through the processing unit access interface 250 (step S1530); otherwise, access through the storage unit The interface reads the value of the specified address from the storage unit (step S1540), and replies the read value to the requesting electronic device through the processing unit access interface 250 (step S1550).

In order to protect the data stored in the three-layer unit (including the message and the horizontal error correction code), the vertical error correction code can be further stored to form a two-dimensional error correction code. In order to improve the efficiency of writing data, the embodiment of the present invention proposes a new message and a method for placing an error correction code. Figure 18A is a diagram showing the arrangement of data of a redundant array of independent disks using an RS (48, 45) vertical error correction code according to an embodiment of the present invention. Suppose i = 3 , j = 3 and each word line can store three pages of messages and horizontal error correction codes, or three pages of vertical error correction codes. A total of 48 pages stored in the first word line WL0 of the 16 storage units 10[ 0 ][ 0 ] to 10[ 3 ][ 3 ] may form an independent disk redundancy array group. Therein, three pages of vertical error correction codes are stored in the first word line WL0 (shaded portion) in the storage unit 10[3][3]. Figure 18B is a diagram showing the arrangement of data of a redundant array of independent disks using an RS (96, 93) vertical error correction code according to an embodiment of the present invention. A total of 16 storage unit 10 [0] [0] to 10 [3] [3] in the first and second two word lines WL0 a redundant array of independent disk WL1 and stored in page 96, can be formed Group. Therein, three pages of vertical error correction codes are stored in the second word line WL1 (shaded portion) in the storage unit 10[3][3]. Since each page data in a redundant array of independent disks is separately placed in different physical storage units, it can avoid the situation that the data cannot be recovered when one of the storage units fails to recover. . In addition, the placement method described above can also improve the efficiency of data writing. Please refer to Figure 6. Processing unit 610 can instruct arbitration unit 660 to write material to the first word line in each storage unit in a predefined order. Fig. 19B is a timing chart of data writing according to an embodiment of the present invention. The storage unit access interfaces 230[0] to 230[3] are represented by channels CH0 to CH3, respectively, and the storage units connected to each storage unit access interface are denoted by CE0 to CE3, respectively. Figure 19B is a data (including message and horizontal error correction code, or vertical error correction code) written to three pages PG0, PG1 and PG2 to all storage units 10[ 0 ][ 0 ] to 10[ 3 ][ An example of the first word line WL0 in 3 ]. The arbitration unit 660 sequentially transfers the data of the three pages PG0, PG1, and PG2 to the buffer (not shown) in the first storage unit CE0 connected to each channel through the channels CH0 to CH3, and then sends a write command. All connected storage units CE0 are used to start the actual write operation. When any one of the storage units CE0 receives the write command, it then enters a busy state to write the data of the three pages PG0, PG1 and PG2 in the buffer to the third layer in the word line WL0. Unit. When all the storage units CE0 start the actual data writing operation, the channels CH0 to CH3 are in an available state, so that the arbitration unit 660 can sequentially transfer the data of the three pages PG0, PG1, and PG2 to each channel by using the channels CH0 to CH3. The second storage unit CE1 is connected. Those skilled in the art can observe that the channels CH0 to CH3 have less idle time due to the use of the above-described independent disk redundant array group data arrangement, and are effectively utilized to transfer data to the storage unit.

The storage units 10[ 0 ][ 0 ] to 10[ j ][ i ] in the architecture shown in FIG. 6 can also be modified to include a plurality of three-layer units. 20A to 20D are flowcharts of a method of writing data executed in a processing unit according to an embodiment of the present invention. In a write operation of a redundant array of independent disks, the processing unit 610 first sets the message counter and the error correction code counter to 0 (step S2011), and controls the multiplexer 640 to couple the dynamic random access memory. The body 620 is to the buffer 650 (step S2013). Then, a loop including steps S2021 to S2087 is repeatedly executed until the message in the independent disk redundancy array group is written into the specified storage unit, for example, the storage unit 10[ 0 ] shown in FIG. 18A. [0] to 10 [3] [3] of the word lines WL0, or, as shown in FIG. 18B, the storage unit 10 [0] [0] to 10 [3] [3] of the word line WL0 and WL1.

Steps S2021 to S2031 are preparation steps of writing data to a specific word line in all the storage units. The processing unit 610 uses the variable q to determine which storage unit access interface is used for this write, and uses the variable p to determine the number of storage units written to the storage unit access interface. In order to stabilize the values stored in the three-layer cell, reference can be made to the word line write method as described in FIG. 14 so that each word line can be written three times repeatedly and in an interleaved manner. In the first memory cell write job of each word line, the variables p = 0 and q = 0 are set (step S2021). For the storage unit 10[ q ][ p ], the processing unit 610 decides the word line or page to be written, for example, the word line WL0 or the pages PG0 to PG2 (step S2023). The processing unit 610 can refer to the write sequence as shown in FIG. 21 to determine the word line or page to be written. Then, the message counter is selectively maintained at 0 or MAXixMAXjxn , and the error correction code counter is set to 0, wherein the constant MAXj represents the total number of storage unit access interfaces, and the constant MAXi represents the storage connected to each storage unit access interface. total number of units, the variable n is the total number of word lines has been completed (step S2025) represents. Taking the data placement of the independent disk redundancy array group using the RS (96, 93) error correction code shown in FIG. 18B as an example, when the write job is associated with the word line WL0, the message counter is used. Maintain at 0 . When this write job is associated with the word line WL1, the message counter is set to 4x4x1 = 16 .

Steps S2031 to S2035 are used to write the message and the horizontal error correction code to the specified storage unit 10[ q ][ p ]. The processing unit 610 instructs the direct memory access controller 621 to store the three page messages stored in the dynamic random access memory 620 to the buffer 650 via the multiplexer 640 and simultaneously store them in the disk array encoding unit 630. A buffer (not shown) (step S2031). Next, the processing unit 610 controls the arbitration unit 660 to read the value in the buffer 650 and instructs the storage unit access interface 230[ q ] to write to the storage unit 10[ q ][ p ] (step S2033). Next, the processing unit 610 adds three to the message counter (step S2035). For the write timing of all memory cells, refer to the description of Figure 19.

Steps S2041 and S2081 to S2087 are used to determine which storage unit access interface and storage unit the next write operation is for. When the processing unit 610 determines that the value of the message counter is less than the threshold (the path of NO in step S2041), the variable q is incremented by one (step S2081). Taking the data placement of the independent disk redundancy array group using the RS (96, 93) error correction code shown in Figure 18B as an example, the value of the message counter is smaller than the threshold (such as 93) to represent an independent magnetic field. The messages in the Dish Redundant Array group have not yet been written. Next, it is determined whether the variable q is greater than or equal to the constant MAXj (step S2083), and if not, the flow proceeds to step S2031; if so, the variable p is incremented by one and the variable q is set to 0 (step S2085), and then It is judged whether or not the variable p is greater than or equal to the constant MAXi (step S2087). When the variable p is greater than or equal to the constant MAXi (the path of YES in step S2087), the designated word line in all the storage units has been written, and the flow proceeds to step S2021 to continue the next character. Line write job. Otherwise (the path of "NO" in step S2087), the flow proceeds to step S2031.

Since the vertical error correction code is also to be written three times to be stable, the embodiment of the present invention provides a program for temporarily storing the first generated vertical error correction code in the dynamic random access memory 620, and subsequently re- The vertical error correction code that has been generated is directly retrieved from the dynamic random access memory 620 at the time of writing without recalculation. For example, the data placement of the independent disk redundancy array group using the RS (96, 93) error correction code shown in FIG. 18B is taken as an example. In another embodiment, when the disk array coding unit 630 is to be generated corresponding to the storage. When the vertical error correction code of the word line WL1 of the cell 10[3][3] is reloaded from the dynamic random access memory 620 into the word lines WL0 and WL1 to be stored in the 16 memory cells. To generate a vertical error correction code, however, this will take a lot of time. Steps S2051 to S2079 are for writing a vertical error correction code to the specified storage unit 10[ q ][ p ]. When the processing unit 610 determines that the value of the message counter is greater than or equal to the threshold (the path of YES in step S2041), the variable p is incremented by one (step S2051). Then, it is determined whether the vertical error correction code of the independent disk redundancy array group has been generated (step S2053), and the storage unit access interface 230[ q ] is temporarily stored in the dynamic random access memory 620. The result is previously calculated and written to the storage unit 10[ q ][ p ] (steps S2061 to S2068); otherwise, the storage unit access interface 230[ q ] is taken to obtain the encoding result of the disk array encoding unit 630, and written To the storage unit 10[ q ][ p ] (steps S2071 to S2079).

The loops as shown in steps S2071 to S2079 are repeatedly executed until all the vertical error correction codes generated by the disk array encoding unit 630 are written into the designated storage unit. In detail, the processing unit 610 controls the multiplexer 640 to couple the disk array encoding unit 630 and the buffer 650 (step S2071), and instructs the disk array encoding unit 630 to perform the three-page vertical error correction code via multiplexing. The 640 is output to the buffer 650, and instructs the direct memory access controller 621 to store the calculation result of the buffer (not shown) in the disk array encoding unit 630 into the dynamic random access memory 620 (step S2073). . Next, the processing unit 610 controls the arbitration unit 660 to read the value in the buffer 650 and instruct the storage unit access interface 230[ q ] to write to the specified word line in the storage unit 10[ q ][ p ] (step S2075) ). The processing unit 610 adds three to the error correction code counter (step S2076), and determines whether the value of the error correction code counter is greater than or equal to a threshold value, for example, a constant l (step S2077). If yes, proceed to step S2069; otherwise, after the variable p is incremented (step S2079), return to step S2073 for writing the unfinished vertical error correction code in the independent disk redundancy array group.

The loops shown in steps S2061 to S2068 are repeatedly executed until all the vertical error correction codes temporarily stored in the DRAM 620 are written to the designated storage unit. In detail, the processing unit 610 instructs the direct memory access controller 621 to store the three-page vertical error correction code temporarily stored in the dynamic random access memory 620 to the buffer 650 via the multiplexer 640 (step S2061). Next, the processing unit 610 controls the arbitration unit 660 to instruct the storage unit access interface 230[ q ] to read the value in the buffer 650 and write to the specified word line in the storage unit 10[ q ][ p ] (step S2063) ). The processing unit 610 adds three to the error correction code counter (step S2065), and determines whether the value of the error correction code counter is greater than or equal to a threshold value, for example, l (step S2067). If yes, proceed to step S2069; otherwise, after the variable p is incremented (step S2068), return to step S2061 for writing the unfinished vertical error correction code in the independent disk redundancy array group. Finally, the processor unit 610 determines whether all the write operations are completed (step S2069), and then ends the entire data write process; otherwise, the control multiplexer 640 is coupled to the dynamic random access memory 620 and the buffer 650. (Step S2080), returning to step S2021, the data writing operation of the next independent disk redundancy array group is continued. The technical details of steps S2033, S2063 and S2075 can be referred to the description of FIG.

Although it is included in Figures 1 to 3, Figure 6, Figure 9, and Figure 12 The components described above, but do not exclude the use of more additional components without departing from the spirit of the invention, have achieved better technical results. Further, although the flowcharts of FIGS. 7A to 7B, 8 and 10 to 11, 14 to 15 and 20A to 20D are executed in a specified order, without the spirit of the invention, Those skilled in the art can modify the order among these steps while achieving the same effect, and therefore, the present invention is not limited to the use of only the order as described above. In addition, those skilled in the art may also integrate several steps into one step, or in addition to these steps, performing more steps sequentially or in parallel, and the present invention is not limited thereby.

Although the present invention has been described using the above embodiments, it should be noted that these descriptions are not intended to limit the invention. On the contrary, this invention covers modifications and similar arrangements that are apparent to those skilled in the art. Therefore, the scope of the claims should be interpreted in the broadest form to include all obvious modifications and similar arrangements.

S1510~S1550‧‧‧ method steps

Claims (12)

A method for accessing a storage unit in a flash memory is performed by a processing unit, comprising: determining, by a processing unit access interface, a read command sent by an electronic device and a read address Whether the value of the read address has not been subjected to at least three write operations to a storage unit; and if so, instructing a memory access controller to read the requested value from a dynamic random access memory and The processing unit access interface is replied to the electronic device. The method for accessing a storage unit in a flash memory according to claim 1, further comprising: if not, reading the value of the read address from the storage unit through a storage unit access interface, and The read value is replied to the electronic device through the processing unit access interface. The method for accessing a storage unit in a flash memory according to the first aspect of the invention, wherein the determining step further comprises: storing, by using the dynamic random access memory or a temporary storage device; The value temporarily stored in the DRAM is stored in the information of the address in the storage unit to determine whether the value associated with the read address has not been stably stored in the storage unit. The method for accessing a storage unit in a flash memory according to claim 1, wherein the storage unit comprises a plurality of three-layer units, and each three-layer unit stores a value of three bits. Accessing the memory unit in the flash memory as described in claim 4 The method, wherein the lowest bits of the plurality of three-layer cells on a character line are combined to form a first page, and the middle bits of the three-layer unit on the character line are combined to form a second page. And the highest bits of the above three-layer unit on the character line are combined to form a third page. The method for accessing a storage unit in a flash memory according to claim 5, wherein the DRAM temporarily stores at least nine pages recently transmitted by the processing unit access interface. value. An apparatus for accessing a storage unit in a flash memory, comprising: a storage unit access interface coupled to a storage unit; a processing unit access interface coupled to an electronic device; and a processing unit coupled Connecting to the storage unit access interface and the processing unit access interface, and receiving, by the processing unit access interface, a read command and a read address sent by the electronic device, determining that the read bit is associated with the read bit Whether the value of the address has not been subjected to at least three write operations to the storage unit; and, if so, instructing a memory access controller to read the requested value from a dynamic random access memory and storing the value through the processing unit The interface is replied to the electronic device. The apparatus for accessing a storage unit in a flash memory according to claim 7, wherein, if not, the processing unit reads the read address from the storage unit through the storage unit access interface. And returning the value read out to the electronic device through the processing unit access interface. The storage order in the access flash memory as described in claim 7 of the patent application scope And the processing unit, wherein the processing unit stores, by the dynamic random access memory or a temporary register, a storage address in the storage unit in which the value temporarily stored in the dynamic random access memory is stored. The information is used to determine whether the value associated with the above read address has not been stably stored in the storage unit. The device for accessing a storage unit in a flash memory according to claim 7, wherein the storage unit comprises a plurality of three-layer units, and each three-layer unit stores a value of three bits. The device for accessing a storage unit in a flash memory according to claim 10, wherein the lowest bits of the plurality of three-layer units on a character line are combined to form a first page, the word The middle bits of the above-mentioned three-layer unit on the meta line are combined to form a second page, and the highest bits of the above-mentioned three-layer unit on the word line are combined to form a third page. The apparatus for accessing a storage unit in a flash memory according to claim 11, wherein the dynamic random access memory temporarily stores at least nine pages recently transmitted by the processing unit access interface. Value.