TWI628741B - Integrated circuit, semiconductor device based on integrated circuit, and standard cell library - Google Patents

Abstract

An integrated circuit (IC) may include at least one unit, the at least one unit comprising: a plurality of conductive lines extending in a first direction and parallel to each other in a second direction perpendicular to the first direction; Points respectively disposed at two sides of at least one of the plurality of conductive lines; and a second contact disposed on the at least one conductive line and the first contact, and electrically connected to the at least one The conductive line and the first contact form a single node.

Description

Integrated circuit, integrated circuit based semiconductor component and standard cell library [Cross-reference to related applications]

Korean Patent Application No. 10-2015, filed on July 22, 2014, in the U.S. Patent Application No. 62/027,401, filed on Jan. 22, 2014, and filed on Jan. 9, 2015, at the Korean Intellectual Property Office. The disclosure of the two applications, the disclosure of which is hereby incorporated by reference in its entirety.

Example embodiments of the inventive concept relate to an integrated circuit (IC) including at least one unit, a semiconductor device based on the IC, and/or a standard cell library storing information about the semiconductor device.

As the size of the transistor is reduced and semiconductor fabrication techniques are further developed, more transistors can be integrated into the semiconductor device. By way of example, a system that integrates all components of a computer or other electronic system into an integrated circuit (IC) in a single wafer. A system-on-chip (SOC) is used in a variety of applications. Increasing performance requirements for applications may require semiconductor devices that include more components.

According to at least one example embodiment of the inventive concept, an integrated circuit (IC) may include at least one unit including a plurality of conductive lines extending in a first direction and parallel to a second direction Positioning with each other, the second direction is perpendicular to the first direction; the first contacts are respectively disposed at two sides of the at least one of the plurality of conductive lines; and the second contact is disposed at the at least one conductive line And forming a single node by electrically connecting to the at least one conductive line and the first contact.

According to other example embodiments of the inventive concepts, a semiconductor device may include: a substrate including a first active region and a second active region having different conductivity types; a plurality of conductive lines extending in the first direction and at the The two directions are disposed parallel to each other, the second direction is perpendicular to the first direction; the first contacts are respectively disposed at two sides of the at least one of the plurality of conductive lines; and the second contact is disposed Forming a single node at least one of the first active region and the second active region at least one of the conductive lines and the first contact, and by electrically connecting to the at least one conductive line and the first contact.

According to other example embodiments of the inventive concept, a standard cell library stored in a non-transitory computer readable storage medium may contain information about a plurality of standard cells. At least one of the plurality of standard cells includes: a first active region and a second active region, the first active region and the second active region having different conductivity types; a plurality of fins, Arranging parallel to each other in the first and second active regions; a plurality of electrically conductive lines extending in the first direction and disposed parallel to each other in the second direction over the plurality of fins, the second direction being perpendicular to a first direction; a first contact disposed on each side of at least one of the plurality of conductive lines; and a second contact electrically connected to the at least one conductive line and the first and second A first node of at least one of the active zones forms a single node.

According to other example embodiments, a semiconductor device may include: a substrate including a first active region having a first conductivity type, and a second active region having a second conductivity type different from the first conductivity type; a plurality of gate electrodes Extending in a first direction such that the plurality of gate electrodes are parallel to each other in the second direction, the second direction being perpendicular to the first direction; the first contact being at the gate electrode of the plurality of gate electrodes At each of the two sides, the skip gate electrode is one of a plurality of gate electrodes connected to the first junction; and a second junction electrically coupled to the skipped gate electrode and said The first contact in the first active area is such that the second contact, the at least one conductive line, and the first contact form a single node in the first active area.

The semiconductor device may include at least one asymmetrical gated integrated circuit (asymmetrical gated IC), and the asymmetric gate IC includes a larger number of transistors in the second active region than the first active region.

The transistor can be a fin transistor.

The semiconductor device may further include a plurality of fins extending in the second direction below the plurality of gate electrodes extending in the first direction such that the plurality of fins and the plurality of gate electrodes correspond to the fin transistors.

100A, 100A', 100B, 100C, 100C', 100D, 200, 200', 300, 300', 400, 400' ‧ ‧ ‧ integrated circuits

100a, 100c, 100d, 200A, 200a, 200B‧‧‧ semiconductor devices

110, 210, 210'‧‧‧ substrates

140a, 140e, 240a‧‧‧ first conductive line

140b, 140f, 240b‧‧‧ second conductive line

140c, 140g, 240c‧‧‧ third conductive line

140h‧‧‧fourth conductive line

150a, 150b, 150c, 150d, 250a, 250b, 250c, 250d‧‧‧ contacts

150b'‧‧‧ first right contact

150e‧‧‧First Center Contact

160a, 160b, 160c‧‧‧ second joint

215‧‧‧First insulation

220a, 420a‧‧‧First active area

220b, 420b‧‧‧Second active area

230a, 230a', 430a‧‧‧ first fin

230b, 230b', 430b‧‧‧ second fin

230c, 230c', 430c‧‧‧ third fin

230d, 430d‧‧‧ fourth fin

230e, 430e‧‧‧ fifth fin

230f, 430f‧‧‧ sixth fin

233‧‧‧First insulation

233', 236‧‧‧second insulation

240a, 240a'‧‧‧ gate electrode

260, 460‧‧‧ second joint

270, 470‧‧‧ cutting area

380a, 380b, 380c‧‧‧ third joint

425a‧‧‧Second device separation zone

425b‧‧‧Second device separation zone

425c‧‧‧Second device separation zone

430g‧‧‧ seventh fin

430h‧‧‧ eighth fin

430i‧‧‧Ninth fin

430j‧‧‧ tenth fin

440a, 440e‧‧‧ dummy gate electrode

440b, 440c, 440d‧‧‧ gate electrodes

450a‧‧‧Source contact

450b‧‧‧汲 contact

480‧‧‧ input terminal

485‧‧‧Input contacts

490‧‧‧Output terminal

500‧‧‧Computer-readable storage media

510‧‧‧ Positioning and wiring program

520‧‧ ‧Library

530‧‧‧ Analysis program

540‧‧‧Information structure

1000‧‧‧ memory card

1100‧‧‧ controller

1200‧‧‧ memory

2000‧‧‧ Computing System

2100‧‧‧ processor

2200‧‧‧ memory device

2300‧‧‧Storage device

2400‧‧‧Power supply

2500‧‧‧Input/Output (I/O) devices

2600‧‧ ‧ busbar

A, B, C‧‧‧ nodes

D1a, D1b, D2a, D2b‧‧‧ distance

H1a, H1b, H1b', H2a, H2b‧‧‧ height

NA1‧‧‧ first node area

NA2‧‧‧Second node area

NA3‧‧‧ third node area

ND1‧‧‧ first node

ND2‧‧‧ second node

ND3‧‧‧ third node

NM1‧‧‧First N-type gold oxide semiconductor (NMOS) transistor

NM2‧‧‧Second N-type MOS transistor

PM1‧‧‧First P-type metal oxide semiconductor (PMOS) fin transistor

PM2‧‧‧Second P-type metal oxide semiconductor (PMOS) fin transistor

PM3‧‧‧ Third P-type metal oxide semiconductor (PMOS) fin transistor

R1‧‧‧ first district

R2‧‧‧Second District

S1, S2‧‧‧ space

W1a, W1b, W1c, W2a, W2b, W2c‧‧‧Width

Lines III-III', VIII-VIII', XII-XII', XIV-XIV', XVI-XVI'‧‧

Example embodiments of the inventive concept will be more clearly understood from the following detailed description of the embodiments of the invention, in which: FIG. 1 is a layout illustrating a portion of an integrated circuit (IC) according to an example embodiment.

2 is a layout illustrating a portion of an IC in accordance with another example embodiment.

3 is a cross-sectional view taken along line III-III' of FIG. 1 illustrating an example of a semiconductor device having the layout of FIG. 1.

4 is a layout illustrating a portion of an IC that is substantially identical to the example embodiment of FIG. 1.

FIG. 5 is a diagram illustrating a layout of a portion of an IC according to another example embodiment.

FIG. 6 is a cross-sectional view illustrating an example of a semiconductor device having the layout of FIG. 5.

FIG. 7 is a diagram illustrating a layout of a portion of an IC according to another example embodiment.

FIG. 8 is a cross-sectional view taken along line VIII-VIII' of FIG. 7 illustrating an example of a semiconductor device having the layout of FIG. 5.

9 is a layout illustrating a portion of an IC substantially identical to the example embodiment of FIG. 5.

FIG. 10 is a diagram illustrating a layout of an IC according to another example embodiment.

11 is a layout illustrating an IC substantially the same as the example embodiment of FIG.

FIG. 12 is a perspective view illustrating an example of a semiconductor device having the layout of FIG.

FIG. 13 is a cross-sectional view of the semiconductor device taken along line XII-XII' of FIG. Sectional view.

FIG. 14 is a perspective view illustrating another example of a semiconductor device having the layout of FIG.

FIG. 15 is a cross-sectional view illustrating the semiconductor device taken along line XIV-XIV' of FIG. 14.

16 is a cross-sectional view, taken along line XVI-XVI' of FIG. 10, illustrating a semiconductor device having the layout of FIG.

FIG. 17 is a diagram illustrating a layout of an IC according to another example embodiment.

18 is a layout illustrating a portion of an IC substantially identical to the example embodiment of FIG.

Fig. 19 is a circuit diagram showing the IC of Fig. 17.

Fig. 20 is a circuit diagram for explaining in detail the third node area of Fig. 19.

21 is a diagram illustrating a layout of an IC according to another example embodiment.

22 is a layout illustrating a portion of an IC substantially identical to the example embodiment of FIG. 21.

23 is a block diagram illustrating a storage medium in accordance with an example embodiment.

FIG. 24 is a block diagram illustrating a memory card including an IC according to an example embodiment.

25 is a block diagram illustrating a computing system including an IC in accordance with an example embodiment.

Reference will now be made in detail to the exemplary embodiments embodiments embodiments provide The present invention is to be considered as being thorough and complete, and the embodiments of the present invention will be fully conveyed by those skilled in the art. Specific example embodiments will be described in the drawings, and the specific example embodiments are described in detail in the written description. However, the present invention is not intended to limit the concept of the invention to the specific mode of practice, and all changes, equivalents, and alternatives are not to be For the sake of convenience of explanation, the size of the components in the drawings can be exaggerated. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items. When preceded by a list of components, an expression such as "at least one of" modifies the entire list of elements and does not modify the individual elements of the list.

The terms used in the specification are only used to describe specific example embodiments and are not intended to limit the inventive concept. Expressions used in the singular encompasses the plural forms of expression unless they have a clearly different meaning in the context. In the present specification, the terms "including," "having," and "including" are intended to mean the presence of the features, numbers, steps, acts, components, components, or combinations thereof disclosed in the specification, and are not intended The possibility of one or more other features, numbers, steps, actions, components, components, or combinations thereof may be eliminated.

Although various terms such as "first" and "second" may be used to describe various components, these components should not be limited to the above terms. The above terms are only used to distinguish one component from another. For example, within the scope of the inventive concept, a first component can be termed a second component, and vice versa.

All terms used in the description, including technical or scientific terms, have the same meaning as commonly understood by those skilled in the art of the example embodiments of the present invention, unless otherwise defined. It should be further understood that the term should be used (such as those terms defined in commonly used dictionaries) are to be interpreted as having a meaning consistent with their meaning in the context of the prior art, and should not be construed as having an idealized or excessively formal meaning unless it is clearly stated in this specification. Defined.

FIG. 1 is a layout illustrating a portion of an integrated circuit (IC) 100A according to an example embodiment.

Referring to Figure 1, IC 100A can include at least one cell defined by cell boundaries indicated by thick lines. The unit may include first to third conductive lines 140a to 140c, a first contact 150a and a first contact 150b, and a second contact 160a. Although not illustrated, a plurality of conductive lines (eg, metal lines) may be additionally disposed at an upper portion of the unit.

According to some example embodiments, the unit may be a standard unit. According to the method of designing the standard cell layout, the reusing device such as the OR gate or the AND gate is pre-designed as a standard unit and stored in the computer system, and the standard unit is placed in the required position during the layout design procedure. And connected. Therefore, the layout can be designed in a relatively short time.

The first to third conductive lines 140a to 140c may extend in a first direction (eg, the Y direction). Also, the first to third conductive lines 140a to 140c may be disposed parallel to each other in a second direction (for example, the X direction) substantially perpendicular to the first direction. The first to third conductive lines 140a to 140c may be formed of a material having conductivity such as polysilicon, metal, and metal alloy.

According to example embodiments, the first conductive line 140a to the third conductive line 140c may correspond to a gate electrode. However, example embodiments are, for example, not limited thereto, and the first to third conductive lines 140a to 140c may be conductive traces. Also, although the unit illustrated in FIG. 1 includes the first conductive line 140a to the third conductive line 140c, Example embodiments are not limited thereto. For example, the unit can include four or more conductive lines that extend in a first direction and are parallel to each other in a second direction.

The first contact 150a and the first contact 150b may extend in the first direction. Also, the first contact 150a and the first contact 150b may be disposed parallel to each other in a second direction substantially perpendicular to the first direction. The first contact 150a and the first contact 150b may be formed of a conductive material such as polysilicon, metal, and metal alloy. Therefore, the first contact 150a and the first contact 150b may provide a power voltage or a ground voltage into a lower region between the first conductive line 140a to the third conductive line 140c.

According to some example embodiments, the first contact 150a and the first contact 150b may be disposed at both sides of the second conductive line 140b, respectively. Specifically, the first contact 150a and the first contact 150b may include: a first left contact 150a disposed at a left side of the second conductive line 140b, and a first portion disposed at a right side of the second conductive line 140b Right junction 150b. In other words, the first left contact 150a may be disposed between the first conductive line 140a and the second conductive line 140b, and the first right contact 150b may be disposed between the second conductive line 140b and the third conductive line 140c .

According to some example embodiments, the length of the first left contact 150a in the second direction (ie, the width W1a) may be smaller than the space S1 between the first conductive line 140a and the second conductive line 140b. Likewise, the length of the first right contact 150b in the second direction (ie, the width W1b) may be smaller than the space S1 between the second conductive line 140b and the third conductive line 140c. According to an example embodiment, the width W1a of the first left contact 150a and the width W1b of the first right contact 150b may be substantially the same. However, example embodiments are not limited thereto. For example, according to another example embodiment, the width W1a of the first left contact 150a may be different from the width W1b of the first right contact 150b.

The second contact 160a can be disposed on the second conductive line 140b and the first contact 150a and the first contact 150b, and can be electrically connected to the second conductive line 140b and the first contact 150a and the first contact 150b forms a single node. Also, the second contact 160a may extend in the second direction, and thus the second contact 160a may be disposed in a direction horizontally intersecting the second conductive line 140b and the first contact 150a and the first contact 150b. The second contact 160a may be formed of a conductive material such as polysilicon, metal, and metal alloy. Accordingly, the second junction 160a can provide, for example, the same power voltage or the same ground voltage to the second conductive line 140b and the first contact 150a and the first contact 150b.

According to some example embodiments, the length of the second contact 160a in the second direction (ie, the width W1c) may be greater than the distance D1a between the first left contact 150a and the first right contact 150b, and is smaller than the first conductive A distance D1b between the line 140a and the third conductive line 140c. Therefore, the second contact 160a can be electrically connected to the second conductive line 140b, the first left contact 150a, and the first right contact 150b, but not to the first conductive line 140a and the third conductive line 140c.

According to some example embodiments, the length of the first left contact 150a in the first direction (ie, the height H1a) may be the same as the length of the first right contact 150b in the first direction (ie, the height H1b). Therefore, the first left contact 150a, the first right contact 150b, and the second contact 160a may form an H-shaped jumper. The jumper is a wire having a relatively short length for connecting two points or two terminals in the IC 100A.

As described above, according to some example embodiments, a single node may be formed by electrically connecting the second conductive line 140b, the first contact 150a, and the first contact 150b and the second contact 160a. Therefore, an IC fabricated based on the layout shown in FIG. In 100A, the second conductive line 140b may be skipped or shielded. Thus, an H-shaped jumper in accordance with some example embodiments may be referred to as a skip device.

According to some example embodiments, the unit skipping the second conductive line 140b may be designed by electrically connecting the second conductive line 140b, the first contact 150a, and the first contact 150b and the second contact 160a. Thus, the first contact 150a and the first contact 150b and the second contact 160a can be separated from the second conductive line 140b to reduce (or alternatively eliminate) the possibility of an electrical short occurring when forming the jumper.

Information about the above layout of the standard cells can be stored in the standard cell library. In particular, the standard cell library can contain information about a plurality of standard cells and is stored in a computer readable storage medium. For example, a non-transitory computer readable storage medium. A standard unit corresponding to information contained in a standard cell library refers to a unit having an IC that satisfies a standard size. For example, the height of the layout of the standard cells (for example, the length in the Y direction of FIG. 1) may be fixed, and the width of the standard cell (for example, the length in the X direction of FIG. 1) may vary according to standard cells. The standard unit can include input fins for processing input signals, and output fins for outputting output signals.

The IC can be a plurality of standard units. The IC design tool can design the IC, that is, complete the layout of the IC by using a standard cell library containing information on a plurality of standard cells. The IC design tool can place a via window on the pins (ie, the input pins and the output pins) included in the standard cell, so that the pins are formed after the pins of the standard cells are formed in the semiconductor manufacturing process. The pattern on the layer is connected. That is, the input signal or the output signal of the standard cell can be transmitted by placing the via window in the pin of the standard cell.

2 is a diagram illustrating a portion of an IC 100B in accordance with other example embodiments. layout.

Referring to FIG. 2, the IC 100B may include first to third conductive lines 140a to 140c, a first left contact 150a, a first right contact 150b', and a second contact 160a. IC 100B is a modified example embodiment of IC 100A shown in FIG. Thus, at least some of the description of FIG. 1 can also be applied to IC 100B, and thus the features and devices already described with reference to FIG. 1 will not be repeated.

According to some example embodiments, the length of the first left contact 150a in the first direction (ie, the height H1a) may be different from the length of the first right contact 150b' (ie, the height H1b'). Therefore, the first left contact 150a, the first right contact 150b', and the second contact 160a may form an L-shaped jumper.

According to some example embodiments, the height H1b' of the first right contact 150b' may be greater than the height H1a of the first left contact 150a. According to other example embodiments, the height H1a of the first left contact 150a may be greater than the height H1b' of the first right contact 150b'. The height H1a of the first left contact 150a and the height H1b' of the first right contact 150b' may vary in various example embodiments.

3 is a cross-sectional view taken along line III-III' of FIG. 1 illustrating an example of a semiconductor device 100a having the layout of FIG. 1.

Referring to FIG. 3, the semiconductor device 100a may include a substrate 110, a second conductive line 140b, a first contact 150a and a first contact 150b, and a second contact 160a. Although not illustrated, a voltage terminal that provides, for example, a power voltage or a ground voltage may be additionally disposed on the second contact 160a.

The substrate 110 may be a semiconductor substrate including, for example, any of the following: germanium, silicon-on-insulator (SOI), sapphire, germanium, germanium-tellurium, and gallium-arsenic Compound. For example, the substrate 110 can be a P-type base board. Also, although not illustrated, the substrate 110 may have an active region doped with impurities.

The second conductive line 140b may be disposed on the substrate 110. According to some example embodiments, the second conductive line 140b can function as a gate electrode. In this case, the gate insulating layer may be additionally disposed between the second conductive line 140b and the active region of the substrate 110.

The first contact 150a and the first contact 150b may be disposed on the substrate 110. Accordingly, the first contact 150a and the first contact 150b can provide, for example, a power voltage or a ground voltage in the active region of the substrate 110. According to some example embodiments, the first contact 150a and the first contact 150b may be disposed at both sides of the second conductive line 140b, respectively. According to some example embodiments, the first contact 150a and the upper portion of the first contact 150b may be at the same level as the upper portion of the second conductive line 140b.

The second contact 160a can be disposed on the second conductive line 140b and the first contact 150a and the first contact 150b, and is electrically connected to the second conductive line 140b and the first contact 150a and the first contact 150b. And form a single node.

4 is a layout illustrating a portion of an IC 100A' that is substantially identical to the example embodiment of FIG. 1.

Referring to FIG. 4, the IC 100A' may include a first conductive line 140a and a third conductive line 140c, and a first contact 150a and a first contact 150b. The first contact 150a and the first contact 150b can be connected to a single metal line disposed at the upper portion. According to other example embodiments, the IC 100A' may include only one of the first contact 150a and the first contact 150b.

The first contact 150a and the first contact 150b and the second contact 160a shown in the layout of FIG. 1 form an H-shaped jumper. Therefore, when the IC 100A is actually manufactured, the IC 100A can be substantially the same as the IC 100A' corresponding to the layout shown in FIG. In other words, due to the H-shaped jumper shown in the layout shown in Figure 1. For the line, the second conductive line 140b can be skipped.

Likewise, the first contact 150a and the first contact 150b' and the second contact 160a shown in the layout of FIG. 2 may form an L-shaped jumper. Therefore, when the IC 100B is actually manufactured, the IC 100B can be substantially the same as the IC 100A' corresponding to the layout shown in FIG. In other words, the second conductive line 140b can be skipped due to the L-shaped jumper shown in the layout in FIG.

FIG. 5 is a layout illustrating a portion of an IC 100C in accordance with other example embodiments.

Referring to Figure 5, IC 100C can include at least one unit that is defined by cell boundaries indicated by thick lines. The unit may include first to fourth conductive lines 140e to 140h, a first contact 150c and a first contact 150d, and a second contact 160b.

The first to fourth conductive lines 140e to 140h may extend in a first direction (eg, the Y direction). Also, the first to fourth conductive lines 140e to 140h may be disposed parallel to each other in a second direction (for example, the X direction) substantially perpendicular to the first direction. The first to fourth conductive lines 140e to 140h may be formed of a material having conductivity of, for example, polysilicon, metal, and/or metal alloy.

According to some example embodiments, the first conductive line 140e to the fourth conductive line 140h may correspond to a gate electrode. However, example embodiments are not limited thereto. For example, the first conductive line 140e to the fourth conductive line 140h may be conductive traces. Also, although FIG. 5 illustrates that the IC 100C includes the first to fourth conductive lines 140e to 140h, example embodiments are not limited thereto, and for example, the IC 100C may include extending in the first direction and parallel to each other in the second direction. Five or more conductive wires.

The first contact 150c and the first contact 150d may extend in the first direction. Moreover, the first contact 150c and the first contact 150d may be substantially perpendicular to the first side The second direction of the orientation is placed parallel to each other. The first contact 150c and the first contact 150d may be formed of a conductive material such as polysilicon, metal, and metal alloy. Therefore, the first contact 150c and the first contact 150d may provide a power voltage or a ground voltage into a lower region between the first conductive line 140e to the fourth conductive line 140h.

According to some example embodiments, the first contact 150c and the first contact 150d may include: a first left contact 150c disposed at a left side of the second conductive line 140f; and a first right contact 150d disposed at The right side of the third conductive line 140g. In other words, the first left contact 150c may be disposed between the first conductive line 140e and the second conductive line 140f, and the first right contact 150d may be disposed between the third conductive line 140g and the fourth conductive line 140h.

According to some example embodiments, the length of the first left contact 150c in the second direction (ie, the width W2a) may be smaller than the space S2 between the first conductive line 140e and the second conductive line 140f. Likewise, the length of the first right contact 150d in the second direction (ie, the width W2b) may be smaller than the space S2 between the third conductive line 140g and the fourth conductive line 140h. According to some example embodiments, the width W2a of the first left contact 150c may be substantially the same as the width W2b of the first right contact 150d. However, example embodiments are not limited thereto. For example, according to other example embodiments, the width W2a of the first left contact 150c may be different from the width W2b of the first right contact 150d.

The second contact 160b can be disposed on the second conductive line 140f and the third conductive line 140g and the first contact 150c and the first contact 150d, and is electrically connected to the second conductive line 140f and the third conductive line 140g. And the first contact 150c and the first contact 150d form a single node. Also, the second contact 160b can extend in the second direction, and thus the second contact 160b can be in contact with the second conductive line 140f and The three conductive wires 140g and the first contact 150c and the first contact 150d are disposed in a horizontally intersecting direction. The second contact 160b may be formed of a conductive material such as polysilicon, metal, and/or metal alloy. Accordingly, the second contact 160b can provide, for example, the same power voltage or the same ground voltage to the second conductive line 140f and the third conductive line 140g, and the first contact 150c and the first contact 150d.

According to some example embodiments, the length of the second contact 160b in the second direction (ie, the width W2c) may be greater than the distance D2a between the first left contact 150c and the first right contact 150d, and is smaller than the first conductive A distance D2b between the line 140e and the fourth conductive line 140h. Therefore, the second contact 160b can be electrically connected to the second conductive line 140f and the third conductive line 140g, the first left contact 150c, and the first right contact 150d, but not connected to the first conductive line 140e and the fourth conductive Line 140h.

According to some example embodiments, the length of the first left contact 150c in the first direction (ie, the height H2a) may be substantially the same as the length of the first right contact 150d in the first direction (ie, the height H2b). Therefore, the first left contact 150c, the first right contact 150d, and the second contact 160b may form an H-shaped jumper. The jumper is a wire having a relatively short length for connecting two points or two terminals in the IC 100C.

Although not illustrated, according to other example embodiments, the length of the first left contact 150c in the first direction (ie, the height H2a) may be different from the length of the first right contact 150d in the first direction (ie, the height) H2b). Therefore, the first left contact 150c, the first right contact 150d, and the second contact 160b may form an L-shaped jumper.

As described above, according to some example embodiments, a single node may be electrically shorted by connecting the second conductive line 140f and the third conductive line 140g, the first contact 150c, and the first contact 150d and the second contact 160b ( Electrical short-circuiting). Therefore, an IC fabricated based on the layout shown in FIG. In 100C, the second conductive line 140f and the third conductive line 140g may be skipped. Thus, an H-shaped jumper in accordance with some example embodiments may be referred to as a skip device.

FIG. 6 is a cross-sectional view illustrating an example of a semiconductor device 100c having the layout of FIG. 5.

Referring to FIG. 6, the semiconductor device 100c may include a substrate 110, a second conductive line 140f and a third conductive line 140g, a first contact 150c, and a first contact 150d and a second contact 160b. Although not illustrated, a voltage terminal that provides, for example, a power voltage or a ground voltage may be additionally disposed on the second contact 160b.

The substrate 110 may be a semiconductor substrate including, for example, any of the following: germanium, SOI, sapphire, germanium, germanium-tellurium, and gallium-arsenide. For example, the substrate 110 can be a P-type substrate. Also, although not illustrated, the substrate 110 may have an active region doped with impurities.

The second conductive line 140f and the third conductive line 140g may be disposed on the substrate 110. According to some example embodiments, the second conductive line 140f and the third conductive line 140g may be used as a gate electrode. In this case, the gate insulating layer may be additionally disposed between the second conductive line 140f and the third conductive line 140g and the active region of the substrate 110.

The first contact 150c and the first contact 150d may be disposed on the substrate 110. Accordingly, the first contact 150c and the first contact 150d can provide, for example, a power voltage or a ground voltage in the active region of the substrate 110. According to some example embodiments, the first contact 150c and the first contact 150d may be disposed on a left side of the second conductive line 140f and a right side of the third conductive line 140g, respectively. According to some example embodiments, the first contact 150c and the upper portion of the first contact 150d may be at the same level as the upper portions of the second conductive line 140f and the third conductive line 140g.

The second contact 160b can be disposed on each of the following and electrically connected to each of the following The second conductive line 140f and the third conductive line 140g, and the first contact 150c and the first contact 150d. Therefore, the second conductive line 140f and the third conductive line 140g, the first contact 150c, and the first contact 150d and the second contact 160b may form a single node.

FIG. 7 is a layout illustrating a portion of an IC 100D in accordance with other example embodiments.

Referring to Figure 7, IC 100D can include at least one unit that is defined by cell boundaries indicated by thick lines. The unit may include first to fourth conductive lines 140e to 140h, a first left contact 150c, a first right contact 150d, a first center contact 150e, and a second contact 160c. IC 100D is a modified example embodiment of IC 100C shown in FIG. 5, and thus at least some of the description of FIG. 5 can also be applied to IC 100D. Therefore, the features and devices already described with reference to FIG. 5 will not be repeated.

Unlike the IC 100C of FIG. 5, the IC 100D according to some example embodiments may further include a first center contact 150e. The first center contact 150e may be disposed between the second conductive line 140f and the third conductive line 140g. According to some example embodiments, the second contact 160c may be electrically connected to the second conductive line 140f and the third conductive line 140g and the first left contact 150c, the first right contact 150d, and the first center contact 150e, and thus Form a single node.

FIG. 8 is a cross-sectional view taken along line VIII-VIII' of FIG. 7 illustrating an example of a semiconductor device 100d having the layout of FIG. 5.

Referring to FIG. 8, the semiconductor device 100d may include a substrate 110, a second conductive line 140f and a third conductive line 140g, a first left contact 150c, a first right contact 150d and a first center contact 150e, and a second contact. 160c. The semiconductor device 100d is a modified embodiment of the semiconductor device 100c of FIG. 6, and thus, the description of FIG. 6 is also It can be applied to the semiconductor device 100d. Therefore, the features and devices already described with reference to FIG. 6 will not be repeated.

The first left contact 150c, the first right contact 150d, and the first center contact 150e may be disposed on the substrate 110, respectively. Accordingly, the first left contact 150c, the first right contact 150d, and the first center contact 150e can provide, for example, a power voltage or a ground voltage to the active region of the substrate 110. According to some example embodiments, the first center contact 150e may be disposed between the second conductive line 140f and the third conductive line 140g. According to some example embodiments, the first left contact 150c, the first right contact 150d, and the upper portion of the first center contact 150e may be substantially opposite to the upper portion of the second conductive line 140f and the third conductive line 140g, respectively. On the same level.

The second contact 160c can be disposed on each of the following and electrically connected to the following: the second conductive line 140f and the third conductive line 140g, and the first left contact 150c, the first right contact 150d, and the first center connection Point 150e. Therefore, the second conductive line 140f and the third conductive line 140g and the first left contact 150c, the first right contact 150d, and the first center contact 150e (respectively) may form a single node with the second contact 160b.

9 is a layout illustrating a portion of an IC 100C' that is substantially identical to the example embodiment of FIG. 5.

Referring to FIG. 9, the IC 100C' may include a first conductive line 140e and a fourth conductive line 140h, and a first contact 150c and a first contact 150d. The first contact 150c and the first contact 150d are connectable to the same metal line disposed above the first contact 150c and the first contact 150d. According to other example embodiments, the IC 100C' may include only one of the first contact 150c and the first contact 150d.

The first contact 150c and the first contact 150d and the second contact 160b included in the layout shown in FIG. 5 may form an H-shaped jumper. So when the actual When the IC 100C is fabricated, the IC 100C may be substantially the same as the IC 100C' corresponding to the layout shown in FIG. In other words, the second conductive line 140f and the third conductive line 140g may be skipped due to the H-shaped jumper shown in the layout in FIG.

Likewise, the first left contact 150c, the first right contact 150d, and the first center contact 150e and the second contact 160c, which are shown in the layout of FIG. 7, may form a jumper. Therefore, when the IC 100D is actually manufactured, the IC 100D can be substantially the same as the IC 100C' corresponding to the layout shown in FIG. In other words, the second conductive line 140f and the third conductive line 140g may be skipped due to the jumper wires shown in the layout in FIG.

FIG. 10 is a diagram illustrating a layout of an IC 200 according to other example embodiments.

Referring to Figure 10, IC 200 can include at least one unit that is defined by cell boundaries drawn with thick lines. In particular, Figure 10 illustrates an example of a standard cell in IC 200. The standard unit includes, but is not limited to, a first active area 220a and a second active area 220b, a plurality of fins, a plurality of conductive lines, a first contact 250a to a first contact 250d, a second contact 260, and a cutting area 270.

According to some example embodiments, the plurality of fins may include the first to sixth fins 230a to 230f, and the plurality of conductive lines may include the first to third conductive lines 240a to 240c. However, example embodiments are not limited thereto. For example, according to other example embodiments, the plurality of fins and the plurality of conductive lines may respectively include various numbers of fins and conductive lines.

The first active region 220a may be disposed at the first fin 230a to the third fin 230c, for example, an N-type metal oxide semiconductor (NMOS) defining layer. For example, the first active region 220a can be a random region in a P-type substrate. The second active region 220b may be disposed between the fourth fin 230d to the sixth fin 230f, for example, a P-type MOS (PMOS) Define the layer. For example, the second active zone 220b can be an N-type well zone. Although not shown, the device separation zone may be disposed between the first active zone 220a and the second active zone 220b.

The first to sixth fins 230a to 230f may be disposed in parallel with each other in a first direction (eg, the Y direction) and extend in a second direction (eg, an X direction) substantially perpendicular to the first direction . According to some example embodiments, the first to sixth fins 230a to 230f may be active fins. The channel width of the fin transistor formed by such fins may increase in proportion to the number of active fins, and thus the amount of current flowing in the fin transistor may increase. Although not shown, the IC 200 may additionally include dummy fins disposed on the separation region of the device.

According to some example embodiments, in the layout of the IC 200, the first fins 230a to the second fins 230f may have the same respective lengths in the first direction, that is, respective widths. The respective widths of the first to sixth fins 230a to 230f are widths displayed on the layout of FIG. 10 in two dimensions. Since FIG. 10 is a 2D layout, the respective heights of the first to sixth fins 230a to 230f are not shown.

The first to third conductive lines 240a to 240c may extend in a first direction (eg, the Y direction). Also, the first to third conductive lines 240a to 240c may be disposed in parallel with each other in a second direction (for example, the X direction) substantially perpendicular to the first direction. The first to third conductive lines 240a to 240c may be formed of a conductive material such as polysilicon, metal, and/or metal alloy. According to some example embodiments, the first conductive line 240a to the third conductive line 240c may correspond to a gate electrode.

The first to second contacts 250a to 250d may extend in a first direction (eg, the Y direction). Also, the first contact 250a to the first contact 250d may be parallel to each other in a second direction (eg, the X direction) substantially perpendicular to the first direction Set. The first contact 250a to the first contact 250d may be formed of a conductive material such as polysilicon, metal, and/or metal alloy.

According to some example embodiments, the first contact 250a to the first contact 250d may include the first lower contact 250a and the first lower contact 250b on the first active area 220a, and the second active area 220b The first upper contact 250c and the first upper contact 250d. The first lower contact 250a and the first lower contact 250b can be contacts that are connected to the first active region 220a, such as source contacts and drain contacts. Accordingly, the first lower contact 250a and the first lower contact 250b can provide, for example, a power voltage or a ground voltage to the first active region 220a. The first upper contact 250c and the first upper contact 250d can be contacts that are connected to the second active region 220b, such as source contacts and drain contacts. Thus, the first upper junction 250c and the first upper junction 250d can provide, for example, a power voltage or ground voltage to the second active region 220b.

According to some example embodiments, the first lower contact 250a and the first lower contact 250b may be disposed at both sides of the second conductive line 240b, respectively. In detail, the first lower contact 250a and the first lower contact 250b may include: a first left lower contact 250a disposed at a left side of the second conductive line 240b, and a right side disposed on the second conductive line 240b The first lower right contact 250b. In other words, the first lower left contact 250a may be disposed between the first conductive line 240a and the second conductive line 240b, and the first lower right contact 250b may be disposed between the second conductive line 240b and the third conductive line 240c. between.

The second contact 260 can be disposed on the second conductive line 240b and the first lower contact 250a and the first lower contact 250b, and is electrically connected to the second conductive line 240b and the first lower contact 250a. And the first lower contact 250b forms a single node. Moreover, the second contact 260 can extend in the second direction, that is, in the X direction. The second contact 260 can be disposed in a direction horizontally intersecting the second conductive line 240b and the first lower contact 250a and the first lower contact 250b. The second contact 260 can be formed of a conductive material such as polysilicon, metal, and/or metal alloy. Accordingly, the second contact 260 can provide, for example, the same power voltage or the same ground voltage to the second conductive line 240b and the first lower contact 250a and the first lower contact 250b.

According to some example embodiments, the first conductive line 240a to the third conductive line 240c, the first lower contact 250a, and the first lower contact 250b and the second contact 260 disposed on the first active region 220a may be combined with The IC 100A illustrated in Figure 1 is substantially identical. Thus, the description of FIG. 1 can also be applied to IC 200, and the features and devices that have been described with reference to FIG. 1 will not be repeated.

As described above, according to some example embodiments, a single node may be provided by the second conductive line 240b, the first lower contact 250a, and the first lower contact 250b and the second contact on the first active region 220a. 260 electrical short circuit connections are formed. Therefore, in the IC 200 fabricated based on the layout shown in FIG. 10, the second conductive line 240b may be skipped in the first active region 220a, but not skipped in the second active region 220b. Thus, IC 200 can include an asymmetric gate in which, for example, two transistors of two NMOS fin transistors are in first active region 220a, and for example, three PMOS fin transistors The three transistors are in the second active region 220b.

Although FIG. 10 illustrates an example embodiment in which the second contact 260 is disposed on the first active region 220a, the example embodiments are not limited thereto. For example, according to other example embodiments, the second contact 260 may be disposed on both the first active area 220a and the second active area 220b. In this case, the same number of transistors can be disposed on the first active region 220a and the second active region 220b. According to other example embodiments, the second connection Point 260 can be disposed on only second active region 220b. In this case, more transistors can be disposed on the first active region 220a than the second active region 220b.

Figure 11 is a diagram illustrating the layout of an IC 200' that is substantially identical to the example embodiment of Figure 10.

Referring to FIG. 11, the IC 200' may include first to third conductive lines 240a to 240c, and first to second contacts 250a to 250d. The first lower contact 250a and the first lower contact 250b disposed on the first active area 220a are connectable to the first lower contact 250a and the same metal line above the first lower contact 250b. According to other example embodiments, the IC 200' may include only one of the first lower contact 250a and the first lower contact 250b.

The first lower contact 250a and the first lower contact 250b and the second contact 260 included in the layout shown in FIG. 10 may form an H-shaped jumper. Therefore, when the IC 200 is actually manufactured, the IC 200 can be substantially the same as the IC 200' corresponding to the layout shown in FIG. In other words, the second conductive line 240b in the first active region 220a may be skipped due to the H-shaped jumper shown in the layout in FIG. Therefore, as illustrated in FIG. 11, the second conductive line 240b may be skipped in the first active region 220a, and thus, the IC 200 and 200' may include two NMOS fin transistors in the first active region 220a. And three PMOS fin transistors are included in the second active region 220b.

FIG. 12 is a perspective view illustrating an example of a semiconductor device 200A having the layout of FIG. FIG. 13 is a cross-sectional view illustrating the semiconductor device 200A taken along line XII-XII' of FIG.

Referring to FIGS. 12 and 13, the semiconductor device 200A may be a bulk type fin transistor. The semiconductor device 200A may include a substrate 210 and a first insulation The layer 233, the second insulating layer 236, the first to third fins 230a to 230c, and the first conductive line (hereinafter referred to as "gate electrode") 240a.

The substrate 210 may be a semiconductor substrate including, for example, any of the following: germanium, SOI, sapphire, germanium, germanium-tellurium, and gallium-arsenide. The substrate 210 may be a P-type substrate and function as the first active region 220a.

The first to third fins 230a to 230c may be disposed such that they are connected to the substrate 210. According to some example embodiments, the first to third fins 230a to 230c may be active regions formed by doping portions perpendicularly protruding from the substrate 210 with n+ or p+ impurities.

The first insulating layer 233 and the second insulating layer 236 may include an insulating material selected from, for example, the following: oxides, nitrides, and/or oxynitrides. The first insulating layer 233 may be disposed on the first to third fins 230a to 230c. The first insulating layer 233 can function as a gate insulating layer by being disposed between the first fin 230a to the third fin 230c and the gate electrode 240a. The second insulating layer 236 may be formed at a certain height at a space between the first fin 230a to the third fin 230c. The second insulating layer 236 can function as a device separation layer by being disposed between the first fins 230a to the third fins 230c.

The gate electrode 240a may be disposed on the first insulating layer 233 and the second insulating layer 236. Therefore, the gate electrode 240a may surround the first to third fins 230a to 230c, the first insulating layer 233, and the second insulating layer 236. In other words, the first to third fins 230a to 230c may be located inside the gate electrode 240a. The gate electrode 240a may include a metal material such as tungsten (W) or tantalum (Ta), a nitride of a metal material, a germanide of a metal material, and/or doped polysilicon, and is formed by using a deposition process.

FIG. 14 is a perspective view illustrating another example of the semiconductor device 200B having the layout of FIG. FIG. 15 is a view along the line XIV- of FIG. 14 illustrating the semiconductor device 200B. XIV' cut out cross section.

Referring to FIGS. 14 and 15, the semiconductor device 200B may be an SOI type fin transistor. The semiconductor device 200B may include a substrate 210', a first insulating layer 215, a second insulating layer 233', first to third fins 230a' to 230c', and a first conductive line (hereinafter referred to as "gate electrode") ) 240a'. Semiconductor device 200B is a modified example embodiment of semiconductor device 200A shown in FIGS. 12 and 13. Therefore, features and devices different from the semiconductor device 200A of the semiconductor 200B will be mainly described, and the features and devices already described with reference to FIGS. 12 and 13 will not be repeated.

The first insulating layer 215 may be disposed on the substrate 210'. The second insulating layer 233' may serve as a gate insulating layer by being disposed between the first fins 230a' to the third fins 230c' and the gate electrodes 240a'. The first fins 230a' to the third fins 230c' may comprise a semiconductor material, such as germanium and/or doped germanium.

The gate electrode 240a' may be disposed on the second insulating layer 233'. Therefore, the gate electrode 240a' may surround the first fins 230a' to the third fins 230c' and the second insulating layer 233'. In other words, the first to third fins 230a' to 230c' may be located inside the gate electrode 240a'.

FIG. 16 is a cross-sectional view taken along line XVI-XVI' of FIG. 10 illustrating the semiconductor device 200a having the layout of FIG.

Referring to FIG. 16, the semiconductor device 200a may include a second fin 230b, a second conductive line 240b, a first lower contact 250a and a first lower contact 250b, and a second contact 260. Although not shown, a voltage terminal that provides, for example, a power voltage or a ground voltage may be additionally disposed on the second contact 260.

The second conductive line 240b may be disposed on the second fin 230b. According to some example embodiments, the second conductive line 240b can be used as a gate electrode, and the gate insulating layer can be additionally The outer portion is disposed between the second conductive line 240b and the second fin 230b.

The first lower contact 250a and the first lower contact 250b may be disposed on the second fin 230b. Thus, the first lower contact 250a and the first lower contact 250b can provide, for example, a power voltage or ground voltage to the second fin 230b. According to some example embodiments, the first lower contact 250a and the first lower contact 250b may be disposed at both sides of the second conductive line 240b, respectively. According to some example embodiments, the upper portions of the first lower contact 250a and the first lower contact 250b may be at the same level as the upper portion of the second conductive line 240b.

The second contact 260 can be disposed on each of the following and electrically connected to the second conductive line 240b and the first lower contact 250a and the first lower contact 250b. Therefore, the second conductive line 240b, the first lower contact 250a, and the first lower contact 250b and the second contact 260 may form a single node.

FIG. 17 is a diagram illustrating a layout of an IC 300 according to other example embodiments.

Referring to Figure 17, IC 300 can include at least one unit defined by cell boundaries drawn with thick lines. In particular, Figure 17 illustrates an example of a standard cell in IC 300. The standard unit may include a first active region 220a and a second active region 220b, first to sixth fins 230a to 230f, first to second conductive lines 240a to 240c, and first to second contacts 250a to 250a. 250d, second contact 260, cutting zone 270, and third to third contacts 380a to 380c. IC 300 is a modified example embodiment of IC 200 shown in FIG. Accordingly, the description of FIG. 10 can also be applied to the IC 300, and thus the features and devices already described with reference to FIG. 10 will not be repeated.

In contrast to IC 200 of FIG. 10, IC 300 in accordance with some example embodiments may additionally include third to third contacts 380a to 380c. The first of the third contacts 380a may be disposed on the first conductive line 240a and electrically connected to the first conductive line. The third of the third contacts 380c may be disposed on the third conductive line 240c and electrically connected to the third conductive line.

The second of the third contacts 380b may be disposed on the second conductive line 240b and electrically connected to the second conductive line. Since the dicing region 270 is in the middle of the second conductive line 240b, the third contact 380b is electrically connected to the second conductive line 240b on only the second active region 220b, but is not electrically connected to the first active region 220a. Two conductive wires 240b.

According to some example embodiments, a single node may be electrically shorted by connecting the second conductive line 240b, the first lower contact 250a, and the first lower contact 250b and the second contact 260 on the first active region 220a. form. Therefore, in the IC 300 fabricated based on the layout shown in FIG. 17, the second conductive line 240b may be skipped in the first active region 220a, but not skipped in the second active region 220b, so that the IC 300 has Asymmetric brake. Thus, IC 300 can include two transistors (eg, two NMOS fin transistors) in first active region 220a and three transistors in second active region 220b (eg, three PMOS fins) Transistor).

Although FIG. 17 illustrates an example embodiment in which the second contact 260 is disposed on the first active region 220a, the example embodiments are not limited thereto. For example, according to other example embodiments, the second contact 260 may be disposed on both the first active area 220a and the second active area 220b. In this case, the same number of transistors can be disposed on the first active region 220a and the second active region 220b. According to other example embodiments, the second contact 260 may be disposed only on the second active region 220b. In this case, more transistors can be disposed on the first active region 220a than the second active region 220b.

FIG. 18 is a layout illustrating a portion of an IC 300' that is substantially identical to the example embodiment of FIG.

Referring to FIG. 18, the IC 300' may include first to third conductive lines 240a to 240c, first to second contacts 250a to 250d, and third to third contacts 380a to 380c. The first lower contact 250a and the first lower contact 250b on the first active region 220a are connectable to the same lower wire 250a and the same metal wire above the first lower contact 250b. According to other example embodiments, the IC 300' may include only one of the first lower contact 250a and the first lower contact 250b.

The first lower contact 250a and the first lower contact 250b and the second contact 260 included in the layout shown in FIG. 17 may form an H-shaped jumper. Therefore, when the IC 300 is actually manufactured, the IC 300 can be substantially the same as the IC 300' corresponding to the layout shown in FIG. In other words, as shown in FIG. 18, the second conductive line 240b in the first active region 220a may be skipped due to the H-shaped jumper shown in the layout in FIG. Thus, IC 300 and IC 300' may include two NMOS fin transistors in first active region 220a and three PMOS fin transistors in second active region 220b.

FIG. 19 is a circuit diagram illustrating the IC 300 of FIG. 17.

Referring to FIGS. 17 and 19, the IC 300 may include first to third PMOS fin transistors PM1 to PM3, and a first NMOS transistor NM1 and a second NMOS transistor NM2. The first PMOS fin transistor PM1 to the third PMOS fin transistor PM3 may be formed on the second active region 220b, and the first NMOS fin transistor NM1 and the second NMOS fin transistor NM2 may be formed in the first Active area 220a.

The respective gates of the first PMOS fin transistor PM1 and the first NMOS fin transistor NM1 are connected to a node A which may correspond to the first one of the third contacts 380a. Moreover, the gate of the second PMOS fin transistor PM2 can be connected to It may correspond to the node B of the second of the third contacts 380b. Moreover, each of the third PMOS fin transistor PM3 and the second NMOS fin transistor NM2 may be connected to a node C that may correspond to a third one of the third contacts 380c.

Specifically, in some example embodiments, the gate of the first PMOS fin transistor PM1 may be connected to the third contact 380a, and the drain of the first PMOS fin transistor PM1 may be connected to the first node region NA1. And the first node area NA1 may correspond to the first upper left contact 250c. The gate of the second PMOS fin transistor PM2 may be connected to the third node 380b, the drain of the second PMOS fin transistor PM2 may be connected to the second node region NA2, and the second node region NA2 may correspond to the first A right upper contact 250d. The gate of the third PMOS fin transistor PM3 may be connected to the third of the third contacts 380c.

The gate of the first NMOS fin transistor NM1 may be connected to the first one of the third contacts 380a, and the gate of the second NMOS fin transistor NM2 may be connected to the third of the third contacts Contacts 380c. The first NMOS fin transistor NM1 and the second NMOS fin transistor NM2 may be connected to the third node region NA3, which may correspond to the first lower contact 250a and the first lower contact 250b of FIG. 17 and The jumper formed by the second contact 260.

FIG. 20 is a circuit diagram illustrating the third node region NA3 of FIG. 19 in detail.

Referring to FIG. 17, FIG. 19 and FIG. 20, a single node region (ie, the third node region NA3) may be formed by connecting the following: a first node between the second fin 230b and the first lower left contact 250a The second node ND2 between the ND1, the second fin 230b and the first lower right contact 250b, and the third node ND3 between the second contact 260 and the second conductive line 240b.

FIG. 21 is a diagram illustrating a layout of an IC 400 according to other example embodiments.

Referring to Figure 21, IC 400 can include at least one unit defined by cell boundaries drawn with thick lines. In particular, Figure 21 illustrates an example of a standard cell in IC 400. The standard unit may include first to tenth fins 430a to 430j, a plurality of gate electrodes 440b, gate electrodes 440c and gate electrodes 440d, a plurality of dummy gate electrodes 440a and dummy gate electrodes 440e, a plurality of source electrodes, and a drain electrode Points 450a and 450b, second contact 460, cutting zone 470, two input terminals 480, two input contacts 485, and output terminals 490.

According to example embodiments, the first fin 430a, the fifth fin 430e, the sixth fin 430f, and the tenth fin 430j may be dummy fins, and the second fin 430d to the fourth fin 430b and the seventh fin The sheets 430g through ninth fins 430i may be active fins. Specifically, the second to fourth fins 430b to 430d may be disposed in the first active region 420a, and the seventh to ninth fins 430g to 430i may be disposed in the second active region 420b. The first fin 430a may be disposed in the first device separation region 425a, the fifth fin 430e and the sixth fin 430f may be disposed in the second device separation region 425b, and the tenth fin 430j may be disposed in the third device In the separation zone 425c.

First, the first to tenth fins 430a to 430j can be formed in advance on a semiconductor substrate (not shown) by performing a single manufacturing process. Second, a plurality of source contacts 450a and drain electrodes 450b and gate electrodes may be formed. The gate electrodes include a plurality of gate electrodes 440b, gate electrodes 440c and gate electrodes 440d, and a plurality of dummy gate electrodes 440a and dummy gates. Electrode 440e. Third, a second contact 460 can be formed on the gate electrode 440c and the plurality of source and drain contacts 450a and 450b. Fourth, two input terminals 480 and an output terminal 490 can be formed.

The first zone R1 is similar to the layout shown in Figure 1, and thus the above reference The example embodiments described with reference to Figures 1 through 9 can be applied to the first zone R1. The second zone R2 is similar to the layout shown in FIG. 10, and thus the example embodiment described above with reference to 10-20 is applicable to the second zone R2. According to some example embodiments, the second to fourth fins 430b to 430d may form an NMOS transistor, and the seventh to ninth fins 430g to 430i may form a PMOS transistor.

Although FIG. 21 illustrates an example embodiment in which the second contact 460 is disposed on the first active region 420a, example embodiments are not limited thereto. For example, according to other example embodiments, the second contact 460 may be disposed on both the first active area 420a and the second active area 420b. In this case, the same number of transistors can be disposed on the first active region 420a and the second active region 420b. According to other example embodiments, the second contact 460 may be disposed only on the second active region 420b. In this case, more transistors can be disposed on the first active region 420a than the second active region 420b.

22 is a layout illustrating a portion of an IC 400' that is substantially identical to the example embodiment of FIG.

Referring to FIG. 22, the IC 400' may include first to tenth fins 430a to 430j, a plurality of gate electrodes 440b, gate electrodes 440c and gate electrodes 440d, a plurality of dummy gate electrodes 440a and dummy gate electrodes 440e, and a plurality of sources. The pole and drain contacts 450a and 450b, the second contact 460, the two input terminals 480, the two input contacts 485, and the output terminal 490. The plurality of source and drain contacts 450a and 450b on the first active region 420a can be connected to a plurality of sources and the same metal lines above the drain contacts 450a and 450b. According to other example embodiments, the IC 400' may include a plurality of sources and only one of the drain contacts 450a and 450b on the first active region 420a.

The plurality of source and drain contacts 450a and 450b and the second contact 460 included in the layout shown in FIG. 21 may form an H-shaped jumper. Therefore, when In actual fabrication of the IC 400, the IC 400 can be substantially identical to the IC 400' corresponding to the layout shown in FIG. In other words, as shown in FIG. 22, the gate electrode 440c in the first active region 420a of FIG. 22 may be skipped due to the H-shaped jumper shown in the layout in FIG. Thus, each of IC 400 and IC 400' can include two NMOS fin transistors in first active region 420a and three PMOS fin transistors in second active region 420b.

FIG. 23 is a block diagram illustrating a computer readable storage medium 500, in accordance with some example embodiments.

Referring to Figure 23, computer readable storage medium 500 can include storage media that can be read by a computer to, for example, provide commands and/or data to a computer. The computer readable storage medium 500 can be non-transitory. For example, the non-transitory computer readable storage medium 500 can include a magnetic storage medium (eg, a magnetic disk or a magnetic tape) and an optical recording medium (CD-ROM, DVD-ROM, CD-R, CD-RW, DVD-R). And DVD-RW), volatile or non-volatile memory (eg RAM, ROM or flash memory), non-volatile memory accessible via USB interface, and microelectromechanical system (MEMS) . The computer readable recording medium can be inserted into a computer, integrated into a computer, or combined with a computer via a communication medium such as a network and/or wireless link.

As shown in FIG. 23, computer readable storage medium 500 may have stored positioning and routing programs 510, libraries 520, analysis programs 530, and data structures 540. The positioning and routing program 510 can store a plurality of commands to perform a method of using a standard cell library, or a method of designing an IC according to an example embodiment of the inventive concept. For example, computer readable storage medium 500 can store positioning and routing programs that include any commands to perform all or a portion of the methods described above with reference to the figures. 510. Library 520 can contain information about standard cells, which are cells included in the IC.

The analysis program 530 can include a plurality of commands for executing a method based on an IC-defined data analysis IC. The data structure 540 can include a storage space for managing data generated during a program that uses the standard cell library in the library 520, extracting tag information from a common standard cell library in the library 520, or analyzing the analysis program 530. The timing characteristics of the executed IC.

24 is a block diagram illustrating a memory card 1000 that includes an IC in accordance with some example embodiments.

Referring to Figure 24, in memory card 1000, controller 1100 and memory 1200 can be positioned to exchange electrical signals, for example, via busbars. For example, when the controller 1100 issues a command, the memory 1200 can transmit data.

The controller 1100 and the memory 1200 may include an IC according to an example embodiment of the inventive concept. Specifically, in at least one of the plurality of semiconductor devices in the controller 1100 and the memory 1200, at least one conductive line can be skipped by forming a single node. A single node may be formed by electrically connecting at least two first contacts extending in a first direction (eg, the Y direction) in a second direction (eg, an X direction) perpendicular to the first direction a second contact extending upward and at least one conductive line extending in the first direction.

The memory card 1000 can be a memory card selected from various types of memory cards, such as a memory stick card, a smart media (SM) card, a secure digital (SD) card, a mini SD card, and a multimedia card (multimedia). Card;MMC).

25 is a block diagram illustrating a computing system 2000 that includes an IC in accordance with some example embodiments.

Referring to FIG. 25, computing system 2000 can include a processor 2100, a memory device 2200, a storage device 2300, a power supply 2400, and an input/output (I/O) device 2500. Although not illustrated in FIG. 25, computing system 2000 can additionally include a device for communicating with a video card, sound card, memory card, USB device, or other electronic device.

The processor 2100, the memory device 2200, the storage device 2300, the power supply 2400, and the I/O device 2500 included in the computing system 2000 may include an IC according to an example embodiment of the inventive concept. Specifically, in the processor 2100, the memory device 2200, the storage device 2300, the power supply 2400, and at least one of the plurality of semiconductor devices in the I/O device 2500, the semiconductor device can be jumped by forming a single node. Pass at least one conductive wire. A single node may be formed by electrically connecting at least two first contacts extending in a first direction (eg, the Y direction) in a second direction (eg, an X direction) perpendicular to the first direction a second contact extending upward and at least one conductive line extending in the first direction.

The processor 2100 can perform the desired (or alternatively predetermined) calculations or tasks. According to an example embodiment, the processor 2100 may be a microprocessor or a central processing unit (CPU). The processor 2100 can communicate with the memory device 2200, the storage device 2300, and the I/O device 2500 via a bus 2600 such as an address bus, a control bus, and a data bus. According to some example embodiments, the processor 2100 may be connected to an expansion bus, such as a peripheral component interconnect (PCI) bus.

The memory device 2200 can store data necessary for the operation of the computing system 2000. For example, the memory device 2200 can be a dynamic random access memory (DRAM), a mobile DRAM, or a static RAM. (static RAM; SRAM), phase-change RAM (PRAM), ferroelectric RAM (FRAM), resistive RAM (RRAM), and/or magnetoresistive RAM (MRAM) . The storage device 2300 may include a solid state drive (SSD), a hard disk drive (HDD), and a CD-ROM.

I/O device 2500 can include input devices such as a keyboard, keypad, and mouse; and output devices such as printers and displays. Power supply 2400 can provide operating voltages necessary for operation of computing system 2000.

ICs according to example embodiments may be assembled into various types of packages. For example, at least some components of an IC can be installed by using a package such as: Package on Package (PoP), Ball Grid Array (BGA), Chip Scale Package (Chip Scale Package) ; CSP), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-Iine Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Iine Package (CERDIP), Plastic Quad Flat Package (Metric Quad) Flat Pack; MQFP), Thin Quad Flat Pack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline; TSOP), System In Package (SIP), Multi Chip Package (MCP), Wafer-Level Fabricated Package (WFP), and Wafer Level Processing Stack Package (Wafer-Level) Proc Essed Stack Package, WSP).

While the embodiments of the present invention have been shown and described with reference to the embodiments of the embodiments of the present invention, it is understood that various changes in form and details may be made without departing from the spirit and scope of the invention.

Claims (25)

An integrated circuit comprising: at least one unit, comprising: a plurality of conductive lines extending in a first direction and parallel to each other in a second direction, the second direction being perpendicular to the first direction; a first contact comprising a first left contact between the first conductive line and the second conductive line of the plurality of conductive lines; and a second contact at the second conductive line and the first a second contact electrically connected to the second conductive line and the first contact and electrically isolating the first conductive line, such that the second contact, the second conductive line And the first contact forms a single node. The integrated circuit of claim 1, wherein the first contact extends in the first direction and the second contact extends in the second direction. The integrated circuit of claim 1, wherein the second contact extends in a direction perpendicular to the first contact. The integrated circuit of claim 1, wherein each of the at least one unit further comprises: a first active area and a second active area having different conductivity types, and wherein the second The contact is on at least one selected one of the first active area and the second active area. The integrated circuit of claim 4, wherein the plurality of conductive lines respectively correspond to the plurality of gate electrodes, and the number of the first transistors in the first active region is smaller than the second active Number of second transistors in the zone Head. The integrated circuit of claim 4, wherein the plurality of conductive lines respectively correspond to the plurality of gate electrodes, and the number of the first transistors in the first active region is equal to or greater than the number The number of second transistors in the two active regions. The integrated circuit of claim 4, wherein each of the at least one unit further comprises: a plurality of fins in the first active area and the second active area Extending in the second direction, the plurality of fins are parallel to each other in the first direction. The integrated circuit of claim 7, wherein the plurality of conductive lines respectively correspond to a plurality of gate electrodes, the plurality of fins respectively correspond to a plurality of fin transistors, and the first A first number of the plurality of fin transistors in the active region is less than a second number of the plurality of fin transistors in the second active region. The integrated circuit of claim 7, wherein the plurality of conductive lines respectively correspond to a plurality of gate electrodes, the plurality of fins respectively correspond to a plurality of fin transistors, and the first The first number of the plurality of fin transistors in the active region is equal to or greater than a second number of the plurality of fin transistors in the second active region. The integrated circuit of claim 4, further comprising: a cutting area between the first active area and the second active area, the cutting area being disposed to make the first conductive line Is insulated from the single node in the second active zone. The integrated circuit of claim 1, wherein the integrated circuit of claim 1 The first contact includes the first left contact and a first right contact, the first left contact is at a second side of the first conductive line, and the first right contact Is at the first side of the second conductive line. The integrated circuit of claim 11, wherein the second contact is on the following and electrically connected to: the first left contact, the first right contact And the second conductive line and the third conductive line of the plurality of conductive lines. The integrated circuit of claim 11, wherein the first contact further comprises: a first center contact between the second conductive line and the third conductive line. The integrated circuit of claim 13, wherein the second contact is on the following and electrically connected to: the first left contact, the first right contact The first center contact, the second conductive line, and the third conductive line. The integrated circuit of claim 1, wherein the plurality of conductive lines comprise first conductive lines, second conductive lines and third conductive lines adjacent to each other, the first contacts comprising the a left contact and a first right contact, the first left contact being between the first conductive line and the second conductive line, and the first right contact being at the second Between the conductive line and the third conductive line, and a length of the second contact in the second direction is greater than a distance between the first left contact and the first right contact, and Less than a distance between the first conductive line and the third conductive line. The integrated circuit according to claim 1, wherein the plurality of circuits are The respective lengths of the first contacts in the second direction are smaller than the space between two of the plurality of conductive lines adjacent to the conductive lines. The integrated circuit of claim 1, wherein the plurality of first contacts have the same length in the first direction, and the first contact and the second contact form an H Shape jumper. The integrated circuit of claim 1, wherein the plurality of first contacts have different lengths in the first direction, and the first contacts and the second contacts form L Shape jumper. A semiconductor device comprising: a substrate comprising a first active region and a second active region, the first active region and the second active region having different conductivity types; a plurality of conductive lines extending in a first direction and Parallel to each other in a second direction, the second direction being perpendicular to the first direction, the plurality of conductive lines comprising at least one first gate electrode and a second gate electrode; a plurality of first contacts, which are And on a respective one of the two sides of the second conductive line among the plurality of conductive lines; and a second contact in at least one of the first active area and the second active area The second conductive line and the first contact, the second contact is electrically connected to the second conductive line and the first contact and electrically isolates the first conductive line, so that the second The junction, the second conductive line, and the first contact form a single node. The semiconductor device of claim 19, wherein the plurality of conductive lines respectively correspond to the plurality of gate electrodes, and the first number of transistors in the first active region is smaller than the second active region The second number of transistors in the cell. The semiconductor device of claim 19, wherein the plurality of conductive lines respectively correspond to the plurality of gate electrodes, and the first number of transistors in the first active region is equal to or greater than the second The second number of transistors in the active region. A standard cell library is stored in a non-transitory computer readable storage medium, the standard cell library includes: information associated with at least one standard cell, the at least one standard cell comprising: a first active zone and a second active a region, the first active region and the second active region have different conductivity types, a plurality of fins, which are parallel to each other in the first active region and the second active region, and a plurality of conductive lines, Above the plurality of fins, the plurality of conductive lines extend in a first direction and are parallel to each other in a second direction, the second direction being perpendicular to the first direction, the plurality of conductive The wire includes at least a first gate electrode and a second gate electrode, a plurality of first contacts on respective sides of the two sides of the second conductive line among the plurality of conductive lines, and a second connection a point electrically connected to the second conductive line and the first contact in at least one of the first active region and the second active region and electrically isolating the first conductive line such that a second contact, the second conductive line, and the first Said contacts in said first active region and said second active region formed in at least one of a single node. An integrated circuit comprising: At least one unit comprising: a plurality of conductive lines extending in a first direction and parallel to each other in a second direction, the second direction being perpendicular to the first direction; the first contact being On each of the two sides of at least one of the conductive lines; and a second contact, at the at least one of the conductive lines and the first contact, the second contact Connecting to the at least one of the conductive lines and the first contact such that the second contact, the at least one of the conductive lines, and the first contact form a single node, wherein the first contact has the following One of: (i) the same length in the first direction such that the first contact and the second contact form an H-shaped jumper, and (ii) in the first direction Different lengths such that the first contact and the second contact form an L-shaped jumper. A semiconductor device comprising: a substrate including a first active region having a first conductivity type; a plurality of gate electrodes extending in a first direction such that the plurality of gate electrodes are parallel to each other in a second direction The second direction is perpendicular to the first direction, the plurality of gate electrodes comprise at least one first gate electrode and a skipped gate electrode; a plurality of first contacts at the plurality of gate electrodes At each of the two sides of the skip gate electrode, the skipped gate electrode is one of the plurality of gate electrodes connected to the first contact; and a second contact Electrically connected to the skipped gate in the first active region And the first contact and electrically isolating the first gate electrode such that the second contact, the skipped gate electrode, and the first contact form a single in the first active region node. The semiconductor device of claim 24, wherein the semiconductor device comprises at least one asymmetric gate integrated circuit, wherein the asymmetric gate integrated circuit is in the first The second active region contains a larger number of transistors.